1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2016 Marvell Technology Group 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada 8040 De 5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi" 9 #include "armada-8040.dtsi"
10 10
11 / { 11 / {
12 model = "Marvell Armada 8040 DB board" 12 model = "Marvell Armada 8040 DB board";
13 compatible = "marvell,armada8040-db", 13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-qua 14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@0 { 20 memory@0 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000> 22 reg = <0x0 0x0 0x0 0x80000000>;
23 }; 23 };
24 24
25 aliases { 25 aliases {
26 ethernet0 = &cp0_eth0; 26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth2; 27 ethernet1 = &cp0_eth2;
28 ethernet2 = &cp1_eth0; 28 ethernet2 = &cp1_eth0;
29 ethernet3 = &cp1_eth1; 29 ethernet3 = &cp1_eth1;
30 i2c1 = &cp0_i2c0; <<
31 i2c2 = &cp1_i2c0; <<
32 }; 30 };
33 31
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 32 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35 compatible = "regulator-fixed" 33 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-v 34 regulator-name = "cp0-usb3h0-vbus";
37 regulator-min-microvolt = <500 35 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <500 36 regulator-max-microvolt = <5000000>;
39 enable-active-high; 37 enable-active-high;
40 gpio = <&expander0 0 GPIO_ACTI 38 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41 }; 39 };
42 40
43 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 41 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44 compatible = "regulator-fixed" 42 compatible = "regulator-fixed";
45 regulator-name = "cp0-usb3h1-v 43 regulator-name = "cp0-usb3h1-vbus";
46 regulator-min-microvolt = <500 44 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <500 45 regulator-max-microvolt = <5000000>;
48 enable-active-high; 46 enable-active-high;
49 gpio = <&expander0 1 GPIO_ACTI 47 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50 }; 48 };
51 49
52 cp0_usb3_0_phy: cp0-usb3-0-phy { 50 cp0_usb3_0_phy: cp0-usb3-0-phy {
53 compatible = "usb-nop-xceiv"; 51 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_0_ 52 vcc-supply = <&cp0_reg_usb3_0_vbus>;
55 }; 53 };
56 54
>> 55 cp0_usb3_1_phy: cp0-usb3-1-phy {
>> 56 compatible = "usb-nop-xceiv";
>> 57 vcc-supply = <&cp0_reg_usb3_1_vbus>;
>> 58 };
>> 59
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { 60 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
58 compatible = "regulator-fixed" 61 compatible = "regulator-fixed";
59 regulator-name = "cp1-usb3h0-v 62 regulator-name = "cp1-usb3h0-vbus";
60 regulator-min-microvolt = <500 63 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <500 64 regulator-max-microvolt = <5000000>;
62 enable-active-high; 65 enable-active-high;
63 gpio = <&expander1 0 GPIO_ACTI 66 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
64 }; 67 };
65 68
66 cp1_usb3_0_phy: cp1-usb3-0-phy { 69 cp1_usb3_0_phy: cp1-usb3-0-phy {
67 compatible = "usb-nop-xceiv"; 70 compatible = "usb-nop-xceiv";
68 vcc-supply = <&cp1_reg_usb3_0_ 71 vcc-supply = <&cp1_reg_usb3_0_vbus>;
69 }; 72 };
70 }; 73 };
71 74
>> 75 &i2c0 {
>> 76 status = "okay";
>> 77 clock-frequency = <100000>;
>> 78 };
>> 79
72 &spi0 { 80 &spi0 {
73 status = "okay"; 81 status = "okay";
74 82
75 flash@0 { !! 83 spi-flash@0 {
76 compatible = "jedec,spi-nor"; 84 compatible = "jedec,spi-nor";
77 reg = <0>; 85 reg = <0>;
78 spi-max-frequency = <10000000> 86 spi-max-frequency = <10000000>;
79 87
80 partitions { 88 partitions {
81 compatible = "fixed-pa 89 compatible = "fixed-partitions";
82 #address-cells = <1>; 90 #address-cells = <1>;
83 #size-cells = <1>; 91 #size-cells = <1>;
84 92
85 partition@0 { 93 partition@0 {
86 label = "U-Boo 94 label = "U-Boot";
87 reg = <0 0x200 95 reg = <0 0x200000>;
88 }; 96 };
89 partition@400000 { 97 partition@400000 {
90 label = "Files 98 label = "Filesystem";
91 reg = <0x20000 99 reg = <0x200000 0xce0000>;
92 }; 100 };
93 }; 101 };
94 }; 102 };
95 }; 103 };
96 104
97 /* Accessible over the mini-USB CON9 connector 105 /* Accessible over the mini-USB CON9 connector on the main board */
98 &uart0 { 106 &uart0 {
99 status = "okay"; 107 status = "okay";
100 pinctrl-0 = <&uart0_pins>; 108 pinctrl-0 = <&uart0_pins>;
101 pinctrl-names = "default"; 109 pinctrl-names = "default";
102 }; 110 };
103 111
104 /* CON6 on CP0 expansion */ 112 /* CON6 on CP0 expansion */
105 &cp0_pcie0 { 113 &cp0_pcie0 {
106 phys = <&cp0_comphy0 0>; <<
107 phy-names = "cp0-pcie0-x1-phy"; <<
108 status = "okay"; 114 status = "okay";
109 }; 115 };
110 116
111 /* CON5 on CP0 expansion */ 117 /* CON5 on CP0 expansion */
112 &cp0_pcie2 { 118 &cp0_pcie2 {
113 phys = <&cp0_comphy5 2>; <<
114 phy-names = "cp0-pcie2-x1-phy"; <<
115 status = "okay"; 119 status = "okay";
116 }; 120 };
117 121
118 &cp0_i2c0 { 122 &cp0_i2c0 {
119 status = "okay"; 123 status = "okay";
120 clock-frequency = <100000>; 124 clock-frequency = <100000>;
121 125
122 /* U31 */ 126 /* U31 */
123 expander0: pca9555@21 { 127 expander0: pca9555@21 {
124 compatible = "nxp,pca9555"; 128 compatible = "nxp,pca9555";
125 pinctrl-names = "default"; 129 pinctrl-names = "default";
126 gpio-controller; 130 gpio-controller;
127 #gpio-cells = <2>; 131 #gpio-cells = <2>;
128 reg = <0x21>; 132 reg = <0x21>;
129 }; 133 };
130 134
131 /* U25 */ 135 /* U25 */
132 expander1: pca9555@25 { 136 expander1: pca9555@25 {
133 compatible = "nxp,pca9555"; 137 compatible = "nxp,pca9555";
134 pinctrl-names = "default"; 138 pinctrl-names = "default";
135 gpio-controller; 139 gpio-controller;
136 #gpio-cells = <2>; 140 #gpio-cells = <2>;
137 reg = <0x25>; 141 reg = <0x25>;
138 }; 142 };
139 143
140 }; 144 };
141 145
142 /* CON4 on CP0 expansion */ 146 /* CON4 on CP0 expansion */
143 &cp0_sata0 { 147 &cp0_sata0 {
144 status = "okay"; 148 status = "okay";
145 <<
146 sata-port@0 { <<
147 phys = <&cp0_comphy1 0>; <<
148 phy-names = "cp0-sata0-0-phy"; <<
149 }; <<
150 sata-port@1 { <<
151 phys = <&cp0_comphy3 1>; <<
152 phy-names = "cp0-sata0-1-phy"; <<
153 }; <<
154 }; 149 };
155 150
156 /* CON9 on CP0 expansion */ 151 /* CON9 on CP0 expansion */
157 &cp0_utmi { <<
158 status = "okay"; <<
159 }; <<
160 <<
161 &cp0_usb3_0 { 152 &cp0_usb3_0 {
162 usb-phy = <&cp0_usb3_0_phy>; 153 usb-phy = <&cp0_usb3_0_phy>;
163 phys = <&cp0_utmi0>; <<
164 phy-names = "utmi"; <<
165 dr_mode = "host"; <<
166 status = "okay"; 154 status = "okay";
167 }; 155 };
168 156
169 &cp0_comphy4 { <<
170 cp0_usbh1_con: connector { <<
171 compatible = "usb-a-connector" <<
172 phy-supply = <&cp0_reg_usb3_1_ <<
173 }; <<
174 }; <<
175 <<
176 /* CON10 on CP0 expansion */ 157 /* CON10 on CP0 expansion */
177 &cp0_usb3_1 { 158 &cp0_usb3_1 {
178 phys = <&cp0_comphy4 1>, <&cp0_utmi1>; !! 159 usb-phy = <&cp0_usb3_1_phy>;
179 phy-names = "usb", "utmi"; <<
180 dr_mode = "host"; <<
181 status = "okay"; 160 status = "okay";
182 }; 161 };
183 162
184 &cp0_mdio { 163 &cp0_mdio {
185 status = "okay"; 164 status = "okay";
186 165
187 phy1: ethernet-phy@1 { 166 phy1: ethernet-phy@1 {
188 reg = <1>; 167 reg = <1>;
189 }; 168 };
190 }; 169 };
191 170
192 &cp0_ethernet { 171 &cp0_ethernet {
193 status = "okay"; 172 status = "okay";
194 }; 173 };
195 174
196 &cp0_eth0 { 175 &cp0_eth0 {
197 status = "okay"; 176 status = "okay";
198 phy-mode = "10gbase-r"; !! 177 phy-mode = "10gbase-kr";
199 178
200 fixed-link { 179 fixed-link {
201 speed = <10000>; 180 speed = <10000>;
202 full-duplex; 181 full-duplex;
203 }; 182 };
204 }; 183 };
205 184
206 &cp0_eth2 { 185 &cp0_eth2 {
207 status = "okay"; 186 status = "okay";
208 phy = <&phy1>; 187 phy = <&phy1>;
209 phy-mode = "rgmii-id"; 188 phy-mode = "rgmii-id";
210 }; 189 };
211 190
212 /* CON6 on CP1 expansion */ 191 /* CON6 on CP1 expansion */
213 &cp1_pcie0 { 192 &cp1_pcie0 {
214 phys = <&cp1_comphy0 0>; <<
215 phy-names = "cp1-pcie0-x1-phy"; <<
216 status = "okay"; 193 status = "okay";
217 }; 194 };
218 195
219 /* CON7 on CP1 expansion */ 196 /* CON7 on CP1 expansion */
220 &cp1_pcie1 { 197 &cp1_pcie1 {
221 phys = <&cp1_comphy4 1>; <<
222 phy-names = "cp1-pcie1-x1-phy"; <<
223 status = "okay"; 198 status = "okay";
224 }; 199 };
225 200
226 /* CON5 on CP1 expansion */ 201 /* CON5 on CP1 expansion */
227 &cp1_pcie2 { 202 &cp1_pcie2 {
228 phys = <&cp1_comphy5 2>; <<
229 phy-names = "cp1-pcie2-x1-phy"; <<
230 status = "okay"; 203 status = "okay";
231 }; 204 };
232 205
233 &cp1_i2c0 { 206 &cp1_i2c0 {
234 status = "okay"; 207 status = "okay";
235 clock-frequency = <100000>; 208 clock-frequency = <100000>;
236 }; 209 };
237 210
238 &cp1_spi1 { 211 &cp1_spi1 {
239 status = "okay"; 212 status = "okay";
240 213
241 flash@0 { !! 214 spi-flash@0 {
242 compatible = "jedec,spi-nor"; 215 compatible = "jedec,spi-nor";
243 reg = <0x0>; 216 reg = <0x0>;
244 spi-max-frequency = <20000000> 217 spi-max-frequency = <20000000>;
245 218
246 partitions { 219 partitions {
247 compatible = "fixed-pa 220 compatible = "fixed-partitions";
248 #address-cells = <1>; 221 #address-cells = <1>;
249 #size-cells = <1>; 222 #size-cells = <1>;
250 223
251 partition@0 { 224 partition@0 {
252 label = "Boot" 225 label = "Boot";
253 reg = <0x0 0x2 226 reg = <0x0 0x200000>;
254 }; 227 };
255 partition@200000 { 228 partition@200000 {
256 label = "Files 229 label = "Filesystem";
257 reg = <0x20000 230 reg = <0x200000 0xd00000>;
258 }; 231 };
259 partition@f00000 { 232 partition@f00000 {
260 label = "Boot_ 233 label = "Boot_2nd";
261 reg = <0xf0000 234 reg = <0xf00000 0x100000>;
262 }; 235 };
263 }; 236 };
264 }; 237 };
265 }; 238 };
266 239
267 /* 240 /*
268 * Proper NAND usage will require DPR-76 to be 241 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
269 * MDIO signal of CP1. 242 * MDIO signal of CP1.
270 */ 243 */
271 &cp1_nand_controller { 244 &cp1_nand_controller {
272 pinctrl-0 = <&nand_pins>, <&nand_rb>; 245 pinctrl-0 = <&nand_pins>, <&nand_rb>;
273 pinctrl-names = "default"; 246 pinctrl-names = "default";
274 247
275 nand@0 { 248 nand@0 {
276 reg = <0>; 249 reg = <0>;
277 nand-rb = <0>; 250 nand-rb = <0>;
278 nand-on-flash-bbt; 251 nand-on-flash-bbt;
279 nand-ecc-strength = <4>; 252 nand-ecc-strength = <4>;
280 nand-ecc-step-size = <512>; 253 nand-ecc-step-size = <512>;
281 254
282 partitions { 255 partitions {
283 compatible = "fixed-pa 256 compatible = "fixed-partitions";
284 #address-cells = <1>; 257 #address-cells = <1>;
285 #size-cells = <1>; 258 #size-cells = <1>;
286 259
287 partition@0 { 260 partition@0 {
288 label = "U-Boo 261 label = "U-Boot";
289 reg = <0 0x200 262 reg = <0 0x200000>;
290 }; 263 };
291 partition@200000 { 264 partition@200000 {
292 label = "Linux 265 label = "Linux";
293 reg = <0x20000 266 reg = <0x200000 0xe00000>;
294 }; 267 };
295 partition@1000000 { 268 partition@1000000 {
296 label = "Files 269 label = "Filesystem";
297 reg = <0x10000 270 reg = <0x1000000 0x3f000000>;
298 }; 271 };
299 }; 272 };
300 }; 273 };
301 }; 274 };
302 275
303 /* CON4 on CP1 expansion */ 276 /* CON4 on CP1 expansion */
304 &cp1_sata0 { 277 &cp1_sata0 {
305 status = "okay"; 278 status = "okay";
306 <<
307 sata-port@0 { <<
308 phys = <&cp1_comphy1 0>; <<
309 phy-names = "cp1-sata0-0-phy"; <<
310 }; <<
311 sata-port@1 { <<
312 phys = <&cp1_comphy3 1>; <<
313 phy-names = "cp1-sata0-1-phy"; <<
314 }; <<
315 }; <<
316 <<
317 &cp1_utmi { <<
318 status = "okay"; <<
319 }; 279 };
320 280
321 /* CON9 on CP1 expansion */ 281 /* CON9 on CP1 expansion */
322 &cp1_usb3_0 { 282 &cp1_usb3_0 {
323 usb-phy = <&cp1_usb3_0_phy>; 283 usb-phy = <&cp1_usb3_0_phy>;
324 phys = <&cp1_utmi0>; <<
325 phy-names = "utmi"; <<
326 dr_mode = "host"; <<
327 status = "okay"; 284 status = "okay";
328 }; 285 };
329 286
330 /* CON10 on CP1 expansion */ 287 /* CON10 on CP1 expansion */
331 &cp1_usb3_1 { 288 &cp1_usb3_1 {
332 phys = <&cp1_utmi1>; <<
333 phy-names = "utmi"; <<
334 status = "okay"; 289 status = "okay";
335 }; 290 };
336 291
337 &cp1_mdio { 292 &cp1_mdio {
338 status = "okay"; 293 status = "okay";
339 294
340 phy0: ethernet-phy@0 { 295 phy0: ethernet-phy@0 {
341 reg = <0>; 296 reg = <0>;
342 }; 297 };
343 }; 298 };
344 299
345 &cp1_ethernet { 300 &cp1_ethernet {
346 status = "okay"; 301 status = "okay";
347 }; 302 };
348 303
349 &cp1_eth0 { 304 &cp1_eth0 {
350 status = "okay"; 305 status = "okay";
351 phy-mode = "10gbase-r"; !! 306 phy-mode = "10gbase-kr";
352 307
353 fixed-link { 308 fixed-link {
354 speed = <10000>; 309 speed = <10000>;
355 full-duplex; 310 full-duplex;
356 }; 311 };
357 }; 312 };
358 313
359 &cp1_eth1 { 314 &cp1_eth1 {
360 status = "okay"; 315 status = "okay";
361 phy = <&phy0>; 316 phy = <&phy0>;
362 phy-mode = "rgmii-id"; 317 phy-mode = "rgmii-id";
363 }; 318 };
364 319
365 &ap_sdhci0 { 320 &ap_sdhci0 {
366 status = "okay"; 321 status = "okay";
367 bus-width = <4>; 322 bus-width = <4>;
368 non-removable; 323 non-removable;
369 }; 324 };
370 325
371 &cp0_sdhci0 { 326 &cp0_sdhci0 {
372 status = "okay"; 327 status = "okay";
373 bus-width = <8>; 328 bus-width = <8>;
374 non-removable; 329 non-removable;
375 }; 330 };
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