1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Copyright (C) 2016 Marvell Technology Group 2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 3 *
>> 4 * This file is dual-licensed: you can use it either under the terms
>> 5 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 6 * licensing only applies to this file, and not this project as a
>> 7 * whole.
>> 8 *
>> 9 * a) This library is free software; you can redistribute it and/or
>> 10 * modify it under the terms of the GNU General Public License as
>> 11 * published by the Free Software Foundation; either version 2 of the
>> 12 * License, or (at your option) any later version.
>> 13 *
>> 14 * This library is distributed in the hope that it will be useful,
>> 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 17 * GNU General Public License for more details.
>> 18 *
>> 19 * Or, alternatively,
>> 20 *
>> 21 * b) Permission is hereby granted, free of charge, to any person
>> 22 * obtaining a copy of this software and associated documentation
>> 23 * files (the "Software"), to deal in the Software without
>> 24 * restriction, including without limitation the rights to use,
>> 25 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 26 * sell copies of the Software, and to permit persons to whom the
>> 27 * Software is furnished to do so, subject to the following
>> 28 * conditions:
>> 29 *
>> 30 * The above copyright notice and this permission notice shall be
>> 31 * included in all copies or substantial portions of the Software.
>> 32 *
>> 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 40 * OTHER DEALINGS IN THE SOFTWARE.
>> 41 */
>> 42
>> 43 /*
5 * Device Tree file for Marvell Armada AP806. 44 * Device Tree file for Marvell Armada AP806.
6 */ 45 */
7 46
8 #include "armada-ap806.dtsi" 47 #include "armada-ap806.dtsi"
9 48
10 / { 49 / {
11 model = "Marvell Armada AP806 Quad"; 50 model = "Marvell Armada AP806 Quad";
12 compatible = "marvell,armada-ap806-qua 51 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
13 52
14 cpus { 53 cpus {
15 #address-cells = <1>; 54 #address-cells = <1>;
16 #size-cells = <0>; 55 #size-cells = <0>;
17 56
18 cpu0: cpu@0 { !! 57 cpu@000 {
19 device_type = "cpu"; 58 device_type = "cpu";
20 compatible = "arm,cort !! 59 compatible = "arm,cortex-a72", "arm,armv8";
21 reg = <0x000>; 60 reg = <0x000>;
22 enable-method = "psci" 61 enable-method = "psci";
23 #cooling-cells = <2>; <<
24 clocks = <&cpu_clk 0>; <<
25 i-cache-size = <0xc000 <<
26 i-cache-line-size = <6 <<
27 i-cache-sets = <256>; <<
28 d-cache-size = <0x8000 <<
29 d-cache-line-size = <6 <<
30 d-cache-sets = <256>; <<
31 next-level-cache = <&l <<
32 }; 62 };
33 cpu1: cpu@1 { !! 63 cpu@001 {
34 device_type = "cpu"; 64 device_type = "cpu";
35 compatible = "arm,cort !! 65 compatible = "arm,cortex-a72", "arm,armv8";
36 reg = <0x001>; 66 reg = <0x001>;
37 enable-method = "psci" 67 enable-method = "psci";
38 #cooling-cells = <2>; <<
39 clocks = <&cpu_clk 0>; <<
40 i-cache-size = <0xc000 <<
41 i-cache-line-size = <6 <<
42 i-cache-sets = <256>; <<
43 d-cache-size = <0x8000 <<
44 d-cache-line-size = <6 <<
45 d-cache-sets = <256>; <<
46 next-level-cache = <&l <<
47 }; 68 };
48 cpu2: cpu@100 { !! 69 cpu@100 {
49 device_type = "cpu"; 70 device_type = "cpu";
50 compatible = "arm,cort !! 71 compatible = "arm,cortex-a72", "arm,armv8";
51 reg = <0x100>; 72 reg = <0x100>;
52 enable-method = "psci" 73 enable-method = "psci";
53 #cooling-cells = <2>; <<
54 clocks = <&cpu_clk 1>; <<
55 i-cache-size = <0xc000 <<
56 i-cache-line-size = <6 <<
57 i-cache-sets = <256>; <<
58 d-cache-size = <0x8000 <<
59 d-cache-line-size = <6 <<
60 d-cache-sets = <256>; <<
61 next-level-cache = <&l <<
62 }; 74 };
63 cpu3: cpu@101 { !! 75 cpu@101 {
64 device_type = "cpu"; 76 device_type = "cpu";
65 compatible = "arm,cort !! 77 compatible = "arm,cortex-a72", "arm,armv8";
66 reg = <0x101>; 78 reg = <0x101>;
67 enable-method = "psci" 79 enable-method = "psci";
68 #cooling-cells = <2>; <<
69 clocks = <&cpu_clk 1>; <<
70 i-cache-size = <0xc000 <<
71 i-cache-line-size = <6 <<
72 i-cache-sets = <256>; <<
73 d-cache-size = <0x8000 <<
74 d-cache-line-size = <6 <<
75 d-cache-sets = <256>; <<
76 next-level-cache = <&l <<
77 }; <<
78 <<
79 l2_0: l2-cache0 { <<
80 compatible = "cache"; <<
81 cache-size = <0x80000> <<
82 cache-line-size = <64> <<
83 cache-sets = <512>; <<
84 cache-level = <2>; <<
85 cache-unified; <<
86 }; <<
87 <<
88 l2_1: l2-cache1 { <<
89 compatible = "cache"; <<
90 cache-size = <0x80000> <<
91 cache-line-size = <64> <<
92 cache-sets = <512>; <<
93 cache-level = <2>; <<
94 cache-unified; <<
95 }; 80 };
96 }; 81 };
97 }; 82 };
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