1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2016 Marvell Technology Group 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada AP806. 5 * Device Tree file for Marvell Armada AP806.
6 */ 6 */
7 7
8 #include "armada-ap806.dtsi" 8 #include "armada-ap806.dtsi"
9 9
10 / { 10 / {
11 model = "Marvell Armada AP806 Quad"; 11 model = "Marvell Armada AP806 Quad";
12 compatible = "marvell,armada-ap806-qua 12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
13 13
14 cpus { 14 cpus {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu0: cpu@0 { 18 cpu0: cpu@0 {
19 device_type = "cpu"; 19 device_type = "cpu";
20 compatible = "arm,cort !! 20 compatible = "arm,cortex-a72", "arm,armv8";
21 reg = <0x000>; 21 reg = <0x000>;
22 enable-method = "psci" 22 enable-method = "psci";
23 #cooling-cells = <2>; <<
24 clocks = <&cpu_clk 0>; <<
25 i-cache-size = <0xc000 <<
26 i-cache-line-size = <6 <<
27 i-cache-sets = <256>; <<
28 d-cache-size = <0x8000 <<
29 d-cache-line-size = <6 <<
30 d-cache-sets = <256>; <<
31 next-level-cache = <&l <<
32 }; 23 };
33 cpu1: cpu@1 { 24 cpu1: cpu@1 {
34 device_type = "cpu"; 25 device_type = "cpu";
35 compatible = "arm,cort !! 26 compatible = "arm,cortex-a72", "arm,armv8";
36 reg = <0x001>; 27 reg = <0x001>;
37 enable-method = "psci" 28 enable-method = "psci";
38 #cooling-cells = <2>; <<
39 clocks = <&cpu_clk 0>; <<
40 i-cache-size = <0xc000 <<
41 i-cache-line-size = <6 <<
42 i-cache-sets = <256>; <<
43 d-cache-size = <0x8000 <<
44 d-cache-line-size = <6 <<
45 d-cache-sets = <256>; <<
46 next-level-cache = <&l <<
47 }; 29 };
48 cpu2: cpu@100 { 30 cpu2: cpu@100 {
49 device_type = "cpu"; 31 device_type = "cpu";
50 compatible = "arm,cort !! 32 compatible = "arm,cortex-a72", "arm,armv8";
51 reg = <0x100>; 33 reg = <0x100>;
52 enable-method = "psci" 34 enable-method = "psci";
53 #cooling-cells = <2>; <<
54 clocks = <&cpu_clk 1>; <<
55 i-cache-size = <0xc000 <<
56 i-cache-line-size = <6 <<
57 i-cache-sets = <256>; <<
58 d-cache-size = <0x8000 <<
59 d-cache-line-size = <6 <<
60 d-cache-sets = <256>; <<
61 next-level-cache = <&l <<
62 }; 35 };
63 cpu3: cpu@101 { 36 cpu3: cpu@101 {
64 device_type = "cpu"; 37 device_type = "cpu";
65 compatible = "arm,cort !! 38 compatible = "arm,cortex-a72", "arm,armv8";
66 reg = <0x101>; 39 reg = <0x101>;
67 enable-method = "psci" 40 enable-method = "psci";
68 #cooling-cells = <2>; <<
69 clocks = <&cpu_clk 1>; <<
70 i-cache-size = <0xc000 <<
71 i-cache-line-size = <6 <<
72 i-cache-sets = <256>; <<
73 d-cache-size = <0x8000 <<
74 d-cache-line-size = <6 <<
75 d-cache-sets = <256>; <<
76 next-level-cache = <&l <<
77 }; <<
78 <<
79 l2_0: l2-cache0 { <<
80 compatible = "cache"; <<
81 cache-size = <0x80000> <<
82 cache-line-size = <64> <<
83 cache-sets = <512>; <<
84 cache-level = <2>; <<
85 cache-unified; <<
86 }; <<
87 <<
88 l2_1: l2-cache1 { <<
89 compatible = "cache"; <<
90 cache-size = <0x80000> <<
91 cache-line-size = <64> <<
92 cache-sets = <512>; <<
93 cache-level = <2>; <<
94 cache-unified; <<
95 }; 41 };
96 }; 42 };
97 }; 43 };
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