1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2019 Marvell Technology Group
4 *
5 * Device Tree file for Marvell Armada AP80x.
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/thermal/thermal.h>
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 gpio0 = &ap_gpio;
21 spi0 = &spi0;
22 };
23
24 psci {
25 compatible = "arm,psci-0.2";
26 method = "smc";
27 };
28
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
32 ranges;
33
34 /*
35 * This area matches the mappi
36 * mainline U-Boot, and should
37 * bootloader.
38 */
39
40 psci-area@4000000 {
41 reg = <0x0 0x4000000 0
42 no-map;
43 };
44
45 tee@4400000 {
46 reg = <0 0x4400000 0 0
47 no-map;
48 };
49 };
50
51 AP_NAME {
52 #address-cells = <2>;
53 #size-cells = <2>;
54 compatible = "simple-bus";
55 interrupt-parent = <&gic>;
56 ranges;
57
58 config-space@f0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-b
62 ranges = <0x0 0x0 0xf0
63
64 smmu: iommu@100000 {
65 compatible = "
66 reg = <0x10000
67 dma-coherent;
68 #iommu-cells =
69 #global-interr
70 interrupts = <
71 <
72 <
73 <
74 <
75 <
76 <
77 <
78 <
79 status = "disa
80 };
81
82 gic: interrupt-control
83 compatible = "
84 #interrupt-cel
85 #address-cells
86 #size-cells =
87 ranges;
88 interrupt-cont
89 interrupts = <
90 reg = <0x21000
91 <0x22000
92 <0x24000
93 <0x26000
94
95 gic_v2m0: v2m@
96 compat
97 msi-co
98 reg =
99 arm,ms
100 arm,ms
101 };
102 gic_v2m1: v2m@
103 compat
104 msi-co
105 reg =
106 arm,ms
107 arm,ms
108 };
109 gic_v2m2: v2m@
110 compat
111 msi-co
112 reg =
113 arm,ms
114 arm,ms
115 };
116 gic_v2m3: v2m@
117 compat
118 msi-co
119 reg =
120 arm,ms
121 arm,ms
122 };
123 };
124
125 timer {
126 compatible = "
127 interrupts = <
128 <
129 <
130 <
131 };
132
133 pmu {
134 compatible = "
135 interrupt-pare
136 interrupts = <
137 };
138
139 odmi: odmi@300000 {
140 compatible = "
141 msi-controller
142 marvell,odmi-f
143 reg = <0x30000
144 <0x30400
145 <0x30800
146 <0x30C00
147 marvell,spi-ba
148 };
149
150 gicp: gicp@3f0040 {
151 compatible = "
152 reg = <0x3f004
153 marvell,spi-ra
154 msi-controller
155 };
156
157 pic: interrupt-control
158 compatible = "
159 reg = <0x3f010
160 #interrupt-cel
161 interrupt-cont
162 interrupts = <
163 };
164
165 sei: interrupt-control
166 compatible = "
167 reg = <0x3f020
168 interrupts = <
169 #interrupt-cel
170 interrupt-cont
171 msi-controller
172 };
173
174 xor@400000 {
175 compatible = "
176 reg = <0x40000
177 <0x41000
178 msi-parent = <
179 clocks = <&ap_
180 dma-coherent;
181 };
182
183 xor@420000 {
184 compatible = "
185 reg = <0x42000
186 <0x43000
187 msi-parent = <
188 clocks = <&ap_
189 dma-coherent;
190 };
191
192 xor@440000 {
193 compatible = "
194 reg = <0x44000
195 <0x45000
196 msi-parent = <
197 clocks = <&ap_
198 dma-coherent;
199 };
200
201 xor@460000 {
202 compatible = "
203 reg = <0x46000
204 <0x47000
205 msi-parent = <
206 clocks = <&ap_
207 dma-coherent;
208 };
209
210 spi0: spi@510600 {
211 compatible = "
212 reg = <0x51060
213 #address-cells
214 #size-cells =
215 interrupts = <
216 clocks = <&ap_
217 status = "disa
218 };
219
220 i2c0: i2c@511000 {
221 compatible = "
222 reg = <0x51100
223 #address-cells
224 #size-cells =
225 interrupts = <
226 clocks = <&ap_
227 status = "disa
228 };
229
230 uart0: serial@512000 {
231 compatible = "
232 reg = <0x51200
233 reg-shift = <2
234 interrupts = <
235 reg-io-width =
236 clocks = <&ap_
237 status = "disa
238 };
239
240 uart1: serial@512100 {
241 compatible = "
242 reg = <0x51210
243 reg-shift = <2
244 interrupts = <
245 reg-io-width =
246 clocks = <&ap_
247 status = "disa
248
249 };
250
251 watchdog: watchdog@610
252 compatible = "
253 reg = <0x61000
254 interrupts = <
255 };
256
257 ap_sdhci0: mmc@6e0000
258 compatible = "
259 reg = <0x6e000
260 interrupts = <
261 clock-names =
262 clocks = <&ap_
263 dma-coherent;
264 marvell,xenon-
265 status = "disa
266 };
267
268 ap_syscon0: system-con
269 compatible = "
270 reg = <0x6f400
271
272 ap_pinctrl: pi
273 compat
274
275 uart0_
276
277
278 };
279 };
280
281 ap_gpio: gpio@
282 compat
283 offset
284 ngpios
285 gpio-c
286 #gpio-
287 gpio-r
288 marvel
289 #pwm-c
290 clocks
291 };
292 };
293
294 ap_syscon1: system-con
295 compatible = "
296 reg = <0x6f800
297 #address-cells
298 #size-cells =
299
300 ap_thermal: th
301 compat
302 reg =
303 interr
304 interr
305 #therm
306 };
307 };
308 };
309 };
310
311 /*
312 * The thermal IP features one interna
313 * remote channel wired to one sensor
314 *
315 * Only one thermal zone per AP/CP may
316 * first one that will have a critical
317 */
318 thermal-zones {
319 ap_thermal_ic: ap-ic-thermal {
320 polling-delay-passive
321 polling-delay = <0>; /
322
323 thermal-sensors = <&ap
324
325 trips {
326 ap_crit: ap-cr
327 temper
328 hyster
329 type =
330 };
331 };
332
333 cooling-maps { };
334 };
335
336 ap_thermal_cpu0: ap-cpu0-therm
337 polling-delay-passive
338 polling-delay = <1000>
339
340 thermal-sensors = <&ap
341
342 trips {
343 cpu0_hot: cpu0
344 temper
345 hyster
346 type =
347 };
348 cpu0_emerg: cp
349 temper
350 hyster
351 type =
352 };
353 };
354
355 cooling-maps {
356 map0_hot: map0
357 trip =
358 coolin
359
360 };
361 map0_emerg: ma
362 trip =
363 coolin
364
365 };
366 };
367 };
368
369 ap_thermal_cpu1: ap-cpu1-therm
370 polling-delay-passive
371 polling-delay = <1000>
372
373 thermal-sensors = <&ap
374
375 trips {
376 cpu1_hot: cpu1
377 temper
378 hyster
379 type =
380 };
381 cpu1_emerg: cp
382 temper
383 hyster
384 type =
385 };
386 };
387
388 cooling-maps {
389 map1_hot: map1
390 trip =
391 coolin
392
393 };
394 map1_emerg: ma
395 trip =
396 coolin
397
398 };
399 };
400 };
401
402 ap_thermal_cpu2: ap-cpu2-therm
403 polling-delay-passive
404 polling-delay = <1000>
405
406 thermal-sensors = <&ap
407
408 trips {
409 cpu2_hot: cpu2
410 temper
411 hyster
412 type =
413 };
414 cpu2_emerg: cp
415 temper
416 hyster
417 type =
418 };
419 };
420
421 cooling-maps {
422 map2_hot: map2
423 trip =
424 coolin
425
426 };
427 map2_emerg: ma
428 trip =
429 coolin
430
431 };
432 };
433 };
434
435 ap_thermal_cpu3: ap-cpu3-therm
436 polling-delay-passive
437 polling-delay = <1000>
438
439 thermal-sensors = <&ap
440
441 trips {
442 cpu3_hot: cpu3
443 temper
444 hyster
445 type =
446 };
447 cpu3_emerg: cp
448 temper
449 hyster
450 type =
451 };
452 };
453
454 cooling-maps {
455 map3_hot: map3
456 trip =
457 coolin
458
459 };
460 map3_emerg: ma
461 trip =
462 coolin
463
464 };
465 };
466 };
467 };
468 };
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