1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2019 Marvell Technology Group 3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada AP80x. 5 * Device Tree file for Marvell Armada AP80x.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h> 9 #include <dt-bindings/thermal/thermal.h>
10 10
11 /dts-v1/; 11 /dts-v1/;
12 12
13 / { 13 / {
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 aliases { 17 aliases {
18 serial0 = &uart0; 18 serial0 = &uart0;
19 serial1 = &uart1; 19 serial1 = &uart1;
20 gpio0 = &ap_gpio; 20 gpio0 = &ap_gpio;
21 spi0 = &spi0; 21 spi0 = &spi0;
22 }; 22 };
23 23
24 psci { 24 psci {
25 compatible = "arm,psci-0.2"; 25 compatible = "arm,psci-0.2";
26 method = "smc"; 26 method = "smc";
27 }; 27 };
28 28
29 reserved-memory { 29 reserved-memory {
30 #address-cells = <2>; 30 #address-cells = <2>;
31 #size-cells = <2>; 31 #size-cells = <2>;
32 ranges; 32 ranges;
33 33
34 /* 34 /*
35 * This area matches the mappi 35 * This area matches the mapping done with a
36 * mainline U-Boot, and should 36 * mainline U-Boot, and should be updated by the
37 * bootloader. 37 * bootloader.
38 */ 38 */
39 39
40 psci-area@4000000 { 40 psci-area@4000000 {
41 reg = <0x0 0x4000000 0 41 reg = <0x0 0x4000000 0x0 0x200000>;
42 no-map; 42 no-map;
43 }; 43 };
44 <<
45 tee@4400000 { <<
46 reg = <0 0x4400000 0 0 <<
47 no-map; <<
48 }; <<
49 }; 44 };
50 45
51 AP_NAME { 46 AP_NAME {
52 #address-cells = <2>; 47 #address-cells = <2>;
53 #size-cells = <2>; 48 #size-cells = <2>;
54 compatible = "simple-bus"; 49 compatible = "simple-bus";
55 interrupt-parent = <&gic>; 50 interrupt-parent = <&gic>;
56 ranges; 51 ranges;
57 52
58 config-space@f0000000 { 53 config-space@f0000000 {
59 #address-cells = <1>; 54 #address-cells = <1>;
60 #size-cells = <1>; 55 #size-cells = <1>;
61 compatible = "simple-b 56 compatible = "simple-bus";
62 ranges = <0x0 0x0 0xf0 57 ranges = <0x0 0x0 0xf0000000 0x1000000>;
63 58
64 smmu: iommu@100000 { !! 59 smmu: iommu@5000000 {
65 compatible = " 60 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
66 reg = <0x10000 61 reg = <0x100000 0x100000>;
67 dma-coherent; 62 dma-coherent;
68 #iommu-cells = 63 #iommu-cells = <1>;
69 #global-interr 64 #global-interrupts = <1>;
70 interrupts = < 65 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71 < 66 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72 < 67 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73 < 68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
74 < 69 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
75 < 70 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
76 < 71 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
77 < 72 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78 < 73 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79 status = "disa 74 status = "disabled";
80 }; 75 };
81 76
82 gic: interrupt-control 77 gic: interrupt-controller@210000 {
83 compatible = " 78 compatible = "arm,gic-400";
84 #interrupt-cel 79 #interrupt-cells = <3>;
85 #address-cells 80 #address-cells = <1>;
86 #size-cells = 81 #size-cells = <1>;
87 ranges; 82 ranges;
88 interrupt-cont 83 interrupt-controller;
89 interrupts = < 84 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 reg = <0x21000 85 reg = <0x210000 0x10000>,
91 <0x22000 86 <0x220000 0x20000>,
92 <0x24000 87 <0x240000 0x20000>,
93 <0x26000 88 <0x260000 0x20000>;
94 89
95 gic_v2m0: v2m@ 90 gic_v2m0: v2m@280000 {
96 compat 91 compatible = "arm,gic-v2m-frame";
97 msi-co 92 msi-controller;
98 reg = 93 reg = <0x280000 0x1000>;
99 arm,ms 94 arm,msi-base-spi = <160>;
100 arm,ms 95 arm,msi-num-spis = <32>;
101 }; 96 };
102 gic_v2m1: v2m@ 97 gic_v2m1: v2m@290000 {
103 compat 98 compatible = "arm,gic-v2m-frame";
104 msi-co 99 msi-controller;
105 reg = 100 reg = <0x290000 0x1000>;
106 arm,ms 101 arm,msi-base-spi = <192>;
107 arm,ms 102 arm,msi-num-spis = <32>;
108 }; 103 };
109 gic_v2m2: v2m@ 104 gic_v2m2: v2m@2a0000 {
110 compat 105 compatible = "arm,gic-v2m-frame";
111 msi-co 106 msi-controller;
112 reg = 107 reg = <0x2a0000 0x1000>;
113 arm,ms 108 arm,msi-base-spi = <224>;
114 arm,ms 109 arm,msi-num-spis = <32>;
115 }; 110 };
116 gic_v2m3: v2m@ 111 gic_v2m3: v2m@2b0000 {
117 compat 112 compatible = "arm,gic-v2m-frame";
118 msi-co 113 msi-controller;
119 reg = 114 reg = <0x2b0000 0x1000>;
120 arm,ms 115 arm,msi-base-spi = <256>;
121 arm,ms 116 arm,msi-num-spis = <32>;
122 }; 117 };
123 }; 118 };
124 119
125 timer { 120 timer {
126 compatible = " 121 compatible = "arm,armv8-timer";
127 interrupts = < 122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 < 123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129 < 124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
130 < 125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
131 }; 126 };
132 127
133 pmu { 128 pmu {
134 compatible = " 129 compatible = "arm,cortex-a72-pmu";
135 interrupt-pare 130 interrupt-parent = <&pic>;
136 interrupts = < 131 interrupts = <17>;
137 }; 132 };
138 133
139 odmi: odmi@300000 { 134 odmi: odmi@300000 {
140 compatible = " 135 compatible = "marvell,odmi-controller";
>> 136 interrupt-controller;
141 msi-controller 137 msi-controller;
142 marvell,odmi-f 138 marvell,odmi-frames = <4>;
143 reg = <0x30000 139 reg = <0x300000 0x4000>,
144 <0x30400 140 <0x304000 0x4000>,
145 <0x30800 141 <0x308000 0x4000>,
146 <0x30C00 142 <0x30C000 0x4000>;
147 marvell,spi-ba 143 marvell,spi-base = <128>, <136>, <144>, <152>;
148 }; 144 };
149 145
150 gicp: gicp@3f0040 { 146 gicp: gicp@3f0040 {
151 compatible = " 147 compatible = "marvell,ap806-gicp";
152 reg = <0x3f004 148 reg = <0x3f0040 0x10>;
153 marvell,spi-ra 149 marvell,spi-ranges = <64 64>, <288 64>;
154 msi-controller 150 msi-controller;
155 }; 151 };
156 152
157 pic: interrupt-control 153 pic: interrupt-controller@3f0100 {
158 compatible = " 154 compatible = "marvell,armada-8k-pic";
159 reg = <0x3f010 155 reg = <0x3f0100 0x10>;
160 #interrupt-cel 156 #interrupt-cells = <1>;
161 interrupt-cont 157 interrupt-controller;
162 interrupts = < 158 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
163 }; 159 };
164 160
165 sei: interrupt-control 161 sei: interrupt-controller@3f0200 {
166 compatible = " 162 compatible = "marvell,ap806-sei";
167 reg = <0x3f020 163 reg = <0x3f0200 0x40>;
168 interrupts = < 164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
169 #interrupt-cel 165 #interrupt-cells = <1>;
170 interrupt-cont 166 interrupt-controller;
171 msi-controller 167 msi-controller;
172 }; 168 };
173 169
174 xor@400000 { 170 xor@400000 {
175 compatible = " 171 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
176 reg = <0x40000 172 reg = <0x400000 0x1000>,
177 <0x41000 173 <0x410000 0x1000>;
178 msi-parent = < 174 msi-parent = <&gic_v2m0>;
179 clocks = <&ap_ 175 clocks = <&ap_clk 3>;
180 dma-coherent; 176 dma-coherent;
181 }; 177 };
182 178
183 xor@420000 { 179 xor@420000 {
184 compatible = " 180 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
185 reg = <0x42000 181 reg = <0x420000 0x1000>,
186 <0x43000 182 <0x430000 0x1000>;
187 msi-parent = < 183 msi-parent = <&gic_v2m0>;
188 clocks = <&ap_ 184 clocks = <&ap_clk 3>;
189 dma-coherent; 185 dma-coherent;
190 }; 186 };
191 187
192 xor@440000 { 188 xor@440000 {
193 compatible = " 189 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
194 reg = <0x44000 190 reg = <0x440000 0x1000>,
195 <0x45000 191 <0x450000 0x1000>;
196 msi-parent = < 192 msi-parent = <&gic_v2m0>;
197 clocks = <&ap_ 193 clocks = <&ap_clk 3>;
198 dma-coherent; 194 dma-coherent;
199 }; 195 };
200 196
201 xor@460000 { 197 xor@460000 {
202 compatible = " 198 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
203 reg = <0x46000 199 reg = <0x460000 0x1000>,
204 <0x47000 200 <0x470000 0x1000>;
205 msi-parent = < 201 msi-parent = <&gic_v2m0>;
206 clocks = <&ap_ 202 clocks = <&ap_clk 3>;
207 dma-coherent; 203 dma-coherent;
208 }; 204 };
209 205
210 spi0: spi@510600 { 206 spi0: spi@510600 {
211 compatible = " 207 compatible = "marvell,armada-380-spi";
212 reg = <0x51060 208 reg = <0x510600 0x50>;
213 #address-cells 209 #address-cells = <1>;
214 #size-cells = 210 #size-cells = <0>;
215 interrupts = < 211 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&ap_ 212 clocks = <&ap_clk 3>;
217 status = "disa 213 status = "disabled";
218 }; 214 };
219 215
220 i2c0: i2c@511000 { 216 i2c0: i2c@511000 {
221 compatible = " 217 compatible = "marvell,mv78230-i2c";
222 reg = <0x51100 218 reg = <0x511000 0x20>;
223 #address-cells 219 #address-cells = <1>;
224 #size-cells = 220 #size-cells = <0>;
225 interrupts = < 221 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&ap_ 222 clocks = <&ap_clk 3>;
227 status = "disa 223 status = "disabled";
228 }; 224 };
229 225
230 uart0: serial@512000 { 226 uart0: serial@512000 {
231 compatible = " 227 compatible = "snps,dw-apb-uart";
232 reg = <0x51200 228 reg = <0x512000 0x100>;
233 reg-shift = <2 229 reg-shift = <2>;
234 interrupts = < 230 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
235 reg-io-width = 231 reg-io-width = <1>;
236 clocks = <&ap_ 232 clocks = <&ap_clk 3>;
237 status = "disa 233 status = "disabled";
238 }; 234 };
239 235
240 uart1: serial@512100 { 236 uart1: serial@512100 {
241 compatible = " 237 compatible = "snps,dw-apb-uart";
242 reg = <0x51210 238 reg = <0x512100 0x100>;
243 reg-shift = <2 239 reg-shift = <2>;
244 interrupts = < 240 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 reg-io-width = 241 reg-io-width = <1>;
246 clocks = <&ap_ 242 clocks = <&ap_clk 3>;
247 status = "disa 243 status = "disabled";
248 244
249 }; 245 };
250 246
251 watchdog: watchdog@610 247 watchdog: watchdog@610000 {
252 compatible = " 248 compatible = "arm,sbsa-gwdt";
253 reg = <0x61000 249 reg = <0x610000 0x1000>, <0x600000 0x1000>;
254 interrupts = < 250 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
255 }; 251 };
256 252
257 ap_sdhci0: mmc@6e0000 !! 253 ap_sdhci0: sdhci@6e0000 {
258 compatible = " 254 compatible = "marvell,armada-ap806-sdhci";
259 reg = <0x6e000 255 reg = <0x6e0000 0x300>;
260 interrupts = < 256 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261 clock-names = 257 clock-names = "core";
262 clocks = <&ap_ 258 clocks = <&ap_clk 4>;
263 dma-coherent; 259 dma-coherent;
264 marvell,xenon- 260 marvell,xenon-phy-slow-mode;
265 status = "disa 261 status = "disabled";
266 }; 262 };
267 263
268 ap_syscon0: system-con 264 ap_syscon0: system-controller@6f4000 {
269 compatible = " 265 compatible = "syscon", "simple-mfd";
270 reg = <0x6f400 266 reg = <0x6f4000 0x2000>;
271 267
272 ap_pinctrl: pi 268 ap_pinctrl: pinctrl {
273 compat 269 compatible = "marvell,ap806-pinctrl";
274 270
275 uart0_ 271 uart0_pins: uart0-pins {
276 272 marvell,pins = "mpp11", "mpp19";
277 273 marvell,function = "uart0";
278 }; 274 };
279 }; 275 };
280 276
281 ap_gpio: gpio@ 277 ap_gpio: gpio@1040 {
282 compat 278 compatible = "marvell,armada-8k-gpio";
283 offset 279 offset = <0x1040>;
284 ngpios 280 ngpios = <20>;
285 gpio-c 281 gpio-controller;
286 #gpio- 282 #gpio-cells = <2>;
287 gpio-r 283 gpio-ranges = <&ap_pinctrl 0 0 20>;
288 marvel <<
289 #pwm-c <<
290 clocks <<
291 }; 284 };
292 }; 285 };
293 286
294 ap_syscon1: system-con 287 ap_syscon1: system-controller@6f8000 {
295 compatible = " 288 compatible = "syscon", "simple-mfd";
296 reg = <0x6f800 289 reg = <0x6f8000 0x1000>;
297 #address-cells 290 #address-cells = <1>;
298 #size-cells = 291 #size-cells = <1>;
299 292
300 ap_thermal: th 293 ap_thermal: thermal-sensor@80 {
301 compat 294 compatible = "marvell,armada-ap806-thermal";
302 reg = 295 reg = <0x80 0x10>;
303 interr 296 interrupt-parent = <&sei>;
304 interr 297 interrupts = <18>;
305 #therm 298 #thermal-sensor-cells = <1>;
306 }; 299 };
307 }; 300 };
308 }; 301 };
309 }; 302 };
310 303
311 /* 304 /*
312 * The thermal IP features one interna 305 * The thermal IP features one internal sensor plus, if applicable, one
313 * remote channel wired to one sensor 306 * remote channel wired to one sensor per CPU.
314 * 307 *
315 * Only one thermal zone per AP/CP may 308 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
316 * first one that will have a critical 309 * first one that will have a critical trip point will be chosen.
317 */ 310 */
318 thermal-zones { 311 thermal-zones {
319 ap_thermal_ic: ap-ic-thermal { !! 312 ap_thermal_ic: ap-thermal-ic {
320 polling-delay-passive 313 polling-delay-passive = <0>; /* Interrupt driven */
321 polling-delay = <0>; / 314 polling-delay = <0>; /* Interrupt driven */
322 315
323 thermal-sensors = <&ap 316 thermal-sensors = <&ap_thermal 0>;
324 317
325 trips { 318 trips {
326 ap_crit: ap-cr 319 ap_crit: ap-crit {
327 temper 320 temperature = <100000>; /* mC degrees */
328 hyster 321 hysteresis = <2000>; /* mC degrees */
329 type = 322 type = "critical";
330 }; 323 };
331 }; 324 };
332 325
333 cooling-maps { }; 326 cooling-maps { };
334 }; 327 };
335 328
336 ap_thermal_cpu0: ap-cpu0-therm !! 329 ap_thermal_cpu0: ap-thermal-cpu0 {
337 polling-delay-passive 330 polling-delay-passive = <1000>;
338 polling-delay = <1000> 331 polling-delay = <1000>;
339 332
340 thermal-sensors = <&ap 333 thermal-sensors = <&ap_thermal 1>;
341 334
342 trips { 335 trips {
343 cpu0_hot: cpu0 336 cpu0_hot: cpu0-hot {
344 temper 337 temperature = <85000>;
345 hyster 338 hysteresis = <2000>;
346 type = 339 type = "passive";
347 }; 340 };
348 cpu0_emerg: cp 341 cpu0_emerg: cpu0-emerg {
349 temper 342 temperature = <95000>;
350 hyster 343 hysteresis = <2000>;
351 type = 344 type = "passive";
352 }; 345 };
353 }; 346 };
354 347
355 cooling-maps { 348 cooling-maps {
356 map0_hot: map0 349 map0_hot: map0-hot {
357 trip = 350 trip = <&cpu0_hot>;
358 coolin 351 cooling-device = <&cpu0 1 2>,
359 352 <&cpu1 1 2>;
360 }; 353 };
361 map0_emerg: ma 354 map0_emerg: map0-ermerg {
362 trip = 355 trip = <&cpu0_emerg>;
363 coolin 356 cooling-device = <&cpu0 3 3>,
364 357 <&cpu1 3 3>;
365 }; 358 };
366 }; 359 };
367 }; 360 };
368 361
369 ap_thermal_cpu1: ap-cpu1-therm !! 362 ap_thermal_cpu1: ap-thermal-cpu1 {
370 polling-delay-passive 363 polling-delay-passive = <1000>;
371 polling-delay = <1000> 364 polling-delay = <1000>;
372 365
373 thermal-sensors = <&ap 366 thermal-sensors = <&ap_thermal 2>;
374 367
375 trips { 368 trips {
376 cpu1_hot: cpu1 369 cpu1_hot: cpu1-hot {
377 temper 370 temperature = <85000>;
378 hyster 371 hysteresis = <2000>;
379 type = 372 type = "passive";
380 }; 373 };
381 cpu1_emerg: cp 374 cpu1_emerg: cpu1-emerg {
382 temper 375 temperature = <95000>;
383 hyster 376 hysteresis = <2000>;
384 type = 377 type = "passive";
385 }; 378 };
386 }; 379 };
387 380
388 cooling-maps { 381 cooling-maps {
389 map1_hot: map1 382 map1_hot: map1-hot {
390 trip = 383 trip = <&cpu1_hot>;
391 coolin 384 cooling-device = <&cpu0 1 2>,
392 385 <&cpu1 1 2>;
393 }; 386 };
394 map1_emerg: ma 387 map1_emerg: map1-emerg {
395 trip = 388 trip = <&cpu1_emerg>;
396 coolin 389 cooling-device = <&cpu0 3 3>,
397 390 <&cpu1 3 3>;
398 }; 391 };
399 }; 392 };
400 }; 393 };
401 394
402 ap_thermal_cpu2: ap-cpu2-therm !! 395 ap_thermal_cpu2: ap-thermal-cpu2 {
403 polling-delay-passive 396 polling-delay-passive = <1000>;
404 polling-delay = <1000> 397 polling-delay = <1000>;
405 398
406 thermal-sensors = <&ap 399 thermal-sensors = <&ap_thermal 3>;
407 400
408 trips { 401 trips {
409 cpu2_hot: cpu2 402 cpu2_hot: cpu2-hot {
410 temper 403 temperature = <85000>;
411 hyster 404 hysteresis = <2000>;
412 type = 405 type = "passive";
413 }; 406 };
414 cpu2_emerg: cp 407 cpu2_emerg: cpu2-emerg {
415 temper 408 temperature = <95000>;
416 hyster 409 hysteresis = <2000>;
417 type = 410 type = "passive";
418 }; 411 };
419 }; 412 };
420 413
421 cooling-maps { 414 cooling-maps {
422 map2_hot: map2 415 map2_hot: map2-hot {
423 trip = 416 trip = <&cpu2_hot>;
424 coolin 417 cooling-device = <&cpu2 1 2>,
425 418 <&cpu3 1 2>;
426 }; 419 };
427 map2_emerg: ma 420 map2_emerg: map2-emerg {
428 trip = 421 trip = <&cpu2_emerg>;
429 coolin 422 cooling-device = <&cpu2 3 3>,
430 423 <&cpu3 3 3>;
431 }; 424 };
432 }; 425 };
433 }; 426 };
434 427
435 ap_thermal_cpu3: ap-cpu3-therm !! 428 ap_thermal_cpu3: ap-thermal-cpu3 {
436 polling-delay-passive 429 polling-delay-passive = <1000>;
437 polling-delay = <1000> 430 polling-delay = <1000>;
438 431
439 thermal-sensors = <&ap 432 thermal-sensors = <&ap_thermal 4>;
440 433
441 trips { 434 trips {
442 cpu3_hot: cpu3 435 cpu3_hot: cpu3-hot {
443 temper 436 temperature = <85000>;
444 hyster 437 hysteresis = <2000>;
445 type = 438 type = "passive";
446 }; 439 };
447 cpu3_emerg: cp 440 cpu3_emerg: cpu3-emerg {
448 temper 441 temperature = <95000>;
449 hyster 442 hysteresis = <2000>;
450 type = 443 type = "passive";
451 }; 444 };
452 }; 445 };
453 446
454 cooling-maps { 447 cooling-maps {
455 map3_hot: map3 448 map3_hot: map3-bhot {
456 trip = 449 trip = <&cpu3_hot>;
457 coolin 450 cooling-device = <&cpu2 1 2>,
458 451 <&cpu3 1 2>;
459 }; 452 };
460 map3_emerg: ma 453 map3_emerg: map3-emerg {
461 trip = 454 trip = <&cpu3_emerg>;
462 coolin 455 cooling-device = <&cpu2 3 3>,
463 456 <&cpu3 3 3>;
464 }; 457 };
465 }; 458 };
466 }; 459 };
467 }; 460 };
468 }; 461 };
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