1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2019 Marvell Technology Group 3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada AP80x. 5 * Device Tree file for Marvell Armada AP80x.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h> 9 #include <dt-bindings/thermal/thermal.h>
10 10
11 /dts-v1/; 11 /dts-v1/;
12 12
13 / { 13 / {
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 aliases { 17 aliases {
18 serial0 = &uart0; 18 serial0 = &uart0;
19 serial1 = &uart1; 19 serial1 = &uart1;
20 gpio0 = &ap_gpio; 20 gpio0 = &ap_gpio;
21 spi0 = &spi0; 21 spi0 = &spi0;
22 }; 22 };
23 23
24 psci { 24 psci {
25 compatible = "arm,psci-0.2"; 25 compatible = "arm,psci-0.2";
26 method = "smc"; 26 method = "smc";
27 }; 27 };
28 28
29 reserved-memory { 29 reserved-memory {
30 #address-cells = <2>; 30 #address-cells = <2>;
31 #size-cells = <2>; 31 #size-cells = <2>;
32 ranges; 32 ranges;
33 33
34 /* 34 /*
35 * This area matches the mappi 35 * This area matches the mapping done with a
36 * mainline U-Boot, and should 36 * mainline U-Boot, and should be updated by the
37 * bootloader. 37 * bootloader.
38 */ 38 */
39 39
40 psci-area@4000000 { 40 psci-area@4000000 {
41 reg = <0x0 0x4000000 0 41 reg = <0x0 0x4000000 0x0 0x200000>;
42 no-map; 42 no-map;
43 }; 43 };
44 44
45 tee@4400000 { 45 tee@4400000 {
46 reg = <0 0x4400000 0 0 46 reg = <0 0x4400000 0 0x1000000>;
47 no-map; 47 no-map;
48 }; 48 };
49 }; 49 };
50 50
51 AP_NAME { 51 AP_NAME {
52 #address-cells = <2>; 52 #address-cells = <2>;
53 #size-cells = <2>; 53 #size-cells = <2>;
54 compatible = "simple-bus"; 54 compatible = "simple-bus";
55 interrupt-parent = <&gic>; 55 interrupt-parent = <&gic>;
56 ranges; 56 ranges;
57 57
58 config-space@f0000000 { 58 config-space@f0000000 {
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <1>; 60 #size-cells = <1>;
61 compatible = "simple-b 61 compatible = "simple-bus";
62 ranges = <0x0 0x0 0xf0 62 ranges = <0x0 0x0 0xf0000000 0x1000000>;
63 63
64 smmu: iommu@100000 { !! 64 smmu: iommu@5000000 {
65 compatible = " 65 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
66 reg = <0x10000 66 reg = <0x100000 0x100000>;
67 dma-coherent; 67 dma-coherent;
68 #iommu-cells = 68 #iommu-cells = <1>;
69 #global-interr 69 #global-interrupts = <1>;
70 interrupts = < 70 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71 < 71 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72 < 72 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73 < 73 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
74 < 74 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
75 < 75 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
76 < 76 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
77 < 77 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78 < 78 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79 status = "disa 79 status = "disabled";
80 }; 80 };
81 81
82 gic: interrupt-control 82 gic: interrupt-controller@210000 {
83 compatible = " 83 compatible = "arm,gic-400";
84 #interrupt-cel 84 #interrupt-cells = <3>;
85 #address-cells 85 #address-cells = <1>;
86 #size-cells = 86 #size-cells = <1>;
87 ranges; 87 ranges;
88 interrupt-cont 88 interrupt-controller;
89 interrupts = < 89 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 reg = <0x21000 90 reg = <0x210000 0x10000>,
91 <0x22000 91 <0x220000 0x20000>,
92 <0x24000 92 <0x240000 0x20000>,
93 <0x26000 93 <0x260000 0x20000>;
94 94
95 gic_v2m0: v2m@ 95 gic_v2m0: v2m@280000 {
96 compat 96 compatible = "arm,gic-v2m-frame";
97 msi-co 97 msi-controller;
98 reg = 98 reg = <0x280000 0x1000>;
99 arm,ms 99 arm,msi-base-spi = <160>;
100 arm,ms 100 arm,msi-num-spis = <32>;
101 }; 101 };
102 gic_v2m1: v2m@ 102 gic_v2m1: v2m@290000 {
103 compat 103 compatible = "arm,gic-v2m-frame";
104 msi-co 104 msi-controller;
105 reg = 105 reg = <0x290000 0x1000>;
106 arm,ms 106 arm,msi-base-spi = <192>;
107 arm,ms 107 arm,msi-num-spis = <32>;
108 }; 108 };
109 gic_v2m2: v2m@ 109 gic_v2m2: v2m@2a0000 {
110 compat 110 compatible = "arm,gic-v2m-frame";
111 msi-co 111 msi-controller;
112 reg = 112 reg = <0x2a0000 0x1000>;
113 arm,ms 113 arm,msi-base-spi = <224>;
114 arm,ms 114 arm,msi-num-spis = <32>;
115 }; 115 };
116 gic_v2m3: v2m@ 116 gic_v2m3: v2m@2b0000 {
117 compat 117 compatible = "arm,gic-v2m-frame";
118 msi-co 118 msi-controller;
119 reg = 119 reg = <0x2b0000 0x1000>;
120 arm,ms 120 arm,msi-base-spi = <256>;
121 arm,ms 121 arm,msi-num-spis = <32>;
122 }; 122 };
123 }; 123 };
124 124
125 timer { 125 timer {
126 compatible = " 126 compatible = "arm,armv8-timer";
127 interrupts = < 127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 < 128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129 < 129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
130 < 130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
131 }; 131 };
132 132
133 pmu { 133 pmu {
134 compatible = " 134 compatible = "arm,cortex-a72-pmu";
135 interrupt-pare 135 interrupt-parent = <&pic>;
136 interrupts = < 136 interrupts = <17>;
137 }; 137 };
138 138
139 odmi: odmi@300000 { 139 odmi: odmi@300000 {
140 compatible = " 140 compatible = "marvell,odmi-controller";
>> 141 interrupt-controller;
141 msi-controller 142 msi-controller;
142 marvell,odmi-f 143 marvell,odmi-frames = <4>;
143 reg = <0x30000 144 reg = <0x300000 0x4000>,
144 <0x30400 145 <0x304000 0x4000>,
145 <0x30800 146 <0x308000 0x4000>,
146 <0x30C00 147 <0x30C000 0x4000>;
147 marvell,spi-ba 148 marvell,spi-base = <128>, <136>, <144>, <152>;
148 }; 149 };
149 150
150 gicp: gicp@3f0040 { 151 gicp: gicp@3f0040 {
151 compatible = " 152 compatible = "marvell,ap806-gicp";
152 reg = <0x3f004 153 reg = <0x3f0040 0x10>;
153 marvell,spi-ra 154 marvell,spi-ranges = <64 64>, <288 64>;
154 msi-controller 155 msi-controller;
155 }; 156 };
156 157
157 pic: interrupt-control 158 pic: interrupt-controller@3f0100 {
158 compatible = " 159 compatible = "marvell,armada-8k-pic";
159 reg = <0x3f010 160 reg = <0x3f0100 0x10>;
160 #interrupt-cel 161 #interrupt-cells = <1>;
161 interrupt-cont 162 interrupt-controller;
162 interrupts = < 163 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
163 }; 164 };
164 165
165 sei: interrupt-control 166 sei: interrupt-controller@3f0200 {
166 compatible = " 167 compatible = "marvell,ap806-sei";
167 reg = <0x3f020 168 reg = <0x3f0200 0x40>;
168 interrupts = < 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
169 #interrupt-cel 170 #interrupt-cells = <1>;
170 interrupt-cont 171 interrupt-controller;
171 msi-controller 172 msi-controller;
172 }; 173 };
173 174
174 xor@400000 { 175 xor@400000 {
175 compatible = " 176 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
176 reg = <0x40000 177 reg = <0x400000 0x1000>,
177 <0x41000 178 <0x410000 0x1000>;
178 msi-parent = < 179 msi-parent = <&gic_v2m0>;
179 clocks = <&ap_ 180 clocks = <&ap_clk 3>;
180 dma-coherent; 181 dma-coherent;
181 }; 182 };
182 183
183 xor@420000 { 184 xor@420000 {
184 compatible = " 185 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
185 reg = <0x42000 186 reg = <0x420000 0x1000>,
186 <0x43000 187 <0x430000 0x1000>;
187 msi-parent = < 188 msi-parent = <&gic_v2m0>;
188 clocks = <&ap_ 189 clocks = <&ap_clk 3>;
189 dma-coherent; 190 dma-coherent;
190 }; 191 };
191 192
192 xor@440000 { 193 xor@440000 {
193 compatible = " 194 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
194 reg = <0x44000 195 reg = <0x440000 0x1000>,
195 <0x45000 196 <0x450000 0x1000>;
196 msi-parent = < 197 msi-parent = <&gic_v2m0>;
197 clocks = <&ap_ 198 clocks = <&ap_clk 3>;
198 dma-coherent; 199 dma-coherent;
199 }; 200 };
200 201
201 xor@460000 { 202 xor@460000 {
202 compatible = " 203 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
203 reg = <0x46000 204 reg = <0x460000 0x1000>,
204 <0x47000 205 <0x470000 0x1000>;
205 msi-parent = < 206 msi-parent = <&gic_v2m0>;
206 clocks = <&ap_ 207 clocks = <&ap_clk 3>;
207 dma-coherent; 208 dma-coherent;
208 }; 209 };
209 210
210 spi0: spi@510600 { 211 spi0: spi@510600 {
211 compatible = " 212 compatible = "marvell,armada-380-spi";
212 reg = <0x51060 213 reg = <0x510600 0x50>;
213 #address-cells 214 #address-cells = <1>;
214 #size-cells = 215 #size-cells = <0>;
215 interrupts = < 216 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&ap_ 217 clocks = <&ap_clk 3>;
217 status = "disa 218 status = "disabled";
218 }; 219 };
219 220
220 i2c0: i2c@511000 { 221 i2c0: i2c@511000 {
221 compatible = " 222 compatible = "marvell,mv78230-i2c";
222 reg = <0x51100 223 reg = <0x511000 0x20>;
223 #address-cells 224 #address-cells = <1>;
224 #size-cells = 225 #size-cells = <0>;
225 interrupts = < 226 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&ap_ 227 clocks = <&ap_clk 3>;
227 status = "disa 228 status = "disabled";
228 }; 229 };
229 230
230 uart0: serial@512000 { 231 uart0: serial@512000 {
231 compatible = " 232 compatible = "snps,dw-apb-uart";
232 reg = <0x51200 233 reg = <0x512000 0x100>;
233 reg-shift = <2 234 reg-shift = <2>;
234 interrupts = < 235 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
235 reg-io-width = 236 reg-io-width = <1>;
236 clocks = <&ap_ 237 clocks = <&ap_clk 3>;
237 status = "disa 238 status = "disabled";
238 }; 239 };
239 240
240 uart1: serial@512100 { 241 uart1: serial@512100 {
241 compatible = " 242 compatible = "snps,dw-apb-uart";
242 reg = <0x51210 243 reg = <0x512100 0x100>;
243 reg-shift = <2 244 reg-shift = <2>;
244 interrupts = < 245 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 reg-io-width = 246 reg-io-width = <1>;
246 clocks = <&ap_ 247 clocks = <&ap_clk 3>;
247 status = "disa 248 status = "disabled";
248 249
249 }; 250 };
250 251
251 watchdog: watchdog@610 252 watchdog: watchdog@610000 {
252 compatible = " 253 compatible = "arm,sbsa-gwdt";
253 reg = <0x61000 254 reg = <0x610000 0x1000>, <0x600000 0x1000>;
254 interrupts = < 255 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
255 }; 256 };
256 257
257 ap_sdhci0: mmc@6e0000 258 ap_sdhci0: mmc@6e0000 {
258 compatible = " 259 compatible = "marvell,armada-ap806-sdhci";
259 reg = <0x6e000 260 reg = <0x6e0000 0x300>;
260 interrupts = < 261 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261 clock-names = 262 clock-names = "core";
262 clocks = <&ap_ 263 clocks = <&ap_clk 4>;
263 dma-coherent; 264 dma-coherent;
264 marvell,xenon- 265 marvell,xenon-phy-slow-mode;
265 status = "disa 266 status = "disabled";
266 }; 267 };
267 268
268 ap_syscon0: system-con 269 ap_syscon0: system-controller@6f4000 {
269 compatible = " 270 compatible = "syscon", "simple-mfd";
270 reg = <0x6f400 271 reg = <0x6f4000 0x2000>;
271 272
272 ap_pinctrl: pi 273 ap_pinctrl: pinctrl {
273 compat 274 compatible = "marvell,ap806-pinctrl";
274 275
275 uart0_ 276 uart0_pins: uart0-pins {
276 277 marvell,pins = "mpp11", "mpp19";
277 278 marvell,function = "uart0";
278 }; 279 };
279 }; 280 };
280 281
281 ap_gpio: gpio@ 282 ap_gpio: gpio@1040 {
282 compat 283 compatible = "marvell,armada-8k-gpio";
283 offset 284 offset = <0x1040>;
284 ngpios 285 ngpios = <20>;
285 gpio-c 286 gpio-controller;
286 #gpio- 287 #gpio-cells = <2>;
287 gpio-r 288 gpio-ranges = <&ap_pinctrl 0 0 20>;
288 marvel 289 marvell,pwm-offset = <0x10c0>;
289 #pwm-c 290 #pwm-cells = <2>;
290 clocks 291 clocks = <&ap_clk 3>;
291 }; 292 };
292 }; 293 };
293 294
294 ap_syscon1: system-con 295 ap_syscon1: system-controller@6f8000 {
295 compatible = " 296 compatible = "syscon", "simple-mfd";
296 reg = <0x6f800 297 reg = <0x6f8000 0x1000>;
297 #address-cells 298 #address-cells = <1>;
298 #size-cells = 299 #size-cells = <1>;
299 300
300 ap_thermal: th 301 ap_thermal: thermal-sensor@80 {
301 compat 302 compatible = "marvell,armada-ap806-thermal";
302 reg = 303 reg = <0x80 0x10>;
303 interr 304 interrupt-parent = <&sei>;
304 interr 305 interrupts = <18>;
305 #therm 306 #thermal-sensor-cells = <1>;
306 }; 307 };
307 }; 308 };
308 }; 309 };
309 }; 310 };
310 311
311 /* 312 /*
312 * The thermal IP features one interna 313 * The thermal IP features one internal sensor plus, if applicable, one
313 * remote channel wired to one sensor 314 * remote channel wired to one sensor per CPU.
314 * 315 *
315 * Only one thermal zone per AP/CP may 316 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
316 * first one that will have a critical 317 * first one that will have a critical trip point will be chosen.
317 */ 318 */
318 thermal-zones { 319 thermal-zones {
319 ap_thermal_ic: ap-ic-thermal { 320 ap_thermal_ic: ap-ic-thermal {
320 polling-delay-passive 321 polling-delay-passive = <0>; /* Interrupt driven */
321 polling-delay = <0>; / 322 polling-delay = <0>; /* Interrupt driven */
322 323
323 thermal-sensors = <&ap 324 thermal-sensors = <&ap_thermal 0>;
324 325
325 trips { 326 trips {
326 ap_crit: ap-cr 327 ap_crit: ap-crit {
327 temper 328 temperature = <100000>; /* mC degrees */
328 hyster 329 hysteresis = <2000>; /* mC degrees */
329 type = 330 type = "critical";
330 }; 331 };
331 }; 332 };
332 333
333 cooling-maps { }; 334 cooling-maps { };
334 }; 335 };
335 336
336 ap_thermal_cpu0: ap-cpu0-therm 337 ap_thermal_cpu0: ap-cpu0-thermal {
337 polling-delay-passive 338 polling-delay-passive = <1000>;
338 polling-delay = <1000> 339 polling-delay = <1000>;
339 340
340 thermal-sensors = <&ap 341 thermal-sensors = <&ap_thermal 1>;
341 342
342 trips { 343 trips {
343 cpu0_hot: cpu0 344 cpu0_hot: cpu0-hot {
344 temper 345 temperature = <85000>;
345 hyster 346 hysteresis = <2000>;
346 type = 347 type = "passive";
347 }; 348 };
348 cpu0_emerg: cp 349 cpu0_emerg: cpu0-emerg {
349 temper 350 temperature = <95000>;
350 hyster 351 hysteresis = <2000>;
351 type = 352 type = "passive";
352 }; 353 };
353 }; 354 };
354 355
355 cooling-maps { 356 cooling-maps {
356 map0_hot: map0 357 map0_hot: map0-hot {
357 trip = 358 trip = <&cpu0_hot>;
358 coolin 359 cooling-device = <&cpu0 1 2>,
359 360 <&cpu1 1 2>;
360 }; 361 };
361 map0_emerg: ma 362 map0_emerg: map0-ermerg {
362 trip = 363 trip = <&cpu0_emerg>;
363 coolin 364 cooling-device = <&cpu0 3 3>,
364 365 <&cpu1 3 3>;
365 }; 366 };
366 }; 367 };
367 }; 368 };
368 369
369 ap_thermal_cpu1: ap-cpu1-therm 370 ap_thermal_cpu1: ap-cpu1-thermal {
370 polling-delay-passive 371 polling-delay-passive = <1000>;
371 polling-delay = <1000> 372 polling-delay = <1000>;
372 373
373 thermal-sensors = <&ap 374 thermal-sensors = <&ap_thermal 2>;
374 375
375 trips { 376 trips {
376 cpu1_hot: cpu1 377 cpu1_hot: cpu1-hot {
377 temper 378 temperature = <85000>;
378 hyster 379 hysteresis = <2000>;
379 type = 380 type = "passive";
380 }; 381 };
381 cpu1_emerg: cp 382 cpu1_emerg: cpu1-emerg {
382 temper 383 temperature = <95000>;
383 hyster 384 hysteresis = <2000>;
384 type = 385 type = "passive";
385 }; 386 };
386 }; 387 };
387 388
388 cooling-maps { 389 cooling-maps {
389 map1_hot: map1 390 map1_hot: map1-hot {
390 trip = 391 trip = <&cpu1_hot>;
391 coolin 392 cooling-device = <&cpu0 1 2>,
392 393 <&cpu1 1 2>;
393 }; 394 };
394 map1_emerg: ma 395 map1_emerg: map1-emerg {
395 trip = 396 trip = <&cpu1_emerg>;
396 coolin 397 cooling-device = <&cpu0 3 3>,
397 398 <&cpu1 3 3>;
398 }; 399 };
399 }; 400 };
400 }; 401 };
401 402
402 ap_thermal_cpu2: ap-cpu2-therm 403 ap_thermal_cpu2: ap-cpu2-thermal {
403 polling-delay-passive 404 polling-delay-passive = <1000>;
404 polling-delay = <1000> 405 polling-delay = <1000>;
405 406
406 thermal-sensors = <&ap 407 thermal-sensors = <&ap_thermal 3>;
407 408
408 trips { 409 trips {
409 cpu2_hot: cpu2 410 cpu2_hot: cpu2-hot {
410 temper 411 temperature = <85000>;
411 hyster 412 hysteresis = <2000>;
412 type = 413 type = "passive";
413 }; 414 };
414 cpu2_emerg: cp 415 cpu2_emerg: cpu2-emerg {
415 temper 416 temperature = <95000>;
416 hyster 417 hysteresis = <2000>;
417 type = 418 type = "passive";
418 }; 419 };
419 }; 420 };
420 421
421 cooling-maps { 422 cooling-maps {
422 map2_hot: map2 423 map2_hot: map2-hot {
423 trip = 424 trip = <&cpu2_hot>;
424 coolin 425 cooling-device = <&cpu2 1 2>,
425 426 <&cpu3 1 2>;
426 }; 427 };
427 map2_emerg: ma 428 map2_emerg: map2-emerg {
428 trip = 429 trip = <&cpu2_emerg>;
429 coolin 430 cooling-device = <&cpu2 3 3>,
430 431 <&cpu3 3 3>;
431 }; 432 };
432 }; 433 };
433 }; 434 };
434 435
435 ap_thermal_cpu3: ap-cpu3-therm 436 ap_thermal_cpu3: ap-cpu3-thermal {
436 polling-delay-passive 437 polling-delay-passive = <1000>;
437 polling-delay = <1000> 438 polling-delay = <1000>;
438 439
439 thermal-sensors = <&ap 440 thermal-sensors = <&ap_thermal 4>;
440 441
441 trips { 442 trips {
442 cpu3_hot: cpu3 443 cpu3_hot: cpu3-hot {
443 temper 444 temperature = <85000>;
444 hyster 445 hysteresis = <2000>;
445 type = 446 type = "passive";
446 }; 447 };
447 cpu3_emerg: cp 448 cpu3_emerg: cpu3-emerg {
448 temper 449 temperature = <95000>;
449 hyster 450 hysteresis = <2000>;
450 type = 451 type = "passive";
451 }; 452 };
452 }; 453 };
453 454
454 cooling-maps { 455 cooling-maps {
455 map3_hot: map3 456 map3_hot: map3-bhot {
456 trip = 457 trip = <&cpu3_hot>;
457 coolin 458 cooling-device = <&cpu2 1 2>,
458 459 <&cpu3 1 2>;
459 }; 460 };
460 map3_emerg: ma 461 map3_emerg: map3-emerg {
461 trip = 462 trip = <&cpu3_emerg>;
462 coolin 463 cooling-device = <&cpu2 3 3>,
463 464 <&cpu3 3 3>;
464 }; 465 };
465 }; 466 };
466 }; 467 };
467 }; 468 };
468 }; 469 };
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