1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) !! 1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> 2 /*
>> 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
>> 4 */
>> 5
2 /* 6 /*
3 * Copyright (C) 2019 Marvell Technology Group <<
4 * <<
5 * Device Tree file for Marvell Armada CP110. 7 * Device Tree file for Marvell Armada CP110.
6 */ 8 */
7 9
8 #define CP11X_TYPE cp110 !! 10 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
>> 11
>> 12 #include "armada-common.dtsi"
>> 13
>> 14 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
>> 15 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
>> 16 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
>> 17
>> 18 / {
>> 19 /*
>> 20 * The contents of the node are defined below, in order to
>> 21 * save one indentation level
>> 22 */
>> 23 CP110_NAME: CP110_NAME { };
>> 24 };
>> 25
>> 26 &CP110_NAME {
>> 27 #address-cells = <2>;
>> 28 #size-cells = <2>;
>> 29 compatible = "simple-bus";
>> 30 interrupt-parent = <&CP110_LABEL(icu)>;
>> 31 ranges;
>> 32
>> 33 config-space@CP110_BASE {
>> 34 #address-cells = <1>;
>> 35 #size-cells = <1>;
>> 36 compatible = "simple-bus";
>> 37 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
>> 38
>> 39 CP110_LABEL(ethernet): ethernet@0 {
>> 40 compatible = "marvell,armada-7k-pp22";
>> 41 reg = <0x0 0x100000>, <0x129000 0xb000>;
>> 42 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
>> 43 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
>> 44 <&CP110_LABEL(clk) 1 18>;
>> 45 clock-names = "pp_clk", "gop_clk",
>> 46 "mg_clk", "mg_core_clk", "axi_clk";
>> 47 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 48 status = "disabled";
>> 49 dma-coherent;
>> 50
>> 51 CP110_LABEL(eth0): eth0 {
>> 52 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
>> 53 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
>> 54 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
>> 55 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
>> 56 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
>> 57 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
>> 58 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
>> 59 "tx-cpu3", "rx-shared", "link";
>> 60 port-id = <0>;
>> 61 gop-port-id = <0>;
>> 62 status = "disabled";
>> 63 };
>> 64
>> 65 CP110_LABEL(eth1): eth1 {
>> 66 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
>> 67 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
>> 68 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
>> 69 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
>> 70 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
>> 71 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
>> 72 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
>> 73 "tx-cpu3", "rx-shared", "link";
>> 74 port-id = <1>;
>> 75 gop-port-id = <2>;
>> 76 status = "disabled";
>> 77 };
>> 78
>> 79 CP110_LABEL(eth2): eth2 {
>> 80 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
>> 81 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
>> 82 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
>> 83 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
>> 84 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
>> 85 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
>> 86 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
>> 87 "tx-cpu3", "rx-shared", "link";
>> 88 port-id = <2>;
>> 89 gop-port-id = <3>;
>> 90 status = "disabled";
>> 91 };
>> 92 };
>> 93
>> 94 CP110_LABEL(comphy): phy@120000 {
>> 95 compatible = "marvell,comphy-cp110";
>> 96 reg = <0x120000 0x6000>;
>> 97 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 98 #address-cells = <1>;
>> 99 #size-cells = <0>;
>> 100
>> 101 CP110_LABEL(comphy0): phy@0 {
>> 102 reg = <0>;
>> 103 #phy-cells = <1>;
>> 104 };
>> 105
>> 106 CP110_LABEL(comphy1): phy@1 {
>> 107 reg = <1>;
>> 108 #phy-cells = <1>;
>> 109 };
>> 110
>> 111 CP110_LABEL(comphy2): phy@2 {
>> 112 reg = <2>;
>> 113 #phy-cells = <1>;
>> 114 };
>> 115
>> 116 CP110_LABEL(comphy3): phy@3 {
>> 117 reg = <3>;
>> 118 #phy-cells = <1>;
>> 119 };
>> 120
>> 121 CP110_LABEL(comphy4): phy@4 {
>> 122 reg = <4>;
>> 123 #phy-cells = <1>;
>> 124 };
>> 125
>> 126 CP110_LABEL(comphy5): phy@5 {
>> 127 reg = <5>;
>> 128 #phy-cells = <1>;
>> 129 };
>> 130 };
>> 131
>> 132 CP110_LABEL(mdio): mdio@12a200 {
>> 133 #address-cells = <1>;
>> 134 #size-cells = <0>;
>> 135 compatible = "marvell,orion-mdio";
>> 136 reg = <0x12a200 0x10>;
>> 137 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
>> 138 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
>> 139 status = "disabled";
>> 140 };
>> 141
>> 142 CP110_LABEL(xmdio): mdio@12a600 {
>> 143 #address-cells = <1>;
>> 144 #size-cells = <0>;
>> 145 compatible = "marvell,xmdio";
>> 146 reg = <0x12a600 0x10>;
>> 147 clocks = <&CP110_LABEL(clk) 1 5>,
>> 148 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
>> 149 status = "disabled";
>> 150 };
>> 151
>> 152 CP110_LABEL(icu): interrupt-controller@1e0000 {
>> 153 compatible = "marvell,cp110-icu";
>> 154 reg = <0x1e0000 0x10>;
>> 155 #interrupt-cells = <3>;
>> 156 interrupt-controller;
>> 157 msi-parent = <&gicp>;
>> 158 };
>> 159
>> 160 CP110_LABEL(rtc): rtc@284000 {
>> 161 compatible = "marvell,armada-8k-rtc";
>> 162 reg = <0x284000 0x20>, <0x284080 0x24>;
>> 163 reg-names = "rtc", "rtc-soc";
>> 164 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
>> 165 };
>> 166
>> 167 CP110_LABEL(thermal): thermal@400078 {
>> 168 compatible = "marvell,armada-cp110-thermal";
>> 169 reg = <0x400078 0x4>,
>> 170 <0x400070 0x8>;
>> 171 };
>> 172
>> 173 CP110_LABEL(syscon0): system-controller@440000 {
>> 174 compatible = "syscon", "simple-mfd";
>> 175 reg = <0x440000 0x2000>;
>> 176
>> 177 CP110_LABEL(clk): clock {
>> 178 compatible = "marvell,cp110-clock";
>> 179 #clock-cells = <2>;
>> 180 };
>> 181
>> 182 CP110_LABEL(gpio1): gpio@100 {
>> 183 compatible = "marvell,armada-8k-gpio";
>> 184 offset = <0x100>;
>> 185 ngpios = <32>;
>> 186 gpio-controller;
>> 187 #gpio-cells = <2>;
>> 188 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
>> 189 interrupt-controller;
>> 190 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
>> 191 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
>> 192 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
>> 193 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
>> 194 status = "disabled";
>> 195 };
>> 196
>> 197 CP110_LABEL(gpio2): gpio@140 {
>> 198 compatible = "marvell,armada-8k-gpio";
>> 199 offset = <0x140>;
>> 200 ngpios = <31>;
>> 201 gpio-controller;
>> 202 #gpio-cells = <2>;
>> 203 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
>> 204 interrupt-controller;
>> 205 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
>> 206 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
>> 207 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
>> 208 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
>> 209 status = "disabled";
>> 210 };
>> 211 };
>> 212
>> 213 CP110_LABEL(usb3_0): usb3@500000 {
>> 214 compatible = "marvell,armada-8k-xhci",
>> 215 "generic-xhci";
>> 216 reg = <0x500000 0x4000>;
>> 217 dma-coherent;
>> 218 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
>> 219 clocks = <&CP110_LABEL(clk) 1 22>;
>> 220 status = "disabled";
>> 221 };
>> 222
>> 223 CP110_LABEL(usb3_1): usb3@510000 {
>> 224 compatible = "marvell,armada-8k-xhci",
>> 225 "generic-xhci";
>> 226 reg = <0x510000 0x4000>;
>> 227 dma-coherent;
>> 228 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
>> 229 clocks = <&CP110_LABEL(clk) 1 23>;
>> 230 status = "disabled";
>> 231 };
>> 232
>> 233 CP110_LABEL(sata0): sata@540000 {
>> 234 compatible = "marvell,armada-8k-ahci",
>> 235 "generic-ahci";
>> 236 reg = <0x540000 0x30000>;
>> 237 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
>> 238 clocks = <&CP110_LABEL(clk) 1 15>;
>> 239 status = "disabled";
>> 240 };
>> 241
>> 242 CP110_LABEL(xor0): xor@6a0000 {
>> 243 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
>> 244 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
>> 245 dma-coherent;
>> 246 msi-parent = <&gic_v2m0>;
>> 247 clocks = <&CP110_LABEL(clk) 1 8>;
>> 248 };
>> 249
>> 250 CP110_LABEL(xor1): xor@6c0000 {
>> 251 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
>> 252 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
>> 253 dma-coherent;
>> 254 msi-parent = <&gic_v2m0>;
>> 255 clocks = <&CP110_LABEL(clk) 1 7>;
>> 256 };
>> 257
>> 258 CP110_LABEL(spi0): spi@700600 {
>> 259 compatible = "marvell,armada-380-spi";
>> 260 reg = <0x700600 0x50>;
>> 261 #address-cells = <0x1>;
>> 262 #size-cells = <0x0>;
>> 263 clocks = <&CP110_LABEL(clk) 1 21>;
>> 264 status = "disabled";
>> 265 };
>> 266
>> 267 CP110_LABEL(spi1): spi@700680 {
>> 268 compatible = "marvell,armada-380-spi";
>> 269 reg = <0x700680 0x50>;
>> 270 #address-cells = <1>;
>> 271 #size-cells = <0>;
>> 272 clocks = <&CP110_LABEL(clk) 1 21>;
>> 273 status = "disabled";
>> 274 };
>> 275
>> 276 CP110_LABEL(i2c0): i2c@701000 {
>> 277 compatible = "marvell,mv78230-i2c";
>> 278 reg = <0x701000 0x20>;
>> 279 #address-cells = <1>;
>> 280 #size-cells = <0>;
>> 281 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
>> 282 clocks = <&CP110_LABEL(clk) 1 21>;
>> 283 status = "disabled";
>> 284 };
>> 285
>> 286 CP110_LABEL(i2c1): i2c@701100 {
>> 287 compatible = "marvell,mv78230-i2c";
>> 288 reg = <0x701100 0x20>;
>> 289 #address-cells = <1>;
>> 290 #size-cells = <0>;
>> 291 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
>> 292 clocks = <&CP110_LABEL(clk) 1 21>;
>> 293 status = "disabled";
>> 294 };
>> 295
>> 296 CP110_LABEL(nand): nand@720000 {
>> 297 /*
>> 298 * Due to the limitation of the pins available
>> 299 * this controller is only usable on the CPM
>> 300 * for A7K and on the CPS for A8K.
>> 301 */
>> 302 compatible = "marvell,armada-8k-nand",
>> 303 "marvell,armada370-nand";
>> 304 reg = <0x720000 0x54>;
>> 305 #address-cells = <1>;
>> 306 #size-cells = <1>;
>> 307 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
>> 308 clocks = <&CP110_LABEL(clk) 1 2>;
>> 309 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 310 status = "disabled";
>> 311 };
>> 312
>> 313 CP110_LABEL(trng): trng@760000 {
>> 314 compatible = "marvell,armada-8k-rng",
>> 315 "inside-secure,safexcel-eip76";
>> 316 reg = <0x760000 0x7d>;
>> 317 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
>> 318 clocks = <&CP110_LABEL(clk) 1 25>;
>> 319 status = "okay";
>> 320 };
>> 321
>> 322 CP110_LABEL(sdhci0): sdhci@780000 {
>> 323 compatible = "marvell,armada-cp110-sdhci";
>> 324 reg = <0x780000 0x300>;
>> 325 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
>> 326 clock-names = "core", "axi";
>> 327 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
>> 328 dma-coherent;
>> 329 status = "disabled";
>> 330 };
>> 331
>> 332 CP110_LABEL(crypto): crypto@800000 {
>> 333 compatible = "inside-secure,safexcel-eip197";
>> 334 reg = <0x800000 0x200000>;
>> 335 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
>> 336 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
>> 337 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
>> 338 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
>> 339 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
>> 340 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
>> 341 interrupt-names = "mem", "ring0", "ring1",
>> 342 "ring2", "ring3", "eip";
>> 343 clocks = <&CP110_LABEL(clk) 1 26>;
>> 344 dma-coherent;
>> 345 };
>> 346 };
>> 347
>> 348 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
>> 349 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 350 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
>> 351 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
>> 352 reg-names = "ctrl", "config";
>> 353 #address-cells = <3>;
>> 354 #size-cells = <2>;
>> 355 #interrupt-cells = <1>;
>> 356 device_type = "pci";
>> 357 dma-coherent;
>> 358 msi-parent = <&gic_v2m0>;
>> 359
>> 360 bus-range = <0 0xff>;
>> 361 ranges =
>> 362 /* downstream I/O */
>> 363 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
>> 364 /* non-prefetchable memory */
>> 365 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
>> 366 interrupt-map-mask = <0 0 0 0>;
>> 367 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
>> 368 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
>> 369 num-lanes = <1>;
>> 370 clocks = <&CP110_LABEL(clk) 1 13>;
>> 371 status = "disabled";
>> 372 };
>> 373
>> 374 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
>> 375 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 376 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
>> 377 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
>> 378 reg-names = "ctrl", "config";
>> 379 #address-cells = <3>;
>> 380 #size-cells = <2>;
>> 381 #interrupt-cells = <1>;
>> 382 device_type = "pci";
>> 383 dma-coherent;
>> 384 msi-parent = <&gic_v2m0>;
>> 385
>> 386 bus-range = <0 0xff>;
>> 387 ranges =
>> 388 /* downstream I/O */
>> 389 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
>> 390 /* non-prefetchable memory */
>> 391 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
>> 392 interrupt-map-mask = <0 0 0 0>;
>> 393 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
>> 394 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
>> 395
>> 396 num-lanes = <1>;
>> 397 clocks = <&CP110_LABEL(clk) 1 11>;
>> 398 status = "disabled";
>> 399 };
>> 400
>> 401 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
>> 402 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 403 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
>> 404 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
>> 405 reg-names = "ctrl", "config";
>> 406 #address-cells = <3>;
>> 407 #size-cells = <2>;
>> 408 #interrupt-cells = <1>;
>> 409 device_type = "pci";
>> 410 dma-coherent;
>> 411 msi-parent = <&gic_v2m0>;
9 412
10 #include "armada-cp11x.dtsi" !! 413 bus-range = <0 0xff>;
>> 414 ranges =
>> 415 /* downstream I/O */
>> 416 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
>> 417 /* non-prefetchable memory */
>> 418 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
>> 419 interrupt-map-mask = <0 0 0 0>;
>> 420 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
>> 421 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
11 422
12 #undef CP11X_TYPE !! 423 num-lanes = <1>;
>> 424 clocks = <&CP110_LABEL(clk) 1 12>;
>> 425 status = "disabled";
>> 426 };
>> 427 };
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