1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2019 Marvell Technology Group !! 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada CP110. 5 * Device Tree file for Marvell Armada CP110.
6 */ 6 */
7 7
8 #define CP11X_TYPE cp110 !! 8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
>> 9 #include <dt-bindings/thermal/thermal.h>
9 10
10 #include "armada-cp11x.dtsi" !! 11 #include "armada-common.dtsi"
11 12
12 #undef CP11X_TYPE !! 13 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
>> 14 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
>> 15 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
>> 16
>> 17 / {
>> 18 /*
>> 19 * The contents of the node are defined below, in order to
>> 20 * save one indentation level
>> 21 */
>> 22 CP110_NAME: CP110_NAME { };
>> 23
>> 24 /*
>> 25 * CPs only have one sensor in the thermal IC.
>> 26 *
>> 27 * The cooling maps are empty as there are no cooling devices.
>> 28 */
>> 29 thermal-zones {
>> 30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
>> 31 polling-delay-passive = <1000>;
>> 32 polling-delay = <1000>;
>> 33
>> 34 thermal-sensors = <&CP110_LABEL(thermal) 0>;
>> 35
>> 36 trips { };
>> 37 cooling-maps { };
>> 38 };
>> 39 };
>> 40 };
>> 41
>> 42 &CP110_NAME {
>> 43 #address-cells = <2>;
>> 44 #size-cells = <2>;
>> 45 compatible = "simple-bus";
>> 46 interrupt-parent = <&CP110_LABEL(icu_nsr)>;
>> 47 ranges;
>> 48
>> 49 config-space@CP110_BASE {
>> 50 #address-cells = <1>;
>> 51 #size-cells = <1>;
>> 52 compatible = "simple-bus";
>> 53 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
>> 54
>> 55 CP110_LABEL(ethernet): ethernet@0 {
>> 56 compatible = "marvell,armada-7k-pp22";
>> 57 reg = <0x0 0x100000>, <0x129000 0xb000>;
>> 58 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
>> 59 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
>> 60 <&CP110_LABEL(clk) 1 18>;
>> 61 clock-names = "pp_clk", "gop_clk",
>> 62 "mg_clk", "mg_core_clk", "axi_clk";
>> 63 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 64 status = "disabled";
>> 65 dma-coherent;
>> 66
>> 67 CP110_LABEL(eth0): eth0 {
>> 68 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
>> 69 <43 IRQ_TYPE_LEVEL_HIGH>,
>> 70 <47 IRQ_TYPE_LEVEL_HIGH>,
>> 71 <51 IRQ_TYPE_LEVEL_HIGH>,
>> 72 <55 IRQ_TYPE_LEVEL_HIGH>,
>> 73 <59 IRQ_TYPE_LEVEL_HIGH>,
>> 74 <63 IRQ_TYPE_LEVEL_HIGH>,
>> 75 <67 IRQ_TYPE_LEVEL_HIGH>,
>> 76 <71 IRQ_TYPE_LEVEL_HIGH>,
>> 77 <129 IRQ_TYPE_LEVEL_HIGH>;
>> 78 interrupt-names = "hif0", "hif1", "hif2",
>> 79 "hif3", "hif4", "hif5", "hif6", "hif7",
>> 80 "hif8", "link";
>> 81 port-id = <0>;
>> 82 gop-port-id = <0>;
>> 83 status = "disabled";
>> 84 };
>> 85
>> 86 CP110_LABEL(eth1): eth1 {
>> 87 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
>> 88 <44 IRQ_TYPE_LEVEL_HIGH>,
>> 89 <48 IRQ_TYPE_LEVEL_HIGH>,
>> 90 <52 IRQ_TYPE_LEVEL_HIGH>,
>> 91 <56 IRQ_TYPE_LEVEL_HIGH>,
>> 92 <60 IRQ_TYPE_LEVEL_HIGH>,
>> 93 <64 IRQ_TYPE_LEVEL_HIGH>,
>> 94 <68 IRQ_TYPE_LEVEL_HIGH>,
>> 95 <72 IRQ_TYPE_LEVEL_HIGH>,
>> 96 <128 IRQ_TYPE_LEVEL_HIGH>;
>> 97 interrupt-names = "hif0", "hif1", "hif2",
>> 98 "hif3", "hif4", "hif5", "hif6", "hif7",
>> 99 "hif8", "link";
>> 100 port-id = <1>;
>> 101 gop-port-id = <2>;
>> 102 status = "disabled";
>> 103 };
>> 104
>> 105 CP110_LABEL(eth2): eth2 {
>> 106 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
>> 107 <45 IRQ_TYPE_LEVEL_HIGH>,
>> 108 <49 IRQ_TYPE_LEVEL_HIGH>,
>> 109 <53 IRQ_TYPE_LEVEL_HIGH>,
>> 110 <57 IRQ_TYPE_LEVEL_HIGH>,
>> 111 <61 IRQ_TYPE_LEVEL_HIGH>,
>> 112 <65 IRQ_TYPE_LEVEL_HIGH>,
>> 113 <69 IRQ_TYPE_LEVEL_HIGH>,
>> 114 <73 IRQ_TYPE_LEVEL_HIGH>,
>> 115 <127 IRQ_TYPE_LEVEL_HIGH>;
>> 116 interrupt-names = "hif0", "hif1", "hif2",
>> 117 "hif3", "hif4", "hif5", "hif6", "hif7",
>> 118 "hif8", "link";
>> 119 port-id = <2>;
>> 120 gop-port-id = <3>;
>> 121 status = "disabled";
>> 122 };
>> 123 };
>> 124
>> 125 CP110_LABEL(comphy): phy@120000 {
>> 126 compatible = "marvell,comphy-cp110";
>> 127 reg = <0x120000 0x6000>;
>> 128 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 129 #address-cells = <1>;
>> 130 #size-cells = <0>;
>> 131
>> 132 CP110_LABEL(comphy0): phy@0 {
>> 133 reg = <0>;
>> 134 #phy-cells = <1>;
>> 135 };
>> 136
>> 137 CP110_LABEL(comphy1): phy@1 {
>> 138 reg = <1>;
>> 139 #phy-cells = <1>;
>> 140 };
>> 141
>> 142 CP110_LABEL(comphy2): phy@2 {
>> 143 reg = <2>;
>> 144 #phy-cells = <1>;
>> 145 };
>> 146
>> 147 CP110_LABEL(comphy3): phy@3 {
>> 148 reg = <3>;
>> 149 #phy-cells = <1>;
>> 150 };
>> 151
>> 152 CP110_LABEL(comphy4): phy@4 {
>> 153 reg = <4>;
>> 154 #phy-cells = <1>;
>> 155 };
>> 156
>> 157 CP110_LABEL(comphy5): phy@5 {
>> 158 reg = <5>;
>> 159 #phy-cells = <1>;
>> 160 };
>> 161 };
>> 162
>> 163 CP110_LABEL(mdio): mdio@12a200 {
>> 164 #address-cells = <1>;
>> 165 #size-cells = <0>;
>> 166 compatible = "marvell,orion-mdio";
>> 167 reg = <0x12a200 0x10>;
>> 168 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
>> 169 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
>> 170 status = "disabled";
>> 171 };
>> 172
>> 173 CP110_LABEL(xmdio): mdio@12a600 {
>> 174 #address-cells = <1>;
>> 175 #size-cells = <0>;
>> 176 compatible = "marvell,xmdio";
>> 177 reg = <0x12a600 0x10>;
>> 178 clocks = <&CP110_LABEL(clk) 1 5>,
>> 179 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
>> 180 status = "disabled";
>> 181 };
>> 182
>> 183 CP110_LABEL(icu): interrupt-controller@1e0000 {
>> 184 compatible = "marvell,cp110-icu";
>> 185 reg = <0x1e0000 0x440>;
>> 186 #address-cells = <1>;
>> 187 #size-cells = <1>;
>> 188
>> 189 CP110_LABEL(icu_nsr): interrupt-controller@10 {
>> 190 compatible = "marvell,cp110-icu-nsr";
>> 191 reg = <0x10 0x20>;
>> 192 #interrupt-cells = <2>;
>> 193 interrupt-controller;
>> 194 msi-parent = <&gicp>;
>> 195 };
>> 196
>> 197 CP110_LABEL(icu_sei): interrupt-controller@50 {
>> 198 compatible = "marvell,cp110-icu-sei";
>> 199 reg = <0x50 0x10>;
>> 200 #interrupt-cells = <2>;
>> 201 interrupt-controller;
>> 202 msi-parent = <&sei>;
>> 203 };
>> 204 };
>> 205
>> 206 CP110_LABEL(rtc): rtc@284000 {
>> 207 compatible = "marvell,armada-8k-rtc";
>> 208 reg = <0x284000 0x20>, <0x284080 0x24>;
>> 209 reg-names = "rtc", "rtc-soc";
>> 210 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
>> 211 };
>> 212
>> 213 CP110_LABEL(syscon0): system-controller@440000 {
>> 214 compatible = "syscon", "simple-mfd";
>> 215 reg = <0x440000 0x2000>;
>> 216
>> 217 CP110_LABEL(clk): clock {
>> 218 compatible = "marvell,cp110-clock";
>> 219 #clock-cells = <2>;
>> 220 };
>> 221
>> 222 CP110_LABEL(gpio1): gpio@100 {
>> 223 compatible = "marvell,armada-8k-gpio";
>> 224 offset = <0x100>;
>> 225 ngpios = <32>;
>> 226 gpio-controller;
>> 227 #gpio-cells = <2>;
>> 228 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
>> 229 interrupt-controller;
>> 230 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
>> 231 <85 IRQ_TYPE_LEVEL_HIGH>,
>> 232 <84 IRQ_TYPE_LEVEL_HIGH>,
>> 233 <83 IRQ_TYPE_LEVEL_HIGH>;
>> 234 status = "disabled";
>> 235 };
>> 236
>> 237 CP110_LABEL(gpio2): gpio@140 {
>> 238 compatible = "marvell,armada-8k-gpio";
>> 239 offset = <0x140>;
>> 240 ngpios = <31>;
>> 241 gpio-controller;
>> 242 #gpio-cells = <2>;
>> 243 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
>> 244 interrupt-controller;
>> 245 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
>> 246 <81 IRQ_TYPE_LEVEL_HIGH>,
>> 247 <80 IRQ_TYPE_LEVEL_HIGH>,
>> 248 <79 IRQ_TYPE_LEVEL_HIGH>;
>> 249 status = "disabled";
>> 250 };
>> 251 };
>> 252
>> 253 CP110_LABEL(syscon1): system-controller@400000 {
>> 254 compatible = "syscon", "simple-mfd";
>> 255 reg = <0x400000 0x1000>;
>> 256 #address-cells = <1>;
>> 257 #size-cells = <1>;
>> 258
>> 259 CP110_LABEL(thermal): thermal-sensor@70 {
>> 260 compatible = "marvell,armada-cp110-thermal";
>> 261 reg = <0x70 0x10>;
>> 262 #thermal-sensor-cells = <1>;
>> 263 };
>> 264 };
>> 265
>> 266 CP110_LABEL(usb3_0): usb3@500000 {
>> 267 compatible = "marvell,armada-8k-xhci",
>> 268 "generic-xhci";
>> 269 reg = <0x500000 0x4000>;
>> 270 dma-coherent;
>> 271 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
>> 272 clock-names = "core", "reg";
>> 273 clocks = <&CP110_LABEL(clk) 1 22>,
>> 274 <&CP110_LABEL(clk) 1 16>;
>> 275 status = "disabled";
>> 276 };
>> 277
>> 278 CP110_LABEL(usb3_1): usb3@510000 {
>> 279 compatible = "marvell,armada-8k-xhci",
>> 280 "generic-xhci";
>> 281 reg = <0x510000 0x4000>;
>> 282 dma-coherent;
>> 283 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
>> 284 clock-names = "core", "reg";
>> 285 clocks = <&CP110_LABEL(clk) 1 23>,
>> 286 <&CP110_LABEL(clk) 1 16>;
>> 287 status = "disabled";
>> 288 };
>> 289
>> 290 CP110_LABEL(sata0): sata@540000 {
>> 291 compatible = "marvell,armada-8k-ahci",
>> 292 "generic-ahci";
>> 293 reg = <0x540000 0x30000>;
>> 294 dma-coherent;
>> 295 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
>> 296 clocks = <&CP110_LABEL(clk) 1 15>,
>> 297 <&CP110_LABEL(clk) 1 16>;
>> 298 status = "disabled";
>> 299 };
>> 300
>> 301 CP110_LABEL(xor0): xor@6a0000 {
>> 302 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
>> 303 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
>> 304 dma-coherent;
>> 305 msi-parent = <&gic_v2m0>;
>> 306 clock-names = "core", "reg";
>> 307 clocks = <&CP110_LABEL(clk) 1 8>,
>> 308 <&CP110_LABEL(clk) 1 14>;
>> 309 };
>> 310
>> 311 CP110_LABEL(xor1): xor@6c0000 {
>> 312 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
>> 313 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
>> 314 dma-coherent;
>> 315 msi-parent = <&gic_v2m0>;
>> 316 clock-names = "core", "reg";
>> 317 clocks = <&CP110_LABEL(clk) 1 7>,
>> 318 <&CP110_LABEL(clk) 1 14>;
>> 319 };
>> 320
>> 321 CP110_LABEL(spi0): spi@700600 {
>> 322 compatible = "marvell,armada-380-spi";
>> 323 reg = <0x700600 0x50>;
>> 324 #address-cells = <0x1>;
>> 325 #size-cells = <0x0>;
>> 326 clock-names = "core", "axi";
>> 327 clocks = <&CP110_LABEL(clk) 1 21>,
>> 328 <&CP110_LABEL(clk) 1 17>;
>> 329 status = "disabled";
>> 330 };
>> 331
>> 332 CP110_LABEL(spi1): spi@700680 {
>> 333 compatible = "marvell,armada-380-spi";
>> 334 reg = <0x700680 0x50>;
>> 335 #address-cells = <1>;
>> 336 #size-cells = <0>;
>> 337 clock-names = "core", "axi";
>> 338 clocks = <&CP110_LABEL(clk) 1 21>,
>> 339 <&CP110_LABEL(clk) 1 17>;
>> 340 status = "disabled";
>> 341 };
>> 342
>> 343 CP110_LABEL(i2c0): i2c@701000 {
>> 344 compatible = "marvell,mv78230-i2c";
>> 345 reg = <0x701000 0x20>;
>> 346 #address-cells = <1>;
>> 347 #size-cells = <0>;
>> 348 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
>> 349 clock-names = "core", "reg";
>> 350 clocks = <&CP110_LABEL(clk) 1 21>,
>> 351 <&CP110_LABEL(clk) 1 17>;
>> 352 status = "disabled";
>> 353 };
>> 354
>> 355 CP110_LABEL(i2c1): i2c@701100 {
>> 356 compatible = "marvell,mv78230-i2c";
>> 357 reg = <0x701100 0x20>;
>> 358 #address-cells = <1>;
>> 359 #size-cells = <0>;
>> 360 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
>> 361 clock-names = "core", "reg";
>> 362 clocks = <&CP110_LABEL(clk) 1 21>,
>> 363 <&CP110_LABEL(clk) 1 17>;
>> 364 status = "disabled";
>> 365 };
>> 366
>> 367 CP110_LABEL(uart0): serial@702000 {
>> 368 compatible = "snps,dw-apb-uart";
>> 369 reg = <0x702000 0x100>;
>> 370 reg-shift = <2>;
>> 371 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
>> 372 reg-io-width = <1>;
>> 373 clock-names = "baudclk", "apb_pclk";
>> 374 clocks = <&CP110_LABEL(clk) 1 21>,
>> 375 <&CP110_LABEL(clk) 1 17>;
>> 376 status = "disabled";
>> 377 };
>> 378
>> 379 CP110_LABEL(uart1): serial@702100 {
>> 380 compatible = "snps,dw-apb-uart";
>> 381 reg = <0x702100 0x100>;
>> 382 reg-shift = <2>;
>> 383 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
>> 384 reg-io-width = <1>;
>> 385 clock-names = "baudclk", "apb_pclk";
>> 386 clocks = <&CP110_LABEL(clk) 1 21>,
>> 387 <&CP110_LABEL(clk) 1 17>;
>> 388 status = "disabled";
>> 389 };
>> 390
>> 391 CP110_LABEL(uart2): serial@702200 {
>> 392 compatible = "snps,dw-apb-uart";
>> 393 reg = <0x702200 0x100>;
>> 394 reg-shift = <2>;
>> 395 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
>> 396 reg-io-width = <1>;
>> 397 clock-names = "baudclk", "apb_pclk";
>> 398 clocks = <&CP110_LABEL(clk) 1 21>,
>> 399 <&CP110_LABEL(clk) 1 17>;
>> 400 status = "disabled";
>> 401 };
>> 402
>> 403 CP110_LABEL(uart3): serial@702300 {
>> 404 compatible = "snps,dw-apb-uart";
>> 405 reg = <0x702300 0x100>;
>> 406 reg-shift = <2>;
>> 407 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
>> 408 reg-io-width = <1>;
>> 409 clock-names = "baudclk", "apb_pclk";
>> 410 clocks = <&CP110_LABEL(clk) 1 21>,
>> 411 <&CP110_LABEL(clk) 1 17>;
>> 412 status = "disabled";
>> 413 };
>> 414
>> 415 CP110_LABEL(nand_controller): nand@720000 {
>> 416 /*
>> 417 * Due to the limitation of the pins available
>> 418 * this controller is only usable on the CPM
>> 419 * for A7K and on the CPS for A8K.
>> 420 */
>> 421 compatible = "marvell,armada-8k-nand-controller",
>> 422 "marvell,armada370-nand-controller";
>> 423 reg = <0x720000 0x54>;
>> 424 #address-cells = <1>;
>> 425 #size-cells = <0>;
>> 426 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
>> 427 clock-names = "core", "reg";
>> 428 clocks = <&CP110_LABEL(clk) 1 2>,
>> 429 <&CP110_LABEL(clk) 1 17>;
>> 430 marvell,system-controller = <&CP110_LABEL(syscon0)>;
>> 431 status = "disabled";
>> 432 };
>> 433
>> 434 CP110_LABEL(trng): trng@760000 {
>> 435 compatible = "marvell,armada-8k-rng",
>> 436 "inside-secure,safexcel-eip76";
>> 437 reg = <0x760000 0x7d>;
>> 438 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
>> 439 clock-names = "core", "reg";
>> 440 clocks = <&CP110_LABEL(clk) 1 25>,
>> 441 <&CP110_LABEL(clk) 1 17>;
>> 442 status = "okay";
>> 443 };
>> 444
>> 445 CP110_LABEL(sdhci0): sdhci@780000 {
>> 446 compatible = "marvell,armada-cp110-sdhci";
>> 447 reg = <0x780000 0x300>;
>> 448 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
>> 449 clock-names = "core", "axi";
>> 450 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
>> 451 dma-coherent;
>> 452 status = "disabled";
>> 453 };
>> 454
>> 455 CP110_LABEL(crypto): crypto@800000 {
>> 456 compatible = "inside-secure,safexcel-eip197b";
>> 457 reg = <0x800000 0x200000>;
>> 458 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
>> 459 <88 IRQ_TYPE_LEVEL_HIGH>,
>> 460 <89 IRQ_TYPE_LEVEL_HIGH>,
>> 461 <90 IRQ_TYPE_LEVEL_HIGH>,
>> 462 <91 IRQ_TYPE_LEVEL_HIGH>,
>> 463 <92 IRQ_TYPE_LEVEL_HIGH>;
>> 464 interrupt-names = "mem", "ring0", "ring1",
>> 465 "ring2", "ring3", "eip";
>> 466 clock-names = "core", "reg";
>> 467 clocks = <&CP110_LABEL(clk) 1 26>,
>> 468 <&CP110_LABEL(clk) 1 17>;
>> 469 dma-coherent;
>> 470 };
>> 471 };
>> 472
>> 473 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
>> 474 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 475 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
>> 476 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
>> 477 reg-names = "ctrl", "config";
>> 478 #address-cells = <3>;
>> 479 #size-cells = <2>;
>> 480 #interrupt-cells = <1>;
>> 481 device_type = "pci";
>> 482 dma-coherent;
>> 483 msi-parent = <&gic_v2m0>;
>> 484
>> 485 bus-range = <0 0xff>;
>> 486 ranges =
>> 487 /* downstream I/O */
>> 488 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
>> 489 /* non-prefetchable memory */
>> 490 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
>> 491 interrupt-map-mask = <0 0 0 0>;
>> 492 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
>> 493 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
>> 494 num-lanes = <1>;
>> 495 clock-names = "core", "reg";
>> 496 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
>> 497 status = "disabled";
>> 498 };
>> 499
>> 500 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
>> 501 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 502 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
>> 503 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
>> 504 reg-names = "ctrl", "config";
>> 505 #address-cells = <3>;
>> 506 #size-cells = <2>;
>> 507 #interrupt-cells = <1>;
>> 508 device_type = "pci";
>> 509 dma-coherent;
>> 510 msi-parent = <&gic_v2m0>;
>> 511
>> 512 bus-range = <0 0xff>;
>> 513 ranges =
>> 514 /* downstream I/O */
>> 515 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
>> 516 /* non-prefetchable memory */
>> 517 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
>> 518 interrupt-map-mask = <0 0 0 0>;
>> 519 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
>> 520 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
>> 521
>> 522 num-lanes = <1>;
>> 523 clock-names = "core", "reg";
>> 524 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
>> 525 status = "disabled";
>> 526 };
>> 527
>> 528 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
>> 529 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
>> 530 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
>> 531 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
>> 532 reg-names = "ctrl", "config";
>> 533 #address-cells = <3>;
>> 534 #size-cells = <2>;
>> 535 #interrupt-cells = <1>;
>> 536 device_type = "pci";
>> 537 dma-coherent;
>> 538 msi-parent = <&gic_v2m0>;
>> 539
>> 540 bus-range = <0 0xff>;
>> 541 ranges =
>> 542 /* downstream I/O */
>> 543 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
>> 544 /* non-prefetchable memory */
>> 545 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
>> 546 interrupt-map-mask = <0 0 0 0>;
>> 547 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
>> 548 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
>> 549
>> 550 num-lanes = <1>;
>> 551 clock-names = "core", "reg";
>> 552 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
>> 553 status = "disabled";
>> 554 };
>> 555 };
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