1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2019 Marvell International Lt 3 * Copyright (C) 2019 Marvell International Ltd.
4 * 4 *
5 * Device tree for the CN9130-DB board. 5 * Device tree for the CN9130-DB board.
6 */ 6 */
7 7
8 #include "cn9130-db.dtsi" !! 8 #include "cn9130.dtsi"
>> 9
>> 10 #include <dt-bindings/gpio/gpio.h>
9 11
10 / { 12 / {
11 model = "Marvell Armada CN9130-DB setu !! 13 model = "Marvell Armada CN9130-DB";
>> 14
>> 15 chosen {
>> 16 stdout-path = "serial0:115200n8";
>> 17 };
>> 18
>> 19 aliases {
>> 20 gpio1 = &cp0_gpio1;
>> 21 gpio2 = &cp0_gpio2;
>> 22 i2c0 = &cp0_i2c0;
>> 23 ethernet0 = &cp0_eth0;
>> 24 ethernet1 = &cp0_eth1;
>> 25 ethernet2 = &cp0_eth2;
>> 26 spi1 = &cp0_spi0;
>> 27 spi2 = &cp0_spi1;
>> 28 };
>> 29
>> 30 memory@00000000 {
>> 31 device_type = "memory";
>> 32 reg = <0x0 0x0 0x0 0x80000000>;
>> 33 };
>> 34
>> 35 ap0_reg_sd_vccq: ap0_sd_vccq@0 {
>> 36 compatible = "regulator-gpio";
>> 37 regulator-name = "ap0_sd_vccq";
>> 38 regulator-min-microvolt = <1800000>;
>> 39 regulator-max-microvolt = <3300000>;
>> 40 gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
>> 41 states = <1800000 0x1 3300000 0x0>;
>> 42 };
>> 43
>> 44 cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
>> 45 compatible = "regulator-fixed";
>> 46 regulator-name = "cp0-xhci0-vbus";
>> 47 regulator-min-microvolt = <5000000>;
>> 48 regulator-max-microvolt = <5000000>;
>> 49 enable-active-high;
>> 50 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
>> 51 };
>> 52
>> 53 cp0_usb3_0_phy0: cp0_usb3_phy@0 {
>> 54 compatible = "usb-nop-xceiv";
>> 55 vcc-supply = <&cp0_reg_usb3_vbus0>;
>> 56 };
>> 57
>> 58 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
>> 59 compatible = "regulator-fixed";
>> 60 regulator-name = "cp0-xhci1-vbus";
>> 61 regulator-min-microvolt = <5000000>;
>> 62 regulator-max-microvolt = <5000000>;
>> 63 enable-active-high;
>> 64 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
>> 65 };
>> 66
>> 67 cp0_usb3_0_phy1: cp0_usb3_phy@1 {
>> 68 compatible = "usb-nop-xceiv";
>> 69 vcc-supply = <&cp0_reg_usb3_vbus1>;
>> 70 };
>> 71
>> 72 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
>> 73 compatible = "regulator-gpio";
>> 74 regulator-name = "cp0_sd_vccq";
>> 75 regulator-min-microvolt = <1800000>;
>> 76 regulator-max-microvolt = <3300000>;
>> 77 gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
>> 78 states = <1800000 0x1
>> 79 3300000 0x0>;
>> 80 };
>> 81
>> 82 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
>> 83 compatible = "regulator-fixed";
>> 84 regulator-name = "cp0_sd_vcc";
>> 85 regulator-min-microvolt = <3300000>;
>> 86 regulator-max-microvolt = <3300000>;
>> 87 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
>> 88 enable-active-high;
>> 89 regulator-always-on;
>> 90 };
>> 91
>> 92 cp0_sfp_eth0: sfp-eth@0 {
>> 93 compatible = "sff,sfp";
>> 94 i2c-bus = <&cp0_sfpp0_i2c>;
>> 95 los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
>> 96 mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
>> 97 tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
>> 98 tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
>> 99 /*
>> 100 * SFP cages are unconnected on early PCBs because of an the I2C
>> 101 * lanes not being connected. Prevent the port for being
>> 102 * unusable by disabling the SFP node.
>> 103 */
>> 104 status = "disabled";
>> 105 };
>> 106 };
>> 107
>> 108 &uart0 {
>> 109 status = "okay";
>> 110 };
>> 111
>> 112 /* on-board eMMC - U9 */
>> 113 &ap_sdhci0 {
>> 114 pinctrl-names = "default";
>> 115 bus-width = <8>;
>> 116 mmc-ddr-1_8v;
>> 117 mmc-hs400-1_8v;
>> 118 vqmmc-supply = <&ap0_reg_sd_vccq>;
>> 119 status = "okay";
>> 120 };
>> 121
>> 122 &cp0_crypto {
>> 123 status = "disabled";
>> 124 };
>> 125
>> 126 &cp0_ethernet {
>> 127 status = "okay";
>> 128 };
>> 129
>> 130 /* SLM-1521-V2, CON9 */
>> 131 &cp0_eth0 {
>> 132 status = "disabled";
>> 133 phy-mode = "10gbase-kr";
>> 134 /* Generic PHY, providing serdes lanes */
>> 135 phys = <&cp0_comphy4 0>;
>> 136 managed = "in-band-status";
>> 137 sfp = <&cp0_sfp_eth0>;
12 }; 138 };
13 139
14 /* Setup A has SPI1 flash as a boot device, wh !! 140 /* CON56 */
15 * Since CP0 SPI1 and CP0 NAND are sharing som !! 141 &cp0_eth1 {
16 * simultaneously. When SPI controller is enab !! 142 status = "okay";
17 */ !! 143 phy = <&phy0>;
>> 144 phy-mode = "rgmii-id";
>> 145 };
>> 146
>> 147 /* CON57 */
>> 148 &cp0_eth2 {
>> 149 status = "okay";
>> 150 phy = <&phy1>;
>> 151 phy-mode = "rgmii-id";
>> 152 };
>> 153
>> 154 &cp0_gpio1 {
>> 155 status = "okay";
>> 156 };
>> 157
>> 158 &cp0_gpio2 {
>> 159 status = "okay";
>> 160 };
>> 161
>> 162 &cp0_i2c0 {
>> 163 status = "okay";
>> 164 pinctrl-names = "default";
>> 165 pinctrl-0 = <&cp0_i2c0_pins>;
>> 166 clock-frequency = <100000>;
>> 167
>> 168 /* U36 */
>> 169 expander0: pca953x@21 {
>> 170 compatible = "nxp,pca9555";
>> 171 pinctrl-names = "default";
>> 172 gpio-controller;
>> 173 #gpio-cells = <2>;
>> 174 reg = <0x21>;
>> 175 status = "okay";
>> 176 };
>> 177
>> 178 /* U42 */
>> 179 eeprom0: eeprom@50 {
>> 180 compatible = "atmel,24c64";
>> 181 reg = <0x50>;
>> 182 pagesize = <0x20>;
>> 183 };
>> 184
>> 185 /* U38 */
>> 186 eeprom1: eeprom@57 {
>> 187 compatible = "atmel,24c64";
>> 188 reg = <0x57>;
>> 189 pagesize = <0x20>;
>> 190 };
>> 191 };
18 192
>> 193 &cp0_i2c1 {
>> 194 status = "okay";
>> 195 clock-frequency = <100000>;
>> 196
>> 197 /* SLM-1521-V2 - U3 */
>> 198 i2c-mux@72 { /* verify address - depends on dpr */
>> 199 compatible = "nxp,pca9544";
>> 200 #address-cells = <1>;
>> 201 #size-cells = <0>;
>> 202 reg = <0x72>;
>> 203 cp0_sfpp0_i2c: i2c@0 {
>> 204 #address-cells = <1>;
>> 205 #size-cells = <0>;
>> 206 reg = <0>;
>> 207 };
>> 208
>> 209 i2c@1 {
>> 210 #address-cells = <1>;
>> 211 #size-cells = <0>;
>> 212 reg = <1>;
>> 213 /* U12 */
>> 214 cp0_module_expander1: pca9555@21 {
>> 215 compatible = "nxp,pca9555";
>> 216 pinctrl-names = "default";
>> 217 gpio-controller;
>> 218 #gpio-cells = <2>;
>> 219 reg = <0x21>;
>> 220 };
>> 221
>> 222 };
>> 223 };
>> 224 };
>> 225
>> 226 &cp0_mdio {
>> 227 status = "okay";
>> 228
>> 229 phy0: ethernet-phy@0 {
>> 230 reg = <0>;
>> 231 };
>> 232
>> 233 phy1: ethernet-phy@1 {
>> 234 reg = <1>;
>> 235 };
>> 236 };
>> 237
>> 238 /* U54 */
>> 239 &cp0_nand_controller {
>> 240 pinctrl-names = "default";
>> 241 pinctrl-0 = <&nand_pins &nand_rb>;
>> 242
>> 243 nand@0 {
>> 244 reg = <0>;
>> 245 label = "main-storage";
>> 246 nand-rb = <0>;
>> 247 nand-ecc-mode = "hw";
>> 248 nand-on-flash-bbt;
>> 249 nand-ecc-strength = <8>;
>> 250 nand-ecc-step-size = <512>;
>> 251
>> 252 partitions {
>> 253 compatible = "fixed-partitions";
>> 254 #address-cells = <1>;
>> 255 #size-cells = <1>;
>> 256
>> 257 partition@0 {
>> 258 label = "U-Boot";
>> 259 reg = <0 0x200000>;
>> 260 };
>> 261 partition@200000 {
>> 262 label = "Linux";
>> 263 reg = <0x200000 0xe00000>;
>> 264 };
>> 265 partition@1000000 {
>> 266 label = "Filesystem";
>> 267 reg = <0x1000000 0x3f000000>;
>> 268 };
>> 269 };
>> 270 };
>> 271 };
>> 272
>> 273 /* SLM-1521-V2, CON6 */
>> 274 &cp0_pcie0 {
>> 275 status = "okay";
>> 276 num-lanes = <4>;
>> 277 num-viewport = <8>;
>> 278 /* Generic PHY, providing serdes lanes */
>> 279 phys = <&cp0_comphy0 0
>> 280 &cp0_comphy1 0
>> 281 &cp0_comphy2 0
>> 282 &cp0_comphy3 0>;
>> 283 };
>> 284
>> 285 &cp0_sata0 {
>> 286 status = "okay";
>> 287
>> 288 /* SLM-1521-V2, CON2 */
>> 289 sata-port@1 {
>> 290 status = "okay";
>> 291 /* Generic PHY, providing serdes lanes */
>> 292 phys = <&cp0_comphy5 1>;
>> 293 };
>> 294 };
>> 295
>> 296 /* CON 28 */
>> 297 &cp0_sdhci0 {
>> 298 status = "okay";
>> 299 pinctrl-names = "default";
>> 300 pinctrl-0 = <&cp0_sdhci_pins
>> 301 &cp0_sdhci_cd_pins>;
>> 302 bus-width = <4>;
>> 303 cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
>> 304 no-1-8-v;
>> 305 vqmmc-supply = <&cp0_reg_sd_vccq>;
>> 306 vmmc-supply = <&cp0_reg_sd_vcc>;
>> 307 };
>> 308
>> 309 /* U55 */
19 &cp0_spi1 { 310 &cp0_spi1 {
20 status = "okay"; 311 status = "okay";
>> 312 pinctrl-names = "default";
>> 313 pinctrl-0 = <&cp0_spi0_pins>;
>> 314 reg = <0x700680 0x50>;
>> 315
>> 316 spi-flash@0 {
>> 317 #address-cells = <0x1>;
>> 318 #size-cells = <0x1>;
>> 319 compatible = "jedec,spi-nor";
>> 320 reg = <0x0>;
>> 321 /* On-board MUX does not allow higher frequencies */
>> 322 spi-max-frequency = <40000000>;
>> 323
>> 324 partitions {
>> 325 compatible = "fixed-partitions";
>> 326 #address-cells = <1>;
>> 327 #size-cells = <1>;
>> 328
>> 329 partition@0 {
>> 330 label = "U-Boot-0";
>> 331 reg = <0x0 0x200000>;
>> 332 };
>> 333
>> 334 partition@400000 {
>> 335 label = "Filesystem-0";
>> 336 reg = <0x200000 0xe00000>;
>> 337 };
>> 338 };
>> 339 };
>> 340 };
>> 341
>> 342 &cp0_syscon0 {
>> 343 cp0_pinctrl: pinctrl {
>> 344 compatible = "marvell,cp115-standalone-pinctrl";
>> 345
>> 346 cp0_i2c0_pins: cp0-i2c-pins-0 {
>> 347 marvell,pins = "mpp37", "mpp38";
>> 348 marvell,function = "i2c0";
>> 349 };
>> 350 cp0_i2c1_pins: cp0-i2c-pins-1 {
>> 351 marvell,pins = "mpp35", "mpp36";
>> 352 marvell,function = "i2c1";
>> 353 };
>> 354 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
>> 355 marvell,pins = "mpp0", "mpp1", "mpp2",
>> 356 "mpp3", "mpp4", "mpp5",
>> 357 "mpp6", "mpp7", "mpp8",
>> 358 "mpp9", "mpp10", "mpp11";
>> 359 marvell,function = "ge0";
>> 360 };
>> 361 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
>> 362 marvell,pins = "mpp44", "mpp45", "mpp46",
>> 363 "mpp47", "mpp48", "mpp49",
>> 364 "mpp50", "mpp51", "mpp52",
>> 365 "mpp53", "mpp54", "mpp55";
>> 366 marvell,function = "ge1";
>> 367 };
>> 368 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
>> 369 marvell,pins = "mpp43";
>> 370 marvell,function = "gpio";
>> 371 };
>> 372 cp0_sdhci_pins: cp0-sdhi-pins-0 {
>> 373 marvell,pins = "mpp56", "mpp57", "mpp58",
>> 374 "mpp59", "mpp60", "mpp61";
>> 375 marvell,function = "sdio";
>> 376 };
>> 377 cp0_spi0_pins: cp0-spi-pins-0 {
>> 378 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
>> 379 marvell,function = "spi1";
>> 380 };
>> 381 nand_pins: nand-pins {
>> 382 marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
>> 383 "mpp19", "mpp20", "mpp21", "mpp22",
>> 384 "mpp23", "mpp24", "mpp25", "mpp26",
>> 385 "mpp27";
>> 386 marvell,function = "dev";
>> 387 };
>> 388 nand_rb: nand-rb {
>> 389 marvell,pins = "mpp13";
>> 390 marvell,function = "nf";
>> 391 };
>> 392 };
>> 393 };
>> 394
>> 395 &cp0_utmi {
>> 396 status = "okay";
21 }; 397 };
22 398
>> 399 &cp0_usb3_0 {
>> 400 status = "okay";
>> 401 usb-phy = <&cp0_usb3_0_phy0>;
>> 402 phys = <&cp0_utmi0>;
>> 403 phy-names = "utmi";
>> 404 dr_mode = "host";
>> 405 };
>> 406
>> 407 &cp0_usb3_1 {
>> 408 status = "okay";
>> 409 usb-phy = <&cp0_usb3_0_phy1>;
>> 410 phys = <&cp0_utmi1>;
>> 411 phy-names = "utmi";
>> 412 dr_mode = "host";
>> 413 };
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