1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2024 Josua Mayer <josua@solid- 3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
4 * 4 *
5 * DTS for SolidRun CN9132 Clearfog. 5 * DTS for SolidRun CN9132 Clearfog.
6 * 6 *
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/leds/common.h>
13 13
14 #include "cn9130.dtsi" 14 #include "cn9130.dtsi"
15 #include "cn9132-sr-cex7.dtsi" 15 #include "cn9132-sr-cex7.dtsi"
16 16
17 / { 17 / {
18 model = "SolidRun CN9132 Clearfog"; 18 model = "SolidRun CN9132 Clearfog";
19 compatible = "solidrun,cn9132-clearfog 19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7" 20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
21 21
22 aliases { 22 aliases {
23 ethernet1 = &cp0_eth2; 23 ethernet1 = &cp0_eth2;
24 ethernet2 = &cp0_eth0; 24 ethernet2 = &cp0_eth0;
25 ethernet3 = &cp2_eth0; 25 ethernet3 = &cp2_eth0;
26 ethernet4 = &cp1_eth0; 26 ethernet4 = &cp1_eth0;
27 i2c7 = &carrier_mpcie_i2c; 27 i2c7 = &carrier_mpcie_i2c;
28 i2c8 = &carrier_ptp_i2c; 28 i2c8 = &carrier_ptp_i2c;
29 mmc1 = &cp0_sdhci0; 29 mmc1 = &cp0_sdhci0;
30 }; 30 };
31 31
32 gpio-keys { 32 gpio-keys {
33 compatible = "gpio-keys"; 33 compatible = "gpio-keys";
34 pinctrl-names = "default"; 34 pinctrl-names = "default";
35 pinctrl-0 = <&cp1_wake0_pins>; 35 pinctrl-0 = <&cp1_wake0_pins>;
36 36
37 button-0 { 37 button-0 {
38 label = "SW2"; 38 label = "SW2";
39 gpios = <&cp1_gpio2 8 39 gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
40 linux,can-disable; 40 linux,can-disable;
41 linux,code = <BTN_2>; 41 linux,code = <BTN_2>;
42 }; 42 };
43 }; 43 };
44 44
45 leds { 45 leds {
46 compatible = "gpio-leds"; 46 compatible = "gpio-leds";
47 pinctrl-names = "default"; 47 pinctrl-names = "default";
48 pinctrl-0 = <&cp1_batlow_pins 48 pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
49 49
50 /* LED11 */ 50 /* LED11 */
51 led-io-0 { 51 led-io-0 {
52 color = <LED_COLOR_ID_ 52 color = <LED_COLOR_ID_GREEN>;
53 function = LED_FUNCTIO 53 function = LED_FUNCTION_DISK;
54 function-enumerator = 54 function-enumerator = <0>;
55 default-state = "off"; 55 default-state = "off";
56 gpios = <&cp1_gpio1 11 56 gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
57 }; 57 };
58 58
59 /* LED12 */ 59 /* LED12 */
60 led-io-1 { 60 led-io-1 {
61 color = <LED_COLOR_ID_ 61 color = <LED_COLOR_ID_GREEN>;
62 function = LED_FUNCTIO 62 function = LED_FUNCTION_DISK;
63 function-enumerator = 63 function-enumerator = <1>;
64 default-state = "off"; 64 default-state = "off";
65 gpios = <&cp2_gpio1 4 65 gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
66 }; 66 };
67 }; 67 };
68 68
69 /* CON4 W_DISABLE1/W_DISABLE2 */ 69 /* CON4 W_DISABLE1/W_DISABLE2 */
70 rfkill-m2-wlan { 70 rfkill-m2-wlan {
71 compatible = "rfkill-gpio"; 71 compatible = "rfkill-gpio";
72 label = "m.2 wlan (CON4)"; 72 label = "m.2 wlan (CON4)";
73 radio-type = "wlan"; 73 radio-type = "wlan";
74 pinctrl-names = "default"; 74 pinctrl-names = "default";
75 pinctrl-0 = <&cp1_10g_phy_rst_ 75 pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
76 /* rfkill-gpio inverts interna 76 /* rfkill-gpio inverts internally */
77 shutdown-gpios = <&cp1_gpio2 1 77 shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
78 }; 78 };
79 79
80 /* CON5 W_DISABLE1/W_DISABLE2 */ 80 /* CON5 W_DISABLE1/W_DISABLE2 */
81 rfkill-m2-wlan { 81 rfkill-m2-wlan {
82 compatible = "rfkill-gpio"; 82 compatible = "rfkill-gpio";
83 label = "m.2 wlan (CON5)"; 83 label = "m.2 wlan (CON5)";
84 radio-type = "wlan"; 84 radio-type = "wlan";
85 pinctrl-names = "default"; 85 pinctrl-names = "default";
86 pinctrl-0 = <&cp1_10g_phy_rst_ 86 pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
87 /* rfkill-gpio inverts interna 87 /* rfkill-gpio inverts internally */
88 shutdown-gpios = <&cp1_gpio2 1 88 shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
89 }; 89 };
90 90
91 /* J21 W_DISABLE1 */ 91 /* J21 W_DISABLE1 */
92 rfkill-m2-wwan { 92 rfkill-m2-wwan {
93 compatible = "rfkill-gpio"; 93 compatible = "rfkill-gpio";
94 label = "m.2 wwan (J21)"; 94 label = "m.2 wwan (J21)";
95 radio-type = "wwan"; 95 radio-type = "wwan";
96 pinctrl-names = "default"; 96 pinctrl-names = "default";
97 pinctrl-0 = <&cp2_rsvd3_pins>; 97 pinctrl-0 = <&cp2_rsvd3_pins>;
98 /* rfkill-gpio inverts interna 98 /* rfkill-gpio inverts internally */
99 shutdown-gpios = <&cp2_gpio1 3 99 shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
100 }; 100 };
101 101
102 /* J21 W_DISABLE1 */ 102 /* J21 W_DISABLE1 */
103 rfkill-m2-gnss { 103 rfkill-m2-gnss {
104 compatible = "rfkill-gpio"; 104 compatible = "rfkill-gpio";
105 label = "m.2 gnss (J21)"; 105 label = "m.2 gnss (J21)";
106 radio-type = "gps"; 106 radio-type = "gps";
107 pinctrl-names = "default"; 107 pinctrl-names = "default";
108 pinctrl-0 = <&cp2_rsvd8_pins>; 108 pinctrl-0 = <&cp2_rsvd8_pins>;
109 /* rfkill-gpio inverts interna 109 /* rfkill-gpio inverts internally */
110 shutdown-gpios = <&cp2_gpio1 8 110 shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
111 }; 111 };
112 112
113 /* J14 W_DISABLE */ 113 /* J14 W_DISABLE */
114 rfkill-mpcie-wlan { 114 rfkill-mpcie-wlan {
115 compatible = "rfkill-gpio"; 115 compatible = "rfkill-gpio";
116 label = "mpcie wlan (J14)"; 116 label = "mpcie wlan (J14)";
117 radio-type = "wlan"; 117 radio-type = "wlan";
118 pinctrl-names = "default"; 118 pinctrl-names = "default";
119 pinctrl-0 = <&cp2_rsvd2_pins>; 119 pinctrl-0 = <&cp2_rsvd2_pins>;
120 /* rfkill-gpio inverts interna 120 /* rfkill-gpio inverts internally */
121 shutdown-gpios = <&cp2_gpio1 2 121 shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
122 }; 122 };
123 123
124 sfp: sfp { 124 sfp: sfp {
125 compatible = "sff,sfp"; 125 compatible = "sff,sfp";
126 i2c-bus = <&com_10g_sfp_i2c0>; 126 i2c-bus = <&com_10g_sfp_i2c0>;
127 pinctrl-names = "default"; 127 pinctrl-names = "default";
128 pinctrl-0 = <&com_10g_int0_pin 128 pinctrl-0 = <&com_10g_int0_pins>;
129 mod-def0-gpios = <&cp0_gpio1 2 129 mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
130 maximum-power-milliwatt = <200 130 maximum-power-milliwatt = <2000>;
131 }; 131 };
132 }; 132 };
133 133
134 &com_smbus { 134 &com_smbus {
135 /* This bus is also routed to STM32 BM 135 /* This bus is also routed to STM32 BMC Microcontroller (U2) */
136 136
137 power-sensor@40 { 137 power-sensor@40 {
138 compatible = "ti,ina220"; 138 compatible = "ti,ina220";
139 reg = <0x40>; 139 reg = <0x40>;
140 #io-channel-cells = <1>; 140 #io-channel-cells = <1>;
141 label = "vdd_12v0"; 141 label = "vdd_12v0";
142 shunt-resistor = <2000>; 142 shunt-resistor = <2000>;
143 }; 143 };
144 144
145 adc@48 { 145 adc@48 {
146 compatible = "ti,tla2021"; 146 compatible = "ti,tla2021";
147 reg = <0x48>; 147 reg = <0x48>;
148 #address-cells = <1>; 148 #address-cells = <1>;
149 #size-cells = <0>; 149 #size-cells = <0>;
150 150
151 /* supplied by chaoskey hardwa 151 /* supplied by chaoskey hardware noise generator circuit */
152 channel@0 { 152 channel@0 {
153 reg = <0>; 153 reg = <0>;
154 }; 154 };
155 }; 155 };
156 }; 156 };
157 157
158 &cp0_eth_phy0 { 158 &cp0_eth_phy0 {
159 /* 159 /*
160 * Configure LEDs default behaviour: 160 * Configure LEDs default behaviour:
161 * - LED[0]: link is 1000Mbps: On (yel 161 * - LED[0]: link is 1000Mbps: On (yellow): 0111
162 * - LED[1]: link/activity: On/Blink ( 162 * - LED[1]: link/activity: On/Blink (green): 0001
163 * - LED[2]: Off (green): 1000 163 * - LED[2]: Off (green): 1000
164 */ 164 */
165 marvell,reg-init = <3 16 0xf000 0x0817 165 marvell,reg-init = <3 16 0xf000 0x0817>;
166 166
167 leds { 167 leds {
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 170
171 led@0 { 171 led@0 {
172 /* link */ 172 /* link */
173 reg = <0>; 173 reg = <0>;
174 color = <LED_COLOR_ID_ 174 color = <LED_COLOR_ID_YELLOW>;
175 function = LED_FUNCTIO 175 function = LED_FUNCTION_LAN;
176 default-state = "keep" 176 default-state = "keep";
177 }; 177 };
178 178
179 led@1 { 179 led@1 {
180 /* act */ 180 /* act */
181 reg = <1>; 181 reg = <1>;
182 color = <LED_COLOR_ID_ 182 color = <LED_COLOR_ID_GREEN>;
183 function = LED_FUNCTIO 183 function = LED_FUNCTION_LAN;
184 default-state = "keep" 184 default-state = "keep";
185 }; 185 };
186 186
187 led@2 { 187 led@2 {
188 /* 1000 */ 188 /* 1000 */
189 reg = <2>; 189 reg = <2>;
190 color = <LED_COLOR_ID_ 190 color = <LED_COLOR_ID_GREEN>;
191 function = LED_FUNCTIO 191 function = LED_FUNCTION_LAN;
192 default-state = "keep" 192 default-state = "keep";
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 196
197 /* SRDS #4 - 10GE */ 197 /* SRDS #4 - 10GE */
198 &cp0_eth0 { 198 &cp0_eth0 {
199 phys = <&cp0_comphy4 0>; 199 phys = <&cp0_comphy4 0>;
200 phy-mode = "10gbase-r"; 200 phy-mode = "10gbase-r";
201 managed = "in-band-status"; 201 managed = "in-band-status";
202 sfp = <&sfp>; 202 sfp = <&sfp>;
203 status = "okay"; 203 status = "okay";
204 }; 204 };
205 205
206 &cp0_eth2 { 206 &cp0_eth2 {
207 phy-mode = "2500base-x"; 207 phy-mode = "2500base-x";
208 phys = <&cp0_comphy5 2>; 208 phys = <&cp0_comphy5 2>;
209 status = "okay"; 209 status = "okay";
210 210
211 fixed-link { 211 fixed-link {
212 speed = <2500>; 212 speed = <2500>;
213 full-duplex; 213 full-duplex;
214 pause; 214 pause;
215 }; 215 };
216 }; 216 };
217 217
218 &cp0_i2c1 { 218 &cp0_i2c1 {
219 /* 219 /*
220 * Both COM and Carrier Board have a P 220 * Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
221 * Describe them as a single device me 221 * Describe them as a single device merging each child bus.
222 */ 222 */
223 223
224 i2c-mux@77 { 224 i2c-mux@77 {
225 i2c@0 { 225 i2c@0 {
226 /* Routed to Full PCIe 226 /* Routed to Full PCIe (J4) */
227 }; 227 };
228 228
229 i2c@1 { 229 i2c@1 {
230 /* Routed to USB Hub ( 230 /* Routed to USB Hub (U29) */
231 }; 231 };
232 232
233 i2c@2 { 233 i2c@2 {
234 /* Routed to M.2 (CON4 234 /* Routed to M.2 (CON4) */
235 }; 235 };
236 236
237 i2c@3 { 237 i2c@3 {
238 /* Routed to M.2 (CON5 238 /* Routed to M.2 (CON5) */
239 }; 239 };
240 240
241 i2c@4 { 241 i2c@4 {
242 /* Routed to M.2 (J21) 242 /* Routed to M.2 (J21) */
243 }; 243 };
244 244
245 carrier_mpcie_i2c: i2c@5 { 245 carrier_mpcie_i2c: i2c@5 {
246 #address-cells = <1>; 246 #address-cells = <1>;
247 #size-cells = <0>; 247 #size-cells = <0>;
248 reg = <5>; 248 reg = <5>;
249 249
250 /* Routed to mini-PCIe 250 /* Routed to mini-PCIe (J14) */
251 }; 251 };
252 252
253 carrier_ptp_i2c: i2c@6 { 253 carrier_ptp_i2c: i2c@6 {
254 #address-cells = <1>; 254 #address-cells = <1>;
255 #size-cells = <0>; 255 #size-cells = <0>;
256 reg = <6>; 256 reg = <6>;
257 257
258 /* Routed to various o 258 /* Routed to various optional PTP related components */
259 }; 259 };
260 }; 260 };
261 }; 261 };
262 262
263 &cp0_mdio { 263 &cp0_mdio {
264 ethernet-switch@4 { 264 ethernet-switch@4 {
265 compatible = "marvell,mv88e608 265 compatible = "marvell,mv88e6085";
266 reg = <4>; 266 reg = <4>;
267 267
268 mdio { 268 mdio {
269 #address-cells = <1>; 269 #address-cells = <1>;
270 #size-cells = <0>; 270 #size-cells = <0>;
271 271
272 sw_phy1: ethernet-phy@ 272 sw_phy1: ethernet-phy@1 {
273 reg = <0x11>; 273 reg = <0x11>;
274 }; 274 };
275 275
276 sw_phy2: ethernet-phy@ 276 sw_phy2: ethernet-phy@2 {
277 reg = <0x12>; 277 reg = <0x12>;
278 }; 278 };
279 279
280 sw_phy3: ethernet-phy@ 280 sw_phy3: ethernet-phy@3 {
281 reg = <0x13>; 281 reg = <0x13>;
282 }; 282 };
283 283
284 sw_phy4: ethernet-phy@ 284 sw_phy4: ethernet-phy@4 {
285 reg = <0x14>; 285 reg = <0x14>;
286 }; 286 };
287 }; 287 };
288 288
289 ethernet-ports { 289 ethernet-ports {
290 #address-cells = <1>; 290 #address-cells = <1>;
291 #size-cells = <0>; 291 #size-cells = <0>;
292 292
293 ethernet-port@1 { 293 ethernet-port@1 {
294 reg = <1>; 294 reg = <1>;
295 label = "lan1" 295 label = "lan1";
296 phy-handle = < 296 phy-handle = <&sw_phy1>;
297 phy-mode = "in 297 phy-mode = "internal";
298 298
299 leds { 299 leds {
300 #addre 300 #address-cells = <1>;
301 #size- 301 #size-cells = <0>;
302 302
303 led@0 303 led@0 {
304 304 reg = <0>;
305 305 color = <LED_COLOR_ID_GREEN>;
306 306 function = LED_FUNCTION_LAN;
307 307 default-state = "keep";
308 }; 308 };
309 309
310 led@1 310 led@1 {
311 311 reg = <1>;
312 312 color = <LED_COLOR_ID_YELLOW>;
313 313 function = LED_FUNCTION_LAN;
314 314 default-state = "keep";
315 }; 315 };
316 }; 316 };
317 }; 317 };
318 318
319 ethernet-port@2 { 319 ethernet-port@2 {
320 reg = <2>; 320 reg = <2>;
321 label = "lan2" 321 label = "lan2";
322 phy-handle = < 322 phy-handle = <&sw_phy2>;
323 phy-mode = "in 323 phy-mode = "internal";
324 324
325 leds { 325 leds {
326 #addre 326 #address-cells = <1>;
327 #size- 327 #size-cells = <0>;
328 328
329 led@0 329 led@0 {
330 330 reg = <0>;
331 331 color = <LED_COLOR_ID_GREEN>;
332 332 function = LED_FUNCTION_LAN;
333 333 default-state = "keep";
334 }; 334 };
335 335
336 led@1 336 led@1 {
337 337 reg = <1>;
338 338 color = <LED_COLOR_ID_YELLOW>;
339 339 function = LED_FUNCTION_LAN;
340 340 default-state = "keep";
341 }; 341 };
342 }; 342 };
343 }; 343 };
344 344
345 ethernet-port@3 { 345 ethernet-port@3 {
346 reg = <3>; 346 reg = <3>;
347 label = "lan3" 347 label = "lan3";
348 phy-handle = < 348 phy-handle = <&sw_phy3>;
349 phy-mode = "in 349 phy-mode = "internal";
350 350
351 leds { 351 leds {
352 #addre 352 #address-cells = <1>;
353 #size- 353 #size-cells = <0>;
354 354
355 led@0 355 led@0 {
356 356 reg = <0>;
357 357 color = <LED_COLOR_ID_GREEN>;
358 358 function = LED_FUNCTION_LAN;
359 359 default-state = "keep";
360 }; 360 };
361 361
362 led@1 362 led@1 {
363 363 reg = <1>;
364 364 color = <LED_COLOR_ID_YELLOW>;
365 365 function = LED_FUNCTION_LAN;
366 366 default-state = "keep";
367 }; 367 };
368 }; 368 };
369 }; 369 };
370 370
371 ethernet-port@4 { 371 ethernet-port@4 {
372 reg = <4>; 372 reg = <4>;
373 label = "lan4" 373 label = "lan4";
374 phy-handle = < 374 phy-handle = <&sw_phy4>;
375 phy-mode = "in 375 phy-mode = "internal";
376 376
377 leds { 377 leds {
378 #addre 378 #address-cells = <1>;
379 #size- 379 #size-cells = <0>;
380 380
381 led@0 381 led@0 {
382 382 reg = <0>;
383 383 color = <LED_COLOR_ID_GREEN>;
384 384 function = LED_FUNCTION_LAN;
385 385 default-state = "keep";
386 }; 386 };
387 387
388 led@1 388 led@1 {
389 389 reg = <1>;
390 390 color = <LED_COLOR_ID_YELLOW>;
391 391 function = LED_FUNCTION_LAN;
392 392 default-state = "keep";
393 }; 393 };
394 }; 394 };
395 }; 395 };
396 396
397 ethernet-port@5 { 397 ethernet-port@5 {
398 reg = <5>; 398 reg = <5>;
399 label = "cpu"; 399 label = "cpu";
400 ethernet = <&c 400 ethernet = <&cp0_eth2>;
401 phy-mode = "25 401 phy-mode = "2500base-x";
402 402
403 fixed-link { 403 fixed-link {
404 speed 404 speed = <2500>;
405 full-d 405 full-duplex;
406 pause; 406 pause;
407 }; 407 };
408 }; 408 };
409 }; 409 };
410 }; 410 };
411 }; 411 };
412 412
413 /* SRDS #0,#1,#2,#3 - PCIe */ 413 /* SRDS #0,#1,#2,#3 - PCIe */
414 &cp0_pcie0 { 414 &cp0_pcie0 {
415 num-lanes = <4>; 415 num-lanes = <4>;
416 phys = <&cp0_comphy0 0>, <&cp0_comphy1 416 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
417 status = "okay"; 417 status = "okay";
418 }; 418 };
419 419
420 &cp0_pinctrl { 420 &cp0_pinctrl {
421 /* 421 /*
422 * configure unused gpios exposed via 422 * configure unused gpios exposed via pin headers:
423 * - J7-10: PWRBTN 423 * - J7-10: PWRBTN
424 */ 424 */
425 pinctrl-names = "default"; 425 pinctrl-names = "default";
426 pinctrl-0 = <&cp0_pwrbtn_pins>; 426 pinctrl-0 = <&cp0_pwrbtn_pins>;
427 }; 427 };
428 428
429 /* microSD */ 429 /* microSD */
430 &cp0_sdhci0 { 430 &cp0_sdhci0 {
431 pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mm 431 pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
432 pinctrl-names = "default"; 432 pinctrl-names = "default";
433 bus-width = <4>; 433 bus-width = <4>;
434 no-1-8-v; 434 no-1-8-v;
435 status = "okay"; 435 status = "okay";
436 }; 436 };
437 437
438 &cp0_spi1 { 438 &cp0_spi1 {
439 /* add CS1 */ 439 /* add CS1 */
440 pinctrl-0 = <&cp0_spi1_pins>, <&cp0_sp 440 pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
441 441
442 flash@1 { 442 flash@1 {
443 compatible = "jedec,spi-nor"; 443 compatible = "jedec,spi-nor";
444 reg = <1>; 444 reg = <1>;
445 /* read command supports max. 445 /* read command supports max. 50MHz */
446 spi-max-frequency = <50000000> 446 spi-max-frequency = <50000000>;
447 }; 447 };
448 }; 448 };
449 449
450 /* J38 */ 450 /* J38 */
451 &cp0_uart2 { 451 &cp0_uart2 {
452 pinctrl-names = "default"; 452 pinctrl-names = "default";
453 pinctrl-0 = <&cp0_uart2_pins>; 453 pinctrl-0 = <&cp0_uart2_pins>;
454 status = "okay"; 454 status = "okay";
455 }; 455 };
456 456
457 &cp0_utmi { 457 &cp0_utmi {
458 /* M.2 "CON5" swaps D+/D- */ 458 /* M.2 "CON5" swaps D+/D- */
459 swap-dx-lanes = <1>; 459 swap-dx-lanes = <1>;
460 }; 460 };
461 461
462 &cp1_ethernet { 462 &cp1_ethernet {
463 status = "okay"; 463 status = "okay";
464 }; 464 };
465 465
466 /* SRDS #2 - 5GE */ 466 /* SRDS #2 - 5GE */
467 &cp1_eth0 { 467 &cp1_eth0 {
468 phys = <&cp1_comphy2 0>; 468 phys = <&cp1_comphy2 0>;
469 phy-mode = "5gbase-r"; 469 phy-mode = "5gbase-r";
470 phy = <&cp1_eth_phy0>; 470 phy = <&cp1_eth_phy0>;
471 managed = "in-band-status"; 471 managed = "in-band-status";
472 status = "okay"; 472 status = "okay";
473 }; 473 };
474 474
475 /* SRDS #0,#1 - PCIe */ 475 /* SRDS #0,#1 - PCIe */
476 &cp1_pcie0 { 476 &cp1_pcie0 {
477 num-lanes = <2>; 477 num-lanes = <2>;
478 phys = <&cp1_comphy0 0>, <&cp1_comphy1 478 phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
479 status = "okay"; 479 status = "okay";
480 }; 480 };
481 481
482 /* SRDS #4 - PCIe */ 482 /* SRDS #4 - PCIe */
483 &cp1_pcie1 { 483 &cp1_pcie1 {
484 num-lanes = <1>; 484 num-lanes = <1>;
485 phys = <&cp1_comphy4 1>; 485 phys = <&cp1_comphy4 1>;
486 status = "okay"; 486 status = "okay";
487 }; 487 };
488 488
489 /* SRDS #5 - PCIe */ 489 /* SRDS #5 - PCIe */
490 &cp1_pcie2 { 490 &cp1_pcie2 {
491 num-lanes = <1>; 491 num-lanes = <1>;
492 phys = <&cp1_comphy5 2>; 492 phys = <&cp1_comphy5 2>;
493 status = "okay"; 493 status = "okay";
494 }; 494 };
495 495
496 &cp1_pinctrl { 496 &cp1_pinctrl {
497 /* 497 /*
498 * configure unused gpios exposed via 498 * configure unused gpios exposed via pin headers:
499 * - J7-8: RSVD16 499 * - J7-8: RSVD16
500 * - J7-10: THRM 500 * - J7-10: THRM
501 * - J10-1: WAKE1 501 * - J10-1: WAKE1
502 * - J10-2: SATA_ACT 502 * - J10-2: SATA_ACT
503 * - J10-8: THERMTRIP 503 * - J10-8: THERMTRIP
504 */ 504 */
505 pinctrl-names = "default"; 505 pinctrl-names = "default";
506 pinctrl-0 = <&cp1_rsvd16_pins &cp1_sat 506 pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
507 <&cp1_thrm_trip_pins &cp1_ 507 <&cp1_thrm_trip_pins &cp1_wake1_pins>;
508 }; 508 };
509 509
510 /* SRDS #3 - SATA */ 510 /* SRDS #3 - SATA */
511 &cp1_sata0 { 511 &cp1_sata0 {
512 status = "okay"; 512 status = "okay";
513 513
514 /* only port 1 is available */ 514 /* only port 1 is available */
515 /delete-node/ sata-port@0; 515 /delete-node/ sata-port@0;
516 516
517 sata-port@1 { 517 sata-port@1 {
518 phys = <&cp1_comphy3 1>; 518 phys = <&cp1_comphy3 1>;
519 }; 519 };
520 }; 520 };
521 521
522 &cp1_utmi { 522 &cp1_utmi {
523 /* M.2 "CON4" swaps D+/D- */ 523 /* M.2 "CON4" swaps D+/D- */
524 swap-dx-lanes = <0>; 524 swap-dx-lanes = <0>;
525 }; 525 };
526 526
527 &cp1_xmdio { 527 &cp1_xmdio {
528 pinctrl-names = "default"; 528 pinctrl-names = "default";
529 pinctrl-0 = <&cp1_xmdio_pins>; 529 pinctrl-0 = <&cp1_xmdio_pins>;
530 status = "okay"; 530 status = "okay";
531 531
532 cp1_eth_phy0: ethernet-phy@8 { 532 cp1_eth_phy0: ethernet-phy@8 {
533 compatible = "ethernet-phy-iee 533 compatible = "ethernet-phy-ieee802.3-c45";
534 reg = <8>; 534 reg = <8>;
535 pinctrl-names = "default"; 535 pinctrl-names = "default";
536 pinctrl-0 = <&com_10g_int1_pin 536 pinctrl-0 = <&com_10g_int1_pins>;
537 interrupt-parent = <&cp1_gpio2 537 interrupt-parent = <&cp1_gpio2>;
538 interrupts = <18 IRQ_TYPE_EDGE 538 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
539 539
540 leds { 540 leds {
541 #address-cells = <1>; 541 #address-cells = <1>;
542 #size-cells = <0>; 542 #size-cells = <0>;
543 543
544 led@1 { 544 led@1 {
545 reg = <1>; 545 reg = <1>;
546 color = <LED_C 546 color = <LED_COLOR_ID_YELLOW>;
547 function = LED 547 function = LED_FUNCTION_LAN;
548 default-state 548 default-state = "keep";
549 }; 549 };
550 550
551 led@2 { 551 led@2 {
552 reg = <2>; 552 reg = <2>;
553 color = <LED_C 553 color = <LED_COLOR_ID_GREEN>;
554 function = LED 554 function = LED_FUNCTION_LAN;
555 default-state 555 default-state = "keep";
556 }; 556 };
557 }; 557 };
558 }; 558 };
559 }; 559 };
560 560
561 &cp2_ethernet { 561 &cp2_ethernet {
562 status = "okay"; 562 status = "okay";
563 }; 563 };
564 564
565 /* SRDS #2 - 5GE */ 565 /* SRDS #2 - 5GE */
566 &cp2_eth0 { 566 &cp2_eth0 {
567 phys = <&cp2_comphy2 0>; 567 phys = <&cp2_comphy2 0>;
568 phy-mode = "5gbase-r"; 568 phy-mode = "5gbase-r";
569 phy = <&cp2_eth_phy0>; 569 phy = <&cp2_eth_phy0>;
570 managed = "in-band-status"; 570 managed = "in-band-status";
571 status = "okay"; 571 status = "okay";
572 }; 572 };
573 573
574 &cp2_gpio1 { 574 &cp2_gpio1 {
575 pinctrl-names= "default"; 575 pinctrl-names= "default";
576 pinctrl-0 = <&cp2_rsvd9_pins>; 576 pinctrl-0 = <&cp2_rsvd9_pins>;
577 577
578 /* J21 */ 578 /* J21 */
579 m2-wwan-reset-hog { 579 m2-wwan-reset-hog {
580 gpio-hog; 580 gpio-hog;
581 gpios = <9 (GPIO_ACTIVE_LOW | 581 gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
582 output-low; 582 output-low;
583 line-name = "m2-wwan-reset"; 583 line-name = "m2-wwan-reset";
584 }; 584 };
585 }; 585 };
586 586
587 /* SRDS #0 - PCIe */ 587 /* SRDS #0 - PCIe */
588 &cp2_pcie0 { 588 &cp2_pcie0 {
589 num-lanes = <1>; 589 num-lanes = <1>;
590 phys = <&cp2_comphy0 0>; 590 phys = <&cp2_comphy0 0>;
591 status = "okay"; 591 status = "okay";
592 }; 592 };
593 593
594 /* SRDS #4 - PCIe */ 594 /* SRDS #4 - PCIe */
595 &cp2_pcie1 { 595 &cp2_pcie1 {
596 num-lanes = <1>; 596 num-lanes = <1>;
597 phys = <&cp2_comphy4 1>; 597 phys = <&cp2_comphy4 1>;
598 status = "okay"; 598 status = "okay";
599 }; 599 };
600 600
601 /* SRDS #5 - PCIe */ 601 /* SRDS #5 - PCIe */
602 &cp2_pcie2 { 602 &cp2_pcie2 {
603 num-lanes = <1>; 603 num-lanes = <1>;
604 phys = <&cp2_comphy5 2>; 604 phys = <&cp2_comphy5 2>;
605 status = "okay"; 605 status = "okay";
606 }; 606 };
607 607
608 &cp2_pinctrl { 608 &cp2_pinctrl {
609 /* 609 /*
610 * configure unused gpios exposed via 610 * configure unused gpios exposed via pin headers:
611 * - J7-1: RSVD10 611 * - J7-1: RSVD10
612 * - J7-3: RSVD11 612 * - J7-3: RSVD11
613 * - J7-5: RSVD56 613 * - J7-5: RSVD56
614 * - J7-6: RSVD7 614 * - J7-6: RSVD7
615 * - J7-7: RSVD27 615 * - J7-7: RSVD27
616 * - J10-3: RSVD31 616 * - J10-3: RSVD31
617 * - J10-5: RSVD5 617 * - J10-5: RSVD5
618 * - J10-6: RSVD32 618 * - J10-6: RSVD32
619 * - J10-7: RSVD0 619 * - J10-7: RSVD0
620 * - J10-9: RSVD1 620 * - J10-9: RSVD1
621 */ 621 */
622 pinctrl-names = "default"; 622 pinctrl-names = "default";
623 pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd 623 pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
624 <&cp2_rsvd7_pins &cp2_rsvd 624 <&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
625 <&cp2_rsvd27_pins &cp2_rsv 625 <&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
626 <&cp2_rsvd56_pins>; 626 <&cp2_rsvd56_pins>;
627 }; 627 };
628 628
629 /* SRDS #3 - SATA */ 629 /* SRDS #3 - SATA */
630 &cp2_sata0 { 630 &cp2_sata0 {
631 status = "okay"; 631 status = "okay";
632 632
633 /* only port 1 is available */ 633 /* only port 1 is available */
634 /delete-node/ sata-port@0; 634 /delete-node/ sata-port@0;
635 635
636 sata-port@1 { 636 sata-port@1 {
637 phys = <&cp2_comphy3 1>; 637 phys = <&cp2_comphy3 1>;
638 }; 638 };
639 }; 639 };
640 640
641 &cp2_xmdio { 641 &cp2_xmdio {
642 pinctrl-names = "default"; 642 pinctrl-names = "default";
643 pinctrl-0 = <&cp2_xmdio_pins>; 643 pinctrl-0 = <&cp2_xmdio_pins>;
644 status = "okay"; 644 status = "okay";
645 645
646 cp2_eth_phy0: ethernet-phy@8 { 646 cp2_eth_phy0: ethernet-phy@8 {
647 compatible = "ethernet-phy-iee 647 compatible = "ethernet-phy-ieee802.3-c45";
648 reg = <8>; 648 reg = <8>;
649 pinctrl-names = "default"; 649 pinctrl-names = "default";
650 pinctrl-0 = <&com_10g_int2_pin 650 pinctrl-0 = <&com_10g_int2_pins>;
651 interrupt-parent = <&cp2_gpio2 651 interrupt-parent = <&cp2_gpio2>;
652 interrupts = <18 IRQ_TYPE_EDGE 652 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
653 653
654 leds { 654 leds {
655 #address-cells = <1>; 655 #address-cells = <1>;
656 #size-cells = <0>; 656 #size-cells = <0>;
657 657
658 led@1 { 658 led@1 {
659 reg = <1>; 659 reg = <1>;
660 color = <LED_C 660 color = <LED_COLOR_ID_YELLOW>;
661 function = LED 661 function = LED_FUNCTION_LAN;
662 default-state 662 default-state = "keep";
663 }; 663 };
664 664
665 led@2 { 665 led@2 {
666 reg = <2>; 666 reg = <2>;
667 color = <LED_C 667 color = <LED_COLOR_ID_GREEN>;
668 function = LED 668 function = LED_FUNCTION_LAN;
669 default-state 669 default-state = "keep";
670 }; 670 };
671 }; 671 };
672 }; 672 };
673 }; 673 };
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