1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2019 Marvell International Lt 3 * Copyright (C) 2019 Marvell International Ltd.
4 * 4 *
5 * Device tree for the CN9132-DB board. 5 * Device tree for the CN9132-DB board.
6 */ 6 */
7 7
8 #include "cn9132-db.dtsi" 8 #include "cn9132-db.dtsi"
9 9
10 / { 10 / {
11 model = "Marvell Armada CN9132-DB setu 11 model = "Marvell Armada CN9132-DB setup B";
12 }; 12 };
13 13
14 /* Setup B has NAND flash as a boot device, wh 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing som 15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is ena 16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
17 */ 17 */
18 18
19 &cp0_nand_controller { 19 &cp0_nand_controller {
20 status = "okay"; 20 status = "okay";
21 }; 21 };
22 22
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