1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2015 MediaTek Inc. 3 * Copyright (c) 2015 MediaTek Inc.
4 * Copyright (C) 2023 Collabora Ltd. !! 4 * Author: Mars.C <mars.cheng@mediatek.com>
5 * Authors: Mars.C <mars.cheng@mediatek.com> <<
6 * AngeloGioacchino Del Regno <angelog <<
7 */ 5 */
8 6
9 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-cl 9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce. <<
13 #include <dt-bindings/memory/mt6795-larb-port. <<
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h 10 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h> <<
16 #include <dt-bindings/reset/mediatek,mt6795-re 11 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
17 12
18 / { 13 / {
19 compatible = "mediatek,mt6795"; 14 compatible = "mediatek,mt6795";
20 interrupt-parent = <&sysirq>; 15 interrupt-parent = <&sysirq>;
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 aliases { <<
25 ovl0 = &ovl0; <<
26 ovl1 = &ovl1; <<
27 rdma0 = &rdma0; <<
28 rdma1 = &rdma1; <<
29 rdma2 = &rdma2; <<
30 wdma0 = &wdma0; <<
31 wdma1 = &wdma1; <<
32 color0 = &color0; <<
33 color1 = &color1; <<
34 split0 = &split0; <<
35 split1 = &split1; <<
36 dpi0 = &dpi0; <<
37 dsi0 = &dsi0; <<
38 dsi1 = &dsi1; <<
39 }; <<
40 <<
41 psci { 19 psci {
42 compatible = "arm,psci-0.2"; 20 compatible = "arm,psci-0.2";
43 method = "smc"; 21 method = "smc";
44 }; 22 };
45 23
46 cpus { 24 cpus {
47 #address-cells = <1>; 25 #address-cells = <1>;
48 #size-cells = <0>; 26 #size-cells = <0>;
49 27
50 cpu0: cpu@0 { 28 cpu0: cpu@0 {
51 device_type = "cpu"; 29 device_type = "cpu";
52 compatible = "arm,cort 30 compatible = "arm,cortex-a53";
53 enable-method = "psci" 31 enable-method = "psci";
54 reg = <0x000>; 32 reg = <0x000>;
55 cci-control-port = <&c 33 cci-control-port = <&cci_control2>;
56 next-level-cache = <&l 34 next-level-cache = <&l2_0>;
57 }; 35 };
58 36
59 cpu1: cpu@1 { 37 cpu1: cpu@1 {
60 device_type = "cpu"; 38 device_type = "cpu";
61 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
62 enable-method = "psci" 40 enable-method = "psci";
63 reg = <0x001>; 41 reg = <0x001>;
64 cci-control-port = <&c 42 cci-control-port = <&cci_control2>;
65 i-cache-size = <32768> <<
66 i-cache-line-size = <6 <<
67 i-cache-sets = <256>; <<
68 d-cache-size = <32768> <<
69 d-cache-line-size = <6 <<
70 d-cache-sets = <128>; <<
71 next-level-cache = <&l 43 next-level-cache = <&l2_0>;
72 }; 44 };
73 45
74 cpu2: cpu@2 { 46 cpu2: cpu@2 {
75 device_type = "cpu"; 47 device_type = "cpu";
76 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
77 enable-method = "psci" 49 enable-method = "psci";
78 reg = <0x002>; 50 reg = <0x002>;
79 cci-control-port = <&c 51 cci-control-port = <&cci_control2>;
80 i-cache-size = <32768> <<
81 i-cache-line-size = <6 <<
82 i-cache-sets = <256>; <<
83 d-cache-size = <32768> <<
84 d-cache-line-size = <6 <<
85 d-cache-sets = <128>; <<
86 next-level-cache = <&l 52 next-level-cache = <&l2_0>;
87 }; 53 };
88 54
89 cpu3: cpu@3 { 55 cpu3: cpu@3 {
90 device_type = "cpu"; 56 device_type = "cpu";
91 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
92 enable-method = "psci" 58 enable-method = "psci";
93 reg = <0x003>; 59 reg = <0x003>;
94 cci-control-port = <&c 60 cci-control-port = <&cci_control2>;
95 i-cache-size = <32768> <<
96 i-cache-line-size = <6 <<
97 i-cache-sets = <256>; <<
98 d-cache-size = <32768> <<
99 d-cache-line-size = <6 <<
100 d-cache-sets = <128>; <<
101 next-level-cache = <&l 61 next-level-cache = <&l2_0>;
102 }; 62 };
103 63
104 cpu4: cpu@100 { 64 cpu4: cpu@100 {
105 device_type = "cpu"; 65 device_type = "cpu";
106 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
107 enable-method = "psci" 67 enable-method = "psci";
108 reg = <0x100>; 68 reg = <0x100>;
109 cci-control-port = <&c 69 cci-control-port = <&cci_control1>;
110 i-cache-size = <32768> <<
111 i-cache-line-size = <6 <<
112 i-cache-sets = <256>; <<
113 d-cache-size = <32768> <<
114 d-cache-line-size = <6 <<
115 d-cache-sets = <128>; <<
116 next-level-cache = <&l 70 next-level-cache = <&l2_1>;
117 }; 71 };
118 72
119 cpu5: cpu@101 { 73 cpu5: cpu@101 {
120 device_type = "cpu"; 74 device_type = "cpu";
121 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
122 enable-method = "psci" 76 enable-method = "psci";
123 reg = <0x101>; 77 reg = <0x101>;
124 cci-control-port = <&c 78 cci-control-port = <&cci_control1>;
125 i-cache-size = <32768> <<
126 i-cache-line-size = <6 <<
127 i-cache-sets = <256>; <<
128 d-cache-size = <32768> <<
129 d-cache-line-size = <6 <<
130 d-cache-sets = <128>; <<
131 next-level-cache = <&l 79 next-level-cache = <&l2_1>;
132 }; 80 };
133 81
134 cpu6: cpu@102 { 82 cpu6: cpu@102 {
135 device_type = "cpu"; 83 device_type = "cpu";
136 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
137 enable-method = "psci" 85 enable-method = "psci";
138 reg = <0x102>; 86 reg = <0x102>;
139 cci-control-port = <&c 87 cci-control-port = <&cci_control1>;
140 i-cache-size = <32768> <<
141 i-cache-line-size = <6 <<
142 i-cache-sets = <256>; <<
143 d-cache-size = <32768> <<
144 d-cache-line-size = <6 <<
145 d-cache-sets = <128>; <<
146 next-level-cache = <&l 88 next-level-cache = <&l2_1>;
147 }; 89 };
148 90
149 cpu7: cpu@103 { 91 cpu7: cpu@103 {
150 device_type = "cpu"; 92 device_type = "cpu";
151 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
152 enable-method = "psci" 94 enable-method = "psci";
153 reg = <0x103>; 95 reg = <0x103>;
154 cci-control-port = <&c 96 cci-control-port = <&cci_control1>;
155 i-cache-size = <32768> <<
156 i-cache-line-size = <6 <<
157 i-cache-sets = <256>; <<
158 d-cache-size = <32768> <<
159 d-cache-line-size = <6 <<
160 d-cache-sets = <128>; <<
161 next-level-cache = <&l 97 next-level-cache = <&l2_1>;
162 }; 98 };
163 99
164 cpu-map { 100 cpu-map {
165 cluster0 { 101 cluster0 {
166 core0 { 102 core0 {
167 cpu = 103 cpu = <&cpu0>;
168 }; 104 };
169 105
170 core1 { 106 core1 {
171 cpu = 107 cpu = <&cpu1>;
172 }; 108 };
173 109
174 core2 { 110 core2 {
175 cpu = 111 cpu = <&cpu2>;
176 }; 112 };
177 113
178 core3 { 114 core3 {
179 cpu = 115 cpu = <&cpu3>;
180 }; 116 };
181 }; 117 };
182 118
183 cluster1 { 119 cluster1 {
184 core0 { 120 core0 {
185 cpu = 121 cpu = <&cpu4>;
186 }; 122 };
187 123
188 core1 { 124 core1 {
189 cpu = 125 cpu = <&cpu5>;
190 }; 126 };
191 127
192 core2 { 128 core2 {
193 cpu = 129 cpu = <&cpu6>;
194 }; 130 };
195 131
196 core3 { 132 core3 {
197 cpu = 133 cpu = <&cpu7>;
198 }; 134 };
199 }; 135 };
200 }; 136 };
201 137
202 l2_0: l2-cache0 { 138 l2_0: l2-cache0 {
203 compatible = "cache"; 139 compatible = "cache";
204 cache-level = <2>; 140 cache-level = <2>;
205 cache-size = <1048576> <<
206 cache-line-size = <64> <<
207 cache-sets = <1024>; <<
208 cache-unified; <<
209 }; 141 };
210 142
211 l2_1: l2-cache1 { 143 l2_1: l2-cache1 {
212 compatible = "cache"; 144 compatible = "cache";
213 cache-level = <2>; 145 cache-level = <2>;
214 cache-size = <1048576> <<
215 cache-line-size = <64> <<
216 cache-sets = <1024>; <<
217 cache-unified; <<
218 }; 146 };
219 }; 147 };
220 148
221 clk26m: oscillator-26m { 149 clk26m: oscillator-26m {
222 compatible = "fixed-clock"; 150 compatible = "fixed-clock";
223 #clock-cells = <0>; 151 #clock-cells = <0>;
224 clock-frequency = <26000000>; 152 clock-frequency = <26000000>;
225 clock-output-names = "clk26m"; 153 clock-output-names = "clk26m";
226 }; 154 };
227 155
228 clk32k: oscillator-32k { 156 clk32k: oscillator-32k {
229 compatible = "fixed-clock"; 157 compatible = "fixed-clock";
230 #clock-cells = <0>; 158 #clock-cells = <0>;
231 clock-frequency = <32000>; 159 clock-frequency = <32000>;
232 clock-output-names = "clk32k"; 160 clock-output-names = "clk32k";
233 }; 161 };
234 162
235 system_clk: dummy13m { 163 system_clk: dummy13m {
236 compatible = "fixed-clock"; 164 compatible = "fixed-clock";
237 clock-frequency = <13000000>; 165 clock-frequency = <13000000>;
238 #clock-cells = <0>; 166 #clock-cells = <0>;
239 }; 167 };
240 168
241 pmu { 169 pmu {
242 compatible = "arm,cortex-a53-p 170 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_SPI 8 IRQ_T 171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
244 <GIC_SPI 9 IRQ_T 172 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_SPI 10 IRQ_T 173 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_SPI 11 IRQ_T 174 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-affinity = <&cpu0>, 175 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
248 }; 176 };
249 177
250 timer { 178 timer {
251 compatible = "arm,armv8-timer" 179 compatible = "arm,armv8-timer";
252 interrupt-parent = <&gic>; 180 interrupt-parent = <&gic>;
253 interrupts = <GIC_PPI 13 181 interrupts = <GIC_PPI 13
254 (GIC_CPU_MASK_SIM 182 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
255 <GIC_PPI 14 183 <GIC_PPI 14
256 (GIC_CPU_MASK_SIM 184 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
257 <GIC_PPI 11 185 <GIC_PPI 11
258 (GIC_CPU_MASK_SIM 186 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 10 187 <GIC_PPI 10
260 (GIC_CPU_MASK_SIM 188 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
261 }; 189 };
262 190
263 soc { 191 soc {
264 #address-cells = <2>; 192 #address-cells = <2>;
265 #size-cells = <2>; 193 #size-cells = <2>;
266 compatible = "simple-bus"; 194 compatible = "simple-bus";
267 ranges; 195 ranges;
268 196
269 topckgen: syscon@10000000 { 197 topckgen: syscon@10000000 {
270 compatible = "mediatek 198 compatible = "mediatek,mt6795-topckgen", "syscon";
271 reg = <0 0x10000000 0 199 reg = <0 0x10000000 0 0x1000>;
272 #clock-cells = <1>; 200 #clock-cells = <1>;
273 }; 201 };
274 202
275 infracfg: syscon@10001000 { 203 infracfg: syscon@10001000 {
276 compatible = "mediatek 204 compatible = "mediatek,mt6795-infracfg", "syscon";
277 reg = <0 0x10001000 0 205 reg = <0 0x10001000 0 0x1000>;
278 #clock-cells = <1>; 206 #clock-cells = <1>;
279 #reset-cells = <1>; 207 #reset-cells = <1>;
280 }; 208 };
281 209
282 pericfg: syscon@10003000 { 210 pericfg: syscon@10003000 {
283 compatible = "mediatek 211 compatible = "mediatek,mt6795-pericfg", "syscon";
284 reg = <0 0x10003000 0 212 reg = <0 0x10003000 0 0x1000>;
285 #clock-cells = <1>; 213 #clock-cells = <1>;
286 #reset-cells = <1>; 214 #reset-cells = <1>;
287 }; 215 };
288 216
289 scpsys: syscon@10006000 { <<
290 compatible = "syscon", <<
291 reg = <0 0x10006000 0 <<
292 #power-domain-cells = <<
293 <<
294 /* System Power Manage <<
295 spm: power-controller <<
296 compatible = " <<
297 #address-cells <<
298 #size-cells = <<
299 #power-domain- <<
300 <<
301 /* power domai <<
302 power-domain@M <<
303 reg = <<
304 clocks <<
305 clock- <<
306 #power <<
307 }; <<
308 power-domain@M <<
309 reg = <<
310 clocks <<
311 <<
312 clock- <<
313 #power <<
314 }; <<
315 power-domain@M <<
316 reg = <<
317 clocks <<
318 clock- <<
319 #power <<
320 }; <<
321 <<
322 power-domain@M <<
323 reg = <<
324 clocks <<
325 clock- <<
326 #power <<
327 mediat <<
328 }; <<
329 <<
330 power-domain@M <<
331 reg = <<
332 clocks <<
333 <<
334 clock- <<
335 #power <<
336 }; <<
337 <<
338 power-domain@M <<
339 reg = <<
340 #power <<
341 }; <<
342 <<
343 mfg_async: pow <<
344 reg = <<
345 clocks <<
346 clock- <<
347 #addre <<
348 #size- <<
349 #power <<
350 <<
351 power- <<
352 <<
353 <<
354 <<
355 <<
356 <<
357 <<
358 <<
359 <<
360 <<
361 <<
362 }; <<
363 }; <<
364 }; <<
365 }; <<
366 <<
367 pio: pinctrl@10005000 { 217 pio: pinctrl@10005000 {
368 compatible = "mediatek 218 compatible = "mediatek,mt6795-pinctrl";
369 reg = <0 0x10005000 0 219 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
370 reg-names = "base", "e 220 reg-names = "base", "eint";
371 interrupts = <GIC_SPI 221 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 222 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
373 gpio-controller; 223 gpio-controller;
374 #gpio-cells = <2>; 224 #gpio-cells = <2>;
375 gpio-ranges = <&pio 0 225 gpio-ranges = <&pio 0 0 196>;
376 interrupt-controller; 226 interrupt-controller;
377 #interrupt-cells = <2> 227 #interrupt-cells = <2>;
378 }; 228 };
379 229
380 watchdog: watchdog@10007000 { 230 watchdog: watchdog@10007000 {
381 compatible = "mediatek 231 compatible = "mediatek,mt6795-wdt";
382 reg = <0 0x10007000 0 232 reg = <0 0x10007000 0 0x100>;
383 interrupts = <GIC_SPI 233 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
384 #reset-cells = <1>; 234 #reset-cells = <1>;
385 timeout-sec = <20>; 235 timeout-sec = <20>;
386 }; 236 };
387 237
388 timer: timer@10008000 { 238 timer: timer@10008000 {
389 compatible = "mediatek 239 compatible = "mediatek,mt6795-timer",
390 "mediatek 240 "mediatek,mt6577-timer";
391 reg = <0 0x10008000 0 241 reg = <0 0x10008000 0 0x1000>;
392 interrupts = <GIC_SPI 242 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
393 clocks = <&system_clk> 243 clocks = <&system_clk>, <&clk32k>;
394 }; 244 };
395 245
396 pwrap: pwrap@1000d000 { <<
397 compatible = "mediatek <<
398 reg = <0 0x1000d000 0 <<
399 reg-names = "pwrap"; <<
400 interrupts = <GIC_SPI <<
401 resets = <&infracfg MT <<
402 reset-names = "pwrap"; <<
403 clocks = <&topckgen CL <<
404 clock-names = "spi", " <<
405 }; <<
406 <<
407 sysirq: intpol-controller@1020 246 sysirq: intpol-controller@10200620 {
408 compatible = "mediatek 247 compatible = "mediatek,mt6795-sysirq",
409 "mediatek 248 "mediatek,mt6577-sysirq";
410 interrupt-controller; 249 interrupt-controller;
411 #interrupt-cells = <3> 250 #interrupt-cells = <3>;
412 interrupt-parent = <&g 251 interrupt-parent = <&gic>;
413 reg = <0 0x10200620 0 252 reg = <0 0x10200620 0 0x20>;
414 }; 253 };
415 254
416 systimer: timer@10200670 { 255 systimer: timer@10200670 {
417 compatible = "mediatek 256 compatible = "mediatek,mt6795-systimer";
418 reg = <0 0x10200670 0 257 reg = <0 0x10200670 0 0x10>;
419 interrupts = <GIC_SPI 258 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&system_clk> 259 clocks = <&system_clk>;
421 clock-names = "clk13m" 260 clock-names = "clk13m";
422 }; 261 };
423 262
424 iommu: iommu@10205000 { <<
425 compatible = "mediatek <<
426 reg = <0 0x10205000 0 <<
427 clocks = <&infracfg CL <<
428 clock-names = "bclk"; <<
429 interrupts = <GIC_SPI <<
430 mediatek,larbs = <&lar <<
431 power-domains = <&spm <<
432 #iommu-cells = <1>; <<
433 }; <<
434 <<
435 apmixedsys: syscon@10209000 { <<
436 compatible = "mediatek <<
437 reg = <0 0x10209000 0 <<
438 #clock-cells = <1>; <<
439 }; <<
440 <<
441 fhctl: clock-controller@10209f <<
442 compatible = "mediatek <<
443 reg = <0 0x10209f00 0 <<
444 status = "disabled"; <<
445 }; <<
446 <<
447 gce: mailbox@10212000 { <<
448 compatible = "mediatek <<
449 reg = <0 0x10212000 0 <<
450 interrupts = <GIC_SPI <<
451 clocks = <&infracfg CL <<
452 clock-names = "gce"; <<
453 #mbox-cells = <2>; <<
454 }; <<
455 <<
456 mipi_tx0: dsi-phy@10215000 { <<
457 compatible = "mediatek <<
458 reg = <0 0x10215000 0 <<
459 clocks = <&clk26m>; <<
460 clock-output-names = " <<
461 #clock-cells = <0>; <<
462 #phy-cells = <0>; <<
463 status = "disabled"; <<
464 }; <<
465 <<
466 mipi_tx1: dsi-phy@10216000 { <<
467 compatible = "mediatek <<
468 reg = <0 0x10216000 0 <<
469 clocks = <&clk26m>; <<
470 clock-output-names = " <<
471 #clock-cells = <0>; <<
472 #phy-cells = <0>; <<
473 status = "disabled"; <<
474 }; <<
475 <<
476 gic: interrupt-controller@1022 263 gic: interrupt-controller@10221000 {
477 compatible = "arm,gic- 264 compatible = "arm,gic-400";
478 #interrupt-cells = <3> 265 #interrupt-cells = <3>;
479 interrupt-parent = <&g 266 interrupt-parent = <&gic>;
480 interrupt-controller; 267 interrupt-controller;
481 reg = <0 0x10221000 0 268 reg = <0 0x10221000 0 0x1000>,
482 <0 0x10222000 0 269 <0 0x10222000 0 0x2000>,
483 <0 0x10224000 0 270 <0 0x10224000 0 0x2000>,
484 <0 0x10226000 0 271 <0 0x10226000 0 0x2000>;
485 interrupts = <GIC_PPI 272 interrupts = <GIC_PPI 9
486 (GIC_CPU_MASK_ 273 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
487 }; 274 };
488 275
489 cci: cci@10390000 { 276 cci: cci@10390000 {
490 compatible = "arm,cci- 277 compatible = "arm,cci-400";
491 #address-cells = <1>; 278 #address-cells = <1>;
492 #size-cells = <1>; 279 #size-cells = <1>;
493 reg = <0 0x10390000 0 280 reg = <0 0x10390000 0 0x1000>;
494 ranges = <0 0 0x103900 281 ranges = <0 0 0x10390000 0x10000>;
495 282
496 cci_control0: slave-if 283 cci_control0: slave-if@1000 {
497 compatible = " 284 compatible = "arm,cci-400-ctrl-if";
498 interface-type 285 interface-type = "ace-lite";
499 reg = <0x1000 286 reg = <0x1000 0x1000>;
500 }; 287 };
501 288
502 cci_control1: slave-if 289 cci_control1: slave-if@4000 {
503 compatible = " 290 compatible = "arm,cci-400-ctrl-if";
504 interface-type 291 interface-type = "ace";
505 reg = <0x4000 292 reg = <0x4000 0x1000>;
506 }; 293 };
507 294
508 cci_control2: slave-if 295 cci_control2: slave-if@5000 {
509 compatible = " 296 compatible = "arm,cci-400-ctrl-if";
510 interface-type 297 interface-type = "ace";
511 reg = <0x5000 298 reg = <0x5000 0x1000>;
512 }; 299 };
513 300
514 pmu@9000 { 301 pmu@9000 {
515 compatible = " 302 compatible = "arm,cci-400-pmu,r1";
516 reg = <0x9000 303 reg = <0x9000 0x5000>;
517 interrupts = < 304 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
518 < 305 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
519 < 306 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
520 < 307 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
521 < 308 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522 }; 309 };
523 }; 310 };
524 311
525 uart0: serial@11002000 { 312 uart0: serial@11002000 {
526 compatible = "mediatek 313 compatible = "mediatek,mt6795-uart",
527 "mediatek 314 "mediatek,mt6577-uart";
528 reg = <0 0x11002000 0 315 reg = <0 0x11002000 0 0x400>;
529 interrupts = <GIC_SPI 316 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
530 clocks = <&pericfg CLK 317 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
531 clock-names = "baud", 318 clock-names = "baud", "bus";
532 dmas = <&apdma 0>, <&a 319 dmas = <&apdma 0>, <&apdma 1>;
533 dma-names = "tx", "rx" 320 dma-names = "tx", "rx";
534 status = "disabled"; 321 status = "disabled";
535 }; 322 };
536 323
537 uart1: serial@11003000 { 324 uart1: serial@11003000 {
538 compatible = "mediatek 325 compatible = "mediatek,mt6795-uart",
539 "mediatek 326 "mediatek,mt6577-uart";
540 reg = <0 0x11003000 0 327 reg = <0 0x11003000 0 0x400>;
541 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
542 clocks = <&pericfg CLK 329 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
543 clock-names = "baud", 330 clock-names = "baud", "bus";
544 dmas = <&apdma 2>, <&a 331 dmas = <&apdma 2>, <&apdma 3>;
545 dma-names = "tx", "rx" 332 dma-names = "tx", "rx";
546 status = "disabled"; 333 status = "disabled";
547 }; 334 };
548 335
549 apdma: dma-controller@11000380 336 apdma: dma-controller@11000380 {
550 compatible = "mediatek 337 compatible = "mediatek,mt6795-uart-dma",
551 "mediatek 338 "mediatek,mt6577-uart-dma";
552 reg = <0 0x11000380 0 339 reg = <0 0x11000380 0 0x60>,
553 <0 0x11000400 0 340 <0 0x11000400 0 0x60>,
554 <0 0x11000480 0 341 <0 0x11000480 0 0x60>,
555 <0 0x11000500 0 342 <0 0x11000500 0 0x60>,
556 <0 0x11000580 0 343 <0 0x11000580 0 0x60>,
557 <0 0x11000600 0 344 <0 0x11000600 0 0x60>,
558 <0 0x11000680 0 345 <0 0x11000680 0 0x60>,
559 <0 0x11000700 0 346 <0 0x11000700 0 0x60>;
560 interrupts = <GIC_SPI 347 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
561 <GIC_SPI 348 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
562 <GIC_SPI 349 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
563 <GIC_SPI 350 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
564 <GIC_SPI 351 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
565 <GIC_SPI 352 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
566 <GIC_SPI 353 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
567 <GIC_SPI 354 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
568 dma-requests = <8>; 355 dma-requests = <8>;
569 clocks = <&pericfg CLK 356 clocks = <&pericfg CLK_PERI_AP_DMA>;
570 clock-names = "apdma"; 357 clock-names = "apdma";
571 mediatek,dma-33bits; 358 mediatek,dma-33bits;
572 #dma-cells = <1>; 359 #dma-cells = <1>;
573 }; 360 };
574 361
575 uart2: serial@11004000 { 362 uart2: serial@11004000 {
576 compatible = "mediatek 363 compatible = "mediatek,mt6795-uart",
577 "mediatek 364 "mediatek,mt6577-uart";
578 reg = <0 0x11004000 0 365 reg = <0 0x11004000 0 0x400>;
579 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
580 clocks = <&pericfg CLK 367 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
581 clock-names = "baud", 368 clock-names = "baud", "bus";
582 dmas = <&apdma 4>, <&a 369 dmas = <&apdma 4>, <&apdma 5>;
583 dma-names = "tx", "rx" 370 dma-names = "tx", "rx";
584 status = "disabled"; 371 status = "disabled";
585 }; 372 };
586 373
587 uart3: serial@11005000 { 374 uart3: serial@11005000 {
588 compatible = "mediatek 375 compatible = "mediatek,mt6795-uart",
589 "mediatek 376 "mediatek,mt6577-uart";
590 reg = <0 0x11005000 0 377 reg = <0 0x11005000 0 0x400>;
591 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
592 clocks = <&pericfg CLK 379 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
593 clock-names = "baud", 380 clock-names = "baud", "bus";
594 dmas = <&apdma 6>, <&a 381 dmas = <&apdma 6>, <&apdma 7>;
595 dma-names = "tx", "rx" 382 dma-names = "tx", "rx";
596 status = "disabled"; 383 status = "disabled";
597 }; 384 };
598 385
599 pwm2: pwm@11006000 { <<
600 compatible = "mediatek <<
601 reg = <0 0x11006000 0 <<
602 #pwm-cells = <2>; <<
603 interrupts = <GIC_SPI <<
604 clocks = <&topckgen CL <<
605 <&pericfg CLK <<
606 <&pericfg CLK <<
607 <&pericfg CLK <<
608 <&pericfg CLK <<
609 <&pericfg CLK <<
610 <&pericfg CLK <<
611 <&pericfg CLK <<
612 <&pericfg CLK <<
613 clock-names = "top", " <<
614 "pwm4", <<
615 status = "disabled"; <<
616 }; <<
617 <<
618 i2c0: i2c@11007000 { <<
619 compatible = "mediatek <<
620 reg = <0 0x11007000 0 <<
621 interrupts = <GIC_SPI <<
622 clock-div = <16>; <<
623 clocks = <&pericfg CLK <<
624 clock-names = "main", <<
625 #address-cells = <1>; <<
626 #size-cells = <0>; <<
627 status = "disabled"; <<
628 }; <<
629 <<
630 i2c1: i2c@11008000 { <<
631 compatible = "mediatek <<
632 reg = <0 0x11008000 0 <<
633 interrupts = <GIC_SPI <<
634 clock-div = <16>; <<
635 clocks = <&pericfg CLK <<
636 clock-names = "main", <<
637 #address-cells = <1>; <<
638 #size-cells = <0>; <<
639 status = "disabled"; <<
640 }; <<
641 <<
642 i2c2: i2c@11009000 { <<
643 compatible = "mediatek <<
644 reg = <0 0x11009000 0 <<
645 interrupts = <GIC_SPI <<
646 clock-div = <16>; <<
647 clocks = <&pericfg CLK <<
648 clock-names = "main", <<
649 #address-cells = <1>; <<
650 #size-cells = <0>; <<
651 status = "disabled"; <<
652 }; <<
653 <<
654 i2c3: i2c@11010000 { <<
655 compatible = "mediatek <<
656 reg = <0 0x11010000 0 <<
657 interrupts = <GIC_SPI <<
658 clock-div = <16>; <<
659 clocks = <&pericfg CLK <<
660 clock-names = "main", <<
661 #address-cells = <1>; <<
662 #size-cells = <0>; <<
663 status = "disabled"; <<
664 }; <<
665 <<
666 i2c4: i2c@11011000 { <<
667 compatible = "mediatek <<
668 reg = <0 0x11011000 0 <<
669 interrupts = <GIC_SPI <<
670 clock-div = <16>; <<
671 clocks = <&pericfg CLK <<
672 clock-names = "main", <<
673 #address-cells = <1>; <<
674 #size-cells = <0>; <<
675 status = "disabled"; <<
676 }; <<
677 <<
678 mmc0: mmc@11230000 { 386 mmc0: mmc@11230000 {
679 compatible = "mediatek 387 compatible = "mediatek,mt6795-mmc";
680 reg = <0 0x11230000 0 388 reg = <0 0x11230000 0 0x1000>;
681 interrupts = <GIC_SPI 389 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
682 clocks = <&pericfg CLK 390 clocks = <&pericfg CLK_PERI_MSDC30_0>,
683 <&topckgen CL 391 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
684 <&topckgen CL 392 <&topckgen CLK_TOP_MSDC50_0_SEL>;
685 clock-names = "source" 393 clock-names = "source", "hclk", "source_cg";
686 status = "disabled"; 394 status = "disabled";
687 }; 395 };
688 396
689 mmc1: mmc@11240000 { 397 mmc1: mmc@11240000 {
690 compatible = "mediatek 398 compatible = "mediatek,mt6795-mmc";
691 reg = <0 0x11240000 0 399 reg = <0 0x11240000 0 0x1000>;
692 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&pericfg CLK 401 clocks = <&pericfg CLK_PERI_MSDC30_1>,
694 <&topckgen CL 402 <&topckgen CLK_TOP_AXI_SEL>;
695 clock-names = "source" 403 clock-names = "source", "hclk";
696 status = "disabled"; 404 status = "disabled";
697 }; 405 };
698 406
699 mmc2: mmc@11250000 { 407 mmc2: mmc@11250000 {
700 compatible = "mediatek 408 compatible = "mediatek,mt6795-mmc";
701 reg = <0 0x11250000 0 409 reg = <0 0x11250000 0 0x1000>;
702 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK 411 clocks = <&pericfg CLK_PERI_MSDC30_2>,
704 <&topckgen CL 412 <&topckgen CLK_TOP_AXI_SEL>;
705 clock-names = "source" 413 clock-names = "source", "hclk";
706 status = "disabled"; 414 status = "disabled";
707 }; 415 };
708 416
709 mmc3: mmc@11260000 { 417 mmc3: mmc@11260000 {
710 compatible = "mediatek 418 compatible = "mediatek,mt6795-mmc";
711 reg = <0 0x11260000 0 419 reg = <0 0x11260000 0 0x1000>;
712 interrupts = <GIC_SPI 420 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
713 clocks = <&pericfg CLK 421 clocks = <&pericfg CLK_PERI_MSDC30_3>,
714 <&topckgen CL 422 <&topckgen CLK_TOP_AXI_SEL>;
715 clock-names = "source" 423 clock-names = "source", "hclk";
716 status = "disabled"; 424 status = "disabled";
717 }; <<
718 <<
719 mmsys: syscon@14000000 { <<
720 compatible = "mediatek <<
721 reg = <0 0x14000000 0 <<
722 power-domains = <&spm <<
723 assigned-clocks = <&to <<
724 assigned-clock-rates = <<
725 #clock-cells = <1>; <<
726 #reset-cells = <1>; <<
727 mboxes = <&gce 0 CMDQ_ <<
728 <&gce 1 CMDQ_ <<
729 mediatek,gce-client-re <<
730 }; <<
731 <<
732 ovl0: ovl@1400c000 { <<
733 compatible = "mediatek <<
734 reg = <0 0x1400c000 0 <<
735 interrupts = <GIC_SPI <<
736 power-domains = <&spm <<
737 clocks = <&mmsys CLK_M <<
738 iommus = <&iommu M4U_P <<
739 mediatek,gce-client-re <<
740 }; <<
741 <<
742 ovl1: ovl@1400d000 { <<
743 compatible = "mediatek <<
744 reg = <0 0x1400d000 0 <<
745 interrupts = <GIC_SPI <<
746 power-domains = <&spm <<
747 clocks = <&mmsys CLK_M <<
748 iommus = <&iommu M4U_P <<
749 mediatek,gce-client-re <<
750 }; <<
751 <<
752 rdma0: rdma@1400e000 { <<
753 compatible = "mediatek <<
754 reg = <0 0x1400e000 0 <<
755 interrupts = <GIC_SPI <<
756 power-domains = <&spm <<
757 clocks = <&mmsys CLK_M <<
758 iommus = <&iommu M4U_P <<
759 mediatek,gce-client-re <<
760 }; <<
761 <<
762 rdma1: rdma@1400f000 { <<
763 compatible = "mediatek <<
764 reg = <0 0x1400f000 0 <<
765 interrupts = <GIC_SPI <<
766 power-domains = <&spm <<
767 clocks = <&mmsys CLK_M <<
768 iommus = <&iommu M4U_P <<
769 mediatek,gce-client-re <<
770 }; <<
771 <<
772 rdma2: rdma@14010000 { <<
773 compatible = "mediatek <<
774 reg = <0 0x14010000 0 <<
775 interrupts = <GIC_SPI <<
776 power-domains = <&spm <<
777 clocks = <&mmsys CLK_M <<
778 iommus = <&iommu M4U_P <<
779 mediatek,gce-client-re <<
780 }; <<
781 <<
782 wdma0: wdma@14011000 { <<
783 compatible = "mediatek <<
784 reg = <0 0x14011000 0 <<
785 interrupts = <GIC_SPI <<
786 power-domains = <&spm <<
787 clocks = <&mmsys CLK_M <<
788 iommus = <&iommu M4U_P <<
789 mediatek,gce-client-re <<
790 }; <<
791 <<
792 wdma1: wdma@14012000 { <<
793 compatible = "mediatek <<
794 reg = <0 0x14012000 0 <<
795 interrupts = <GIC_SPI <<
796 power-domains = <&spm <<
797 clocks = <&mmsys CLK_M <<
798 iommus = <&iommu M4U_P <<
799 mediatek,gce-client-re <<
800 }; <<
801 <<
802 color0: color@14013000 { <<
803 compatible = "mediatek <<
804 reg = <0 0x14013000 0 <<
805 interrupts = <GIC_SPI <<
806 power-domains = <&spm <<
807 clocks = <&mmsys CLK_M <<
808 mediatek,gce-client-re <<
809 }; <<
810 <<
811 color1: color@14014000 { <<
812 compatible = "mediatek <<
813 reg = <0 0x14014000 0 <<
814 interrupts = <GIC_SPI <<
815 power-domains = <&spm <<
816 clocks = <&mmsys CLK_M <<
817 mediatek,gce-client-re <<
818 }; <<
819 <<
820 aal@14015000 { <<
821 compatible = "mediatek <<
822 reg = <0 0x14015000 0 <<
823 interrupts = <GIC_SPI <<
824 power-domains = <&spm <<
825 clocks = <&mmsys CLK_M <<
826 mediatek,gce-client-re <<
827 }; <<
828 <<
829 gamma@14016000 { <<
830 compatible = "mediatek <<
831 reg = <0 0x14016000 0 <<
832 interrupts = <GIC_SPI <<
833 power-domains = <&spm <<
834 clocks = <&mmsys CLK_M <<
835 mediatek,gce-client-re <<
836 }; <<
837 <<
838 merge@14017000 { <<
839 compatible = "mediatek <<
840 reg = <0 0x14017000 0 <<
841 power-domains = <&spm <<
842 clocks = <&mmsys CLK_M <<
843 }; <<
844 <<
845 split0: split@14018000 { <<
846 compatible = "mediatek <<
847 reg = <0 0x14018000 0 <<
848 power-domains = <&spm <<
849 clocks = <&mmsys CLK_M <<
850 }; <<
851 <<
852 split1: split@14019000 { <<
853 compatible = "mediatek <<
854 reg = <0 0x14019000 0 <<
855 power-domains = <&spm <<
856 clocks = <&mmsys CLK_M <<
857 }; <<
858 <<
859 ufoe@1401a000 { <<
860 compatible = "mediatek <<
861 reg = <0 0x1401a000 0 <<
862 interrupts = <GIC_SPI <<
863 power-domains = <&spm <<
864 clocks = <&mmsys CLK_M <<
865 mediatek,gce-client-re <<
866 }; <<
867 <<
868 dsi0: dsi@1401b000 { <<
869 compatible = "mediatek <<
870 reg = <0 0x1401b000 0 <<
871 interrupts = <GIC_SPI <<
872 power-domains = <&spm <<
873 clocks = <&mmsys CLK_M <<
874 <&mmsys CLK_M <<
875 <&mipi_tx0>; <<
876 clock-names = "engine" <<
877 phys = <&mipi_tx0>; <<
878 phy-names = "dphy"; <<
879 status = "disabled"; <<
880 }; <<
881 <<
882 dsi1: dsi@1401c000 { <<
883 compatible = "mediatek <<
884 reg = <0 0x1401c000 0 <<
885 interrupts = <GIC_SPI <<
886 power-domains = <&spm <<
887 clocks = <&mmsys CLK_M <<
888 <&mmsys CLK_M <<
889 <&mipi_tx1>; <<
890 clock-names = "engine" <<
891 phys = <&mipi_tx1>; <<
892 phy-names = "dphy"; <<
893 status = "disabled"; <<
894 }; <<
895 <<
896 dpi0: dpi@1401d000 { <<
897 compatible = "mediatek <<
898 reg = <0 0x1401d000 0 <<
899 interrupts = <GIC_SPI <<
900 power-domains = <&spm <<
901 clocks = <&mmsys CLK_M <<
902 <&mmsys CLK_M <<
903 <&apmixedsys <<
904 clock-names = "pixel", <<
905 status = "disabled"; <<
906 }; <<
907 <<
908 pwm0: pwm@1401e000 { <<
909 compatible = "mediatek <<
910 reg = <0 0x1401e000 0 <<
911 #pwm-cells = <2>; <<
912 clocks = <&mmsys CLK_M <<
913 clock-names = "main", <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 pwm1: pwm@1401f000 { <<
918 compatible = "mediatek <<
919 reg = <0 0x1401f000 0 <<
920 #pwm-cells = <2>; <<
921 clocks = <&mmsys CLK_M <<
922 clock-names = "main", <<
923 status = "disabled"; <<
924 }; <<
925 <<
926 mutex: mutex@14020000 { <<
927 compatible = "mediatek <<
928 reg = <0 0x14020000 0 <<
929 interrupts = <GIC_SPI <<
930 power-domains = <&spm <<
931 clocks = <&mmsys CLK_M <<
932 mediatek,gce-events = <<
933 <<
934 mediatek,gce-client-re <<
935 }; <<
936 <<
937 larb0: larb@14021000 { <<
938 compatible = "mediatek <<
939 reg = <0 0x14021000 0 <<
940 clocks = <&mmsys CLK_M <<
941 clock-names = "apb", " <<
942 mediatek,smi = <&smi_c <<
943 mediatek,larb-id = <0> <<
944 power-domains = <&spm <<
945 }; <<
946 <<
947 smi_common: smi@14022000 { <<
948 compatible = "mediatek <<
949 reg = <0 0x14022000 0 <<
950 power-domains = <&spm <<
951 clocks = <&infracfg CL <<
952 clock-names = "apb", " <<
953 }; <<
954 <<
955 od@14023000 { <<
956 compatible = "mediatek <<
957 reg = <0 0x14023000 0 <<
958 clocks = <&mmsys CLK_M <<
959 mediatek,gce-client-re <<
960 }; <<
961 <<
962 larb2: larb@15001000 { <<
963 compatible = "mediatek <<
964 reg = <0 0x15001000 0 <<
965 clocks = <&mmsys CLK_M <<
966 clock-names = "apb", " <<
967 mediatek,smi = <&smi_c <<
968 mediatek,larb-id = <2> <<
969 power-domains = <&spm <<
970 }; <<
971 <<
972 vdecsys: clock-controller@1600 <<
973 compatible = "mediatek <<
974 reg = <0 0x16000000 0 <<
975 #clock-cells = <1>; <<
976 }; <<
977 <<
978 larb1: larb@16010000 { <<
979 compatible = "mediatek <<
980 reg = <0 0x16010000 0 <<
981 mediatek,smi = <&smi_c <<
982 mediatek,larb-id = <1> <<
983 clocks = <&vdecsys CLK <<
984 clock-names = "apb", " <<
985 power-domains = <&spm <<
986 }; <<
987 <<
988 vencsys: clock-controller@1800 <<
989 compatible = "mediatek <<
990 reg = <0 0x18000000 0 <<
991 #clock-cells = <1>; <<
992 }; <<
993 <<
994 larb3: larb@18001000 { <<
995 compatible = "mediatek <<
996 reg = <0 0x18001000 0 <<
997 clocks = <&vencsys CLK <<
998 clock-names = "apb", " <<
999 mediatek,smi = <&smi_c <<
1000 mediatek,larb-id = <3 <<
1001 power-domains = <&spm <<
1002 }; 425 };
1003 }; 426 };
1004 }; 427 };
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