1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2015 MediaTek Inc. 3 * Copyright (c) 2015 MediaTek Inc.
4 * Copyright (C) 2023 Collabora Ltd. !! 4 * Author: Mars.C <mars.cheng@mediatek.com>
5 * Authors: Mars.C <mars.cheng@mediatek.com> <<
6 * AngeloGioacchino Del Regno <angelog <<
7 */ 5 */
8 6
9 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-cl 9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce. <<
13 #include <dt-bindings/memory/mt6795-larb-port. <<
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h 10 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h> 11 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-re 12 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
17 13
18 / { 14 / {
19 compatible = "mediatek,mt6795"; 15 compatible = "mediatek,mt6795";
20 interrupt-parent = <&sysirq>; 16 interrupt-parent = <&sysirq>;
21 #address-cells = <2>; 17 #address-cells = <2>;
22 #size-cells = <2>; 18 #size-cells = <2>;
23 19
24 aliases { <<
25 ovl0 = &ovl0; <<
26 ovl1 = &ovl1; <<
27 rdma0 = &rdma0; <<
28 rdma1 = &rdma1; <<
29 rdma2 = &rdma2; <<
30 wdma0 = &wdma0; <<
31 wdma1 = &wdma1; <<
32 color0 = &color0; <<
33 color1 = &color1; <<
34 split0 = &split0; <<
35 split1 = &split1; <<
36 dpi0 = &dpi0; <<
37 dsi0 = &dsi0; <<
38 dsi1 = &dsi1; <<
39 }; <<
40 <<
41 psci { 20 psci {
42 compatible = "arm,psci-0.2"; 21 compatible = "arm,psci-0.2";
43 method = "smc"; 22 method = "smc";
44 }; 23 };
45 24
46 cpus { 25 cpus {
47 #address-cells = <1>; 26 #address-cells = <1>;
48 #size-cells = <0>; 27 #size-cells = <0>;
49 28
50 cpu0: cpu@0 { 29 cpu0: cpu@0 {
51 device_type = "cpu"; 30 device_type = "cpu";
52 compatible = "arm,cort 31 compatible = "arm,cortex-a53";
53 enable-method = "psci" 32 enable-method = "psci";
54 reg = <0x000>; 33 reg = <0x000>;
55 cci-control-port = <&c 34 cci-control-port = <&cci_control2>;
56 next-level-cache = <&l 35 next-level-cache = <&l2_0>;
57 }; 36 };
58 37
59 cpu1: cpu@1 { 38 cpu1: cpu@1 {
60 device_type = "cpu"; 39 device_type = "cpu";
61 compatible = "arm,cort 40 compatible = "arm,cortex-a53";
62 enable-method = "psci" 41 enable-method = "psci";
63 reg = <0x001>; 42 reg = <0x001>;
64 cci-control-port = <&c 43 cci-control-port = <&cci_control2>;
65 i-cache-size = <32768> 44 i-cache-size = <32768>;
66 i-cache-line-size = <6 45 i-cache-line-size = <64>;
67 i-cache-sets = <256>; 46 i-cache-sets = <256>;
68 d-cache-size = <32768> 47 d-cache-size = <32768>;
69 d-cache-line-size = <6 48 d-cache-line-size = <64>;
70 d-cache-sets = <128>; 49 d-cache-sets = <128>;
71 next-level-cache = <&l 50 next-level-cache = <&l2_0>;
72 }; 51 };
73 52
74 cpu2: cpu@2 { 53 cpu2: cpu@2 {
75 device_type = "cpu"; 54 device_type = "cpu";
76 compatible = "arm,cort 55 compatible = "arm,cortex-a53";
77 enable-method = "psci" 56 enable-method = "psci";
78 reg = <0x002>; 57 reg = <0x002>;
79 cci-control-port = <&c 58 cci-control-port = <&cci_control2>;
80 i-cache-size = <32768> 59 i-cache-size = <32768>;
81 i-cache-line-size = <6 60 i-cache-line-size = <64>;
82 i-cache-sets = <256>; 61 i-cache-sets = <256>;
83 d-cache-size = <32768> 62 d-cache-size = <32768>;
84 d-cache-line-size = <6 63 d-cache-line-size = <64>;
85 d-cache-sets = <128>; 64 d-cache-sets = <128>;
86 next-level-cache = <&l 65 next-level-cache = <&l2_0>;
87 }; 66 };
88 67
89 cpu3: cpu@3 { 68 cpu3: cpu@3 {
90 device_type = "cpu"; 69 device_type = "cpu";
91 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
92 enable-method = "psci" 71 enable-method = "psci";
93 reg = <0x003>; 72 reg = <0x003>;
94 cci-control-port = <&c 73 cci-control-port = <&cci_control2>;
95 i-cache-size = <32768> 74 i-cache-size = <32768>;
96 i-cache-line-size = <6 75 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 76 i-cache-sets = <256>;
98 d-cache-size = <32768> 77 d-cache-size = <32768>;
99 d-cache-line-size = <6 78 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 79 d-cache-sets = <128>;
101 next-level-cache = <&l 80 next-level-cache = <&l2_0>;
102 }; 81 };
103 82
104 cpu4: cpu@100 { 83 cpu4: cpu@100 {
105 device_type = "cpu"; 84 device_type = "cpu";
106 compatible = "arm,cort 85 compatible = "arm,cortex-a53";
107 enable-method = "psci" 86 enable-method = "psci";
108 reg = <0x100>; 87 reg = <0x100>;
109 cci-control-port = <&c 88 cci-control-port = <&cci_control1>;
110 i-cache-size = <32768> 89 i-cache-size = <32768>;
111 i-cache-line-size = <6 90 i-cache-line-size = <64>;
112 i-cache-sets = <256>; 91 i-cache-sets = <256>;
113 d-cache-size = <32768> 92 d-cache-size = <32768>;
114 d-cache-line-size = <6 93 d-cache-line-size = <64>;
115 d-cache-sets = <128>; 94 d-cache-sets = <128>;
116 next-level-cache = <&l 95 next-level-cache = <&l2_1>;
117 }; 96 };
118 97
119 cpu5: cpu@101 { 98 cpu5: cpu@101 {
120 device_type = "cpu"; 99 device_type = "cpu";
121 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
122 enable-method = "psci" 101 enable-method = "psci";
123 reg = <0x101>; 102 reg = <0x101>;
124 cci-control-port = <&c 103 cci-control-port = <&cci_control1>;
125 i-cache-size = <32768> 104 i-cache-size = <32768>;
126 i-cache-line-size = <6 105 i-cache-line-size = <64>;
127 i-cache-sets = <256>; 106 i-cache-sets = <256>;
128 d-cache-size = <32768> 107 d-cache-size = <32768>;
129 d-cache-line-size = <6 108 d-cache-line-size = <64>;
130 d-cache-sets = <128>; 109 d-cache-sets = <128>;
131 next-level-cache = <&l 110 next-level-cache = <&l2_1>;
132 }; 111 };
133 112
134 cpu6: cpu@102 { 113 cpu6: cpu@102 {
135 device_type = "cpu"; 114 device_type = "cpu";
136 compatible = "arm,cort 115 compatible = "arm,cortex-a53";
137 enable-method = "psci" 116 enable-method = "psci";
138 reg = <0x102>; 117 reg = <0x102>;
139 cci-control-port = <&c 118 cci-control-port = <&cci_control1>;
140 i-cache-size = <32768> 119 i-cache-size = <32768>;
141 i-cache-line-size = <6 120 i-cache-line-size = <64>;
142 i-cache-sets = <256>; 121 i-cache-sets = <256>;
143 d-cache-size = <32768> 122 d-cache-size = <32768>;
144 d-cache-line-size = <6 123 d-cache-line-size = <64>;
145 d-cache-sets = <128>; 124 d-cache-sets = <128>;
146 next-level-cache = <&l 125 next-level-cache = <&l2_1>;
147 }; 126 };
148 127
149 cpu7: cpu@103 { 128 cpu7: cpu@103 {
150 device_type = "cpu"; 129 device_type = "cpu";
151 compatible = "arm,cort 130 compatible = "arm,cortex-a53";
152 enable-method = "psci" 131 enable-method = "psci";
153 reg = <0x103>; 132 reg = <0x103>;
154 cci-control-port = <&c 133 cci-control-port = <&cci_control1>;
155 i-cache-size = <32768> 134 i-cache-size = <32768>;
156 i-cache-line-size = <6 135 i-cache-line-size = <64>;
157 i-cache-sets = <256>; 136 i-cache-sets = <256>;
158 d-cache-size = <32768> 137 d-cache-size = <32768>;
159 d-cache-line-size = <6 138 d-cache-line-size = <64>;
160 d-cache-sets = <128>; 139 d-cache-sets = <128>;
161 next-level-cache = <&l 140 next-level-cache = <&l2_1>;
162 }; 141 };
163 142
164 cpu-map { 143 cpu-map {
165 cluster0 { 144 cluster0 {
166 core0 { 145 core0 {
167 cpu = 146 cpu = <&cpu0>;
168 }; 147 };
169 148
170 core1 { 149 core1 {
171 cpu = 150 cpu = <&cpu1>;
172 }; 151 };
173 152
174 core2 { 153 core2 {
175 cpu = 154 cpu = <&cpu2>;
176 }; 155 };
177 156
178 core3 { 157 core3 {
179 cpu = 158 cpu = <&cpu3>;
180 }; 159 };
181 }; 160 };
182 161
183 cluster1 { 162 cluster1 {
184 core0 { 163 core0 {
185 cpu = 164 cpu = <&cpu4>;
186 }; 165 };
187 166
188 core1 { 167 core1 {
189 cpu = 168 cpu = <&cpu5>;
190 }; 169 };
191 170
192 core2 { 171 core2 {
193 cpu = 172 cpu = <&cpu6>;
194 }; 173 };
195 174
196 core3 { 175 core3 {
197 cpu = 176 cpu = <&cpu7>;
198 }; 177 };
199 }; 178 };
200 }; 179 };
201 180
202 l2_0: l2-cache0 { 181 l2_0: l2-cache0 {
203 compatible = "cache"; 182 compatible = "cache";
204 cache-level = <2>; 183 cache-level = <2>;
205 cache-size = <1048576> 184 cache-size = <1048576>;
206 cache-line-size = <64> 185 cache-line-size = <64>;
207 cache-sets = <1024>; 186 cache-sets = <1024>;
208 cache-unified; 187 cache-unified;
209 }; 188 };
210 189
211 l2_1: l2-cache1 { 190 l2_1: l2-cache1 {
212 compatible = "cache"; 191 compatible = "cache";
213 cache-level = <2>; 192 cache-level = <2>;
214 cache-size = <1048576> 193 cache-size = <1048576>;
215 cache-line-size = <64> 194 cache-line-size = <64>;
216 cache-sets = <1024>; 195 cache-sets = <1024>;
217 cache-unified; 196 cache-unified;
218 }; 197 };
219 }; 198 };
220 199
221 clk26m: oscillator-26m { 200 clk26m: oscillator-26m {
222 compatible = "fixed-clock"; 201 compatible = "fixed-clock";
223 #clock-cells = <0>; 202 #clock-cells = <0>;
224 clock-frequency = <26000000>; 203 clock-frequency = <26000000>;
225 clock-output-names = "clk26m"; 204 clock-output-names = "clk26m";
226 }; 205 };
227 206
228 clk32k: oscillator-32k { 207 clk32k: oscillator-32k {
229 compatible = "fixed-clock"; 208 compatible = "fixed-clock";
230 #clock-cells = <0>; 209 #clock-cells = <0>;
231 clock-frequency = <32000>; 210 clock-frequency = <32000>;
232 clock-output-names = "clk32k"; 211 clock-output-names = "clk32k";
233 }; 212 };
234 213
235 system_clk: dummy13m { 214 system_clk: dummy13m {
236 compatible = "fixed-clock"; 215 compatible = "fixed-clock";
237 clock-frequency = <13000000>; 216 clock-frequency = <13000000>;
238 #clock-cells = <0>; 217 #clock-cells = <0>;
239 }; 218 };
240 219
241 pmu { 220 pmu {
242 compatible = "arm,cortex-a53-p 221 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_SPI 8 IRQ_T 222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
244 <GIC_SPI 9 IRQ_T 223 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_SPI 10 IRQ_T 224 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_SPI 11 IRQ_T 225 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-affinity = <&cpu0>, 226 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
248 }; 227 };
249 228
250 timer { 229 timer {
251 compatible = "arm,armv8-timer" 230 compatible = "arm,armv8-timer";
252 interrupt-parent = <&gic>; 231 interrupt-parent = <&gic>;
253 interrupts = <GIC_PPI 13 232 interrupts = <GIC_PPI 13
254 (GIC_CPU_MASK_SIM 233 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
255 <GIC_PPI 14 234 <GIC_PPI 14
256 (GIC_CPU_MASK_SIM 235 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
257 <GIC_PPI 11 236 <GIC_PPI 11
258 (GIC_CPU_MASK_SIM 237 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 10 238 <GIC_PPI 10
260 (GIC_CPU_MASK_SIM 239 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
261 }; 240 };
262 241
263 soc { 242 soc {
264 #address-cells = <2>; 243 #address-cells = <2>;
265 #size-cells = <2>; 244 #size-cells = <2>;
266 compatible = "simple-bus"; 245 compatible = "simple-bus";
267 ranges; 246 ranges;
268 247
269 topckgen: syscon@10000000 { 248 topckgen: syscon@10000000 {
270 compatible = "mediatek 249 compatible = "mediatek,mt6795-topckgen", "syscon";
271 reg = <0 0x10000000 0 250 reg = <0 0x10000000 0 0x1000>;
272 #clock-cells = <1>; 251 #clock-cells = <1>;
273 }; 252 };
274 253
275 infracfg: syscon@10001000 { 254 infracfg: syscon@10001000 {
276 compatible = "mediatek 255 compatible = "mediatek,mt6795-infracfg", "syscon";
277 reg = <0 0x10001000 0 256 reg = <0 0x10001000 0 0x1000>;
278 #clock-cells = <1>; 257 #clock-cells = <1>;
279 #reset-cells = <1>; 258 #reset-cells = <1>;
280 }; 259 };
281 260
282 pericfg: syscon@10003000 { 261 pericfg: syscon@10003000 {
283 compatible = "mediatek 262 compatible = "mediatek,mt6795-pericfg", "syscon";
284 reg = <0 0x10003000 0 263 reg = <0 0x10003000 0 0x1000>;
285 #clock-cells = <1>; 264 #clock-cells = <1>;
286 #reset-cells = <1>; 265 #reset-cells = <1>;
287 }; 266 };
288 267
289 scpsys: syscon@10006000 { 268 scpsys: syscon@10006000 {
290 compatible = "syscon", 269 compatible = "syscon", "simple-mfd";
291 reg = <0 0x10006000 0 270 reg = <0 0x10006000 0 0x1000>;
292 #power-domain-cells = 271 #power-domain-cells = <1>;
293 272
294 /* System Power Manage 273 /* System Power Manager */
295 spm: power-controller 274 spm: power-controller {
296 compatible = " 275 compatible = "mediatek,mt6795-power-controller";
297 #address-cells 276 #address-cells = <1>;
298 #size-cells = 277 #size-cells = <0>;
299 #power-domain- 278 #power-domain-cells = <1>;
300 279
301 /* power domai 280 /* power domains of the SoC */
302 power-domain@M 281 power-domain@MT6795_POWER_DOMAIN_VDEC {
303 reg = 282 reg = <MT6795_POWER_DOMAIN_VDEC>;
304 clocks 283 clocks = <&topckgen CLK_TOP_MM_SEL>;
305 clock- 284 clock-names = "mm";
306 #power 285 #power-domain-cells = <0>;
307 }; 286 };
308 power-domain@M 287 power-domain@MT6795_POWER_DOMAIN_VENC {
309 reg = 288 reg = <MT6795_POWER_DOMAIN_VENC>;
310 clocks 289 clocks = <&topckgen CLK_TOP_MM_SEL>,
311 290 <&topckgen CLK_TOP_VENC_SEL>;
312 clock- 291 clock-names = "mm", "venc";
313 #power 292 #power-domain-cells = <0>;
314 }; 293 };
315 power-domain@M 294 power-domain@MT6795_POWER_DOMAIN_ISP {
316 reg = 295 reg = <MT6795_POWER_DOMAIN_ISP>;
317 clocks 296 clocks = <&topckgen CLK_TOP_MM_SEL>;
318 clock- 297 clock-names = "mm";
319 #power 298 #power-domain-cells = <0>;
320 }; 299 };
321 300
322 power-domain@M 301 power-domain@MT6795_POWER_DOMAIN_MM {
323 reg = 302 reg = <MT6795_POWER_DOMAIN_MM>;
324 clocks 303 clocks = <&topckgen CLK_TOP_MM_SEL>;
325 clock- 304 clock-names = "mm";
326 #power 305 #power-domain-cells = <0>;
327 mediat 306 mediatek,infracfg = <&infracfg>;
328 }; 307 };
329 308
330 power-domain@M 309 power-domain@MT6795_POWER_DOMAIN_MJC {
331 reg = 310 reg = <MT6795_POWER_DOMAIN_MJC>;
332 clocks 311 clocks = <&topckgen CLK_TOP_MM_SEL>,
333 312 <&topckgen CLK_TOP_MJC_SEL>;
334 clock- 313 clock-names = "mm", "mjc";
335 #power 314 #power-domain-cells = <0>;
336 }; 315 };
337 316
338 power-domain@M 317 power-domain@MT6795_POWER_DOMAIN_AUDIO {
339 reg = 318 reg = <MT6795_POWER_DOMAIN_AUDIO>;
340 #power 319 #power-domain-cells = <0>;
341 }; 320 };
342 321
343 mfg_async: pow 322 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
344 reg = 323 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>;
345 clocks 324 clocks = <&clk26m>;
346 clock- 325 clock-names = "mfg";
347 #addre 326 #address-cells = <1>;
348 #size- 327 #size-cells = <0>;
349 #power 328 #power-domain-cells = <1>;
350 329
351 power- 330 power-domain@MT6795_POWER_DOMAIN_MFG_2D {
352 331 reg = <MT6795_POWER_DOMAIN_MFG_2D>;
353 332 #address-cells = <1>;
354 333 #size-cells = <0>;
355 334 #power-domain-cells = <1>;
356 335
357 336 power-domain@MT6795_POWER_DOMAIN_MFG {
358 337 reg = <MT6795_POWER_DOMAIN_MFG>;
359 338 #power-domain-cells = <0>;
360 339 mediatek,infracfg = <&infracfg>;
361 340 };
362 }; 341 };
363 }; 342 };
364 }; 343 };
365 }; 344 };
366 345
367 pio: pinctrl@10005000 { 346 pio: pinctrl@10005000 {
368 compatible = "mediatek 347 compatible = "mediatek,mt6795-pinctrl";
369 reg = <0 0x10005000 0 348 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
370 reg-names = "base", "e 349 reg-names = "base", "eint";
371 interrupts = <GIC_SPI 350 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 351 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
373 gpio-controller; 352 gpio-controller;
374 #gpio-cells = <2>; 353 #gpio-cells = <2>;
375 gpio-ranges = <&pio 0 354 gpio-ranges = <&pio 0 0 196>;
376 interrupt-controller; 355 interrupt-controller;
377 #interrupt-cells = <2> 356 #interrupt-cells = <2>;
378 }; 357 };
379 358
380 watchdog: watchdog@10007000 { 359 watchdog: watchdog@10007000 {
381 compatible = "mediatek 360 compatible = "mediatek,mt6795-wdt";
382 reg = <0 0x10007000 0 361 reg = <0 0x10007000 0 0x100>;
383 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
384 #reset-cells = <1>; 363 #reset-cells = <1>;
385 timeout-sec = <20>; 364 timeout-sec = <20>;
386 }; 365 };
387 366
388 timer: timer@10008000 { 367 timer: timer@10008000 {
389 compatible = "mediatek 368 compatible = "mediatek,mt6795-timer",
390 "mediatek 369 "mediatek,mt6577-timer";
391 reg = <0 0x10008000 0 370 reg = <0 0x10008000 0 0x1000>;
392 interrupts = <GIC_SPI 371 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
393 clocks = <&system_clk> 372 clocks = <&system_clk>, <&clk32k>;
394 }; 373 };
395 374
396 pwrap: pwrap@1000d000 { <<
397 compatible = "mediatek <<
398 reg = <0 0x1000d000 0 <<
399 reg-names = "pwrap"; <<
400 interrupts = <GIC_SPI <<
401 resets = <&infracfg MT <<
402 reset-names = "pwrap"; <<
403 clocks = <&topckgen CL <<
404 clock-names = "spi", " <<
405 }; <<
406 <<
407 sysirq: intpol-controller@1020 375 sysirq: intpol-controller@10200620 {
408 compatible = "mediatek 376 compatible = "mediatek,mt6795-sysirq",
409 "mediatek 377 "mediatek,mt6577-sysirq";
410 interrupt-controller; 378 interrupt-controller;
411 #interrupt-cells = <3> 379 #interrupt-cells = <3>;
412 interrupt-parent = <&g 380 interrupt-parent = <&gic>;
413 reg = <0 0x10200620 0 381 reg = <0 0x10200620 0 0x20>;
414 }; 382 };
415 383
416 systimer: timer@10200670 { 384 systimer: timer@10200670 {
417 compatible = "mediatek 385 compatible = "mediatek,mt6795-systimer";
418 reg = <0 0x10200670 0 386 reg = <0 0x10200670 0 0x10>;
419 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&system_clk> 388 clocks = <&system_clk>;
421 clock-names = "clk13m" 389 clock-names = "clk13m";
422 }; 390 };
423 391
424 iommu: iommu@10205000 { <<
425 compatible = "mediatek <<
426 reg = <0 0x10205000 0 <<
427 clocks = <&infracfg CL <<
428 clock-names = "bclk"; <<
429 interrupts = <GIC_SPI <<
430 mediatek,larbs = <&lar <<
431 power-domains = <&spm <<
432 #iommu-cells = <1>; <<
433 }; <<
434 <<
435 apmixedsys: syscon@10209000 { 392 apmixedsys: syscon@10209000 {
436 compatible = "mediatek 393 compatible = "mediatek,mt6795-apmixedsys", "syscon";
437 reg = <0 0x10209000 0 394 reg = <0 0x10209000 0 0x1000>;
438 #clock-cells = <1>; 395 #clock-cells = <1>;
439 }; 396 };
440 397
441 fhctl: clock-controller@10209f 398 fhctl: clock-controller@10209f00 {
442 compatible = "mediatek 399 compatible = "mediatek,mt6795-fhctl";
443 reg = <0 0x10209f00 0 400 reg = <0 0x10209f00 0 0x100>;
444 status = "disabled"; 401 status = "disabled";
445 }; 402 };
446 403
447 gce: mailbox@10212000 { <<
448 compatible = "mediatek <<
449 reg = <0 0x10212000 0 <<
450 interrupts = <GIC_SPI <<
451 clocks = <&infracfg CL <<
452 clock-names = "gce"; <<
453 #mbox-cells = <2>; <<
454 }; <<
455 <<
456 mipi_tx0: dsi-phy@10215000 { <<
457 compatible = "mediatek <<
458 reg = <0 0x10215000 0 <<
459 clocks = <&clk26m>; <<
460 clock-output-names = " <<
461 #clock-cells = <0>; <<
462 #phy-cells = <0>; <<
463 status = "disabled"; <<
464 }; <<
465 <<
466 mipi_tx1: dsi-phy@10216000 { <<
467 compatible = "mediatek <<
468 reg = <0 0x10216000 0 <<
469 clocks = <&clk26m>; <<
470 clock-output-names = " <<
471 #clock-cells = <0>; <<
472 #phy-cells = <0>; <<
473 status = "disabled"; <<
474 }; <<
475 <<
476 gic: interrupt-controller@1022 404 gic: interrupt-controller@10221000 {
477 compatible = "arm,gic- 405 compatible = "arm,gic-400";
478 #interrupt-cells = <3> 406 #interrupt-cells = <3>;
479 interrupt-parent = <&g 407 interrupt-parent = <&gic>;
480 interrupt-controller; 408 interrupt-controller;
481 reg = <0 0x10221000 0 409 reg = <0 0x10221000 0 0x1000>,
482 <0 0x10222000 0 410 <0 0x10222000 0 0x2000>,
483 <0 0x10224000 0 411 <0 0x10224000 0 0x2000>,
484 <0 0x10226000 0 412 <0 0x10226000 0 0x2000>;
485 interrupts = <GIC_PPI 413 interrupts = <GIC_PPI 9
486 (GIC_CPU_MASK_ 414 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
487 }; 415 };
488 416
489 cci: cci@10390000 { 417 cci: cci@10390000 {
490 compatible = "arm,cci- 418 compatible = "arm,cci-400";
491 #address-cells = <1>; 419 #address-cells = <1>;
492 #size-cells = <1>; 420 #size-cells = <1>;
493 reg = <0 0x10390000 0 421 reg = <0 0x10390000 0 0x1000>;
494 ranges = <0 0 0x103900 422 ranges = <0 0 0x10390000 0x10000>;
495 423
496 cci_control0: slave-if 424 cci_control0: slave-if@1000 {
497 compatible = " 425 compatible = "arm,cci-400-ctrl-if";
498 interface-type 426 interface-type = "ace-lite";
499 reg = <0x1000 427 reg = <0x1000 0x1000>;
500 }; 428 };
501 429
502 cci_control1: slave-if 430 cci_control1: slave-if@4000 {
503 compatible = " 431 compatible = "arm,cci-400-ctrl-if";
504 interface-type 432 interface-type = "ace";
505 reg = <0x4000 433 reg = <0x4000 0x1000>;
506 }; 434 };
507 435
508 cci_control2: slave-if 436 cci_control2: slave-if@5000 {
509 compatible = " 437 compatible = "arm,cci-400-ctrl-if";
510 interface-type 438 interface-type = "ace";
511 reg = <0x5000 439 reg = <0x5000 0x1000>;
512 }; 440 };
513 441
514 pmu@9000 { 442 pmu@9000 {
515 compatible = " 443 compatible = "arm,cci-400-pmu,r1";
516 reg = <0x9000 444 reg = <0x9000 0x5000>;
517 interrupts = < 445 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
518 < 446 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
519 < 447 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
520 < 448 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
521 < 449 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522 }; 450 };
523 }; 451 };
524 452
525 uart0: serial@11002000 { 453 uart0: serial@11002000 {
526 compatible = "mediatek 454 compatible = "mediatek,mt6795-uart",
527 "mediatek 455 "mediatek,mt6577-uart";
528 reg = <0 0x11002000 0 456 reg = <0 0x11002000 0 0x400>;
529 interrupts = <GIC_SPI 457 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
530 clocks = <&pericfg CLK 458 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
531 clock-names = "baud", 459 clock-names = "baud", "bus";
532 dmas = <&apdma 0>, <&a 460 dmas = <&apdma 0>, <&apdma 1>;
533 dma-names = "tx", "rx" 461 dma-names = "tx", "rx";
534 status = "disabled"; 462 status = "disabled";
535 }; 463 };
536 464
537 uart1: serial@11003000 { 465 uart1: serial@11003000 {
538 compatible = "mediatek 466 compatible = "mediatek,mt6795-uart",
539 "mediatek 467 "mediatek,mt6577-uart";
540 reg = <0 0x11003000 0 468 reg = <0 0x11003000 0 0x400>;
541 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
542 clocks = <&pericfg CLK 470 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
543 clock-names = "baud", 471 clock-names = "baud", "bus";
544 dmas = <&apdma 2>, <&a 472 dmas = <&apdma 2>, <&apdma 3>;
545 dma-names = "tx", "rx" 473 dma-names = "tx", "rx";
546 status = "disabled"; 474 status = "disabled";
547 }; 475 };
548 476
549 apdma: dma-controller@11000380 477 apdma: dma-controller@11000380 {
550 compatible = "mediatek 478 compatible = "mediatek,mt6795-uart-dma",
551 "mediatek 479 "mediatek,mt6577-uart-dma";
552 reg = <0 0x11000380 0 480 reg = <0 0x11000380 0 0x60>,
553 <0 0x11000400 0 481 <0 0x11000400 0 0x60>,
554 <0 0x11000480 0 482 <0 0x11000480 0 0x60>,
555 <0 0x11000500 0 483 <0 0x11000500 0 0x60>,
556 <0 0x11000580 0 484 <0 0x11000580 0 0x60>,
557 <0 0x11000600 0 485 <0 0x11000600 0 0x60>,
558 <0 0x11000680 0 486 <0 0x11000680 0 0x60>,
559 <0 0x11000700 0 487 <0 0x11000700 0 0x60>;
560 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
561 <GIC_SPI 489 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
562 <GIC_SPI 490 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
563 <GIC_SPI 491 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
564 <GIC_SPI 492 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
565 <GIC_SPI 493 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
566 <GIC_SPI 494 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
567 <GIC_SPI 495 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
568 dma-requests = <8>; 496 dma-requests = <8>;
569 clocks = <&pericfg CLK 497 clocks = <&pericfg CLK_PERI_AP_DMA>;
570 clock-names = "apdma"; 498 clock-names = "apdma";
571 mediatek,dma-33bits; 499 mediatek,dma-33bits;
572 #dma-cells = <1>; 500 #dma-cells = <1>;
573 }; 501 };
574 502
575 uart2: serial@11004000 { 503 uart2: serial@11004000 {
576 compatible = "mediatek 504 compatible = "mediatek,mt6795-uart",
577 "mediatek 505 "mediatek,mt6577-uart";
578 reg = <0 0x11004000 0 506 reg = <0 0x11004000 0 0x400>;
579 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
580 clocks = <&pericfg CLK 508 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
581 clock-names = "baud", 509 clock-names = "baud", "bus";
582 dmas = <&apdma 4>, <&a 510 dmas = <&apdma 4>, <&apdma 5>;
583 dma-names = "tx", "rx" 511 dma-names = "tx", "rx";
584 status = "disabled"; 512 status = "disabled";
585 }; 513 };
586 514
587 uart3: serial@11005000 { 515 uart3: serial@11005000 {
588 compatible = "mediatek 516 compatible = "mediatek,mt6795-uart",
589 "mediatek 517 "mediatek,mt6577-uart";
590 reg = <0 0x11005000 0 518 reg = <0 0x11005000 0 0x400>;
591 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
592 clocks = <&pericfg CLK 520 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
593 clock-names = "baud", 521 clock-names = "baud", "bus";
594 dmas = <&apdma 6>, <&a 522 dmas = <&apdma 6>, <&apdma 7>;
595 dma-names = "tx", "rx" 523 dma-names = "tx", "rx";
596 status = "disabled"; 524 status = "disabled";
597 }; 525 };
598 526
599 pwm2: pwm@11006000 { 527 pwm2: pwm@11006000 {
600 compatible = "mediatek 528 compatible = "mediatek,mt6795-pwm";
601 reg = <0 0x11006000 0 529 reg = <0 0x11006000 0 0x1000>;
602 #pwm-cells = <2>; 530 #pwm-cells = <2>;
603 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CL 532 clocks = <&topckgen CLK_TOP_PWM_SEL>,
605 <&pericfg CLK 533 <&pericfg CLK_PERI_PWM>,
606 <&pericfg CLK 534 <&pericfg CLK_PERI_PWM1>,
607 <&pericfg CLK 535 <&pericfg CLK_PERI_PWM2>,
608 <&pericfg CLK 536 <&pericfg CLK_PERI_PWM3>,
609 <&pericfg CLK 537 <&pericfg CLK_PERI_PWM4>,
610 <&pericfg CLK 538 <&pericfg CLK_PERI_PWM5>,
611 <&pericfg CLK 539 <&pericfg CLK_PERI_PWM6>,
612 <&pericfg CLK 540 <&pericfg CLK_PERI_PWM7>;
613 clock-names = "top", " 541 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
614 "pwm4", 542 "pwm4", "pwm5", "pwm6", "pwm7";
615 status = "disabled"; 543 status = "disabled";
616 }; 544 };
617 545
618 i2c0: i2c@11007000 { 546 i2c0: i2c@11007000 {
619 compatible = "mediatek 547 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
620 reg = <0 0x11007000 0 548 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
621 interrupts = <GIC_SPI 549 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
622 clock-div = <16>; 550 clock-div = <16>;
623 clocks = <&pericfg CLK 551 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
624 clock-names = "main", 552 clock-names = "main", "dma";
625 #address-cells = <1>; 553 #address-cells = <1>;
626 #size-cells = <0>; 554 #size-cells = <0>;
627 status = "disabled"; 555 status = "disabled";
628 }; 556 };
629 557
630 i2c1: i2c@11008000 { 558 i2c1: i2c@11008000 {
631 compatible = "mediatek 559 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
632 reg = <0 0x11008000 0 560 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
633 interrupts = <GIC_SPI 561 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
634 clock-div = <16>; 562 clock-div = <16>;
635 clocks = <&pericfg CLK 563 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
636 clock-names = "main", 564 clock-names = "main", "dma";
637 #address-cells = <1>; 565 #address-cells = <1>;
638 #size-cells = <0>; 566 #size-cells = <0>;
639 status = "disabled"; 567 status = "disabled";
640 }; 568 };
641 569
642 i2c2: i2c@11009000 { 570 i2c2: i2c@11009000 {
643 compatible = "mediatek 571 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
644 reg = <0 0x11009000 0 572 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
645 interrupts = <GIC_SPI 573 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
646 clock-div = <16>; 574 clock-div = <16>;
647 clocks = <&pericfg CLK 575 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
648 clock-names = "main", 576 clock-names = "main", "dma";
649 #address-cells = <1>; 577 #address-cells = <1>;
650 #size-cells = <0>; 578 #size-cells = <0>;
651 status = "disabled"; 579 status = "disabled";
652 }; 580 };
653 581
654 i2c3: i2c@11010000 { 582 i2c3: i2c@11010000 {
655 compatible = "mediatek 583 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
656 reg = <0 0x11010000 0 584 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
657 interrupts = <GIC_SPI 585 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
658 clock-div = <16>; 586 clock-div = <16>;
659 clocks = <&pericfg CLK 587 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
660 clock-names = "main", 588 clock-names = "main", "dma";
661 #address-cells = <1>; 589 #address-cells = <1>;
662 #size-cells = <0>; 590 #size-cells = <0>;
663 status = "disabled"; 591 status = "disabled";
664 }; 592 };
665 593
666 i2c4: i2c@11011000 { 594 i2c4: i2c@11011000 {
667 compatible = "mediatek 595 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
668 reg = <0 0x11011000 0 596 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
669 interrupts = <GIC_SPI 597 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
670 clock-div = <16>; 598 clock-div = <16>;
671 clocks = <&pericfg CLK 599 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
672 clock-names = "main", 600 clock-names = "main", "dma";
673 #address-cells = <1>; 601 #address-cells = <1>;
674 #size-cells = <0>; 602 #size-cells = <0>;
675 status = "disabled"; 603 status = "disabled";
676 }; 604 };
677 605
678 mmc0: mmc@11230000 { 606 mmc0: mmc@11230000 {
679 compatible = "mediatek 607 compatible = "mediatek,mt6795-mmc";
680 reg = <0 0x11230000 0 608 reg = <0 0x11230000 0 0x1000>;
681 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
682 clocks = <&pericfg CLK 610 clocks = <&pericfg CLK_PERI_MSDC30_0>,
683 <&topckgen CL 611 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
684 <&topckgen CL 612 <&topckgen CLK_TOP_MSDC50_0_SEL>;
685 clock-names = "source" 613 clock-names = "source", "hclk", "source_cg";
686 status = "disabled"; 614 status = "disabled";
687 }; 615 };
688 616
689 mmc1: mmc@11240000 { 617 mmc1: mmc@11240000 {
690 compatible = "mediatek 618 compatible = "mediatek,mt6795-mmc";
691 reg = <0 0x11240000 0 619 reg = <0 0x11240000 0 0x1000>;
692 interrupts = <GIC_SPI 620 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&pericfg CLK 621 clocks = <&pericfg CLK_PERI_MSDC30_1>,
694 <&topckgen CL 622 <&topckgen CLK_TOP_AXI_SEL>;
695 clock-names = "source" 623 clock-names = "source", "hclk";
696 status = "disabled"; 624 status = "disabled";
697 }; 625 };
698 626
699 mmc2: mmc@11250000 { 627 mmc2: mmc@11250000 {
700 compatible = "mediatek 628 compatible = "mediatek,mt6795-mmc";
701 reg = <0 0x11250000 0 629 reg = <0 0x11250000 0 0x1000>;
702 interrupts = <GIC_SPI 630 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK 631 clocks = <&pericfg CLK_PERI_MSDC30_2>,
704 <&topckgen CL 632 <&topckgen CLK_TOP_AXI_SEL>;
705 clock-names = "source" 633 clock-names = "source", "hclk";
706 status = "disabled"; 634 status = "disabled";
707 }; 635 };
708 636
709 mmc3: mmc@11260000 { 637 mmc3: mmc@11260000 {
710 compatible = "mediatek 638 compatible = "mediatek,mt6795-mmc";
711 reg = <0 0x11260000 0 639 reg = <0 0x11260000 0 0x1000>;
712 interrupts = <GIC_SPI 640 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
713 clocks = <&pericfg CLK 641 clocks = <&pericfg CLK_PERI_MSDC30_3>,
714 <&topckgen CL 642 <&topckgen CLK_TOP_AXI_SEL>;
715 clock-names = "source" 643 clock-names = "source", "hclk";
716 status = "disabled"; 644 status = "disabled";
717 }; 645 };
718 646
719 mmsys: syscon@14000000 { <<
720 compatible = "mediatek <<
721 reg = <0 0x14000000 0 <<
722 power-domains = <&spm <<
723 assigned-clocks = <&to <<
724 assigned-clock-rates = <<
725 #clock-cells = <1>; <<
726 #reset-cells = <1>; <<
727 mboxes = <&gce 0 CMDQ_ <<
728 <&gce 1 CMDQ_ <<
729 mediatek,gce-client-re <<
730 }; <<
731 <<
732 ovl0: ovl@1400c000 { <<
733 compatible = "mediatek <<
734 reg = <0 0x1400c000 0 <<
735 interrupts = <GIC_SPI <<
736 power-domains = <&spm <<
737 clocks = <&mmsys CLK_M <<
738 iommus = <&iommu M4U_P <<
739 mediatek,gce-client-re <<
740 }; <<
741 <<
742 ovl1: ovl@1400d000 { <<
743 compatible = "mediatek <<
744 reg = <0 0x1400d000 0 <<
745 interrupts = <GIC_SPI <<
746 power-domains = <&spm <<
747 clocks = <&mmsys CLK_M <<
748 iommus = <&iommu M4U_P <<
749 mediatek,gce-client-re <<
750 }; <<
751 <<
752 rdma0: rdma@1400e000 { <<
753 compatible = "mediatek <<
754 reg = <0 0x1400e000 0 <<
755 interrupts = <GIC_SPI <<
756 power-domains = <&spm <<
757 clocks = <&mmsys CLK_M <<
758 iommus = <&iommu M4U_P <<
759 mediatek,gce-client-re <<
760 }; <<
761 <<
762 rdma1: rdma@1400f000 { <<
763 compatible = "mediatek <<
764 reg = <0 0x1400f000 0 <<
765 interrupts = <GIC_SPI <<
766 power-domains = <&spm <<
767 clocks = <&mmsys CLK_M <<
768 iommus = <&iommu M4U_P <<
769 mediatek,gce-client-re <<
770 }; <<
771 <<
772 rdma2: rdma@14010000 { <<
773 compatible = "mediatek <<
774 reg = <0 0x14010000 0 <<
775 interrupts = <GIC_SPI <<
776 power-domains = <&spm <<
777 clocks = <&mmsys CLK_M <<
778 iommus = <&iommu M4U_P <<
779 mediatek,gce-client-re <<
780 }; <<
781 <<
782 wdma0: wdma@14011000 { <<
783 compatible = "mediatek <<
784 reg = <0 0x14011000 0 <<
785 interrupts = <GIC_SPI <<
786 power-domains = <&spm <<
787 clocks = <&mmsys CLK_M <<
788 iommus = <&iommu M4U_P <<
789 mediatek,gce-client-re <<
790 }; <<
791 <<
792 wdma1: wdma@14012000 { <<
793 compatible = "mediatek <<
794 reg = <0 0x14012000 0 <<
795 interrupts = <GIC_SPI <<
796 power-domains = <&spm <<
797 clocks = <&mmsys CLK_M <<
798 iommus = <&iommu M4U_P <<
799 mediatek,gce-client-re <<
800 }; <<
801 <<
802 color0: color@14013000 { <<
803 compatible = "mediatek <<
804 reg = <0 0x14013000 0 <<
805 interrupts = <GIC_SPI <<
806 power-domains = <&spm <<
807 clocks = <&mmsys CLK_M <<
808 mediatek,gce-client-re <<
809 }; <<
810 <<
811 color1: color@14014000 { <<
812 compatible = "mediatek <<
813 reg = <0 0x14014000 0 <<
814 interrupts = <GIC_SPI <<
815 power-domains = <&spm <<
816 clocks = <&mmsys CLK_M <<
817 mediatek,gce-client-re <<
818 }; <<
819 <<
820 aal@14015000 { <<
821 compatible = "mediatek <<
822 reg = <0 0x14015000 0 <<
823 interrupts = <GIC_SPI <<
824 power-domains = <&spm <<
825 clocks = <&mmsys CLK_M <<
826 mediatek,gce-client-re <<
827 }; <<
828 <<
829 gamma@14016000 { <<
830 compatible = "mediatek <<
831 reg = <0 0x14016000 0 <<
832 interrupts = <GIC_SPI <<
833 power-domains = <&spm <<
834 clocks = <&mmsys CLK_M <<
835 mediatek,gce-client-re <<
836 }; <<
837 <<
838 merge@14017000 { <<
839 compatible = "mediatek <<
840 reg = <0 0x14017000 0 <<
841 power-domains = <&spm <<
842 clocks = <&mmsys CLK_M <<
843 }; <<
844 <<
845 split0: split@14018000 { <<
846 compatible = "mediatek <<
847 reg = <0 0x14018000 0 <<
848 power-domains = <&spm <<
849 clocks = <&mmsys CLK_M <<
850 }; <<
851 <<
852 split1: split@14019000 { <<
853 compatible = "mediatek <<
854 reg = <0 0x14019000 0 <<
855 power-domains = <&spm <<
856 clocks = <&mmsys CLK_M <<
857 }; <<
858 <<
859 ufoe@1401a000 { <<
860 compatible = "mediatek <<
861 reg = <0 0x1401a000 0 <<
862 interrupts = <GIC_SPI <<
863 power-domains = <&spm <<
864 clocks = <&mmsys CLK_M <<
865 mediatek,gce-client-re <<
866 }; <<
867 <<
868 dsi0: dsi@1401b000 { <<
869 compatible = "mediatek <<
870 reg = <0 0x1401b000 0 <<
871 interrupts = <GIC_SPI <<
872 power-domains = <&spm <<
873 clocks = <&mmsys CLK_M <<
874 <&mmsys CLK_M <<
875 <&mipi_tx0>; <<
876 clock-names = "engine" <<
877 phys = <&mipi_tx0>; <<
878 phy-names = "dphy"; <<
879 status = "disabled"; <<
880 }; <<
881 <<
882 dsi1: dsi@1401c000 { <<
883 compatible = "mediatek <<
884 reg = <0 0x1401c000 0 <<
885 interrupts = <GIC_SPI <<
886 power-domains = <&spm <<
887 clocks = <&mmsys CLK_M <<
888 <&mmsys CLK_M <<
889 <&mipi_tx1>; <<
890 clock-names = "engine" <<
891 phys = <&mipi_tx1>; <<
892 phy-names = "dphy"; <<
893 status = "disabled"; <<
894 }; <<
895 <<
896 dpi0: dpi@1401d000 { <<
897 compatible = "mediatek <<
898 reg = <0 0x1401d000 0 <<
899 interrupts = <GIC_SPI <<
900 power-domains = <&spm <<
901 clocks = <&mmsys CLK_M <<
902 <&mmsys CLK_M <<
903 <&apmixedsys <<
904 clock-names = "pixel", <<
905 status = "disabled"; <<
906 }; <<
907 <<
908 pwm0: pwm@1401e000 { <<
909 compatible = "mediatek <<
910 reg = <0 0x1401e000 0 <<
911 #pwm-cells = <2>; <<
912 clocks = <&mmsys CLK_M <<
913 clock-names = "main", <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 pwm1: pwm@1401f000 { <<
918 compatible = "mediatek <<
919 reg = <0 0x1401f000 0 <<
920 #pwm-cells = <2>; <<
921 clocks = <&mmsys CLK_M <<
922 clock-names = "main", <<
923 status = "disabled"; <<
924 }; <<
925 <<
926 mutex: mutex@14020000 { <<
927 compatible = "mediatek <<
928 reg = <0 0x14020000 0 <<
929 interrupts = <GIC_SPI <<
930 power-domains = <&spm <<
931 clocks = <&mmsys CLK_M <<
932 mediatek,gce-events = <<
933 <<
934 mediatek,gce-client-re <<
935 }; <<
936 <<
937 larb0: larb@14021000 { <<
938 compatible = "mediatek <<
939 reg = <0 0x14021000 0 <<
940 clocks = <&mmsys CLK_M <<
941 clock-names = "apb", " <<
942 mediatek,smi = <&smi_c <<
943 mediatek,larb-id = <0> <<
944 power-domains = <&spm <<
945 }; <<
946 <<
947 smi_common: smi@14022000 { <<
948 compatible = "mediatek <<
949 reg = <0 0x14022000 0 <<
950 power-domains = <&spm <<
951 clocks = <&infracfg CL <<
952 clock-names = "apb", " <<
953 }; <<
954 <<
955 od@14023000 { <<
956 compatible = "mediatek <<
957 reg = <0 0x14023000 0 <<
958 clocks = <&mmsys CLK_M <<
959 mediatek,gce-client-re <<
960 }; <<
961 <<
962 larb2: larb@15001000 { <<
963 compatible = "mediatek <<
964 reg = <0 0x15001000 0 <<
965 clocks = <&mmsys CLK_M <<
966 clock-names = "apb", " <<
967 mediatek,smi = <&smi_c <<
968 mediatek,larb-id = <2> <<
969 power-domains = <&spm <<
970 }; <<
971 <<
972 vdecsys: clock-controller@1600 647 vdecsys: clock-controller@16000000 {
973 compatible = "mediatek 648 compatible = "mediatek,mt6795-vdecsys";
974 reg = <0 0x16000000 0 649 reg = <0 0x16000000 0 0x1000>;
975 #clock-cells = <1>; 650 #clock-cells = <1>;
976 }; 651 };
977 652
978 larb1: larb@16010000 { <<
979 compatible = "mediatek <<
980 reg = <0 0x16010000 0 <<
981 mediatek,smi = <&smi_c <<
982 mediatek,larb-id = <1> <<
983 clocks = <&vdecsys CLK <<
984 clock-names = "apb", " <<
985 power-domains = <&spm <<
986 }; <<
987 <<
988 vencsys: clock-controller@1800 653 vencsys: clock-controller@18000000 {
989 compatible = "mediatek 654 compatible = "mediatek,mt6795-vencsys";
990 reg = <0 0x18000000 0 655 reg = <0 0x18000000 0 0x1000>;
991 #clock-cells = <1>; 656 #clock-cells = <1>;
992 }; <<
993 <<
994 larb3: larb@18001000 { <<
995 compatible = "mediatek <<
996 reg = <0 0x18001000 0 <<
997 clocks = <&vencsys CLK <<
998 clock-names = "apb", " <<
999 mediatek,smi = <&smi_c <<
1000 mediatek,larb-id = <3 <<
1001 power-domains = <&spm <<
1002 }; 657 };
1003 }; 658 };
1004 }; 659 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.