1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2015 MediaTek Inc. 3 * Copyright (c) 2015 MediaTek Inc.
4 * Copyright (C) 2023 Collabora Ltd. !! 4 * Author: Mars.C <mars.cheng@mediatek.com>
5 * Authors: Mars.C <mars.cheng@mediatek.com> <<
6 * AngeloGioacchino Del Regno <angelog <<
7 */ 5 */
8 6
9 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-cl 9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce. 10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port. 11 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h 12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h> 13 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-re 14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
17 15
18 / { 16 / {
19 compatible = "mediatek,mt6795"; 17 compatible = "mediatek,mt6795";
20 interrupt-parent = <&sysirq>; 18 interrupt-parent = <&sysirq>;
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 aliases { <<
25 ovl0 = &ovl0; <<
26 ovl1 = &ovl1; <<
27 rdma0 = &rdma0; <<
28 rdma1 = &rdma1; <<
29 rdma2 = &rdma2; <<
30 wdma0 = &wdma0; <<
31 wdma1 = &wdma1; <<
32 color0 = &color0; <<
33 color1 = &color1; <<
34 split0 = &split0; <<
35 split1 = &split1; <<
36 dpi0 = &dpi0; <<
37 dsi0 = &dsi0; <<
38 dsi1 = &dsi1; <<
39 }; <<
40 <<
41 psci { 22 psci {
42 compatible = "arm,psci-0.2"; 23 compatible = "arm,psci-0.2";
43 method = "smc"; 24 method = "smc";
44 }; 25 };
45 26
46 cpus { 27 cpus {
47 #address-cells = <1>; 28 #address-cells = <1>;
48 #size-cells = <0>; 29 #size-cells = <0>;
49 30
50 cpu0: cpu@0 { 31 cpu0: cpu@0 {
51 device_type = "cpu"; 32 device_type = "cpu";
52 compatible = "arm,cort 33 compatible = "arm,cortex-a53";
53 enable-method = "psci" 34 enable-method = "psci";
54 reg = <0x000>; 35 reg = <0x000>;
55 cci-control-port = <&c 36 cci-control-port = <&cci_control2>;
56 next-level-cache = <&l 37 next-level-cache = <&l2_0>;
57 }; 38 };
58 39
59 cpu1: cpu@1 { 40 cpu1: cpu@1 {
60 device_type = "cpu"; 41 device_type = "cpu";
61 compatible = "arm,cort 42 compatible = "arm,cortex-a53";
62 enable-method = "psci" 43 enable-method = "psci";
63 reg = <0x001>; 44 reg = <0x001>;
64 cci-control-port = <&c 45 cci-control-port = <&cci_control2>;
65 i-cache-size = <32768> 46 i-cache-size = <32768>;
66 i-cache-line-size = <6 47 i-cache-line-size = <64>;
67 i-cache-sets = <256>; 48 i-cache-sets = <256>;
68 d-cache-size = <32768> 49 d-cache-size = <32768>;
69 d-cache-line-size = <6 50 d-cache-line-size = <64>;
70 d-cache-sets = <128>; 51 d-cache-sets = <128>;
71 next-level-cache = <&l 52 next-level-cache = <&l2_0>;
72 }; 53 };
73 54
74 cpu2: cpu@2 { 55 cpu2: cpu@2 {
75 device_type = "cpu"; 56 device_type = "cpu";
76 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
77 enable-method = "psci" 58 enable-method = "psci";
78 reg = <0x002>; 59 reg = <0x002>;
79 cci-control-port = <&c 60 cci-control-port = <&cci_control2>;
80 i-cache-size = <32768> 61 i-cache-size = <32768>;
81 i-cache-line-size = <6 62 i-cache-line-size = <64>;
82 i-cache-sets = <256>; 63 i-cache-sets = <256>;
83 d-cache-size = <32768> 64 d-cache-size = <32768>;
84 d-cache-line-size = <6 65 d-cache-line-size = <64>;
85 d-cache-sets = <128>; 66 d-cache-sets = <128>;
86 next-level-cache = <&l 67 next-level-cache = <&l2_0>;
87 }; 68 };
88 69
89 cpu3: cpu@3 { 70 cpu3: cpu@3 {
90 device_type = "cpu"; 71 device_type = "cpu";
91 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
92 enable-method = "psci" 73 enable-method = "psci";
93 reg = <0x003>; 74 reg = <0x003>;
94 cci-control-port = <&c 75 cci-control-port = <&cci_control2>;
95 i-cache-size = <32768> 76 i-cache-size = <32768>;
96 i-cache-line-size = <6 77 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 78 i-cache-sets = <256>;
98 d-cache-size = <32768> 79 d-cache-size = <32768>;
99 d-cache-line-size = <6 80 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 81 d-cache-sets = <128>;
101 next-level-cache = <&l 82 next-level-cache = <&l2_0>;
102 }; 83 };
103 84
104 cpu4: cpu@100 { 85 cpu4: cpu@100 {
105 device_type = "cpu"; 86 device_type = "cpu";
106 compatible = "arm,cort 87 compatible = "arm,cortex-a53";
107 enable-method = "psci" 88 enable-method = "psci";
108 reg = <0x100>; 89 reg = <0x100>;
109 cci-control-port = <&c 90 cci-control-port = <&cci_control1>;
110 i-cache-size = <32768> 91 i-cache-size = <32768>;
111 i-cache-line-size = <6 92 i-cache-line-size = <64>;
112 i-cache-sets = <256>; 93 i-cache-sets = <256>;
113 d-cache-size = <32768> 94 d-cache-size = <32768>;
114 d-cache-line-size = <6 95 d-cache-line-size = <64>;
115 d-cache-sets = <128>; 96 d-cache-sets = <128>;
116 next-level-cache = <&l 97 next-level-cache = <&l2_1>;
117 }; 98 };
118 99
119 cpu5: cpu@101 { 100 cpu5: cpu@101 {
120 device_type = "cpu"; 101 device_type = "cpu";
121 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
122 enable-method = "psci" 103 enable-method = "psci";
123 reg = <0x101>; 104 reg = <0x101>;
124 cci-control-port = <&c 105 cci-control-port = <&cci_control1>;
125 i-cache-size = <32768> 106 i-cache-size = <32768>;
126 i-cache-line-size = <6 107 i-cache-line-size = <64>;
127 i-cache-sets = <256>; 108 i-cache-sets = <256>;
128 d-cache-size = <32768> 109 d-cache-size = <32768>;
129 d-cache-line-size = <6 110 d-cache-line-size = <64>;
130 d-cache-sets = <128>; 111 d-cache-sets = <128>;
131 next-level-cache = <&l 112 next-level-cache = <&l2_1>;
132 }; 113 };
133 114
134 cpu6: cpu@102 { 115 cpu6: cpu@102 {
135 device_type = "cpu"; 116 device_type = "cpu";
136 compatible = "arm,cort 117 compatible = "arm,cortex-a53";
137 enable-method = "psci" 118 enable-method = "psci";
138 reg = <0x102>; 119 reg = <0x102>;
139 cci-control-port = <&c 120 cci-control-port = <&cci_control1>;
140 i-cache-size = <32768> 121 i-cache-size = <32768>;
141 i-cache-line-size = <6 122 i-cache-line-size = <64>;
142 i-cache-sets = <256>; 123 i-cache-sets = <256>;
143 d-cache-size = <32768> 124 d-cache-size = <32768>;
144 d-cache-line-size = <6 125 d-cache-line-size = <64>;
145 d-cache-sets = <128>; 126 d-cache-sets = <128>;
146 next-level-cache = <&l 127 next-level-cache = <&l2_1>;
147 }; 128 };
148 129
149 cpu7: cpu@103 { 130 cpu7: cpu@103 {
150 device_type = "cpu"; 131 device_type = "cpu";
151 compatible = "arm,cort 132 compatible = "arm,cortex-a53";
152 enable-method = "psci" 133 enable-method = "psci";
153 reg = <0x103>; 134 reg = <0x103>;
154 cci-control-port = <&c 135 cci-control-port = <&cci_control1>;
155 i-cache-size = <32768> 136 i-cache-size = <32768>;
156 i-cache-line-size = <6 137 i-cache-line-size = <64>;
157 i-cache-sets = <256>; 138 i-cache-sets = <256>;
158 d-cache-size = <32768> 139 d-cache-size = <32768>;
159 d-cache-line-size = <6 140 d-cache-line-size = <64>;
160 d-cache-sets = <128>; 141 d-cache-sets = <128>;
161 next-level-cache = <&l 142 next-level-cache = <&l2_1>;
162 }; 143 };
163 144
164 cpu-map { 145 cpu-map {
165 cluster0 { 146 cluster0 {
166 core0 { 147 core0 {
167 cpu = 148 cpu = <&cpu0>;
168 }; 149 };
169 150
170 core1 { 151 core1 {
171 cpu = 152 cpu = <&cpu1>;
172 }; 153 };
173 154
174 core2 { 155 core2 {
175 cpu = 156 cpu = <&cpu2>;
176 }; 157 };
177 158
178 core3 { 159 core3 {
179 cpu = 160 cpu = <&cpu3>;
180 }; 161 };
181 }; 162 };
182 163
183 cluster1 { 164 cluster1 {
184 core0 { 165 core0 {
185 cpu = 166 cpu = <&cpu4>;
186 }; 167 };
187 168
188 core1 { 169 core1 {
189 cpu = 170 cpu = <&cpu5>;
190 }; 171 };
191 172
192 core2 { 173 core2 {
193 cpu = 174 cpu = <&cpu6>;
194 }; 175 };
195 176
196 core3 { 177 core3 {
197 cpu = 178 cpu = <&cpu7>;
198 }; 179 };
199 }; 180 };
200 }; 181 };
201 182
202 l2_0: l2-cache0 { 183 l2_0: l2-cache0 {
203 compatible = "cache"; 184 compatible = "cache";
204 cache-level = <2>; 185 cache-level = <2>;
205 cache-size = <1048576> 186 cache-size = <1048576>;
206 cache-line-size = <64> 187 cache-line-size = <64>;
207 cache-sets = <1024>; 188 cache-sets = <1024>;
208 cache-unified; 189 cache-unified;
209 }; 190 };
210 191
211 l2_1: l2-cache1 { 192 l2_1: l2-cache1 {
212 compatible = "cache"; 193 compatible = "cache";
213 cache-level = <2>; 194 cache-level = <2>;
214 cache-size = <1048576> 195 cache-size = <1048576>;
215 cache-line-size = <64> 196 cache-line-size = <64>;
216 cache-sets = <1024>; 197 cache-sets = <1024>;
217 cache-unified; 198 cache-unified;
218 }; 199 };
219 }; 200 };
220 201
221 clk26m: oscillator-26m { 202 clk26m: oscillator-26m {
222 compatible = "fixed-clock"; 203 compatible = "fixed-clock";
223 #clock-cells = <0>; 204 #clock-cells = <0>;
224 clock-frequency = <26000000>; 205 clock-frequency = <26000000>;
225 clock-output-names = "clk26m"; 206 clock-output-names = "clk26m";
226 }; 207 };
227 208
228 clk32k: oscillator-32k { 209 clk32k: oscillator-32k {
229 compatible = "fixed-clock"; 210 compatible = "fixed-clock";
230 #clock-cells = <0>; 211 #clock-cells = <0>;
231 clock-frequency = <32000>; 212 clock-frequency = <32000>;
232 clock-output-names = "clk32k"; 213 clock-output-names = "clk32k";
233 }; 214 };
234 215
235 system_clk: dummy13m { 216 system_clk: dummy13m {
236 compatible = "fixed-clock"; 217 compatible = "fixed-clock";
237 clock-frequency = <13000000>; 218 clock-frequency = <13000000>;
238 #clock-cells = <0>; 219 #clock-cells = <0>;
239 }; 220 };
240 221
241 pmu { 222 pmu {
242 compatible = "arm,cortex-a53-p 223 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_SPI 8 IRQ_T 224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
244 <GIC_SPI 9 IRQ_T 225 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_SPI 10 IRQ_T 226 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_SPI 11 IRQ_T 227 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-affinity = <&cpu0>, 228 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
248 }; 229 };
249 230
250 timer { 231 timer {
251 compatible = "arm,armv8-timer" 232 compatible = "arm,armv8-timer";
252 interrupt-parent = <&gic>; 233 interrupt-parent = <&gic>;
253 interrupts = <GIC_PPI 13 234 interrupts = <GIC_PPI 13
254 (GIC_CPU_MASK_SIM 235 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
255 <GIC_PPI 14 236 <GIC_PPI 14
256 (GIC_CPU_MASK_SIM 237 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
257 <GIC_PPI 11 238 <GIC_PPI 11
258 (GIC_CPU_MASK_SIM 239 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 10 240 <GIC_PPI 10
260 (GIC_CPU_MASK_SIM 241 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
261 }; 242 };
262 243
263 soc { 244 soc {
264 #address-cells = <2>; 245 #address-cells = <2>;
265 #size-cells = <2>; 246 #size-cells = <2>;
266 compatible = "simple-bus"; 247 compatible = "simple-bus";
267 ranges; 248 ranges;
268 249
269 topckgen: syscon@10000000 { 250 topckgen: syscon@10000000 {
270 compatible = "mediatek 251 compatible = "mediatek,mt6795-topckgen", "syscon";
271 reg = <0 0x10000000 0 252 reg = <0 0x10000000 0 0x1000>;
272 #clock-cells = <1>; 253 #clock-cells = <1>;
273 }; 254 };
274 255
275 infracfg: syscon@10001000 { 256 infracfg: syscon@10001000 {
276 compatible = "mediatek 257 compatible = "mediatek,mt6795-infracfg", "syscon";
277 reg = <0 0x10001000 0 258 reg = <0 0x10001000 0 0x1000>;
278 #clock-cells = <1>; 259 #clock-cells = <1>;
279 #reset-cells = <1>; 260 #reset-cells = <1>;
280 }; 261 };
281 262
282 pericfg: syscon@10003000 { 263 pericfg: syscon@10003000 {
283 compatible = "mediatek 264 compatible = "mediatek,mt6795-pericfg", "syscon";
284 reg = <0 0x10003000 0 265 reg = <0 0x10003000 0 0x1000>;
285 #clock-cells = <1>; 266 #clock-cells = <1>;
286 #reset-cells = <1>; 267 #reset-cells = <1>;
287 }; 268 };
288 269
289 scpsys: syscon@10006000 { 270 scpsys: syscon@10006000 {
290 compatible = "syscon", 271 compatible = "syscon", "simple-mfd";
291 reg = <0 0x10006000 0 272 reg = <0 0x10006000 0 0x1000>;
292 #power-domain-cells = 273 #power-domain-cells = <1>;
293 274
294 /* System Power Manage 275 /* System Power Manager */
295 spm: power-controller 276 spm: power-controller {
296 compatible = " 277 compatible = "mediatek,mt6795-power-controller";
297 #address-cells 278 #address-cells = <1>;
298 #size-cells = 279 #size-cells = <0>;
299 #power-domain- 280 #power-domain-cells = <1>;
300 281
301 /* power domai 282 /* power domains of the SoC */
302 power-domain@M 283 power-domain@MT6795_POWER_DOMAIN_VDEC {
303 reg = 284 reg = <MT6795_POWER_DOMAIN_VDEC>;
304 clocks 285 clocks = <&topckgen CLK_TOP_MM_SEL>;
305 clock- 286 clock-names = "mm";
306 #power 287 #power-domain-cells = <0>;
307 }; 288 };
308 power-domain@M 289 power-domain@MT6795_POWER_DOMAIN_VENC {
309 reg = 290 reg = <MT6795_POWER_DOMAIN_VENC>;
310 clocks 291 clocks = <&topckgen CLK_TOP_MM_SEL>,
311 292 <&topckgen CLK_TOP_VENC_SEL>;
312 clock- 293 clock-names = "mm", "venc";
313 #power 294 #power-domain-cells = <0>;
314 }; 295 };
315 power-domain@M 296 power-domain@MT6795_POWER_DOMAIN_ISP {
316 reg = 297 reg = <MT6795_POWER_DOMAIN_ISP>;
317 clocks 298 clocks = <&topckgen CLK_TOP_MM_SEL>;
318 clock- 299 clock-names = "mm";
319 #power 300 #power-domain-cells = <0>;
320 }; 301 };
321 302
322 power-domain@M 303 power-domain@MT6795_POWER_DOMAIN_MM {
323 reg = 304 reg = <MT6795_POWER_DOMAIN_MM>;
324 clocks 305 clocks = <&topckgen CLK_TOP_MM_SEL>;
325 clock- 306 clock-names = "mm";
326 #power 307 #power-domain-cells = <0>;
327 mediat 308 mediatek,infracfg = <&infracfg>;
328 }; 309 };
329 310
330 power-domain@M 311 power-domain@MT6795_POWER_DOMAIN_MJC {
331 reg = 312 reg = <MT6795_POWER_DOMAIN_MJC>;
332 clocks 313 clocks = <&topckgen CLK_TOP_MM_SEL>,
333 314 <&topckgen CLK_TOP_MJC_SEL>;
334 clock- 315 clock-names = "mm", "mjc";
335 #power 316 #power-domain-cells = <0>;
336 }; 317 };
337 318
338 power-domain@M 319 power-domain@MT6795_POWER_DOMAIN_AUDIO {
339 reg = 320 reg = <MT6795_POWER_DOMAIN_AUDIO>;
340 #power 321 #power-domain-cells = <0>;
341 }; 322 };
342 323
343 mfg_async: pow 324 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
344 reg = 325 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>;
345 clocks 326 clocks = <&clk26m>;
346 clock- 327 clock-names = "mfg";
347 #addre 328 #address-cells = <1>;
348 #size- 329 #size-cells = <0>;
349 #power 330 #power-domain-cells = <1>;
350 331
351 power- 332 power-domain@MT6795_POWER_DOMAIN_MFG_2D {
352 333 reg = <MT6795_POWER_DOMAIN_MFG_2D>;
353 334 #address-cells = <1>;
354 335 #size-cells = <0>;
355 336 #power-domain-cells = <1>;
356 337
357 338 power-domain@MT6795_POWER_DOMAIN_MFG {
358 339 reg = <MT6795_POWER_DOMAIN_MFG>;
359 340 #power-domain-cells = <0>;
360 341 mediatek,infracfg = <&infracfg>;
361 342 };
362 }; 343 };
363 }; 344 };
364 }; 345 };
365 }; 346 };
366 347
367 pio: pinctrl@10005000 { 348 pio: pinctrl@10005000 {
368 compatible = "mediatek 349 compatible = "mediatek,mt6795-pinctrl";
369 reg = <0 0x10005000 0 350 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
370 reg-names = "base", "e 351 reg-names = "base", "eint";
371 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 353 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
373 gpio-controller; 354 gpio-controller;
374 #gpio-cells = <2>; 355 #gpio-cells = <2>;
375 gpio-ranges = <&pio 0 356 gpio-ranges = <&pio 0 0 196>;
376 interrupt-controller; 357 interrupt-controller;
377 #interrupt-cells = <2> 358 #interrupt-cells = <2>;
378 }; 359 };
379 360
380 watchdog: watchdog@10007000 { 361 watchdog: watchdog@10007000 {
381 compatible = "mediatek 362 compatible = "mediatek,mt6795-wdt";
382 reg = <0 0x10007000 0 363 reg = <0 0x10007000 0 0x100>;
383 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
384 #reset-cells = <1>; 365 #reset-cells = <1>;
385 timeout-sec = <20>; 366 timeout-sec = <20>;
386 }; 367 };
387 368
388 timer: timer@10008000 { 369 timer: timer@10008000 {
389 compatible = "mediatek 370 compatible = "mediatek,mt6795-timer",
390 "mediatek 371 "mediatek,mt6577-timer";
391 reg = <0 0x10008000 0 372 reg = <0 0x10008000 0 0x1000>;
392 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
393 clocks = <&system_clk> 374 clocks = <&system_clk>, <&clk32k>;
394 }; 375 };
395 376
396 pwrap: pwrap@1000d000 { 377 pwrap: pwrap@1000d000 {
397 compatible = "mediatek 378 compatible = "mediatek,mt6795-pwrap";
398 reg = <0 0x1000d000 0 379 reg = <0 0x1000d000 0 0x1000>;
399 reg-names = "pwrap"; 380 reg-names = "pwrap";
400 interrupts = <GIC_SPI 381 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
401 resets = <&infracfg MT 382 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>;
402 reset-names = "pwrap"; 383 reset-names = "pwrap";
403 clocks = <&topckgen CL 384 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>;
404 clock-names = "spi", " 385 clock-names = "spi", "wrap";
405 }; 386 };
406 387
407 sysirq: intpol-controller@1020 388 sysirq: intpol-controller@10200620 {
408 compatible = "mediatek 389 compatible = "mediatek,mt6795-sysirq",
409 "mediatek 390 "mediatek,mt6577-sysirq";
410 interrupt-controller; 391 interrupt-controller;
411 #interrupt-cells = <3> 392 #interrupt-cells = <3>;
412 interrupt-parent = <&g 393 interrupt-parent = <&gic>;
413 reg = <0 0x10200620 0 394 reg = <0 0x10200620 0 0x20>;
414 }; 395 };
415 396
416 systimer: timer@10200670 { 397 systimer: timer@10200670 {
417 compatible = "mediatek 398 compatible = "mediatek,mt6795-systimer";
418 reg = <0 0x10200670 0 399 reg = <0 0x10200670 0 0x10>;
419 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&system_clk> 401 clocks = <&system_clk>;
421 clock-names = "clk13m" 402 clock-names = "clk13m";
422 }; 403 };
423 404
424 iommu: iommu@10205000 { 405 iommu: iommu@10205000 {
425 compatible = "mediatek 406 compatible = "mediatek,mt6795-m4u";
426 reg = <0 0x10205000 0 407 reg = <0 0x10205000 0 0x1000>;
427 clocks = <&infracfg CL 408 clocks = <&infracfg CLK_INFRA_M4U>;
428 clock-names = "bclk"; 409 clock-names = "bclk";
429 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
430 mediatek,larbs = <&lar 411 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
431 power-domains = <&spm 412 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
432 #iommu-cells = <1>; 413 #iommu-cells = <1>;
433 }; 414 };
434 415
435 apmixedsys: syscon@10209000 { 416 apmixedsys: syscon@10209000 {
436 compatible = "mediatek 417 compatible = "mediatek,mt6795-apmixedsys", "syscon";
437 reg = <0 0x10209000 0 418 reg = <0 0x10209000 0 0x1000>;
438 #clock-cells = <1>; 419 #clock-cells = <1>;
439 }; 420 };
440 421
441 fhctl: clock-controller@10209f 422 fhctl: clock-controller@10209f00 {
442 compatible = "mediatek 423 compatible = "mediatek,mt6795-fhctl";
443 reg = <0 0x10209f00 0 424 reg = <0 0x10209f00 0 0x100>;
444 status = "disabled"; 425 status = "disabled";
445 }; 426 };
446 427
447 gce: mailbox@10212000 { 428 gce: mailbox@10212000 {
448 compatible = "mediatek 429 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
449 reg = <0 0x10212000 0 430 reg = <0 0x10212000 0 0x1000>;
450 interrupts = <GIC_SPI 431 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
451 clocks = <&infracfg CL 432 clocks = <&infracfg CLK_INFRA_GCE>;
452 clock-names = "gce"; 433 clock-names = "gce";
453 #mbox-cells = <2>; 434 #mbox-cells = <2>;
454 }; 435 };
455 436
456 mipi_tx0: dsi-phy@10215000 { <<
457 compatible = "mediatek <<
458 reg = <0 0x10215000 0 <<
459 clocks = <&clk26m>; <<
460 clock-output-names = " <<
461 #clock-cells = <0>; <<
462 #phy-cells = <0>; <<
463 status = "disabled"; <<
464 }; <<
465 <<
466 mipi_tx1: dsi-phy@10216000 { <<
467 compatible = "mediatek <<
468 reg = <0 0x10216000 0 <<
469 clocks = <&clk26m>; <<
470 clock-output-names = " <<
471 #clock-cells = <0>; <<
472 #phy-cells = <0>; <<
473 status = "disabled"; <<
474 }; <<
475 <<
476 gic: interrupt-controller@1022 437 gic: interrupt-controller@10221000 {
477 compatible = "arm,gic- 438 compatible = "arm,gic-400";
478 #interrupt-cells = <3> 439 #interrupt-cells = <3>;
479 interrupt-parent = <&g 440 interrupt-parent = <&gic>;
480 interrupt-controller; 441 interrupt-controller;
481 reg = <0 0x10221000 0 442 reg = <0 0x10221000 0 0x1000>,
482 <0 0x10222000 0 443 <0 0x10222000 0 0x2000>,
483 <0 0x10224000 0 444 <0 0x10224000 0 0x2000>,
484 <0 0x10226000 0 445 <0 0x10226000 0 0x2000>;
485 interrupts = <GIC_PPI 446 interrupts = <GIC_PPI 9
486 (GIC_CPU_MASK_ 447 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
487 }; 448 };
488 449
489 cci: cci@10390000 { 450 cci: cci@10390000 {
490 compatible = "arm,cci- 451 compatible = "arm,cci-400";
491 #address-cells = <1>; 452 #address-cells = <1>;
492 #size-cells = <1>; 453 #size-cells = <1>;
493 reg = <0 0x10390000 0 454 reg = <0 0x10390000 0 0x1000>;
494 ranges = <0 0 0x103900 455 ranges = <0 0 0x10390000 0x10000>;
495 456
496 cci_control0: slave-if 457 cci_control0: slave-if@1000 {
497 compatible = " 458 compatible = "arm,cci-400-ctrl-if";
498 interface-type 459 interface-type = "ace-lite";
499 reg = <0x1000 460 reg = <0x1000 0x1000>;
500 }; 461 };
501 462
502 cci_control1: slave-if 463 cci_control1: slave-if@4000 {
503 compatible = " 464 compatible = "arm,cci-400-ctrl-if";
504 interface-type 465 interface-type = "ace";
505 reg = <0x4000 466 reg = <0x4000 0x1000>;
506 }; 467 };
507 468
508 cci_control2: slave-if 469 cci_control2: slave-if@5000 {
509 compatible = " 470 compatible = "arm,cci-400-ctrl-if";
510 interface-type 471 interface-type = "ace";
511 reg = <0x5000 472 reg = <0x5000 0x1000>;
512 }; 473 };
513 474
514 pmu@9000 { 475 pmu@9000 {
515 compatible = " 476 compatible = "arm,cci-400-pmu,r1";
516 reg = <0x9000 477 reg = <0x9000 0x5000>;
517 interrupts = < 478 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
518 < 479 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
519 < 480 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
520 < 481 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
521 < 482 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522 }; 483 };
523 }; 484 };
524 485
525 uart0: serial@11002000 { 486 uart0: serial@11002000 {
526 compatible = "mediatek 487 compatible = "mediatek,mt6795-uart",
527 "mediatek 488 "mediatek,mt6577-uart";
528 reg = <0 0x11002000 0 489 reg = <0 0x11002000 0 0x400>;
529 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
530 clocks = <&pericfg CLK 491 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
531 clock-names = "baud", 492 clock-names = "baud", "bus";
532 dmas = <&apdma 0>, <&a 493 dmas = <&apdma 0>, <&apdma 1>;
533 dma-names = "tx", "rx" 494 dma-names = "tx", "rx";
534 status = "disabled"; 495 status = "disabled";
535 }; 496 };
536 497
537 uart1: serial@11003000 { 498 uart1: serial@11003000 {
538 compatible = "mediatek 499 compatible = "mediatek,mt6795-uart",
539 "mediatek 500 "mediatek,mt6577-uart";
540 reg = <0 0x11003000 0 501 reg = <0 0x11003000 0 0x400>;
541 interrupts = <GIC_SPI 502 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
542 clocks = <&pericfg CLK 503 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
543 clock-names = "baud", 504 clock-names = "baud", "bus";
544 dmas = <&apdma 2>, <&a 505 dmas = <&apdma 2>, <&apdma 3>;
545 dma-names = "tx", "rx" 506 dma-names = "tx", "rx";
546 status = "disabled"; 507 status = "disabled";
547 }; 508 };
548 509
549 apdma: dma-controller@11000380 510 apdma: dma-controller@11000380 {
550 compatible = "mediatek 511 compatible = "mediatek,mt6795-uart-dma",
551 "mediatek 512 "mediatek,mt6577-uart-dma";
552 reg = <0 0x11000380 0 513 reg = <0 0x11000380 0 0x60>,
553 <0 0x11000400 0 514 <0 0x11000400 0 0x60>,
554 <0 0x11000480 0 515 <0 0x11000480 0 0x60>,
555 <0 0x11000500 0 516 <0 0x11000500 0 0x60>,
556 <0 0x11000580 0 517 <0 0x11000580 0 0x60>,
557 <0 0x11000600 0 518 <0 0x11000600 0 0x60>,
558 <0 0x11000680 0 519 <0 0x11000680 0 0x60>,
559 <0 0x11000700 0 520 <0 0x11000700 0 0x60>;
560 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
561 <GIC_SPI 522 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
562 <GIC_SPI 523 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
563 <GIC_SPI 524 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
564 <GIC_SPI 525 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
565 <GIC_SPI 526 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
566 <GIC_SPI 527 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
567 <GIC_SPI 528 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
568 dma-requests = <8>; 529 dma-requests = <8>;
569 clocks = <&pericfg CLK 530 clocks = <&pericfg CLK_PERI_AP_DMA>;
570 clock-names = "apdma"; 531 clock-names = "apdma";
571 mediatek,dma-33bits; 532 mediatek,dma-33bits;
572 #dma-cells = <1>; 533 #dma-cells = <1>;
573 }; 534 };
574 535
575 uart2: serial@11004000 { 536 uart2: serial@11004000 {
576 compatible = "mediatek 537 compatible = "mediatek,mt6795-uart",
577 "mediatek 538 "mediatek,mt6577-uart";
578 reg = <0 0x11004000 0 539 reg = <0 0x11004000 0 0x400>;
579 interrupts = <GIC_SPI 540 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
580 clocks = <&pericfg CLK 541 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
581 clock-names = "baud", 542 clock-names = "baud", "bus";
582 dmas = <&apdma 4>, <&a 543 dmas = <&apdma 4>, <&apdma 5>;
583 dma-names = "tx", "rx" 544 dma-names = "tx", "rx";
584 status = "disabled"; 545 status = "disabled";
585 }; 546 };
586 547
587 uart3: serial@11005000 { 548 uart3: serial@11005000 {
588 compatible = "mediatek 549 compatible = "mediatek,mt6795-uart",
589 "mediatek 550 "mediatek,mt6577-uart";
590 reg = <0 0x11005000 0 551 reg = <0 0x11005000 0 0x400>;
591 interrupts = <GIC_SPI 552 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
592 clocks = <&pericfg CLK 553 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
593 clock-names = "baud", 554 clock-names = "baud", "bus";
594 dmas = <&apdma 6>, <&a 555 dmas = <&apdma 6>, <&apdma 7>;
595 dma-names = "tx", "rx" 556 dma-names = "tx", "rx";
596 status = "disabled"; 557 status = "disabled";
597 }; 558 };
598 559
599 pwm2: pwm@11006000 { 560 pwm2: pwm@11006000 {
600 compatible = "mediatek 561 compatible = "mediatek,mt6795-pwm";
601 reg = <0 0x11006000 0 562 reg = <0 0x11006000 0 0x1000>;
602 #pwm-cells = <2>; 563 #pwm-cells = <2>;
603 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CL 565 clocks = <&topckgen CLK_TOP_PWM_SEL>,
605 <&pericfg CLK 566 <&pericfg CLK_PERI_PWM>,
606 <&pericfg CLK 567 <&pericfg CLK_PERI_PWM1>,
607 <&pericfg CLK 568 <&pericfg CLK_PERI_PWM2>,
608 <&pericfg CLK 569 <&pericfg CLK_PERI_PWM3>,
609 <&pericfg CLK 570 <&pericfg CLK_PERI_PWM4>,
610 <&pericfg CLK 571 <&pericfg CLK_PERI_PWM5>,
611 <&pericfg CLK 572 <&pericfg CLK_PERI_PWM6>,
612 <&pericfg CLK 573 <&pericfg CLK_PERI_PWM7>;
613 clock-names = "top", " 574 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
614 "pwm4", 575 "pwm4", "pwm5", "pwm6", "pwm7";
615 status = "disabled"; 576 status = "disabled";
616 }; 577 };
617 578
618 i2c0: i2c@11007000 { 579 i2c0: i2c@11007000 {
619 compatible = "mediatek 580 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
620 reg = <0 0x11007000 0 581 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
621 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
622 clock-div = <16>; 583 clock-div = <16>;
623 clocks = <&pericfg CLK 584 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
624 clock-names = "main", 585 clock-names = "main", "dma";
625 #address-cells = <1>; 586 #address-cells = <1>;
626 #size-cells = <0>; 587 #size-cells = <0>;
627 status = "disabled"; 588 status = "disabled";
628 }; 589 };
629 590
630 i2c1: i2c@11008000 { 591 i2c1: i2c@11008000 {
631 compatible = "mediatek 592 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
632 reg = <0 0x11008000 0 593 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
633 interrupts = <GIC_SPI 594 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
634 clock-div = <16>; 595 clock-div = <16>;
635 clocks = <&pericfg CLK 596 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
636 clock-names = "main", 597 clock-names = "main", "dma";
637 #address-cells = <1>; 598 #address-cells = <1>;
638 #size-cells = <0>; 599 #size-cells = <0>;
639 status = "disabled"; 600 status = "disabled";
640 }; 601 };
641 602
642 i2c2: i2c@11009000 { 603 i2c2: i2c@11009000 {
643 compatible = "mediatek 604 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
644 reg = <0 0x11009000 0 605 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
645 interrupts = <GIC_SPI 606 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
646 clock-div = <16>; 607 clock-div = <16>;
647 clocks = <&pericfg CLK 608 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
648 clock-names = "main", 609 clock-names = "main", "dma";
649 #address-cells = <1>; 610 #address-cells = <1>;
650 #size-cells = <0>; 611 #size-cells = <0>;
651 status = "disabled"; 612 status = "disabled";
652 }; 613 };
653 614
654 i2c3: i2c@11010000 { 615 i2c3: i2c@11010000 {
655 compatible = "mediatek 616 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
656 reg = <0 0x11010000 0 617 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
657 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
658 clock-div = <16>; 619 clock-div = <16>;
659 clocks = <&pericfg CLK 620 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
660 clock-names = "main", 621 clock-names = "main", "dma";
661 #address-cells = <1>; 622 #address-cells = <1>;
662 #size-cells = <0>; 623 #size-cells = <0>;
663 status = "disabled"; 624 status = "disabled";
664 }; 625 };
665 626
666 i2c4: i2c@11011000 { 627 i2c4: i2c@11011000 {
667 compatible = "mediatek 628 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
668 reg = <0 0x11011000 0 629 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
669 interrupts = <GIC_SPI 630 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
670 clock-div = <16>; 631 clock-div = <16>;
671 clocks = <&pericfg CLK 632 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
672 clock-names = "main", 633 clock-names = "main", "dma";
673 #address-cells = <1>; 634 #address-cells = <1>;
674 #size-cells = <0>; 635 #size-cells = <0>;
675 status = "disabled"; 636 status = "disabled";
676 }; 637 };
677 638
678 mmc0: mmc@11230000 { 639 mmc0: mmc@11230000 {
679 compatible = "mediatek 640 compatible = "mediatek,mt6795-mmc";
680 reg = <0 0x11230000 0 641 reg = <0 0x11230000 0 0x1000>;
681 interrupts = <GIC_SPI 642 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
682 clocks = <&pericfg CLK 643 clocks = <&pericfg CLK_PERI_MSDC30_0>,
683 <&topckgen CL 644 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
684 <&topckgen CL 645 <&topckgen CLK_TOP_MSDC50_0_SEL>;
685 clock-names = "source" 646 clock-names = "source", "hclk", "source_cg";
686 status = "disabled"; 647 status = "disabled";
687 }; 648 };
688 649
689 mmc1: mmc@11240000 { 650 mmc1: mmc@11240000 {
690 compatible = "mediatek 651 compatible = "mediatek,mt6795-mmc";
691 reg = <0 0x11240000 0 652 reg = <0 0x11240000 0 0x1000>;
692 interrupts = <GIC_SPI 653 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&pericfg CLK 654 clocks = <&pericfg CLK_PERI_MSDC30_1>,
694 <&topckgen CL 655 <&topckgen CLK_TOP_AXI_SEL>;
695 clock-names = "source" 656 clock-names = "source", "hclk";
696 status = "disabled"; 657 status = "disabled";
697 }; 658 };
698 659
699 mmc2: mmc@11250000 { 660 mmc2: mmc@11250000 {
700 compatible = "mediatek 661 compatible = "mediatek,mt6795-mmc";
701 reg = <0 0x11250000 0 662 reg = <0 0x11250000 0 0x1000>;
702 interrupts = <GIC_SPI 663 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK 664 clocks = <&pericfg CLK_PERI_MSDC30_2>,
704 <&topckgen CL 665 <&topckgen CLK_TOP_AXI_SEL>;
705 clock-names = "source" 666 clock-names = "source", "hclk";
706 status = "disabled"; 667 status = "disabled";
707 }; 668 };
708 669
709 mmc3: mmc@11260000 { 670 mmc3: mmc@11260000 {
710 compatible = "mediatek 671 compatible = "mediatek,mt6795-mmc";
711 reg = <0 0x11260000 0 672 reg = <0 0x11260000 0 0x1000>;
712 interrupts = <GIC_SPI 673 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
713 clocks = <&pericfg CLK 674 clocks = <&pericfg CLK_PERI_MSDC30_3>,
714 <&topckgen CL 675 <&topckgen CLK_TOP_AXI_SEL>;
715 clock-names = "source" 676 clock-names = "source", "hclk";
716 status = "disabled"; 677 status = "disabled";
717 }; 678 };
718 679
719 mmsys: syscon@14000000 { 680 mmsys: syscon@14000000 {
720 compatible = "mediatek 681 compatible = "mediatek,mt6795-mmsys", "syscon";
721 reg = <0 0x14000000 0 682 reg = <0 0x14000000 0 0x1000>;
722 power-domains = <&spm 683 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
723 assigned-clocks = <&to 684 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
724 assigned-clock-rates = 685 assigned-clock-rates = <400000000>;
725 #clock-cells = <1>; 686 #clock-cells = <1>;
726 #reset-cells = <1>; 687 #reset-cells = <1>;
727 mboxes = <&gce 0 CMDQ_ 688 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
728 <&gce 1 CMDQ_ 689 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
729 mediatek,gce-client-re 690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
730 }; 691 };
731 692
732 ovl0: ovl@1400c000 { <<
733 compatible = "mediatek <<
734 reg = <0 0x1400c000 0 <<
735 interrupts = <GIC_SPI <<
736 power-domains = <&spm <<
737 clocks = <&mmsys CLK_M <<
738 iommus = <&iommu M4U_P <<
739 mediatek,gce-client-re <<
740 }; <<
741 <<
742 ovl1: ovl@1400d000 { <<
743 compatible = "mediatek <<
744 reg = <0 0x1400d000 0 <<
745 interrupts = <GIC_SPI <<
746 power-domains = <&spm <<
747 clocks = <&mmsys CLK_M <<
748 iommus = <&iommu M4U_P <<
749 mediatek,gce-client-re <<
750 }; <<
751 <<
752 rdma0: rdma@1400e000 { <<
753 compatible = "mediatek <<
754 reg = <0 0x1400e000 0 <<
755 interrupts = <GIC_SPI <<
756 power-domains = <&spm <<
757 clocks = <&mmsys CLK_M <<
758 iommus = <&iommu M4U_P <<
759 mediatek,gce-client-re <<
760 }; <<
761 <<
762 rdma1: rdma@1400f000 { <<
763 compatible = "mediatek <<
764 reg = <0 0x1400f000 0 <<
765 interrupts = <GIC_SPI <<
766 power-domains = <&spm <<
767 clocks = <&mmsys CLK_M <<
768 iommus = <&iommu M4U_P <<
769 mediatek,gce-client-re <<
770 }; <<
771 <<
772 rdma2: rdma@14010000 { <<
773 compatible = "mediatek <<
774 reg = <0 0x14010000 0 <<
775 interrupts = <GIC_SPI <<
776 power-domains = <&spm <<
777 clocks = <&mmsys CLK_M <<
778 iommus = <&iommu M4U_P <<
779 mediatek,gce-client-re <<
780 }; <<
781 <<
782 wdma0: wdma@14011000 { <<
783 compatible = "mediatek <<
784 reg = <0 0x14011000 0 <<
785 interrupts = <GIC_SPI <<
786 power-domains = <&spm <<
787 clocks = <&mmsys CLK_M <<
788 iommus = <&iommu M4U_P <<
789 mediatek,gce-client-re <<
790 }; <<
791 <<
792 wdma1: wdma@14012000 { <<
793 compatible = "mediatek <<
794 reg = <0 0x14012000 0 <<
795 interrupts = <GIC_SPI <<
796 power-domains = <&spm <<
797 clocks = <&mmsys CLK_M <<
798 iommus = <&iommu M4U_P <<
799 mediatek,gce-client-re <<
800 }; <<
801 <<
802 color0: color@14013000 { <<
803 compatible = "mediatek <<
804 reg = <0 0x14013000 0 <<
805 interrupts = <GIC_SPI <<
806 power-domains = <&spm <<
807 clocks = <&mmsys CLK_M <<
808 mediatek,gce-client-re <<
809 }; <<
810 <<
811 color1: color@14014000 { <<
812 compatible = "mediatek <<
813 reg = <0 0x14014000 0 <<
814 interrupts = <GIC_SPI <<
815 power-domains = <&spm <<
816 clocks = <&mmsys CLK_M <<
817 mediatek,gce-client-re <<
818 }; <<
819 <<
820 aal@14015000 { <<
821 compatible = "mediatek <<
822 reg = <0 0x14015000 0 <<
823 interrupts = <GIC_SPI <<
824 power-domains = <&spm <<
825 clocks = <&mmsys CLK_M <<
826 mediatek,gce-client-re <<
827 }; <<
828 <<
829 gamma@14016000 { <<
830 compatible = "mediatek <<
831 reg = <0 0x14016000 0 <<
832 interrupts = <GIC_SPI <<
833 power-domains = <&spm <<
834 clocks = <&mmsys CLK_M <<
835 mediatek,gce-client-re <<
836 }; <<
837 <<
838 merge@14017000 { <<
839 compatible = "mediatek <<
840 reg = <0 0x14017000 0 <<
841 power-domains = <&spm <<
842 clocks = <&mmsys CLK_M <<
843 }; <<
844 <<
845 split0: split@14018000 { <<
846 compatible = "mediatek <<
847 reg = <0 0x14018000 0 <<
848 power-domains = <&spm <<
849 clocks = <&mmsys CLK_M <<
850 }; <<
851 <<
852 split1: split@14019000 { <<
853 compatible = "mediatek <<
854 reg = <0 0x14019000 0 <<
855 power-domains = <&spm <<
856 clocks = <&mmsys CLK_M <<
857 }; <<
858 <<
859 ufoe@1401a000 { <<
860 compatible = "mediatek <<
861 reg = <0 0x1401a000 0 <<
862 interrupts = <GIC_SPI <<
863 power-domains = <&spm <<
864 clocks = <&mmsys CLK_M <<
865 mediatek,gce-client-re <<
866 }; <<
867 <<
868 dsi0: dsi@1401b000 { <<
869 compatible = "mediatek <<
870 reg = <0 0x1401b000 0 <<
871 interrupts = <GIC_SPI <<
872 power-domains = <&spm <<
873 clocks = <&mmsys CLK_M <<
874 <&mmsys CLK_M <<
875 <&mipi_tx0>; <<
876 clock-names = "engine" <<
877 phys = <&mipi_tx0>; <<
878 phy-names = "dphy"; <<
879 status = "disabled"; <<
880 }; <<
881 <<
882 dsi1: dsi@1401c000 { <<
883 compatible = "mediatek <<
884 reg = <0 0x1401c000 0 <<
885 interrupts = <GIC_SPI <<
886 power-domains = <&spm <<
887 clocks = <&mmsys CLK_M <<
888 <&mmsys CLK_M <<
889 <&mipi_tx1>; <<
890 clock-names = "engine" <<
891 phys = <&mipi_tx1>; <<
892 phy-names = "dphy"; <<
893 status = "disabled"; <<
894 }; <<
895 <<
896 dpi0: dpi@1401d000 { <<
897 compatible = "mediatek <<
898 reg = <0 0x1401d000 0 <<
899 interrupts = <GIC_SPI <<
900 power-domains = <&spm <<
901 clocks = <&mmsys CLK_M <<
902 <&mmsys CLK_M <<
903 <&apmixedsys <<
904 clock-names = "pixel", <<
905 status = "disabled"; <<
906 }; <<
907 <<
908 pwm0: pwm@1401e000 { <<
909 compatible = "mediatek <<
910 reg = <0 0x1401e000 0 <<
911 #pwm-cells = <2>; <<
912 clocks = <&mmsys CLK_M <<
913 clock-names = "main", <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 pwm1: pwm@1401f000 { <<
918 compatible = "mediatek <<
919 reg = <0 0x1401f000 0 <<
920 #pwm-cells = <2>; <<
921 clocks = <&mmsys CLK_M <<
922 clock-names = "main", <<
923 status = "disabled"; <<
924 }; <<
925 <<
926 mutex: mutex@14020000 { <<
927 compatible = "mediatek <<
928 reg = <0 0x14020000 0 <<
929 interrupts = <GIC_SPI <<
930 power-domains = <&spm <<
931 clocks = <&mmsys CLK_M <<
932 mediatek,gce-events = <<
933 <<
934 mediatek,gce-client-re <<
935 }; <<
936 <<
937 larb0: larb@14021000 { 693 larb0: larb@14021000 {
938 compatible = "mediatek 694 compatible = "mediatek,mt6795-smi-larb";
939 reg = <0 0x14021000 0 695 reg = <0 0x14021000 0 0x1000>;
940 clocks = <&mmsys CLK_M 696 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
941 clock-names = "apb", " 697 clock-names = "apb", "smi";
942 mediatek,smi = <&smi_c 698 mediatek,smi = <&smi_common>;
943 mediatek,larb-id = <0> 699 mediatek,larb-id = <0>;
944 power-domains = <&spm 700 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
945 }; 701 };
946 702
947 smi_common: smi@14022000 { 703 smi_common: smi@14022000 {
948 compatible = "mediatek 704 compatible = "mediatek,mt6795-smi-common";
949 reg = <0 0x14022000 0 705 reg = <0 0x14022000 0 0x1000>;
950 power-domains = <&spm 706 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
951 clocks = <&infracfg CL 707 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
952 clock-names = "apb", " 708 clock-names = "apb", "smi";
953 }; <<
954 <<
955 od@14023000 { <<
956 compatible = "mediatek <<
957 reg = <0 0x14023000 0 <<
958 clocks = <&mmsys CLK_M <<
959 mediatek,gce-client-re <<
960 }; 709 };
961 710
962 larb2: larb@15001000 { 711 larb2: larb@15001000 {
963 compatible = "mediatek 712 compatible = "mediatek,mt6795-smi-larb";
964 reg = <0 0x15001000 0 713 reg = <0 0x15001000 0 0x1000>;
965 clocks = <&mmsys CLK_M 714 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
966 clock-names = "apb", " 715 clock-names = "apb", "smi";
967 mediatek,smi = <&smi_c 716 mediatek,smi = <&smi_common>;
968 mediatek,larb-id = <2> 717 mediatek,larb-id = <2>;
969 power-domains = <&spm 718 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
970 }; 719 };
971 720
972 vdecsys: clock-controller@1600 721 vdecsys: clock-controller@16000000 {
973 compatible = "mediatek 722 compatible = "mediatek,mt6795-vdecsys";
974 reg = <0 0x16000000 0 723 reg = <0 0x16000000 0 0x1000>;
975 #clock-cells = <1>; 724 #clock-cells = <1>;
976 }; 725 };
977 726
978 larb1: larb@16010000 { 727 larb1: larb@16010000 {
979 compatible = "mediatek 728 compatible = "mediatek,mt6795-smi-larb";
980 reg = <0 0x16010000 0 729 reg = <0 0x16010000 0 0x1000>;
981 mediatek,smi = <&smi_c 730 mediatek,smi = <&smi_common>;
982 mediatek,larb-id = <1> 731 mediatek,larb-id = <1>;
983 clocks = <&vdecsys CLK 732 clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>;
984 clock-names = "apb", " 733 clock-names = "apb", "smi";
985 power-domains = <&spm 734 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
986 }; 735 };
987 736
988 vencsys: clock-controller@1800 737 vencsys: clock-controller@18000000 {
989 compatible = "mediatek 738 compatible = "mediatek,mt6795-vencsys";
990 reg = <0 0x18000000 0 739 reg = <0 0x18000000 0 0x1000>;
991 #clock-cells = <1>; 740 #clock-cells = <1>;
992 }; 741 };
993 742
994 larb3: larb@18001000 { 743 larb3: larb@18001000 {
995 compatible = "mediatek 744 compatible = "mediatek,mt6795-smi-larb";
996 reg = <0 0x18001000 0 745 reg = <0 0x18001000 0 0x1000>;
997 clocks = <&vencsys CLK 746 clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>;
998 clock-names = "apb", " 747 clock-names = "apb", "smi";
999 mediatek,smi = <&smi_c 748 mediatek,smi = <&smi_common>;
1000 mediatek,larb-id = <3 749 mediatek,larb-id = <3>;
1001 power-domains = <&spm 750 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;
1002 }; 751 };
1003 }; 752 };
1004 }; 753 };
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