1 /* 1 /*
2 * Copyright (c) 2017 MediaTek Inc. 2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com> 3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com>
5 * 5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h> <<
12 #include <dt-bindings/phy/phy.h> <<
13 #include <dt-bindings/power/mt7622-power.h> <<
14 #include <dt-bindings/reset/mt7622-reset.h> <<
15 #include <dt-bindings/thermal/thermal.h> <<
16 11
17 / { 12 / {
18 compatible = "mediatek,mt7622"; 13 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>; 14 interrupt-parent = <&sysirq>;
20 #address-cells = <2>; 15 #address-cells = <2>;
21 #size-cells = <2>; 16 #size-cells = <2>;
22 17
23 cpu_opp_table: opp-table { <<
24 compatible = "operating-points <<
25 opp-shared; <<
26 opp-300000000 { <<
27 opp-hz = /bits/ 64 <30 <<
28 opp-microvolt = <95000 <<
29 }; <<
30 <<
31 opp-437500000 { <<
32 opp-hz = /bits/ 64 <43 <<
33 opp-microvolt = <10000 <<
34 }; <<
35 <<
36 opp-600000000 { <<
37 opp-hz = /bits/ 64 <60 <<
38 opp-microvolt = <10500 <<
39 }; <<
40 <<
41 opp-812500000 { <<
42 opp-hz = /bits/ 64 <81 <<
43 opp-microvolt = <11000 <<
44 }; <<
45 <<
46 opp-1025000000 { <<
47 opp-hz = /bits/ 64 <10 <<
48 opp-microvolt = <11500 <<
49 }; <<
50 <<
51 opp-1137500000 { <<
52 opp-hz = /bits/ 64 <11 <<
53 opp-microvolt = <12000 <<
54 }; <<
55 <<
56 opp-1262500000 { <<
57 opp-hz = /bits/ 64 <12 <<
58 opp-microvolt = <12500 <<
59 }; <<
60 <<
61 opp-1350000000 { <<
62 opp-hz = /bits/ 64 <13 <<
63 opp-microvolt = <13100 <<
64 }; <<
65 }; <<
66 <<
67 cpus { 18 cpus {
68 #address-cells = <2>; 19 #address-cells = <2>;
69 #size-cells = <0>; 20 #size-cells = <0>;
70 21
71 cpu0: cpu@0 { 22 cpu0: cpu@0 {
72 device_type = "cpu"; 23 device_type = "cpu";
73 compatible = "arm,cort !! 24 compatible = "arm,cortex-a53", "arm,armv8";
74 reg = <0x0 0x0>; 25 reg = <0x0 0x0>;
75 clocks = <&infracfg CL <<
76 <&apmixedsys <<
77 clock-names = "cpu", " <<
78 operating-points-v2 = <<
79 #cooling-cells = <2>; <<
80 enable-method = "psci" 26 enable-method = "psci";
81 clock-frequency = <130 27 clock-frequency = <1300000000>;
82 cci-control-port = <&c <<
83 next-level-cache = <&L <<
84 }; 28 };
85 29
86 cpu1: cpu@1 { 30 cpu1: cpu@1 {
87 device_type = "cpu"; 31 device_type = "cpu";
88 compatible = "arm,cort !! 32 compatible = "arm,cortex-a53", "arm,armv8";
89 reg = <0x0 0x1>; 33 reg = <0x0 0x1>;
90 clocks = <&infracfg CL <<
91 <&apmixedsys <<
92 clock-names = "cpu", " <<
93 operating-points-v2 = <<
94 #cooling-cells = <2>; <<
95 enable-method = "psci" 34 enable-method = "psci";
96 clock-frequency = <130 35 clock-frequency = <1300000000>;
97 cci-control-port = <&c <<
98 next-level-cache = <&L <<
99 }; <<
100 <<
101 L2: l2-cache { <<
102 compatible = "cache"; <<
103 cache-level = <2>; <<
104 cache-unified; <<
105 }; 36 };
106 }; 37 };
107 38
108 pwrap_clk: dummy40m { !! 39 uart_clk: dummy25m {
109 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
110 clock-frequency = <40000000>; <<
111 #clock-cells = <0>; 41 #clock-cells = <0>;
>> 42 clock-frequency = <25000000>;
112 }; 43 };
113 44
114 clk25m: oscillator { !! 45 bus_clk: dummy280m {
115 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
116 #clock-cells = <0>; 47 #clock-cells = <0>;
117 clock-frequency = <25000000>; !! 48 clock-frequency = <280000000>;
118 clock-output-names = "clkxtal" <<
119 }; 49 };
120 50
121 psci { 51 psci {
122 compatible = "arm,psci-0.2"; !! 52 compatible = "arm,psci-0.2";
123 method = "smc"; !! 53 method = "smc";
124 }; <<
125 <<
126 pmu { <<
127 compatible = "arm,cortex-a53-p <<
128 interrupts = <GIC_SPI 8 IRQ_TY <<
129 <GIC_SPI 9 IRQ_TY <<
130 interrupt-affinity = <&cpu0>, <<
131 }; 54 };
132 55
133 reserved-memory { 56 reserved-memory {
134 #address-cells = <2>; 57 #address-cells = <2>;
135 #size-cells = <2>; 58 #size-cells = <2>;
136 ranges; 59 ranges;
137 60
138 /* 192 KiB reserved for ARM Tr 61 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
139 secmon_reserved: secmon@430000 62 secmon_reserved: secmon@43000000 {
140 reg = <0 0x43000000 0 63 reg = <0 0x43000000 0 0x30000>;
141 no-map; 64 no-map;
142 }; 65 };
143 }; 66 };
144 67
145 thermal-zones { <<
146 cpu_thermal: cpu-thermal { <<
147 polling-delay-passive <<
148 polling-delay = <1000> <<
149 <<
150 thermal-sensors = <&th <<
151 <<
152 trips { <<
153 cpu_passive: c <<
154 temper <<
155 hyster <<
156 type = <<
157 }; <<
158 <<
159 cpu_active: cp <<
160 temper <<
161 hyster <<
162 type = <<
163 }; <<
164 <<
165 cpu_hot: cpu-h <<
166 temper <<
167 hyster <<
168 type = <<
169 }; <<
170 <<
171 cpu-crit { <<
172 temper <<
173 hyster <<
174 type = <<
175 }; <<
176 }; <<
177 <<
178 cooling-maps { <<
179 map0 { <<
180 trip = <<
181 coolin <<
182 <<
183 }; <<
184 <<
185 map1 { <<
186 trip = <<
187 coolin <<
188 <<
189 }; <<
190 <<
191 map2 { <<
192 trip = <<
193 coolin <<
194 <<
195 }; <<
196 }; <<
197 }; <<
198 }; <<
199 <<
200 timer { 68 timer {
201 compatible = "arm,armv8-timer" 69 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>; 70 interrupt-parent = <&gic>;
203 interrupts = <GIC_PPI 13 (GIC_ 71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_LEVEL_H 72 IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_ 73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_LEVEL_H 74 IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 (GIC_ 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_LEVEL_H 76 IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 (GIC_ 77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_LEVEL_H 78 IRQ_TYPE_LEVEL_HIGH)>;
211 }; 79 };
212 80
213 infracfg: infracfg@10000000 { <<
214 compatible = "mediatek,mt7622- <<
215 "syscon"; <<
216 reg = <0 0x10000000 0 0x1000>; <<
217 #clock-cells = <1>; <<
218 #reset-cells = <1>; <<
219 }; <<
220 <<
221 pwrap: pwrap@10001000 { <<
222 compatible = "mediatek,mt7622- <<
223 reg = <0 0x10001000 0 0x250>; <<
224 reg-names = "pwrap"; <<
225 clocks = <&infracfg CLK_INFRA_ <<
226 clock-names = "spi", "wrap"; <<
227 resets = <&infracfg MT7622_INF <<
228 reset-names = "pwrap"; <<
229 interrupts = <GIC_SPI 163 IRQ_ <<
230 status = "disabled"; <<
231 }; <<
232 <<
233 pericfg: pericfg@10002000 { <<
234 compatible = "mediatek,mt7622- <<
235 "syscon"; <<
236 reg = <0 0x10002000 0 0x1000>; <<
237 #clock-cells = <1>; <<
238 #reset-cells = <1>; <<
239 }; <<
240 <<
241 scpsys: power-controller@10006000 { <<
242 compatible = "mediatek,mt7622- <<
243 "syscon"; <<
244 #power-domain-cells = <1>; <<
245 reg = <0 0x10006000 0 0x1000>; <<
246 interrupts = <GIC_SPI 165 IRQ_ <<
247 <GIC_SPI 166 IRQ_ <<
248 <GIC_SPI 167 IRQ_ <<
249 <GIC_SPI 168 IRQ_ <<
250 infracfg = <&infracfg>; <<
251 clocks = <&topckgen CLK_TOP_HI <<
252 clock-names = "hif_sel"; <<
253 }; <<
254 <<
255 cir: ir-receiver@10009000 { <<
256 compatible = "mediatek,mt7622- <<
257 reg = <0 0x10009000 0 0x1000>; <<
258 interrupts = <GIC_SPI 175 IRQ_ <<
259 clocks = <&infracfg CLK_INFRA_ <<
260 <&topckgen CLK_TOP_AX <<
261 clock-names = "clk", "bus"; <<
262 status = "disabled"; <<
263 }; <<
264 <<
265 sysirq: interrupt-controller@10200620 81 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622- 82 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577- 83 "mediatek,mt6577-sysirq";
268 interrupt-controller; 84 interrupt-controller;
269 #interrupt-cells = <3>; 85 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>; 86 interrupt-parent = <&gic>;
271 reg = <0 0x10200620 0 0x20>; 87 reg = <0 0x10200620 0 0x20>;
272 }; 88 };
273 89
274 efuse: efuse@10206000 { <<
275 compatible = "mediatek,mt7622- <<
276 "mediatek,efuse"; <<
277 reg = <0 0x10206000 0 0x1000>; <<
278 #address-cells = <1>; <<
279 #size-cells = <1>; <<
280 <<
281 thermal_calibration: calib@198 <<
282 reg = <0x198 0xc>; <<
283 }; <<
284 }; <<
285 <<
286 apmixedsys: clock-controller@10209000 <<
287 compatible = "mediatek,mt7622- <<
288 reg = <0 0x10209000 0 0x1000>; <<
289 #clock-cells = <1>; <<
290 }; <<
291 <<
292 topckgen: clock-controller@10210000 { <<
293 compatible = "mediatek,mt7622- <<
294 reg = <0 0x10210000 0 0x1000>; <<
295 #clock-cells = <1>; <<
296 }; <<
297 <<
298 rng: rng@1020f000 { <<
299 compatible = "mediatek,mt7622- <<
300 "mediatek,mt7623- <<
301 reg = <0 0x1020f000 0 0x1000>; <<
302 clocks = <&infracfg CLK_INFRA_ <<
303 clock-names = "rng"; <<
304 }; <<
305 <<
306 pio: pinctrl@10211000 { <<
307 compatible = "mediatek,mt7622- <<
308 reg = <0 0x10211000 0 0x1000>, <<
309 <0 0x10005000 0 0x1000>; <<
310 reg-names = "base", "eint"; <<
311 gpio-controller; <<
312 #gpio-cells = <2>; <<
313 gpio-ranges = <&pio 0 0 103>; <<
314 interrupt-controller; <<
315 interrupts = <GIC_SPI 153 IRQ_ <<
316 interrupt-parent = <&gic>; <<
317 #interrupt-cells = <2>; <<
318 }; <<
319 <<
320 watchdog: watchdog@10212000 { <<
321 compatible = "mediatek,mt7622- <<
322 "mediatek,mt6589- <<
323 reg = <0 0x10212000 0 0x800>; <<
324 }; <<
325 <<
326 rtc: rtc@10212800 { <<
327 compatible = "mediatek,mt7622- <<
328 "mediatek,soc-rtc <<
329 reg = <0 0x10212800 0 0x200>; <<
330 interrupts = <GIC_SPI 129 IRQ_ <<
331 clocks = <&topckgen CLK_TOP_RT <<
332 clock-names = "rtc"; <<
333 }; <<
334 <<
335 gic: interrupt-controller@10300000 { 90 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400"; 91 compatible = "arm,gic-400";
337 interrupt-controller; 92 interrupt-controller;
338 #interrupt-cells = <3>; 93 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>; 94 interrupt-parent = <&gic>;
340 reg = <0 0x10310000 0 0x1000>, 95 reg = <0 0x10310000 0 0x1000>,
341 <0 0x10320000 0 0x1000>, 96 <0 0x10320000 0 0x1000>,
342 <0 0x10340000 0 0x2000>, 97 <0 0x10340000 0 0x2000>,
343 <0 0x10360000 0 0x2000>; 98 <0 0x10360000 0 0x2000>;
344 }; 99 };
345 100
346 cci: cci@10390000 { <<
347 compatible = "arm,cci-400"; <<
348 #address-cells = <1>; <<
349 #size-cells = <1>; <<
350 reg = <0 0x10390000 0 0x1000>; <<
351 ranges = <0 0 0x10390000 0x100 <<
352 <<
353 cci_control0: slave-if@1000 { <<
354 compatible = "arm,cci- <<
355 interface-type = "ace- <<
356 reg = <0x1000 0x1000>; <<
357 }; <<
358 <<
359 cci_control1: slave-if@4000 { <<
360 compatible = "arm,cci- <<
361 interface-type = "ace" <<
362 reg = <0x4000 0x1000>; <<
363 }; <<
364 <<
365 cci_control2: slave-if@5000 { <<
366 compatible = "arm,cci- <<
367 interface-type = "ace" <<
368 reg = <0x5000 0x1000>; <<
369 }; <<
370 <<
371 pmu@9000 { <<
372 compatible = "arm,cci- <<
373 reg = <0x9000 0x5000>; <<
374 interrupts = <GIC_SPI <<
375 <GIC_SPI <<
376 <GIC_SPI <<
377 <GIC_SPI <<
378 <GIC_SPI <<
379 }; <<
380 }; <<
381 <<
382 auxadc: adc@11001000 { <<
383 compatible = "mediatek,mt7622- <<
384 reg = <0 0x11001000 0 0x1000>; <<
385 clocks = <&pericfg CLK_PERI_AU <<
386 clock-names = "main"; <<
387 #io-channel-cells = <1>; <<
388 }; <<
389 <<
390 uart0: serial@11002000 { 101 uart0: serial@11002000 {
391 compatible = "mediatek,mt7622- 102 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577- 103 "mediatek,mt6577-uart";
393 reg = <0 0x11002000 0 0x400>; 104 reg = <0 0x11002000 0 0x400>;
394 interrupts = <GIC_SPI 91 IRQ_T 105 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&topckgen CLK_TOP_UA !! 106 clocks = <&uart_clk>, <&bus_clk>;
396 <&pericfg CLK_PERI_UA <<
397 clock-names = "baud", "bus"; 107 clock-names = "baud", "bus";
398 status = "disabled"; 108 status = "disabled";
399 }; <<
400 <<
401 uart1: serial@11003000 { <<
402 compatible = "mediatek,mt7622- <<
403 "mediatek,mt6577- <<
404 reg = <0 0x11003000 0 0x400>; <<
405 interrupts = <GIC_SPI 92 IRQ_T <<
406 clocks = <&topckgen CLK_TOP_UA <<
407 <&pericfg CLK_PERI_UA <<
408 clock-names = "baud", "bus"; <<
409 status = "disabled"; <<
410 }; <<
411 <<
412 uart2: serial@11004000 { <<
413 compatible = "mediatek,mt7622- <<
414 "mediatek,mt6577- <<
415 reg = <0 0x11004000 0 0x400>; <<
416 interrupts = <GIC_SPI 93 IRQ_T <<
417 clocks = <&topckgen CLK_TOP_UA <<
418 <&pericfg CLK_PERI_UA <<
419 clock-names = "baud", "bus"; <<
420 status = "disabled"; <<
421 }; <<
422 <<
423 uart3: serial@11005000 { <<
424 compatible = "mediatek,mt7622- <<
425 "mediatek,mt6577- <<
426 reg = <0 0x11005000 0 0x400>; <<
427 interrupts = <GIC_SPI 94 IRQ_T <<
428 clocks = <&topckgen CLK_TOP_UA <<
429 <&pericfg CLK_PERI_UA <<
430 clock-names = "baud", "bus"; <<
431 status = "disabled"; <<
432 }; <<
433 <<
434 pwm: pwm@11006000 { <<
435 compatible = "mediatek,mt7622- <<
436 reg = <0 0x11006000 0 0x1000>; <<
437 #pwm-cells = <2>; <<
438 interrupts = <GIC_SPI 77 IRQ_T <<
439 clocks = <&topckgen CLK_TOP_PW <<
440 <&pericfg CLK_PERI_PW <<
441 <&pericfg CLK_PERI_PW <<
442 <&pericfg CLK_PERI_PW <<
443 <&pericfg CLK_PERI_PW <<
444 <&pericfg CLK_PERI_PW <<
445 <&pericfg CLK_PERI_PW <<
446 <&pericfg CLK_PERI_PW <<
447 clock-names = "top", "main", " <<
448 "pwm5", "pwm6"; <<
449 status = "disabled"; <<
450 }; <<
451 <<
452 i2c0: i2c@11007000 { <<
453 compatible = "mediatek,mt7622- <<
454 reg = <0 0x11007000 0 0x90>, <<
455 <0 0x11000100 0 0x80>; <<
456 interrupts = <GIC_SPI 84 IRQ_T <<
457 clock-div = <16>; <<
458 clocks = <&pericfg CLK_PERI_I2 <<
459 <&pericfg CLK_PERI_AP <<
460 clock-names = "main", "dma"; <<
461 #address-cells = <1>; <<
462 #size-cells = <0>; <<
463 status = "disabled"; <<
464 }; <<
465 <<
466 i2c1: i2c@11008000 { <<
467 compatible = "mediatek,mt7622- <<
468 reg = <0 0x11008000 0 0x90>, <<
469 <0 0x11000180 0 0x80>; <<
470 interrupts = <GIC_SPI 85 IRQ_T <<
471 clock-div = <16>; <<
472 clocks = <&pericfg CLK_PERI_I2 <<
473 <&pericfg CLK_PERI_AP <<
474 clock-names = "main", "dma"; <<
475 #address-cells = <1>; <<
476 #size-cells = <0>; <<
477 status = "disabled"; <<
478 }; <<
479 <<
480 i2c2: i2c@11009000 { <<
481 compatible = "mediatek,mt7622- <<
482 reg = <0 0x11009000 0 0x90>, <<
483 <0 0x11000200 0 0x80>; <<
484 interrupts = <GIC_SPI 86 IRQ_T <<
485 clock-div = <16>; <<
486 clocks = <&pericfg CLK_PERI_I2 <<
487 <&pericfg CLK_PERI_AP <<
488 clock-names = "main", "dma"; <<
489 #address-cells = <1>; <<
490 #size-cells = <0>; <<
491 status = "disabled"; <<
492 }; <<
493 <<
494 spi0: spi@1100a000 { <<
495 compatible = "mediatek,mt7622- <<
496 reg = <0 0x1100a000 0 0x100>; <<
497 interrupts = <GIC_SPI 118 IRQ_ <<
498 clocks = <&topckgen CLK_TOP_SY <<
499 <&topckgen CLK_TOP_SP <<
500 <&pericfg CLK_PERI_SP <<
501 clock-names = "parent-clk", "s <<
502 #address-cells = <1>; <<
503 #size-cells = <0>; <<
504 status = "disabled"; <<
505 }; <<
506 <<
507 thermal: thermal@1100b000 { <<
508 #thermal-sensor-cells = <1>; <<
509 compatible = "mediatek,mt7622- <<
510 reg = <0 0x1100b000 0 0x1000>; <<
511 interrupts = <0 78 IRQ_TYPE_LE <<
512 clocks = <&pericfg CLK_PERI_TH <<
513 <&pericfg CLK_PERI_AU <<
514 clock-names = "therm", "auxadc <<
515 resets = <&pericfg MT7622_PERI <<
516 mediatek,auxadc = <&auxadc>; <<
517 mediatek,apmixedsys = <&apmixe <<
518 nvmem-cells = <&thermal_calibr <<
519 nvmem-cell-names = "calibratio <<
520 }; <<
521 <<
522 btif: serial@1100c000 { <<
523 compatible = "mediatek,mt7622- <<
524 "mediatek,mtk-bti <<
525 reg = <0 0x1100c000 0 0x1000>; <<
526 interrupts = <GIC_SPI 90 IRQ_T <<
527 clocks = <&pericfg CLK_PERI_BT <<
528 reg-shift = <2>; <<
529 reg-io-width = <4>; <<
530 status = "disabled"; <<
531 <<
532 bluetooth { <<
533 compatible = "mediatek <<
534 power-domains = <&scps <<
535 clocks = <&clk25m>; <<
536 clock-names = "ref"; <<
537 }; <<
538 }; <<
539 <<
540 nandc: nand-controller@1100d000 { <<
541 compatible = "mediatek,mt7622- <<
542 reg = <0 0x1100D000 0 0x1000>; <<
543 interrupts = <GIC_SPI 96 IRQ_T <<
544 clocks = <&pericfg CLK_PERI_NF <<
545 <&pericfg CLK_PERI_SN <<
546 clock-names = "nfi_clk", "pad_ <<
547 ecc-engine = <&bch>; <<
548 #address-cells = <1>; <<
549 #size-cells = <0>; <<
550 status = "disabled"; <<
551 }; <<
552 <<
553 snfi: spi@1100d000 { <<
554 compatible = "mediatek,mt7622- <<
555 reg = <0 0x1100d000 0 0x1000>; <<
556 interrupts = <GIC_SPI 96 IRQ_T <<
557 clocks = <&pericfg CLK_PERI_NF <<
558 clock-names = "nfi_clk", "pad_ <<
559 nand-ecc-engine = <&bch>; <<
560 #address-cells = <1>; <<
561 #size-cells = <0>; <<
562 status = "disabled"; <<
563 }; <<
564 <<
565 bch: ecc@1100e000 { <<
566 compatible = "mediatek,mt7622- <<
567 reg = <0 0x1100e000 0 0x1000>; <<
568 interrupts = <GIC_SPI 95 IRQ_T <<
569 clocks = <&pericfg CLK_PERI_NF <<
570 clock-names = "nfiecc_clk"; <<
571 status = "disabled"; <<
572 }; <<
573 <<
574 nor_flash: spi@11014000 { <<
575 compatible = "mediatek,mt7622- <<
576 "mediatek,mt8173- <<
577 reg = <0 0x11014000 0 0xe0>; <<
578 clocks = <&pericfg CLK_PERI_FL <<
579 <&topckgen CLK_TOP_FL <<
580 clock-names = "spi", "sf"; <<
581 #address-cells = <1>; <<
582 #size-cells = <0>; <<
583 status = "disabled"; <<
584 }; <<
585 <<
586 spi1: spi@11016000 { <<
587 compatible = "mediatek,mt7622- <<
588 reg = <0 0x11016000 0 0x100>; <<
589 interrupts = <GIC_SPI 122 IRQ_ <<
590 clocks = <&topckgen CLK_TOP_SY <<
591 <&topckgen CLK_TOP_SP <<
592 <&pericfg CLK_PERI_SP <<
593 clock-names = "parent-clk", "s <<
594 #address-cells = <1>; <<
595 #size-cells = <0>; <<
596 status = "disabled"; <<
597 }; <<
598 <<
599 uart4: serial@11019000 { <<
600 compatible = "mediatek,mt7622- <<
601 "mediatek,mt6577- <<
602 reg = <0 0x11019000 0 0x400>; <<
603 interrupts = <GIC_SPI 89 IRQ_T <<
604 clocks = <&topckgen CLK_TOP_UA <<
605 <&pericfg CLK_PERI_UA <<
606 clock-names = "baud", "bus"; <<
607 status = "disabled"; <<
608 }; <<
609 <<
610 audsys: clock-controller@11220000 { <<
611 compatible = "mediatek,mt7622- <<
612 reg = <0 0x11220000 0 0x2000>; <<
613 #clock-cells = <1>; <<
614 <<
615 afe: audio-controller { <<
616 compatible = "mediatek <<
617 interrupts = <GIC_SPI <<
618 <GIC_SPI <<
619 interrupt-names = "afe <<
620 <<
621 clocks = <&infracfg CL <<
622 <&topckgen CL <<
623 <&topckgen CL <<
624 <&topckgen CL <<
625 <&topckgen CL <<
626 <&topckgen CL <<
627 <&topckgen CL <<
628 <&topckgen CL <<
629 <&topckgen CL <<
630 <&topckgen CL <<
631 <&topckgen CL <<
632 <&topckgen CL <<
633 <&topckgen CL <<
634 <&topckgen CL <<
635 <&topckgen CL <<
636 <&topckgen CL <<
637 <&topckgen CL <<
638 <&audsys CLK_ <<
639 <&audsys CLK_ <<
640 <&audsys CLK_ <<
641 <&audsys CLK_ <<
642 <&audsys CLK_ <<
643 <&audsys CLK_ <<
644 <&audsys CLK_ <<
645 <&audsys CLK_ <<
646 <&audsys CLK_ <<
647 <&audsys CLK_ <<
648 <&audsys CLK_ <<
649 <&audsys CLK_ <<
650 <&audsys CLK_ <<
651 <&audsys CLK_ <<
652 <&audsys CLK_ <<
653 <&audsys CLK_ <<
654 <<
655 clock-names = "infra_s <<
656 "top_aud <<
657 "top_aud <<
658 "top_aud <<
659 "top_aud <<
660 "i2s0_sr <<
661 "i2s1_sr <<
662 "i2s2_sr <<
663 "i2s3_sr <<
664 "i2s0_sr <<
665 "i2s1_sr <<
666 "i2s2_sr <<
667 "i2s3_sr <<
668 "i2s0_mc <<
669 "i2s1_mc <<
670 "i2s2_mc <<
671 "i2s3_mc <<
672 "i2so0_h <<
673 "i2so1_h <<
674 "i2so2_h <<
675 "i2so3_h <<
676 "i2si0_h <<
677 "i2si1_h <<
678 "i2si2_h <<
679 "i2si3_h <<
680 "asrc0_o <<
681 "asrc1_o <<
682 "asrc2_o <<
683 "asrc3_o <<
684 "audio_a <<
685 "audio_a <<
686 "audio_a <<
687 "audio_a <<
688 <<
689 assigned-clocks = <&to <<
690 <&to <<
691 <&to <<
692 <&to <<
693 assigned-clock-parents <<
694 <<
695 assigned-clock-rates = <<
696 }; <<
697 }; <<
698 <<
699 mmc0: mmc@11230000 { <<
700 compatible = "mediatek,mt7622- <<
701 reg = <0 0x11230000 0 0x1000>; <<
702 interrupts = <GIC_SPI 79 IRQ_T <<
703 clocks = <&pericfg CLK_PERI_MS <<
704 <&topckgen CLK_TOP_MS <<
705 clock-names = "source", "hclk" <<
706 resets = <&pericfg MT7622_PERI <<
707 reset-names = "hrst"; <<
708 status = "disabled"; <<
709 }; <<
710 <<
711 mmc1: mmc@11240000 { <<
712 compatible = "mediatek,mt7622- <<
713 reg = <0 0x11240000 0 0x1000>; <<
714 interrupts = <GIC_SPI 80 IRQ_T <<
715 clocks = <&pericfg CLK_PERI_MS <<
716 <&topckgen CLK_TOP_AX <<
717 clock-names = "source", "hclk" <<
718 resets = <&pericfg MT7622_PERI <<
719 reset-names = "hrst"; <<
720 status = "disabled"; <<
721 }; <<
722 <<
723 wmac: wmac@18000000 { <<
724 compatible = "mediatek,mt7622- <<
725 reg = <0 0x18000000 0 0x100000 <<
726 interrupts = <GIC_SPI 211 IRQ_ <<
727 <<
728 mediatek,infracfg = <&infracfg <<
729 status = "disabled"; <<
730 <<
731 power-domains = <&scpsys MT762 <<
732 }; <<
733 <<
734 ssusbsys: clock-controller@1a000000 { <<
735 compatible = "mediatek,mt7622- <<
736 reg = <0 0x1a000000 0 0x1000>; <<
737 #clock-cells = <1>; <<
738 #reset-cells = <1>; <<
739 }; <<
740 <<
741 ssusb: usb@1a0c0000 { <<
742 compatible = "mediatek,mt7622- <<
743 "mediatek,mtk-xhc <<
744 reg = <0 0x1a0c0000 0 0x01000> <<
745 <0 0x1a0c4700 0 0x0100>; <<
746 reg-names = "mac", "ippc"; <<
747 interrupts = <GIC_SPI 232 IRQ_ <<
748 power-domains = <&scpsys MT762 <<
749 clocks = <&ssusbsys CLK_SSUSB_ <<
750 <&ssusbsys CLK_SSUSB_ <<
751 <&ssusbsys CLK_SSUSB_ <<
752 <&ssusbsys CLK_SSUSB_ <<
753 clock-names = "sys_ck", "ref_c <<
754 phys = <&u2port0 PHY_TYPE_USB2 <<
755 <&u3port0 PHY_TYPE_USB3 <<
756 <&u2port1 PHY_TYPE_USB2 <<
757 <<
758 status = "disabled"; <<
759 }; <<
760 <<
761 u3phy: t-phy@1a0c4000 { <<
762 compatible = "mediatek,mt7622- <<
763 "mediatek,generic <<
764 reg = <0 0x1a0c4000 0 0x700>; <<
765 #address-cells = <2>; <<
766 #size-cells = <2>; <<
767 ranges; <<
768 status = "disabled"; <<
769 <<
770 u2port0: usb-phy@1a0c4800 { <<
771 reg = <0 0x1a0c4800 0 <<
772 #phy-cells = <1>; <<
773 clocks = <&ssusbsys CL <<
774 clock-names = "ref"; <<
775 }; <<
776 <<
777 u3port0: usb-phy@1a0c4900 { <<
778 reg = <0 0x1a0c4900 0 <<
779 #phy-cells = <1>; <<
780 clocks = <&clk25m>; <<
781 clock-names = "ref"; <<
782 }; <<
783 <<
784 u2port1: usb-phy@1a0c5000 { <<
785 reg = <0 0x1a0c5000 0 <<
786 #phy-cells = <1>; <<
787 clocks = <&ssusbsys CL <<
788 clock-names = "ref"; <<
789 }; <<
790 }; <<
791 <<
792 pciesys: clock-controller@1a100800 { <<
793 compatible = "mediatek,mt7622- <<
794 reg = <0 0x1a100800 0 0x1000>; <<
795 #clock-cells = <1>; <<
796 #reset-cells = <1>; <<
797 }; <<
798 <<
799 pciecfg: pciecfg@1a140000 { <<
800 compatible = "mediatek,generic <<
801 reg = <0 0x1a140000 0 0x1000>; <<
802 }; <<
803 <<
804 pcie0: pcie@1a143000 { <<
805 compatible = "mediatek,mt7622- <<
806 device_type = "pci"; <<
807 reg = <0 0x1a143000 0 0x1000>; <<
808 reg-names = "port0"; <<
809 linux,pci-domain = <0>; <<
810 #address-cells = <3>; <<
811 #size-cells = <2>; <<
812 interrupts = <GIC_SPI 228 IRQ_ <<
813 interrupt-names = "pcie_irq"; <<
814 clocks = <&pciesys CLK_PCIE_P0 <<
815 <&pciesys CLK_PCIE_P0 <<
816 <&pciesys CLK_PCIE_P0 <<
817 <&pciesys CLK_PCIE_P0 <<
818 <&pciesys CLK_PCIE_P0 <<
819 <&pciesys CLK_PCIE_P0 <<
820 clock-names = "sys_ck0", "ahb_ <<
821 "axi_ck0", "obff <<
822 <<
823 power-domains = <&scpsys MT762 <<
824 bus-range = <0x00 0xff>; <<
825 ranges = <0x82000000 0 0x20000 <<
826 status = "disabled"; <<
827 <<
828 #interrupt-cells = <1>; <<
829 interrupt-map-mask = <0 0 0 7> <<
830 interrupt-map = <0 0 0 1 &pcie <<
831 <0 0 0 2 &pcie <<
832 <0 0 0 3 &pcie <<
833 <0 0 0 4 &pcie <<
834 pcie_intc0: interrupt-controll <<
835 interrupt-controller; <<
836 #address-cells = <0>; <<
837 #interrupt-cells = <1> <<
838 }; <<
839 }; <<
840 <<
841 pcie1: pcie@1a145000 { <<
842 compatible = "mediatek,mt7622- <<
843 device_type = "pci"; <<
844 reg = <0 0x1a145000 0 0x1000>; <<
845 reg-names = "port1"; <<
846 linux,pci-domain = <1>; <<
847 #address-cells = <3>; <<
848 #size-cells = <2>; <<
849 interrupts = <GIC_SPI 229 IRQ_ <<
850 interrupt-names = "pcie_irq"; <<
851 clocks = <&pciesys CLK_PCIE_P1 <<
852 /* designer has conne <<
853 <&pciesys CLK_PCIE_P0 <<
854 <&pciesys CLK_PCIE_P1 <<
855 <&pciesys CLK_PCIE_P1 <<
856 <&pciesys CLK_PCIE_P1 <<
857 <&pciesys CLK_PCIE_P1 <<
858 clock-names = "sys_ck1", "ahb_ <<
859 "axi_ck1", "obff <<
860 <<
861 power-domains = <&scpsys MT762 <<
862 bus-range = <0x00 0xff>; <<
863 ranges = <0x82000000 0 0x28000 <<
864 status = "disabled"; <<
865 <<
866 #interrupt-cells = <1>; <<
867 interrupt-map-mask = <0 0 0 7> <<
868 interrupt-map = <0 0 0 1 &pcie <<
869 <0 0 0 2 &pcie <<
870 <0 0 0 3 &pcie <<
871 <0 0 0 4 &pcie <<
872 pcie_intc1: interrupt-controll <<
873 interrupt-controller; <<
874 #address-cells = <0>; <<
875 #interrupt-cells = <1> <<
876 }; <<
877 }; <<
878 <<
879 sata: sata@1a200000 { <<
880 compatible = "mediatek,mt7622- <<
881 "mediatek,mtk-ahc <<
882 reg = <0 0x1a200000 0 0x1100>; <<
883 interrupts = <GIC_SPI 233 IRQ_ <<
884 interrupt-names = "hostc"; <<
885 clocks = <&pciesys CLK_SATA_AH <<
886 <&pciesys CLK_SATA_AX <<
887 <&pciesys CLK_SATA_AS <<
888 <&pciesys CLK_SATA_RB <<
889 <&pciesys CLK_SATA_PM <<
890 clock-names = "ahb", "axi", "a <<
891 phys = <&sata_port PHY_TYPE_SA <<
892 phy-names = "sata-phy"; <<
893 ports-implemented = <0x1>; <<
894 power-domains = <&scpsys MT762 <<
895 resets = <&pciesys MT7622_SATA <<
896 <&pciesys MT7622_SATA <<
897 <&pciesys MT7622_SATA <<
898 reset-names = "axi", "sw", "re <<
899 mediatek,phy-mode = <&pciesys> <<
900 status = "disabled"; <<
901 }; <<
902 <<
903 sata_phy: t-phy { <<
904 compatible = "mediatek,mt7622- <<
905 "mediatek,generic <<
906 #address-cells = <2>; <<
907 #size-cells = <2>; <<
908 ranges; <<
909 status = "disabled"; <<
910 <<
911 sata_port: sata-phy@1a243000 { <<
912 reg = <0 0x1a243000 0 <<
913 clocks = <&topckgen CL <<
914 clock-names = "ref"; <<
915 #phy-cells = <1>; <<
916 }; <<
917 }; <<
918 <<
919 hifsys: clock-controller@1af00000 { <<
920 compatible = "mediatek,mt7622- <<
921 reg = <0 0x1af00000 0 0x70>; <<
922 #clock-cells = <1>; <<
923 }; <<
924 <<
925 ethsys: clock-controller@1b000000 { <<
926 compatible = "mediatek,mt7622- <<
927 "syscon"; <<
928 reg = <0 0x1b000000 0 0x1000>; <<
929 #clock-cells = <1>; <<
930 #reset-cells = <1>; <<
931 }; <<
932 <<
933 hsdma: dma-controller@1b007000 { <<
934 compatible = "mediatek,mt7622- <<
935 reg = <0 0x1b007000 0 0x1000>; <<
936 interrupts = <GIC_SPI 219 IRQ_ <<
937 clocks = <ðsys CLK_ETH_HSDM <<
938 clock-names = "hsdma"; <<
939 power-domains = <&scpsys MT762 <<
940 #dma-cells = <1>; <<
941 dma-requests = <3>; <<
942 }; <<
943 <<
944 pcie_mirror: pcie-mirror@10000400 { <<
945 compatible = "mediatek,mt7622- <<
946 "syscon"; <<
947 reg = <0 0x10000400 0 0x10>; <<
948 }; <<
949 <<
950 wed0: wed@1020a000 { <<
951 compatible = "mediatek,mt7622- <<
952 "syscon"; <<
953 reg = <0 0x1020a000 0 0x1000>; <<
954 interrupts = <GIC_SPI 214 IRQ_ <<
955 }; <<
956 <<
957 wed1: wed@1020b000 { <<
958 compatible = "mediatek,mt7622- <<
959 "syscon"; <<
960 reg = <0 0x1020b000 0 0x1000>; <<
961 interrupts = <GIC_SPI 215 IRQ_ <<
962 }; <<
963 <<
964 eth: ethernet@1b100000 { <<
965 compatible = "mediatek,mt7622- <<
966 reg = <0 0x1b100000 0 0x20000> <<
967 interrupts = <GIC_SPI 223 IRQ_ <<
968 <GIC_SPI 224 IRQ_ <<
969 <GIC_SPI 225 IRQ_ <<
970 clocks = <&topckgen CLK_TOP_ET <<
971 <ðsys CLK_ETH_ESW_ <<
972 <ðsys CLK_ETH_GP0_ <<
973 <ðsys CLK_ETH_GP1_ <<
974 <ðsys CLK_ETH_GP2_ <<
975 <&sgmiisys CLK_SGMII_ <<
976 <&sgmiisys CLK_SGMII_ <<
977 <&sgmiisys CLK_SGMII_ <<
978 <&sgmiisys CLK_SGMII_ <<
979 <&topckgen CLK_TOP_SG <<
980 <&apmixedsys CLK_APMI <<
981 clock-names = "ethif", "esw", <<
982 "sgmii_tx250m", <<
983 "sgmii_cdr_ref", <<
984 "eth2pll"; <<
985 power-domains = <&scpsys MT762 <<
986 mediatek,ethsys = <ðsys>; <<
987 mediatek,sgmiisys = <&sgmiisys <<
988 cci-control-port = <&cci_contr <<
989 mediatek,wed = <&wed0>, <&wed1 <<
990 mediatek,pcie-mirror = <&pcie_ <<
991 mediatek,hifsys = <&hifsys>; <<
992 dma-coherent; <<
993 #address-cells = <1>; <<
994 #size-cells = <0>; <<
995 status = "disabled"; <<
996 }; <<
997 <<
998 sgmiisys: sgmiisys@1b128000 { <<
999 compatible = "mediatek,mt7622- <<
1000 "syscon"; <<
1001 reg = <0 0x1b128000 0 0x3000> <<
1002 #clock-cells = <1>; <<
1003 }; 109 };
1004 }; 110 };
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