1 /* 1 /*
2 * Copyright (c) 2017 MediaTek Inc. 2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com> 3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com>
5 * 5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h> 11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h> 13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h> 14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 compatible = "mediatek,mt7622"; 18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>; 19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 cpu_opp_table: opp-table { 23 cpu_opp_table: opp-table {
24 compatible = "operating-points 24 compatible = "operating-points-v2";
25 opp-shared; 25 opp-shared;
26 opp-300000000 { 26 opp-300000000 {
27 opp-hz = /bits/ 64 <30 27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <95000 28 opp-microvolt = <950000>;
29 }; 29 };
30 30
31 opp-437500000 { 31 opp-437500000 {
32 opp-hz = /bits/ 64 <43 32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <10000 33 opp-microvolt = <1000000>;
34 }; 34 };
35 35
36 opp-600000000 { 36 opp-600000000 {
37 opp-hz = /bits/ 64 <60 37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <10500 38 opp-microvolt = <1050000>;
39 }; 39 };
40 40
41 opp-812500000 { 41 opp-812500000 {
42 opp-hz = /bits/ 64 <81 42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <11000 43 opp-microvolt = <1100000>;
44 }; 44 };
45 45
46 opp-1025000000 { 46 opp-1025000000 {
47 opp-hz = /bits/ 64 <10 47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <11500 48 opp-microvolt = <1150000>;
49 }; 49 };
50 50
51 opp-1137500000 { 51 opp-1137500000 {
52 opp-hz = /bits/ 64 <11 52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <12000 53 opp-microvolt = <1200000>;
54 }; 54 };
55 55
56 opp-1262500000 { 56 opp-1262500000 {
57 opp-hz = /bits/ 64 <12 57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <12500 58 opp-microvolt = <1250000>;
59 }; 59 };
60 60
61 opp-1350000000 { 61 opp-1350000000 {
62 opp-hz = /bits/ 64 <13 62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <13100 63 opp-microvolt = <1310000>;
64 }; 64 };
65 }; 65 };
66 66
67 cpus { 67 cpus {
68 #address-cells = <2>; 68 #address-cells = <2>;
69 #size-cells = <0>; 69 #size-cells = <0>;
70 70
71 cpu0: cpu@0 { 71 cpu0: cpu@0 {
72 device_type = "cpu"; 72 device_type = "cpu";
73 compatible = "arm,cort !! 73 compatible = "arm,cortex-a53", "arm,armv8";
74 reg = <0x0 0x0>; 74 reg = <0x0 0x0>;
75 clocks = <&infracfg CL 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", " 77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = 78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 enable-method = "psci" 80 enable-method = "psci";
81 clock-frequency = <130 81 clock-frequency = <1300000000>;
82 cci-control-port = <&c <<
83 next-level-cache = <&L <<
84 }; 82 };
85 83
86 cpu1: cpu@1 { 84 cpu1: cpu@1 {
87 device_type = "cpu"; 85 device_type = "cpu";
88 compatible = "arm,cort !! 86 compatible = "arm,cortex-a53", "arm,armv8";
89 reg = <0x0 0x1>; 87 reg = <0x0 0x1>;
90 clocks = <&infracfg CL 88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys 89 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", " 90 clock-names = "cpu", "intermediate";
93 operating-points-v2 = 91 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; <<
95 enable-method = "psci" 92 enable-method = "psci";
96 clock-frequency = <130 93 clock-frequency = <1300000000>;
97 cci-control-port = <&c <<
98 next-level-cache = <&L <<
99 }; <<
100 <<
101 L2: l2-cache { <<
102 compatible = "cache"; <<
103 cache-level = <2>; <<
104 cache-unified; <<
105 }; 94 };
106 }; 95 };
107 96
108 pwrap_clk: dummy40m { 97 pwrap_clk: dummy40m {
109 compatible = "fixed-clock"; 98 compatible = "fixed-clock";
110 clock-frequency = <40000000>; 99 clock-frequency = <40000000>;
111 #clock-cells = <0>; 100 #clock-cells = <0>;
112 }; 101 };
113 102
114 clk25m: oscillator { 103 clk25m: oscillator {
115 compatible = "fixed-clock"; 104 compatible = "fixed-clock";
116 #clock-cells = <0>; 105 #clock-cells = <0>;
117 clock-frequency = <25000000>; 106 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal" 107 clock-output-names = "clkxtal";
119 }; 108 };
120 109
121 psci { 110 psci {
122 compatible = "arm,psci-0.2"; !! 111 compatible = "arm,psci-0.2";
123 method = "smc"; !! 112 method = "smc";
124 }; <<
125 <<
126 pmu { <<
127 compatible = "arm,cortex-a53-p <<
128 interrupts = <GIC_SPI 8 IRQ_TY <<
129 <GIC_SPI 9 IRQ_TY <<
130 interrupt-affinity = <&cpu0>, <<
131 }; 113 };
132 114
133 reserved-memory { 115 reserved-memory {
134 #address-cells = <2>; 116 #address-cells = <2>;
135 #size-cells = <2>; 117 #size-cells = <2>;
136 ranges; 118 ranges;
137 119
138 /* 192 KiB reserved for ARM Tr 120 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
139 secmon_reserved: secmon@430000 121 secmon_reserved: secmon@43000000 {
140 reg = <0 0x43000000 0 122 reg = <0 0x43000000 0 0x30000>;
141 no-map; 123 no-map;
142 }; 124 };
143 }; 125 };
144 126
145 thermal-zones { 127 thermal-zones {
146 cpu_thermal: cpu-thermal { 128 cpu_thermal: cpu-thermal {
147 polling-delay-passive 129 polling-delay-passive = <1000>;
148 polling-delay = <1000> 130 polling-delay = <1000>;
149 131
150 thermal-sensors = <&th 132 thermal-sensors = <&thermal 0>;
151 133
152 trips { 134 trips {
153 cpu_passive: c 135 cpu_passive: cpu-passive {
154 temper 136 temperature = <47000>;
155 hyster 137 hysteresis = <2000>;
156 type = 138 type = "passive";
157 }; 139 };
158 140
159 cpu_active: cp 141 cpu_active: cpu-active {
160 temper 142 temperature = <67000>;
161 hyster 143 hysteresis = <2000>;
162 type = 144 type = "active";
163 }; 145 };
164 146
165 cpu_hot: cpu-h 147 cpu_hot: cpu-hot {
166 temper 148 temperature = <87000>;
167 hyster 149 hysteresis = <2000>;
168 type = 150 type = "hot";
169 }; 151 };
170 152
171 cpu-crit { 153 cpu-crit {
172 temper 154 temperature = <107000>;
173 hyster 155 hysteresis = <2000>;
174 type = 156 type = "critical";
175 }; 157 };
176 }; 158 };
177 159
178 cooling-maps { 160 cooling-maps {
179 map0 { 161 map0 {
180 trip = 162 trip = <&cpu_passive>;
181 coolin !! 163 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 <<
183 }; 164 };
184 165
185 map1 { 166 map1 {
186 trip = 167 trip = <&cpu_active>;
187 coolin !! 168 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
188 <<
189 }; 169 };
190 170
191 map2 { 171 map2 {
192 trip = 172 trip = <&cpu_hot>;
193 coolin !! 173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 <<
195 }; 174 };
196 }; 175 };
197 }; 176 };
198 }; 177 };
199 178
200 timer { 179 timer {
201 compatible = "arm,armv8-timer" 180 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>; 181 interrupt-parent = <&gic>;
203 interrupts = <GIC_PPI 13 (GIC_ 182 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_LEVEL_H 183 IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_ 184 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_LEVEL_H 185 IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 (GIC_ 186 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_LEVEL_H 187 IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 (GIC_ 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_LEVEL_H 189 IRQ_TYPE_LEVEL_HIGH)>;
211 }; 190 };
212 191
213 infracfg: infracfg@10000000 { 192 infracfg: infracfg@10000000 {
214 compatible = "mediatek,mt7622- 193 compatible = "mediatek,mt7622-infracfg",
215 "syscon"; 194 "syscon";
216 reg = <0 0x10000000 0 0x1000>; 195 reg = <0 0x10000000 0 0x1000>;
217 #clock-cells = <1>; 196 #clock-cells = <1>;
218 #reset-cells = <1>; 197 #reset-cells = <1>;
219 }; 198 };
220 199
221 pwrap: pwrap@10001000 { 200 pwrap: pwrap@10001000 {
222 compatible = "mediatek,mt7622- 201 compatible = "mediatek,mt7622-pwrap";
223 reg = <0 0x10001000 0 0x250>; 202 reg = <0 0x10001000 0 0x250>;
224 reg-names = "pwrap"; 203 reg-names = "pwrap";
225 clocks = <&infracfg CLK_INFRA_ 204 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
226 clock-names = "spi", "wrap"; 205 clock-names = "spi", "wrap";
227 resets = <&infracfg MT7622_INF 206 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
228 reset-names = "pwrap"; 207 reset-names = "pwrap";
229 interrupts = <GIC_SPI 163 IRQ_ 208 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
230 status = "disabled"; 209 status = "disabled";
231 }; 210 };
232 211
233 pericfg: pericfg@10002000 { 212 pericfg: pericfg@10002000 {
234 compatible = "mediatek,mt7622- 213 compatible = "mediatek,mt7622-pericfg",
235 "syscon"; 214 "syscon";
236 reg = <0 0x10002000 0 0x1000>; 215 reg = <0 0x10002000 0 0x1000>;
237 #clock-cells = <1>; 216 #clock-cells = <1>;
238 #reset-cells = <1>; 217 #reset-cells = <1>;
239 }; 218 };
240 219
241 scpsys: power-controller@10006000 { !! 220 scpsys: scpsys@10006000 {
242 compatible = "mediatek,mt7622- 221 compatible = "mediatek,mt7622-scpsys",
243 "syscon"; 222 "syscon";
244 #power-domain-cells = <1>; 223 #power-domain-cells = <1>;
245 reg = <0 0x10006000 0 0x1000>; 224 reg = <0 0x10006000 0 0x1000>;
246 interrupts = <GIC_SPI 165 IRQ_ 225 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 166 IRQ_ 226 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 167 IRQ_ 227 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
249 <GIC_SPI 168 IRQ_ 228 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
250 infracfg = <&infracfg>; 229 infracfg = <&infracfg>;
251 clocks = <&topckgen CLK_TOP_HI 230 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 clock-names = "hif_sel"; 231 clock-names = "hif_sel";
253 }; 232 };
254 233
255 cir: ir-receiver@10009000 { !! 234 cir: cir@10009000 {
256 compatible = "mediatek,mt7622- 235 compatible = "mediatek,mt7622-cir";
257 reg = <0 0x10009000 0 0x1000>; 236 reg = <0 0x10009000 0 0x1000>;
258 interrupts = <GIC_SPI 175 IRQ_ 237 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
259 clocks = <&infracfg CLK_INFRA_ 238 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
260 <&topckgen CLK_TOP_AX 239 <&topckgen CLK_TOP_AXI_SEL>;
261 clock-names = "clk", "bus"; 240 clock-names = "clk", "bus";
262 status = "disabled"; 241 status = "disabled";
263 }; 242 };
264 243
265 sysirq: interrupt-controller@10200620 244 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622- 245 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577- 246 "mediatek,mt6577-sysirq";
268 interrupt-controller; 247 interrupt-controller;
269 #interrupt-cells = <3>; 248 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>; 249 interrupt-parent = <&gic>;
271 reg = <0 0x10200620 0 0x20>; 250 reg = <0 0x10200620 0 0x20>;
272 }; 251 };
273 252
274 efuse: efuse@10206000 { 253 efuse: efuse@10206000 {
275 compatible = "mediatek,mt7622- 254 compatible = "mediatek,mt7622-efuse",
276 "mediatek,efuse"; 255 "mediatek,efuse";
277 reg = <0 0x10206000 0 0x1000>; 256 reg = <0 0x10206000 0 0x1000>;
278 #address-cells = <1>; 257 #address-cells = <1>;
279 #size-cells = <1>; 258 #size-cells = <1>;
280 259
281 thermal_calibration: calib@198 260 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>; 261 reg = <0x198 0xc>;
283 }; 262 };
284 }; 263 };
285 264
286 apmixedsys: clock-controller@10209000 !! 265 apmixedsys: apmixedsys@10209000 {
287 compatible = "mediatek,mt7622- !! 266 compatible = "mediatek,mt7622-apmixedsys",
>> 267 "syscon";
288 reg = <0 0x10209000 0 0x1000>; 268 reg = <0 0x10209000 0 0x1000>;
289 #clock-cells = <1>; 269 #clock-cells = <1>;
290 }; 270 };
291 271
292 topckgen: clock-controller@10210000 { !! 272 topckgen: topckgen@10210000 {
293 compatible = "mediatek,mt7622- !! 273 compatible = "mediatek,mt7622-topckgen",
>> 274 "syscon";
294 reg = <0 0x10210000 0 0x1000>; 275 reg = <0 0x10210000 0 0x1000>;
295 #clock-cells = <1>; 276 #clock-cells = <1>;
296 }; 277 };
297 278
298 rng: rng@1020f000 { 279 rng: rng@1020f000 {
299 compatible = "mediatek,mt7622- 280 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623- 281 "mediatek,mt7623-rng";
301 reg = <0 0x1020f000 0 0x1000>; 282 reg = <0 0x1020f000 0 0x1000>;
302 clocks = <&infracfg CLK_INFRA_ 283 clocks = <&infracfg CLK_INFRA_TRNG>;
303 clock-names = "rng"; 284 clock-names = "rng";
304 }; 285 };
305 286
306 pio: pinctrl@10211000 { 287 pio: pinctrl@10211000 {
307 compatible = "mediatek,mt7622- 288 compatible = "mediatek,mt7622-pinctrl";
308 reg = <0 0x10211000 0 0x1000>, !! 289 reg = <0 0x10211000 0 0x1000>;
309 <0 0x10005000 0 0x1000>; <<
310 reg-names = "base", "eint"; <<
311 gpio-controller; 290 gpio-controller;
312 #gpio-cells = <2>; 291 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 103>; <<
314 interrupt-controller; <<
315 interrupts = <GIC_SPI 153 IRQ_ <<
316 interrupt-parent = <&gic>; <<
317 #interrupt-cells = <2>; <<
318 }; 292 };
319 293
320 watchdog: watchdog@10212000 { 294 watchdog: watchdog@10212000 {
321 compatible = "mediatek,mt7622- 295 compatible = "mediatek,mt7622-wdt",
322 "mediatek,mt6589- 296 "mediatek,mt6589-wdt";
323 reg = <0 0x10212000 0 0x800>; 297 reg = <0 0x10212000 0 0x800>;
324 }; 298 };
325 299
326 rtc: rtc@10212800 { 300 rtc: rtc@10212800 {
327 compatible = "mediatek,mt7622- 301 compatible = "mediatek,mt7622-rtc",
328 "mediatek,soc-rtc 302 "mediatek,soc-rtc";
329 reg = <0 0x10212800 0 0x200>; 303 reg = <0 0x10212800 0 0x200>;
330 interrupts = <GIC_SPI 129 IRQ_ 304 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
331 clocks = <&topckgen CLK_TOP_RT 305 clocks = <&topckgen CLK_TOP_RTC>;
332 clock-names = "rtc"; 306 clock-names = "rtc";
333 }; 307 };
334 308
335 gic: interrupt-controller@10300000 { 309 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400"; 310 compatible = "arm,gic-400";
337 interrupt-controller; 311 interrupt-controller;
338 #interrupt-cells = <3>; 312 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>; 313 interrupt-parent = <&gic>;
340 reg = <0 0x10310000 0 0x1000>, 314 reg = <0 0x10310000 0 0x1000>,
341 <0 0x10320000 0 0x1000>, 315 <0 0x10320000 0 0x1000>,
342 <0 0x10340000 0 0x2000>, 316 <0 0x10340000 0 0x2000>,
343 <0 0x10360000 0 0x2000>; 317 <0 0x10360000 0 0x2000>;
344 }; 318 };
345 319
346 cci: cci@10390000 { <<
347 compatible = "arm,cci-400"; <<
348 #address-cells = <1>; <<
349 #size-cells = <1>; <<
350 reg = <0 0x10390000 0 0x1000>; <<
351 ranges = <0 0 0x10390000 0x100 <<
352 <<
353 cci_control0: slave-if@1000 { <<
354 compatible = "arm,cci- <<
355 interface-type = "ace- <<
356 reg = <0x1000 0x1000>; <<
357 }; <<
358 <<
359 cci_control1: slave-if@4000 { <<
360 compatible = "arm,cci- <<
361 interface-type = "ace" <<
362 reg = <0x4000 0x1000>; <<
363 }; <<
364 <<
365 cci_control2: slave-if@5000 { <<
366 compatible = "arm,cci- <<
367 interface-type = "ace" <<
368 reg = <0x5000 0x1000>; <<
369 }; <<
370 <<
371 pmu@9000 { <<
372 compatible = "arm,cci- <<
373 reg = <0x9000 0x5000>; <<
374 interrupts = <GIC_SPI <<
375 <GIC_SPI <<
376 <GIC_SPI <<
377 <GIC_SPI <<
378 <GIC_SPI <<
379 }; <<
380 }; <<
381 <<
382 auxadc: adc@11001000 { 320 auxadc: adc@11001000 {
383 compatible = "mediatek,mt7622- 321 compatible = "mediatek,mt7622-auxadc";
384 reg = <0 0x11001000 0 0x1000>; 322 reg = <0 0x11001000 0 0x1000>;
385 clocks = <&pericfg CLK_PERI_AU 323 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
386 clock-names = "main"; 324 clock-names = "main";
387 #io-channel-cells = <1>; 325 #io-channel-cells = <1>;
388 }; 326 };
389 327
390 uart0: serial@11002000 { 328 uart0: serial@11002000 {
391 compatible = "mediatek,mt7622- 329 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577- 330 "mediatek,mt6577-uart";
393 reg = <0 0x11002000 0 0x400>; 331 reg = <0 0x11002000 0 0x400>;
394 interrupts = <GIC_SPI 91 IRQ_T 332 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&topckgen CLK_TOP_UA 333 clocks = <&topckgen CLK_TOP_UART_SEL>,
396 <&pericfg CLK_PERI_UA !! 334 <&pericfg CLK_PERI_UART1_PD>;
397 clock-names = "baud", "bus"; 335 clock-names = "baud", "bus";
398 status = "disabled"; 336 status = "disabled";
399 }; 337 };
400 338
401 uart1: serial@11003000 { 339 uart1: serial@11003000 {
402 compatible = "mediatek,mt7622- 340 compatible = "mediatek,mt7622-uart",
403 "mediatek,mt6577- 341 "mediatek,mt6577-uart";
404 reg = <0 0x11003000 0 0x400>; 342 reg = <0 0x11003000 0 0x400>;
405 interrupts = <GIC_SPI 92 IRQ_T 343 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
406 clocks = <&topckgen CLK_TOP_UA 344 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 <&pericfg CLK_PERI_UA 345 <&pericfg CLK_PERI_UART1_PD>;
408 clock-names = "baud", "bus"; 346 clock-names = "baud", "bus";
409 status = "disabled"; 347 status = "disabled";
410 }; 348 };
411 349
412 uart2: serial@11004000 { 350 uart2: serial@11004000 {
413 compatible = "mediatek,mt7622- 351 compatible = "mediatek,mt7622-uart",
414 "mediatek,mt6577- 352 "mediatek,mt6577-uart";
415 reg = <0 0x11004000 0 0x400>; 353 reg = <0 0x11004000 0 0x400>;
416 interrupts = <GIC_SPI 93 IRQ_T 354 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&topckgen CLK_TOP_UA 355 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 <&pericfg CLK_PERI_UA 356 <&pericfg CLK_PERI_UART2_PD>;
419 clock-names = "baud", "bus"; 357 clock-names = "baud", "bus";
420 status = "disabled"; 358 status = "disabled";
421 }; 359 };
422 360
423 uart3: serial@11005000 { 361 uart3: serial@11005000 {
424 compatible = "mediatek,mt7622- 362 compatible = "mediatek,mt7622-uart",
425 "mediatek,mt6577- 363 "mediatek,mt6577-uart";
426 reg = <0 0x11005000 0 0x400>; 364 reg = <0 0x11005000 0 0x400>;
427 interrupts = <GIC_SPI 94 IRQ_T 365 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
428 clocks = <&topckgen CLK_TOP_UA 366 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 <&pericfg CLK_PERI_UA 367 <&pericfg CLK_PERI_UART3_PD>;
430 clock-names = "baud", "bus"; 368 clock-names = "baud", "bus";
431 status = "disabled"; 369 status = "disabled";
432 }; 370 };
433 371
434 pwm: pwm@11006000 { 372 pwm: pwm@11006000 {
435 compatible = "mediatek,mt7622- 373 compatible = "mediatek,mt7622-pwm";
436 reg = <0 0x11006000 0 0x1000>; 374 reg = <0 0x11006000 0 0x1000>;
437 #pwm-cells = <2>; <<
438 interrupts = <GIC_SPI 77 IRQ_T 375 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_PW 376 clocks = <&topckgen CLK_TOP_PWM_SEL>,
440 <&pericfg CLK_PERI_PW 377 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PW 378 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PW 379 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PW 380 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PW 381 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PW 382 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PW 383 <&pericfg CLK_PERI_PWM6_PD>;
447 clock-names = "top", "main", " 384 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
448 "pwm5", "pwm6"; 385 "pwm5", "pwm6";
449 status = "disabled"; 386 status = "disabled";
450 }; 387 };
451 388
452 i2c0: i2c@11007000 { 389 i2c0: i2c@11007000 {
453 compatible = "mediatek,mt7622- 390 compatible = "mediatek,mt7622-i2c";
454 reg = <0 0x11007000 0 0x90>, 391 reg = <0 0x11007000 0 0x90>,
455 <0 0x11000100 0 0x80>; 392 <0 0x11000100 0 0x80>;
456 interrupts = <GIC_SPI 84 IRQ_T 393 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>; 394 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2 395 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP 396 <&pericfg CLK_PERI_AP_DMA_PD>;
460 clock-names = "main", "dma"; 397 clock-names = "main", "dma";
461 #address-cells = <1>; 398 #address-cells = <1>;
462 #size-cells = <0>; 399 #size-cells = <0>;
463 status = "disabled"; 400 status = "disabled";
464 }; 401 };
465 402
466 i2c1: i2c@11008000 { 403 i2c1: i2c@11008000 {
467 compatible = "mediatek,mt7622- 404 compatible = "mediatek,mt7622-i2c";
468 reg = <0 0x11008000 0 0x90>, 405 reg = <0 0x11008000 0 0x90>,
469 <0 0x11000180 0 0x80>; 406 <0 0x11000180 0 0x80>;
470 interrupts = <GIC_SPI 85 IRQ_T 407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
471 clock-div = <16>; 408 clock-div = <16>;
472 clocks = <&pericfg CLK_PERI_I2 409 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP 410 <&pericfg CLK_PERI_AP_DMA_PD>;
474 clock-names = "main", "dma"; 411 clock-names = "main", "dma";
475 #address-cells = <1>; 412 #address-cells = <1>;
476 #size-cells = <0>; 413 #size-cells = <0>;
477 status = "disabled"; 414 status = "disabled";
478 }; 415 };
479 416
480 i2c2: i2c@11009000 { 417 i2c2: i2c@11009000 {
481 compatible = "mediatek,mt7622- 418 compatible = "mediatek,mt7622-i2c";
482 reg = <0 0x11009000 0 0x90>, 419 reg = <0 0x11009000 0 0x90>,
483 <0 0x11000200 0 0x80>; 420 <0 0x11000200 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_T 421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
485 clock-div = <16>; 422 clock-div = <16>;
486 clocks = <&pericfg CLK_PERI_I2 423 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP 424 <&pericfg CLK_PERI_AP_DMA_PD>;
488 clock-names = "main", "dma"; 425 clock-names = "main", "dma";
489 #address-cells = <1>; 426 #address-cells = <1>;
490 #size-cells = <0>; 427 #size-cells = <0>;
491 status = "disabled"; 428 status = "disabled";
492 }; 429 };
493 430
494 spi0: spi@1100a000 { 431 spi0: spi@1100a000 {
495 compatible = "mediatek,mt7622- 432 compatible = "mediatek,mt7622-spi";
496 reg = <0 0x1100a000 0 0x100>; 433 reg = <0 0x1100a000 0 0x100>;
497 interrupts = <GIC_SPI 118 IRQ_ 434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&topckgen CLK_TOP_SY 435 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SP 436 <&topckgen CLK_TOP_SPI0_SEL>,
500 <&pericfg CLK_PERI_SP 437 <&pericfg CLK_PERI_SPI0_PD>;
501 clock-names = "parent-clk", "s 438 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>; 439 #address-cells = <1>;
503 #size-cells = <0>; 440 #size-cells = <0>;
504 status = "disabled"; 441 status = "disabled";
505 }; 442 };
506 443
507 thermal: thermal@1100b000 { 444 thermal: thermal@1100b000 {
508 #thermal-sensor-cells = <1>; 445 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622- 446 compatible = "mediatek,mt7622-thermal";
510 reg = <0 0x1100b000 0 0x1000>; 447 reg = <0 0x1100b000 0 0x1000>;
511 interrupts = <0 78 IRQ_TYPE_LE 448 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_TH 449 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AU 450 <&pericfg CLK_PERI_AUXADC_PD>;
514 clock-names = "therm", "auxadc 451 clock-names = "therm", "auxadc";
515 resets = <&pericfg MT7622_PERI 452 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
>> 453 reset-names = "therm";
516 mediatek,auxadc = <&auxadc>; 454 mediatek,auxadc = <&auxadc>;
517 mediatek,apmixedsys = <&apmixe 455 mediatek,apmixedsys = <&apmixedsys>;
518 nvmem-cells = <&thermal_calibr 456 nvmem-cells = <&thermal_calibration>;
519 nvmem-cell-names = "calibratio 457 nvmem-cell-names = "calibration-data";
520 }; 458 };
521 459
522 btif: serial@1100c000 { 460 btif: serial@1100c000 {
523 compatible = "mediatek,mt7622- 461 compatible = "mediatek,mt7622-btif",
524 "mediatek,mtk-bti 462 "mediatek,mtk-btif";
525 reg = <0 0x1100c000 0 0x1000>; 463 reg = <0 0x1100c000 0 0x1000>;
526 interrupts = <GIC_SPI 90 IRQ_T 464 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&pericfg CLK_PERI_BT 465 clocks = <&pericfg CLK_PERI_BTIF_PD>;
>> 466 clock-names = "main";
528 reg-shift = <2>; 467 reg-shift = <2>;
529 reg-io-width = <4>; 468 reg-io-width = <4>;
530 status = "disabled"; 469 status = "disabled";
531 <<
532 bluetooth { <<
533 compatible = "mediatek <<
534 power-domains = <&scps <<
535 clocks = <&clk25m>; <<
536 clock-names = "ref"; <<
537 }; <<
538 }; 470 };
539 471
540 nandc: nand-controller@1100d000 { !! 472 nandc: nfi@1100d000 {
541 compatible = "mediatek,mt7622- 473 compatible = "mediatek,mt7622-nfc";
542 reg = <0 0x1100D000 0 0x1000>; 474 reg = <0 0x1100D000 0 0x1000>;
543 interrupts = <GIC_SPI 96 IRQ_T 475 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_NF 476 clocks = <&pericfg CLK_PERI_NFI_PD>,
545 <&pericfg CLK_PERI_SN 477 <&pericfg CLK_PERI_SNFI_PD>;
546 clock-names = "nfi_clk", "pad_ 478 clock-names = "nfi_clk", "pad_clk";
547 ecc-engine = <&bch>; 479 ecc-engine = <&bch>;
548 #address-cells = <1>; 480 #address-cells = <1>;
549 #size-cells = <0>; 481 #size-cells = <0>;
550 status = "disabled"; 482 status = "disabled";
551 }; 483 };
552 484
553 snfi: spi@1100d000 { <<
554 compatible = "mediatek,mt7622- <<
555 reg = <0 0x1100d000 0 0x1000>; <<
556 interrupts = <GIC_SPI 96 IRQ_T <<
557 clocks = <&pericfg CLK_PERI_NF <<
558 clock-names = "nfi_clk", "pad_ <<
559 nand-ecc-engine = <&bch>; <<
560 #address-cells = <1>; <<
561 #size-cells = <0>; <<
562 status = "disabled"; <<
563 }; <<
564 <<
565 bch: ecc@1100e000 { 485 bch: ecc@1100e000 {
566 compatible = "mediatek,mt7622- 486 compatible = "mediatek,mt7622-ecc";
567 reg = <0 0x1100e000 0 0x1000>; 487 reg = <0 0x1100e000 0 0x1000>;
568 interrupts = <GIC_SPI 95 IRQ_T 488 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
569 clocks = <&pericfg CLK_PERI_NF 489 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
570 clock-names = "nfiecc_clk"; 490 clock-names = "nfiecc_clk";
571 status = "disabled"; 491 status = "disabled";
572 }; 492 };
573 493
574 nor_flash: spi@11014000 { 494 nor_flash: spi@11014000 {
575 compatible = "mediatek,mt7622- 495 compatible = "mediatek,mt7622-nor",
576 "mediatek,mt8173- 496 "mediatek,mt8173-nor";
577 reg = <0 0x11014000 0 0xe0>; 497 reg = <0 0x11014000 0 0xe0>;
578 clocks = <&pericfg CLK_PERI_FL 498 clocks = <&pericfg CLK_PERI_FLASH_PD>,
579 <&topckgen CLK_TOP_FL 499 <&topckgen CLK_TOP_FLASH_SEL>;
580 clock-names = "spi", "sf"; 500 clock-names = "spi", "sf";
581 #address-cells = <1>; 501 #address-cells = <1>;
582 #size-cells = <0>; 502 #size-cells = <0>;
583 status = "disabled"; 503 status = "disabled";
584 }; 504 };
585 505
586 spi1: spi@11016000 { 506 spi1: spi@11016000 {
587 compatible = "mediatek,mt7622- 507 compatible = "mediatek,mt7622-spi";
588 reg = <0 0x11016000 0 0x100>; 508 reg = <0 0x11016000 0 0x100>;
589 interrupts = <GIC_SPI 122 IRQ_ 509 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&topckgen CLK_TOP_SY 510 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SP 511 <&topckgen CLK_TOP_SPI1_SEL>,
592 <&pericfg CLK_PERI_SP 512 <&pericfg CLK_PERI_SPI1_PD>;
593 clock-names = "parent-clk", "s 513 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 #address-cells = <1>; 514 #address-cells = <1>;
595 #size-cells = <0>; 515 #size-cells = <0>;
596 status = "disabled"; 516 status = "disabled";
597 }; 517 };
598 518
599 uart4: serial@11019000 { 519 uart4: serial@11019000 {
600 compatible = "mediatek,mt7622- 520 compatible = "mediatek,mt7622-uart",
601 "mediatek,mt6577- 521 "mediatek,mt6577-uart";
602 reg = <0 0x11019000 0 0x400>; 522 reg = <0 0x11019000 0 0x400>;
603 interrupts = <GIC_SPI 89 IRQ_T 523 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CLK_TOP_UA 524 clocks = <&topckgen CLK_TOP_UART_SEL>,
605 <&pericfg CLK_PERI_UA 525 <&pericfg CLK_PERI_UART4_PD>;
606 clock-names = "baud", "bus"; 526 clock-names = "baud", "bus";
607 status = "disabled"; 527 status = "disabled";
608 }; 528 };
609 529
610 audsys: clock-controller@11220000 { <<
611 compatible = "mediatek,mt7622- <<
612 reg = <0 0x11220000 0 0x2000>; <<
613 #clock-cells = <1>; <<
614 <<
615 afe: audio-controller { <<
616 compatible = "mediatek <<
617 interrupts = <GIC_SPI <<
618 <GIC_SPI <<
619 interrupt-names = "afe <<
620 <<
621 clocks = <&infracfg CL <<
622 <&topckgen CL <<
623 <&topckgen CL <<
624 <&topckgen CL <<
625 <&topckgen CL <<
626 <&topckgen CL <<
627 <&topckgen CL <<
628 <&topckgen CL <<
629 <&topckgen CL <<
630 <&topckgen CL <<
631 <&topckgen CL <<
632 <&topckgen CL <<
633 <&topckgen CL <<
634 <&topckgen CL <<
635 <&topckgen CL <<
636 <&topckgen CL <<
637 <&topckgen CL <<
638 <&audsys CLK_ <<
639 <&audsys CLK_ <<
640 <&audsys CLK_ <<
641 <&audsys CLK_ <<
642 <&audsys CLK_ <<
643 <&audsys CLK_ <<
644 <&audsys CLK_ <<
645 <&audsys CLK_ <<
646 <&audsys CLK_ <<
647 <&audsys CLK_ <<
648 <&audsys CLK_ <<
649 <&audsys CLK_ <<
650 <&audsys CLK_ <<
651 <&audsys CLK_ <<
652 <&audsys CLK_ <<
653 <&audsys CLK_ <<
654 <<
655 clock-names = "infra_s <<
656 "top_aud <<
657 "top_aud <<
658 "top_aud <<
659 "top_aud <<
660 "i2s0_sr <<
661 "i2s1_sr <<
662 "i2s2_sr <<
663 "i2s3_sr <<
664 "i2s0_sr <<
665 "i2s1_sr <<
666 "i2s2_sr <<
667 "i2s3_sr <<
668 "i2s0_mc <<
669 "i2s1_mc <<
670 "i2s2_mc <<
671 "i2s3_mc <<
672 "i2so0_h <<
673 "i2so1_h <<
674 "i2so2_h <<
675 "i2so3_h <<
676 "i2si0_h <<
677 "i2si1_h <<
678 "i2si2_h <<
679 "i2si3_h <<
680 "asrc0_o <<
681 "asrc1_o <<
682 "asrc2_o <<
683 "asrc3_o <<
684 "audio_a <<
685 "audio_a <<
686 "audio_a <<
687 "audio_a <<
688 <<
689 assigned-clocks = <&to <<
690 <&to <<
691 <&to <<
692 <&to <<
693 assigned-clock-parents <<
694 <<
695 assigned-clock-rates = <<
696 }; <<
697 }; <<
698 <<
699 mmc0: mmc@11230000 { 530 mmc0: mmc@11230000 {
700 compatible = "mediatek,mt7622- 531 compatible = "mediatek,mt7622-mmc";
701 reg = <0 0x11230000 0 0x1000>; 532 reg = <0 0x11230000 0 0x1000>;
702 interrupts = <GIC_SPI 79 IRQ_T 533 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK_PERI_MS 534 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
704 <&topckgen CLK_TOP_MS 535 <&topckgen CLK_TOP_MSDC50_0_SEL>;
705 clock-names = "source", "hclk" 536 clock-names = "source", "hclk";
706 resets = <&pericfg MT7622_PERI <<
707 reset-names = "hrst"; <<
708 status = "disabled"; 537 status = "disabled";
709 }; 538 };
710 539
711 mmc1: mmc@11240000 { 540 mmc1: mmc@11240000 {
712 compatible = "mediatek,mt7622- 541 compatible = "mediatek,mt7622-mmc";
713 reg = <0 0x11240000 0 0x1000>; 542 reg = <0 0x11240000 0 0x1000>;
714 interrupts = <GIC_SPI 80 IRQ_T 543 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
715 clocks = <&pericfg CLK_PERI_MS 544 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
716 <&topckgen CLK_TOP_AX 545 <&topckgen CLK_TOP_AXI_SEL>;
717 clock-names = "source", "hclk" 546 clock-names = "source", "hclk";
718 resets = <&pericfg MT7622_PERI <<
719 reset-names = "hrst"; <<
720 status = "disabled"; <<
721 }; <<
722 <<
723 wmac: wmac@18000000 { <<
724 compatible = "mediatek,mt7622- <<
725 reg = <0 0x18000000 0 0x100000 <<
726 interrupts = <GIC_SPI 211 IRQ_ <<
727 <<
728 mediatek,infracfg = <&infracfg <<
729 status = "disabled"; 547 status = "disabled";
730 <<
731 power-domains = <&scpsys MT762 <<
732 }; 548 };
733 549
734 ssusbsys: clock-controller@1a000000 { !! 550 ssusbsys: ssusbsys@1a000000 {
735 compatible = "mediatek,mt7622- !! 551 compatible = "mediatek,mt7622-ssusbsys",
>> 552 "syscon";
736 reg = <0 0x1a000000 0 0x1000>; 553 reg = <0 0x1a000000 0 0x1000>;
737 #clock-cells = <1>; 554 #clock-cells = <1>;
738 #reset-cells = <1>; 555 #reset-cells = <1>;
739 }; 556 };
740 557
741 ssusb: usb@1a0c0000 { 558 ssusb: usb@1a0c0000 {
742 compatible = "mediatek,mt7622- 559 compatible = "mediatek,mt7622-xhci",
743 "mediatek,mtk-xhc 560 "mediatek,mtk-xhci";
744 reg = <0 0x1a0c0000 0 0x01000> 561 reg = <0 0x1a0c0000 0 0x01000>,
745 <0 0x1a0c4700 0 0x0100>; 562 <0 0x1a0c4700 0 0x0100>;
746 reg-names = "mac", "ippc"; 563 reg-names = "mac", "ippc";
747 interrupts = <GIC_SPI 232 IRQ_ 564 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
748 power-domains = <&scpsys MT762 565 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
749 clocks = <&ssusbsys CLK_SSUSB_ 566 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
750 <&ssusbsys CLK_SSUSB_ 567 <&ssusbsys CLK_SSUSB_REF_EN>,
751 <&ssusbsys CLK_SSUSB_ 568 <&ssusbsys CLK_SSUSB_MCU_EN>,
752 <&ssusbsys CLK_SSUSB_ 569 <&ssusbsys CLK_SSUSB_DMA_EN>;
753 clock-names = "sys_ck", "ref_c 570 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
754 phys = <&u2port0 PHY_TYPE_USB2 571 phys = <&u2port0 PHY_TYPE_USB2>,
755 <&u3port0 PHY_TYPE_USB3 572 <&u3port0 PHY_TYPE_USB3>,
756 <&u2port1 PHY_TYPE_USB2 573 <&u2port1 PHY_TYPE_USB2>;
757 574
758 status = "disabled"; 575 status = "disabled";
759 }; 576 };
760 577
761 u3phy: t-phy@1a0c4000 { !! 578 u3phy: usb-phy@1a0c4000 {
762 compatible = "mediatek,mt7622- !! 579 compatible = "mediatek,mt7622-u3phy",
763 "mediatek,generic 580 "mediatek,generic-tphy-v1";
764 reg = <0 0x1a0c4000 0 0x700>; 581 reg = <0 0x1a0c4000 0 0x700>;
765 #address-cells = <2>; 582 #address-cells = <2>;
766 #size-cells = <2>; 583 #size-cells = <2>;
767 ranges; 584 ranges;
768 status = "disabled"; 585 status = "disabled";
769 586
770 u2port0: usb-phy@1a0c4800 { 587 u2port0: usb-phy@1a0c4800 {
771 reg = <0 0x1a0c4800 0 588 reg = <0 0x1a0c4800 0 0x0100>;
772 #phy-cells = <1>; 589 #phy-cells = <1>;
773 clocks = <&ssusbsys CL 590 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
774 clock-names = "ref"; 591 clock-names = "ref";
775 }; 592 };
776 593
777 u3port0: usb-phy@1a0c4900 { 594 u3port0: usb-phy@1a0c4900 {
778 reg = <0 0x1a0c4900 0 595 reg = <0 0x1a0c4900 0 0x0700>;
779 #phy-cells = <1>; 596 #phy-cells = <1>;
780 clocks = <&clk25m>; 597 clocks = <&clk25m>;
781 clock-names = "ref"; 598 clock-names = "ref";
782 }; 599 };
783 600
784 u2port1: usb-phy@1a0c5000 { 601 u2port1: usb-phy@1a0c5000 {
785 reg = <0 0x1a0c5000 0 602 reg = <0 0x1a0c5000 0 0x0100>;
786 #phy-cells = <1>; 603 #phy-cells = <1>;
787 clocks = <&ssusbsys CL 604 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
788 clock-names = "ref"; 605 clock-names = "ref";
789 }; 606 };
790 }; 607 };
791 608
792 pciesys: clock-controller@1a100800 { !! 609 pciesys: pciesys@1a100800 {
793 compatible = "mediatek,mt7622- !! 610 compatible = "mediatek,mt7622-pciesys",
>> 611 "syscon";
794 reg = <0 0x1a100800 0 0x1000>; 612 reg = <0 0x1a100800 0 0x1000>;
795 #clock-cells = <1>; 613 #clock-cells = <1>;
796 #reset-cells = <1>; 614 #reset-cells = <1>;
797 }; 615 };
798 616
799 pciecfg: pciecfg@1a140000 { !! 617 pcie: pcie@1a140000 {
800 compatible = "mediatek,generic <<
801 reg = <0 0x1a140000 0 0x1000>; <<
802 }; <<
803 <<
804 pcie0: pcie@1a143000 { <<
805 compatible = "mediatek,mt7622- 618 compatible = "mediatek,mt7622-pcie";
806 device_type = "pci"; 619 device_type = "pci";
807 reg = <0 0x1a143000 0 0x1000>; !! 620 reg = <0 0x1a140000 0 0x1000>,
808 reg-names = "port0"; !! 621 <0 0x1a143000 0 0x1000>,
809 linux,pci-domain = <0>; !! 622 <0 0x1a145000 0 0x1000>;
>> 623 reg-names = "subsys", "port0", "port1";
810 #address-cells = <3>; 624 #address-cells = <3>;
811 #size-cells = <2>; 625 #size-cells = <2>;
812 interrupts = <GIC_SPI 228 IRQ_ !! 626 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
813 interrupt-names = "pcie_irq"; !! 627 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
814 clocks = <&pciesys CLK_PCIE_P0 628 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
>> 629 <&pciesys CLK_PCIE_P1_MAC_EN>,
>> 630 <&pciesys CLK_PCIE_P0_AHB_EN>,
815 <&pciesys CLK_PCIE_P0 631 <&pciesys CLK_PCIE_P0_AHB_EN>,
816 <&pciesys CLK_PCIE_P0 632 <&pciesys CLK_PCIE_P0_AUX_EN>,
>> 633 <&pciesys CLK_PCIE_P1_AUX_EN>,
817 <&pciesys CLK_PCIE_P0 634 <&pciesys CLK_PCIE_P0_AXI_EN>,
>> 635 <&pciesys CLK_PCIE_P1_AXI_EN>,
818 <&pciesys CLK_PCIE_P0 636 <&pciesys CLK_PCIE_P0_OBFF_EN>,
819 <&pciesys CLK_PCIE_P0 !! 637 <&pciesys CLK_PCIE_P1_OBFF_EN>,
820 clock-names = "sys_ck0", "ahb_ !! 638 <&pciesys CLK_PCIE_P0_PIPE_EN>,
821 "axi_ck0", "obff !! 639 <&pciesys CLK_PCIE_P1_PIPE_EN>;
822 !! 640 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
>> 641 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
>> 642 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
823 power-domains = <&scpsys MT762 643 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
824 bus-range = <0x00 0xff>; 644 bus-range = <0x00 0xff>;
825 ranges = <0x82000000 0 0x20000 !! 645 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
826 status = "disabled"; 646 status = "disabled";
827 647
828 #interrupt-cells = <1>; !! 648 pcie0: pcie@0,0 {
829 interrupt-map-mask = <0 0 0 7> !! 649 reg = <0x0000 0 0 0 0>;
830 interrupt-map = <0 0 0 1 &pcie !! 650 #address-cells = <3>;
831 <0 0 0 2 &pcie !! 651 #size-cells = <2>;
832 <0 0 0 3 &pcie <<
833 <0 0 0 4 &pcie <<
834 pcie_intc0: interrupt-controll <<
835 interrupt-controller; <<
836 #address-cells = <0>; <<
837 #interrupt-cells = <1> 652 #interrupt-cells = <1>;
838 }; !! 653 ranges;
839 }; !! 654 status = "disabled";
840 655
841 pcie1: pcie@1a145000 { !! 656 num-lanes = <1>;
842 compatible = "mediatek,mt7622- !! 657 interrupt-map-mask = <0 0 0 7>;
843 device_type = "pci"; !! 658 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
844 reg = <0 0x1a145000 0 0x1000>; !! 659 <0 0 0 2 &pcie_intc0 1>,
845 reg-names = "port1"; !! 660 <0 0 0 3 &pcie_intc0 2>,
846 linux,pci-domain = <1>; !! 661 <0 0 0 4 &pcie_intc0 3>;
847 #address-cells = <3>; !! 662 pcie_intc0: interrupt-controller {
848 #size-cells = <2>; !! 663 interrupt-controller;
849 interrupts = <GIC_SPI 229 IRQ_ !! 664 #address-cells = <0>;
850 interrupt-names = "pcie_irq"; !! 665 #interrupt-cells = <1>;
851 clocks = <&pciesys CLK_PCIE_P1 !! 666 };
852 /* designer has conne !! 667 };
853 <&pciesys CLK_PCIE_P0 <<
854 <&pciesys CLK_PCIE_P1 <<
855 <&pciesys CLK_PCIE_P1 <<
856 <&pciesys CLK_PCIE_P1 <<
857 <&pciesys CLK_PCIE_P1 <<
858 clock-names = "sys_ck1", "ahb_ <<
859 "axi_ck1", "obff <<
860 <<
861 power-domains = <&scpsys MT762 <<
862 bus-range = <0x00 0xff>; <<
863 ranges = <0x82000000 0 0x28000 <<
864 status = "disabled"; <<
865 668
866 #interrupt-cells = <1>; !! 669 pcie1: pcie@1,0 {
867 interrupt-map-mask = <0 0 0 7> !! 670 reg = <0x0800 0 0 0 0>;
868 interrupt-map = <0 0 0 1 &pcie !! 671 #address-cells = <3>;
869 <0 0 0 2 &pcie !! 672 #size-cells = <2>;
870 <0 0 0 3 &pcie <<
871 <0 0 0 4 &pcie <<
872 pcie_intc1: interrupt-controll <<
873 interrupt-controller; <<
874 #address-cells = <0>; <<
875 #interrupt-cells = <1> 673 #interrupt-cells = <1>;
>> 674 ranges;
>> 675 status = "disabled";
>> 676
>> 677 num-lanes = <1>;
>> 678 interrupt-map-mask = <0 0 0 7>;
>> 679 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
>> 680 <0 0 0 2 &pcie_intc1 1>,
>> 681 <0 0 0 3 &pcie_intc1 2>,
>> 682 <0 0 0 4 &pcie_intc1 3>;
>> 683 pcie_intc1: interrupt-controller {
>> 684 interrupt-controller;
>> 685 #address-cells = <0>;
>> 686 #interrupt-cells = <1>;
>> 687 };
876 }; 688 };
877 }; 689 };
878 690
879 sata: sata@1a200000 { 691 sata: sata@1a200000 {
880 compatible = "mediatek,mt7622- 692 compatible = "mediatek,mt7622-ahci",
881 "mediatek,mtk-ahc 693 "mediatek,mtk-ahci";
882 reg = <0 0x1a200000 0 0x1100>; 694 reg = <0 0x1a200000 0 0x1100>;
883 interrupts = <GIC_SPI 233 IRQ_ 695 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "hostc"; 696 interrupt-names = "hostc";
885 clocks = <&pciesys CLK_SATA_AH 697 clocks = <&pciesys CLK_SATA_AHB_EN>,
886 <&pciesys CLK_SATA_AX 698 <&pciesys CLK_SATA_AXI_EN>,
887 <&pciesys CLK_SATA_AS 699 <&pciesys CLK_SATA_ASIC_EN>,
888 <&pciesys CLK_SATA_RB 700 <&pciesys CLK_SATA_RBC_EN>,
889 <&pciesys CLK_SATA_PM 701 <&pciesys CLK_SATA_PM_EN>;
890 clock-names = "ahb", "axi", "a 702 clock-names = "ahb", "axi", "asic", "rbc", "pm";
891 phys = <&sata_port PHY_TYPE_SA 703 phys = <&sata_port PHY_TYPE_SATA>;
892 phy-names = "sata-phy"; 704 phy-names = "sata-phy";
893 ports-implemented = <0x1>; 705 ports-implemented = <0x1>;
894 power-domains = <&scpsys MT762 706 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
895 resets = <&pciesys MT7622_SATA 707 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
896 <&pciesys MT7622_SATA 708 <&pciesys MT7622_SATA_PHY_SW_RST>,
897 <&pciesys MT7622_SATA 709 <&pciesys MT7622_SATA_PHY_REG_RST>;
898 reset-names = "axi", "sw", "re 710 reset-names = "axi", "sw", "reg";
899 mediatek,phy-mode = <&pciesys> 711 mediatek,phy-mode = <&pciesys>;
900 status = "disabled"; 712 status = "disabled";
901 }; 713 };
902 714
903 sata_phy: t-phy { !! 715 sata_phy: sata-phy@1a243000 {
904 compatible = "mediatek,mt7622- !! 716 compatible = "mediatek,generic-tphy-v1";
905 "mediatek,generic <<
906 #address-cells = <2>; 717 #address-cells = <2>;
907 #size-cells = <2>; 718 #size-cells = <2>;
908 ranges; 719 ranges;
909 status = "disabled"; 720 status = "disabled";
910 721
911 sata_port: sata-phy@1a243000 { 722 sata_port: sata-phy@1a243000 {
912 reg = <0 0x1a243000 0 723 reg = <0 0x1a243000 0 0x0100>;
913 clocks = <&topckgen CL 724 clocks = <&topckgen CLK_TOP_ETH_500M>;
914 clock-names = "ref"; 725 clock-names = "ref";
915 #phy-cells = <1>; 726 #phy-cells = <1>;
916 }; 727 };
917 }; 728 };
918 729
919 hifsys: clock-controller@1af00000 { !! 730 ethsys: syscon@1b000000 {
920 compatible = "mediatek,mt7622- <<
921 reg = <0 0x1af00000 0 0x70>; <<
922 #clock-cells = <1>; <<
923 }; <<
924 <<
925 ethsys: clock-controller@1b000000 { <<
926 compatible = "mediatek,mt7622- 731 compatible = "mediatek,mt7622-ethsys",
927 "syscon"; 732 "syscon";
928 reg = <0 0x1b000000 0 0x1000>; 733 reg = <0 0x1b000000 0 0x1000>;
929 #clock-cells = <1>; 734 #clock-cells = <1>;
930 #reset-cells = <1>; 735 #reset-cells = <1>;
931 }; 736 };
932 737
933 hsdma: dma-controller@1b007000 { <<
934 compatible = "mediatek,mt7622- <<
935 reg = <0 0x1b007000 0 0x1000>; <<
936 interrupts = <GIC_SPI 219 IRQ_ <<
937 clocks = <ðsys CLK_ETH_HSDM <<
938 clock-names = "hsdma"; <<
939 power-domains = <&scpsys MT762 <<
940 #dma-cells = <1>; <<
941 dma-requests = <3>; <<
942 }; <<
943 <<
944 pcie_mirror: pcie-mirror@10000400 { <<
945 compatible = "mediatek,mt7622- <<
946 "syscon"; <<
947 reg = <0 0x10000400 0 0x10>; <<
948 }; <<
949 <<
950 wed0: wed@1020a000 { <<
951 compatible = "mediatek,mt7622- <<
952 "syscon"; <<
953 reg = <0 0x1020a000 0 0x1000>; <<
954 interrupts = <GIC_SPI 214 IRQ_ <<
955 }; <<
956 <<
957 wed1: wed@1020b000 { <<
958 compatible = "mediatek,mt7622- <<
959 "syscon"; <<
960 reg = <0 0x1020b000 0 0x1000>; <<
961 interrupts = <GIC_SPI 215 IRQ_ <<
962 }; <<
963 <<
964 eth: ethernet@1b100000 { 738 eth: ethernet@1b100000 {
965 compatible = "mediatek,mt7622- !! 739 compatible = "mediatek,mt7622-eth",
>> 740 "mediatek,mt2701-eth",
>> 741 "syscon";
966 reg = <0 0x1b100000 0 0x20000> 742 reg = <0 0x1b100000 0 0x20000>;
967 interrupts = <GIC_SPI 223 IRQ_ 743 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
968 <GIC_SPI 224 IRQ_ 744 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
969 <GIC_SPI 225 IRQ_ 745 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
970 clocks = <&topckgen CLK_TOP_ET 746 clocks = <&topckgen CLK_TOP_ETH_SEL>,
971 <ðsys CLK_ETH_ESW_ 747 <ðsys CLK_ETH_ESW_EN>,
972 <ðsys CLK_ETH_GP0_ 748 <ðsys CLK_ETH_GP0_EN>,
973 <ðsys CLK_ETH_GP1_ 749 <ðsys CLK_ETH_GP1_EN>,
974 <ðsys CLK_ETH_GP2_ 750 <ðsys CLK_ETH_GP2_EN>,
975 <&sgmiisys CLK_SGMII_ 751 <&sgmiisys CLK_SGMII_TX250M_EN>,
976 <&sgmiisys CLK_SGMII_ 752 <&sgmiisys CLK_SGMII_RX250M_EN>,
977 <&sgmiisys CLK_SGMII_ 753 <&sgmiisys CLK_SGMII_CDR_REF>,
978 <&sgmiisys CLK_SGMII_ 754 <&sgmiisys CLK_SGMII_CDR_FB>,
979 <&topckgen CLK_TOP_SG 755 <&topckgen CLK_TOP_SGMIIPLL>,
980 <&apmixedsys CLK_APMI 756 <&apmixedsys CLK_APMIXED_ETH2PLL>;
981 clock-names = "ethif", "esw", 757 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
982 "sgmii_tx250m", 758 "sgmii_tx250m", "sgmii_rx250m",
983 "sgmii_cdr_ref", 759 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
984 "eth2pll"; 760 "eth2pll";
985 power-domains = <&scpsys MT762 761 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
986 mediatek,ethsys = <ðsys>; 762 mediatek,ethsys = <ðsys>;
987 mediatek,sgmiisys = <&sgmiisys 763 mediatek,sgmiisys = <&sgmiisys>;
988 cci-control-port = <&cci_contr <<
989 mediatek,wed = <&wed0>, <&wed1 <<
990 mediatek,pcie-mirror = <&pcie_ <<
991 mediatek,hifsys = <&hifsys>; <<
992 dma-coherent; <<
993 #address-cells = <1>; 764 #address-cells = <1>;
994 #size-cells = <0>; 765 #size-cells = <0>;
995 status = "disabled"; 766 status = "disabled";
996 }; 767 };
997 768
998 sgmiisys: sgmiisys@1b128000 { 769 sgmiisys: sgmiisys@1b128000 {
999 compatible = "mediatek,mt7622- 770 compatible = "mediatek,mt7622-sgmiisys",
1000 "syscon"; 771 "syscon";
1001 reg = <0 0x1b128000 0 0x3000> !! 772 reg = <0 0x1b128000 0 0x1000>;
1002 #clock-cells = <1>; 773 #clock-cells = <1>;
1003 }; 774 };
1004 }; 775 };
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