1 /* 1 /*
2 * Copyright (c) 2017 MediaTek Inc. 2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com> 3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com>
5 * 5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h> 11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h> 13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h> 14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 compatible = "mediatek,mt7622"; 18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>; 19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 cpu_opp_table: opp-table { 23 cpu_opp_table: opp-table {
24 compatible = "operating-points 24 compatible = "operating-points-v2";
25 opp-shared; 25 opp-shared;
26 opp-300000000 { 26 opp-300000000 {
27 opp-hz = /bits/ 64 <30 27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <95000 28 opp-microvolt = <950000>;
29 }; 29 };
30 30
31 opp-437500000 { 31 opp-437500000 {
32 opp-hz = /bits/ 64 <43 32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <10000 33 opp-microvolt = <1000000>;
34 }; 34 };
35 35
36 opp-600000000 { 36 opp-600000000 {
37 opp-hz = /bits/ 64 <60 37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <10500 38 opp-microvolt = <1050000>;
39 }; 39 };
40 40
41 opp-812500000 { 41 opp-812500000 {
42 opp-hz = /bits/ 64 <81 42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <11000 43 opp-microvolt = <1100000>;
44 }; 44 };
45 45
46 opp-1025000000 { 46 opp-1025000000 {
47 opp-hz = /bits/ 64 <10 47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <11500 48 opp-microvolt = <1150000>;
49 }; 49 };
50 50
51 opp-1137500000 { 51 opp-1137500000 {
52 opp-hz = /bits/ 64 <11 52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <12000 53 opp-microvolt = <1200000>;
54 }; 54 };
55 55
56 opp-1262500000 { 56 opp-1262500000 {
57 opp-hz = /bits/ 64 <12 57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <12500 58 opp-microvolt = <1250000>;
59 }; 59 };
60 60
61 opp-1350000000 { 61 opp-1350000000 {
62 opp-hz = /bits/ 64 <13 62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <13100 63 opp-microvolt = <1310000>;
64 }; 64 };
65 }; 65 };
66 66
67 cpus { 67 cpus {
68 #address-cells = <2>; 68 #address-cells = <2>;
69 #size-cells = <0>; 69 #size-cells = <0>;
70 70
71 cpu0: cpu@0 { 71 cpu0: cpu@0 {
72 device_type = "cpu"; 72 device_type = "cpu";
73 compatible = "arm,cort !! 73 compatible = "arm,cortex-a53", "arm,armv8";
74 reg = <0x0 0x0>; 74 reg = <0x0 0x0>;
75 clocks = <&infracfg CL 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", " 77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = 78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 enable-method = "psci" 80 enable-method = "psci";
81 clock-frequency = <130 81 clock-frequency = <1300000000>;
82 cci-control-port = <&c <<
83 next-level-cache = <&L <<
84 }; 82 };
85 83
86 cpu1: cpu@1 { 84 cpu1: cpu@1 {
87 device_type = "cpu"; 85 device_type = "cpu";
88 compatible = "arm,cort !! 86 compatible = "arm,cortex-a53", "arm,armv8";
89 reg = <0x0 0x1>; 87 reg = <0x0 0x1>;
90 clocks = <&infracfg CL 88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys 89 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", " 90 clock-names = "cpu", "intermediate";
93 operating-points-v2 = 91 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; 92 #cooling-cells = <2>;
95 enable-method = "psci" 93 enable-method = "psci";
96 clock-frequency = <130 94 clock-frequency = <1300000000>;
97 cci-control-port = <&c <<
98 next-level-cache = <&L <<
99 }; <<
100 <<
101 L2: l2-cache { <<
102 compatible = "cache"; <<
103 cache-level = <2>; <<
104 cache-unified; <<
105 }; 95 };
106 }; 96 };
107 97
108 pwrap_clk: dummy40m { 98 pwrap_clk: dummy40m {
109 compatible = "fixed-clock"; 99 compatible = "fixed-clock";
110 clock-frequency = <40000000>; 100 clock-frequency = <40000000>;
111 #clock-cells = <0>; 101 #clock-cells = <0>;
112 }; 102 };
113 103
114 clk25m: oscillator { 104 clk25m: oscillator {
115 compatible = "fixed-clock"; 105 compatible = "fixed-clock";
116 #clock-cells = <0>; 106 #clock-cells = <0>;
117 clock-frequency = <25000000>; 107 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal" 108 clock-output-names = "clkxtal";
119 }; 109 };
120 110
121 psci { 111 psci {
122 compatible = "arm,psci-0.2"; !! 112 compatible = "arm,psci-0.2";
123 method = "smc"; !! 113 method = "smc";
124 }; <<
125 <<
126 pmu { <<
127 compatible = "arm,cortex-a53-p <<
128 interrupts = <GIC_SPI 8 IRQ_TY <<
129 <GIC_SPI 9 IRQ_TY <<
130 interrupt-affinity = <&cpu0>, <<
131 }; 114 };
132 115
133 reserved-memory { 116 reserved-memory {
134 #address-cells = <2>; 117 #address-cells = <2>;
135 #size-cells = <2>; 118 #size-cells = <2>;
136 ranges; 119 ranges;
137 120
138 /* 192 KiB reserved for ARM Tr 121 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
139 secmon_reserved: secmon@430000 122 secmon_reserved: secmon@43000000 {
140 reg = <0 0x43000000 0 123 reg = <0 0x43000000 0 0x30000>;
141 no-map; 124 no-map;
142 }; 125 };
143 }; 126 };
144 127
145 thermal-zones { 128 thermal-zones {
146 cpu_thermal: cpu-thermal { 129 cpu_thermal: cpu-thermal {
147 polling-delay-passive 130 polling-delay-passive = <1000>;
148 polling-delay = <1000> 131 polling-delay = <1000>;
149 132
150 thermal-sensors = <&th 133 thermal-sensors = <&thermal 0>;
151 134
152 trips { 135 trips {
153 cpu_passive: c 136 cpu_passive: cpu-passive {
154 temper 137 temperature = <47000>;
155 hyster 138 hysteresis = <2000>;
156 type = 139 type = "passive";
157 }; 140 };
158 141
159 cpu_active: cp 142 cpu_active: cpu-active {
160 temper 143 temperature = <67000>;
161 hyster 144 hysteresis = <2000>;
162 type = 145 type = "active";
163 }; 146 };
164 147
165 cpu_hot: cpu-h 148 cpu_hot: cpu-hot {
166 temper 149 temperature = <87000>;
167 hyster 150 hysteresis = <2000>;
168 type = 151 type = "hot";
169 }; 152 };
170 153
171 cpu-crit { 154 cpu-crit {
172 temper 155 temperature = <107000>;
173 hyster 156 hysteresis = <2000>;
174 type = 157 type = "critical";
175 }; 158 };
176 }; 159 };
177 160
178 cooling-maps { 161 cooling-maps {
179 map0 { 162 map0 {
180 trip = 163 trip = <&cpu_passive>;
181 coolin !! 164 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 <<
183 }; 165 };
184 166
185 map1 { 167 map1 {
186 trip = 168 trip = <&cpu_active>;
187 coolin !! 169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
188 <<
189 }; 170 };
190 171
191 map2 { 172 map2 {
192 trip = 173 trip = <&cpu_hot>;
193 coolin !! 174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 <<
195 }; 175 };
196 }; 176 };
197 }; 177 };
198 }; 178 };
199 179
200 timer { 180 timer {
201 compatible = "arm,armv8-timer" 181 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>; 182 interrupt-parent = <&gic>;
203 interrupts = <GIC_PPI 13 (GIC_ 183 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_LEVEL_H 184 IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_ 185 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_LEVEL_H 186 IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 (GIC_ 187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_LEVEL_H 188 IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 (GIC_ 189 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_LEVEL_H 190 IRQ_TYPE_LEVEL_HIGH)>;
211 }; 191 };
212 192
213 infracfg: infracfg@10000000 { 193 infracfg: infracfg@10000000 {
214 compatible = "mediatek,mt7622- 194 compatible = "mediatek,mt7622-infracfg",
215 "syscon"; 195 "syscon";
216 reg = <0 0x10000000 0 0x1000>; 196 reg = <0 0x10000000 0 0x1000>;
217 #clock-cells = <1>; 197 #clock-cells = <1>;
218 #reset-cells = <1>; 198 #reset-cells = <1>;
219 }; 199 };
220 200
221 pwrap: pwrap@10001000 { 201 pwrap: pwrap@10001000 {
222 compatible = "mediatek,mt7622- 202 compatible = "mediatek,mt7622-pwrap";
223 reg = <0 0x10001000 0 0x250>; 203 reg = <0 0x10001000 0 0x250>;
224 reg-names = "pwrap"; 204 reg-names = "pwrap";
225 clocks = <&infracfg CLK_INFRA_ 205 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
226 clock-names = "spi", "wrap"; 206 clock-names = "spi", "wrap";
227 resets = <&infracfg MT7622_INF 207 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
228 reset-names = "pwrap"; 208 reset-names = "pwrap";
229 interrupts = <GIC_SPI 163 IRQ_ 209 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
230 status = "disabled"; 210 status = "disabled";
231 }; 211 };
232 212
233 pericfg: pericfg@10002000 { 213 pericfg: pericfg@10002000 {
234 compatible = "mediatek,mt7622- 214 compatible = "mediatek,mt7622-pericfg",
235 "syscon"; 215 "syscon";
236 reg = <0 0x10002000 0 0x1000>; 216 reg = <0 0x10002000 0 0x1000>;
237 #clock-cells = <1>; 217 #clock-cells = <1>;
238 #reset-cells = <1>; 218 #reset-cells = <1>;
239 }; 219 };
240 220
241 scpsys: power-controller@10006000 { !! 221 scpsys: scpsys@10006000 {
242 compatible = "mediatek,mt7622- 222 compatible = "mediatek,mt7622-scpsys",
243 "syscon"; 223 "syscon";
244 #power-domain-cells = <1>; 224 #power-domain-cells = <1>;
245 reg = <0 0x10006000 0 0x1000>; 225 reg = <0 0x10006000 0 0x1000>;
246 interrupts = <GIC_SPI 165 IRQ_ 226 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 166 IRQ_ 227 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 167 IRQ_ 228 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
249 <GIC_SPI 168 IRQ_ 229 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
250 infracfg = <&infracfg>; 230 infracfg = <&infracfg>;
251 clocks = <&topckgen CLK_TOP_HI 231 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 clock-names = "hif_sel"; 232 clock-names = "hif_sel";
253 }; 233 };
254 234
255 cir: ir-receiver@10009000 { 235 cir: ir-receiver@10009000 {
256 compatible = "mediatek,mt7622- 236 compatible = "mediatek,mt7622-cir";
257 reg = <0 0x10009000 0 0x1000>; 237 reg = <0 0x10009000 0 0x1000>;
258 interrupts = <GIC_SPI 175 IRQ_ 238 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
259 clocks = <&infracfg CLK_INFRA_ 239 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
260 <&topckgen CLK_TOP_AX 240 <&topckgen CLK_TOP_AXI_SEL>;
261 clock-names = "clk", "bus"; 241 clock-names = "clk", "bus";
262 status = "disabled"; 242 status = "disabled";
263 }; 243 };
264 244
265 sysirq: interrupt-controller@10200620 245 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622- 246 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577- 247 "mediatek,mt6577-sysirq";
268 interrupt-controller; 248 interrupt-controller;
269 #interrupt-cells = <3>; 249 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>; 250 interrupt-parent = <&gic>;
271 reg = <0 0x10200620 0 0x20>; 251 reg = <0 0x10200620 0 0x20>;
272 }; 252 };
273 253
274 efuse: efuse@10206000 { 254 efuse: efuse@10206000 {
275 compatible = "mediatek,mt7622- 255 compatible = "mediatek,mt7622-efuse",
276 "mediatek,efuse"; 256 "mediatek,efuse";
277 reg = <0 0x10206000 0 0x1000>; 257 reg = <0 0x10206000 0 0x1000>;
278 #address-cells = <1>; 258 #address-cells = <1>;
279 #size-cells = <1>; 259 #size-cells = <1>;
280 260
281 thermal_calibration: calib@198 261 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>; 262 reg = <0x198 0xc>;
283 }; 263 };
284 }; 264 };
285 265
286 apmixedsys: clock-controller@10209000 !! 266 apmixedsys: apmixedsys@10209000 {
287 compatible = "mediatek,mt7622- !! 267 compatible = "mediatek,mt7622-apmixedsys",
>> 268 "syscon";
288 reg = <0 0x10209000 0 0x1000>; 269 reg = <0 0x10209000 0 0x1000>;
289 #clock-cells = <1>; 270 #clock-cells = <1>;
290 }; 271 };
291 272
292 topckgen: clock-controller@10210000 { !! 273 topckgen: topckgen@10210000 {
293 compatible = "mediatek,mt7622- !! 274 compatible = "mediatek,mt7622-topckgen",
>> 275 "syscon";
294 reg = <0 0x10210000 0 0x1000>; 276 reg = <0 0x10210000 0 0x1000>;
295 #clock-cells = <1>; 277 #clock-cells = <1>;
296 }; 278 };
297 279
298 rng: rng@1020f000 { 280 rng: rng@1020f000 {
299 compatible = "mediatek,mt7622- 281 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623- 282 "mediatek,mt7623-rng";
301 reg = <0 0x1020f000 0 0x1000>; 283 reg = <0 0x1020f000 0 0x1000>;
302 clocks = <&infracfg CLK_INFRA_ 284 clocks = <&infracfg CLK_INFRA_TRNG>;
303 clock-names = "rng"; 285 clock-names = "rng";
304 }; 286 };
305 287
306 pio: pinctrl@10211000 { 288 pio: pinctrl@10211000 {
307 compatible = "mediatek,mt7622- 289 compatible = "mediatek,mt7622-pinctrl";
308 reg = <0 0x10211000 0 0x1000>, 290 reg = <0 0x10211000 0 0x1000>,
309 <0 0x10005000 0 0x1000>; 291 <0 0x10005000 0 0x1000>;
310 reg-names = "base", "eint"; 292 reg-names = "base", "eint";
311 gpio-controller; 293 gpio-controller;
312 #gpio-cells = <2>; 294 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 103>; 295 gpio-ranges = <&pio 0 0 103>;
314 interrupt-controller; 296 interrupt-controller;
315 interrupts = <GIC_SPI 153 IRQ_ 297 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-parent = <&gic>; 298 interrupt-parent = <&gic>;
317 #interrupt-cells = <2>; 299 #interrupt-cells = <2>;
318 }; 300 };
319 301
320 watchdog: watchdog@10212000 { 302 watchdog: watchdog@10212000 {
321 compatible = "mediatek,mt7622- 303 compatible = "mediatek,mt7622-wdt",
322 "mediatek,mt6589- 304 "mediatek,mt6589-wdt";
323 reg = <0 0x10212000 0 0x800>; 305 reg = <0 0x10212000 0 0x800>;
324 }; 306 };
325 307
326 rtc: rtc@10212800 { 308 rtc: rtc@10212800 {
327 compatible = "mediatek,mt7622- 309 compatible = "mediatek,mt7622-rtc",
328 "mediatek,soc-rtc 310 "mediatek,soc-rtc";
329 reg = <0 0x10212800 0 0x200>; 311 reg = <0 0x10212800 0 0x200>;
330 interrupts = <GIC_SPI 129 IRQ_ 312 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
331 clocks = <&topckgen CLK_TOP_RT 313 clocks = <&topckgen CLK_TOP_RTC>;
332 clock-names = "rtc"; 314 clock-names = "rtc";
333 }; 315 };
334 316
335 gic: interrupt-controller@10300000 { 317 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400"; 318 compatible = "arm,gic-400";
337 interrupt-controller; 319 interrupt-controller;
338 #interrupt-cells = <3>; 320 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>; 321 interrupt-parent = <&gic>;
340 reg = <0 0x10310000 0 0x1000>, 322 reg = <0 0x10310000 0 0x1000>,
341 <0 0x10320000 0 0x1000>, 323 <0 0x10320000 0 0x1000>,
342 <0 0x10340000 0 0x2000>, 324 <0 0x10340000 0 0x2000>,
343 <0 0x10360000 0 0x2000>; 325 <0 0x10360000 0 0x2000>;
344 }; 326 };
345 327
346 cci: cci@10390000 { <<
347 compatible = "arm,cci-400"; <<
348 #address-cells = <1>; <<
349 #size-cells = <1>; <<
350 reg = <0 0x10390000 0 0x1000>; <<
351 ranges = <0 0 0x10390000 0x100 <<
352 <<
353 cci_control0: slave-if@1000 { <<
354 compatible = "arm,cci- <<
355 interface-type = "ace- <<
356 reg = <0x1000 0x1000>; <<
357 }; <<
358 <<
359 cci_control1: slave-if@4000 { <<
360 compatible = "arm,cci- <<
361 interface-type = "ace" <<
362 reg = <0x4000 0x1000>; <<
363 }; <<
364 <<
365 cci_control2: slave-if@5000 { <<
366 compatible = "arm,cci- <<
367 interface-type = "ace" <<
368 reg = <0x5000 0x1000>; <<
369 }; <<
370 <<
371 pmu@9000 { <<
372 compatible = "arm,cci- <<
373 reg = <0x9000 0x5000>; <<
374 interrupts = <GIC_SPI <<
375 <GIC_SPI <<
376 <GIC_SPI <<
377 <GIC_SPI <<
378 <GIC_SPI <<
379 }; <<
380 }; <<
381 <<
382 auxadc: adc@11001000 { 328 auxadc: adc@11001000 {
383 compatible = "mediatek,mt7622- 329 compatible = "mediatek,mt7622-auxadc";
384 reg = <0 0x11001000 0 0x1000>; 330 reg = <0 0x11001000 0 0x1000>;
385 clocks = <&pericfg CLK_PERI_AU 331 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
386 clock-names = "main"; 332 clock-names = "main";
387 #io-channel-cells = <1>; 333 #io-channel-cells = <1>;
388 }; 334 };
389 335
390 uart0: serial@11002000 { 336 uart0: serial@11002000 {
391 compatible = "mediatek,mt7622- 337 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577- 338 "mediatek,mt6577-uart";
393 reg = <0 0x11002000 0 0x400>; 339 reg = <0 0x11002000 0 0x400>;
394 interrupts = <GIC_SPI 91 IRQ_T 340 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&topckgen CLK_TOP_UA 341 clocks = <&topckgen CLK_TOP_UART_SEL>,
396 <&pericfg CLK_PERI_UA 342 <&pericfg CLK_PERI_UART0_PD>;
397 clock-names = "baud", "bus"; 343 clock-names = "baud", "bus";
398 status = "disabled"; 344 status = "disabled";
399 }; 345 };
400 346
401 uart1: serial@11003000 { 347 uart1: serial@11003000 {
402 compatible = "mediatek,mt7622- 348 compatible = "mediatek,mt7622-uart",
403 "mediatek,mt6577- 349 "mediatek,mt6577-uart";
404 reg = <0 0x11003000 0 0x400>; 350 reg = <0 0x11003000 0 0x400>;
405 interrupts = <GIC_SPI 92 IRQ_T 351 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
406 clocks = <&topckgen CLK_TOP_UA 352 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 <&pericfg CLK_PERI_UA 353 <&pericfg CLK_PERI_UART1_PD>;
408 clock-names = "baud", "bus"; 354 clock-names = "baud", "bus";
409 status = "disabled"; 355 status = "disabled";
410 }; 356 };
411 357
412 uart2: serial@11004000 { 358 uart2: serial@11004000 {
413 compatible = "mediatek,mt7622- 359 compatible = "mediatek,mt7622-uart",
414 "mediatek,mt6577- 360 "mediatek,mt6577-uart";
415 reg = <0 0x11004000 0 0x400>; 361 reg = <0 0x11004000 0 0x400>;
416 interrupts = <GIC_SPI 93 IRQ_T 362 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&topckgen CLK_TOP_UA 363 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 <&pericfg CLK_PERI_UA 364 <&pericfg CLK_PERI_UART2_PD>;
419 clock-names = "baud", "bus"; 365 clock-names = "baud", "bus";
420 status = "disabled"; 366 status = "disabled";
421 }; 367 };
422 368
423 uart3: serial@11005000 { 369 uart3: serial@11005000 {
424 compatible = "mediatek,mt7622- 370 compatible = "mediatek,mt7622-uart",
425 "mediatek,mt6577- 371 "mediatek,mt6577-uart";
426 reg = <0 0x11005000 0 0x400>; 372 reg = <0 0x11005000 0 0x400>;
427 interrupts = <GIC_SPI 94 IRQ_T 373 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
428 clocks = <&topckgen CLK_TOP_UA 374 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 <&pericfg CLK_PERI_UA 375 <&pericfg CLK_PERI_UART3_PD>;
430 clock-names = "baud", "bus"; 376 clock-names = "baud", "bus";
431 status = "disabled"; 377 status = "disabled";
432 }; 378 };
433 379
434 pwm: pwm@11006000 { 380 pwm: pwm@11006000 {
435 compatible = "mediatek,mt7622- 381 compatible = "mediatek,mt7622-pwm";
436 reg = <0 0x11006000 0 0x1000>; 382 reg = <0 0x11006000 0 0x1000>;
437 #pwm-cells = <2>; 383 #pwm-cells = <2>;
438 interrupts = <GIC_SPI 77 IRQ_T 384 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_PW 385 clocks = <&topckgen CLK_TOP_PWM_SEL>,
440 <&pericfg CLK_PERI_PW 386 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PW 387 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PW 388 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PW 389 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PW 390 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PW 391 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PW 392 <&pericfg CLK_PERI_PWM6_PD>;
447 clock-names = "top", "main", " 393 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
448 "pwm5", "pwm6"; 394 "pwm5", "pwm6";
449 status = "disabled"; 395 status = "disabled";
450 }; 396 };
451 397
452 i2c0: i2c@11007000 { 398 i2c0: i2c@11007000 {
453 compatible = "mediatek,mt7622- 399 compatible = "mediatek,mt7622-i2c";
454 reg = <0 0x11007000 0 0x90>, 400 reg = <0 0x11007000 0 0x90>,
455 <0 0x11000100 0 0x80>; 401 <0 0x11000100 0 0x80>;
456 interrupts = <GIC_SPI 84 IRQ_T 402 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>; 403 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2 404 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP 405 <&pericfg CLK_PERI_AP_DMA_PD>;
460 clock-names = "main", "dma"; 406 clock-names = "main", "dma";
461 #address-cells = <1>; 407 #address-cells = <1>;
462 #size-cells = <0>; 408 #size-cells = <0>;
463 status = "disabled"; 409 status = "disabled";
464 }; 410 };
465 411
466 i2c1: i2c@11008000 { 412 i2c1: i2c@11008000 {
467 compatible = "mediatek,mt7622- 413 compatible = "mediatek,mt7622-i2c";
468 reg = <0 0x11008000 0 0x90>, 414 reg = <0 0x11008000 0 0x90>,
469 <0 0x11000180 0 0x80>; 415 <0 0x11000180 0 0x80>;
470 interrupts = <GIC_SPI 85 IRQ_T 416 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
471 clock-div = <16>; 417 clock-div = <16>;
472 clocks = <&pericfg CLK_PERI_I2 418 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP 419 <&pericfg CLK_PERI_AP_DMA_PD>;
474 clock-names = "main", "dma"; 420 clock-names = "main", "dma";
475 #address-cells = <1>; 421 #address-cells = <1>;
476 #size-cells = <0>; 422 #size-cells = <0>;
477 status = "disabled"; 423 status = "disabled";
478 }; 424 };
479 425
480 i2c2: i2c@11009000 { 426 i2c2: i2c@11009000 {
481 compatible = "mediatek,mt7622- 427 compatible = "mediatek,mt7622-i2c";
482 reg = <0 0x11009000 0 0x90>, 428 reg = <0 0x11009000 0 0x90>,
483 <0 0x11000200 0 0x80>; 429 <0 0x11000200 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_T 430 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
485 clock-div = <16>; 431 clock-div = <16>;
486 clocks = <&pericfg CLK_PERI_I2 432 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP 433 <&pericfg CLK_PERI_AP_DMA_PD>;
488 clock-names = "main", "dma"; 434 clock-names = "main", "dma";
489 #address-cells = <1>; 435 #address-cells = <1>;
490 #size-cells = <0>; 436 #size-cells = <0>;
491 status = "disabled"; 437 status = "disabled";
492 }; 438 };
493 439
494 spi0: spi@1100a000 { 440 spi0: spi@1100a000 {
495 compatible = "mediatek,mt7622- 441 compatible = "mediatek,mt7622-spi";
496 reg = <0 0x1100a000 0 0x100>; 442 reg = <0 0x1100a000 0 0x100>;
497 interrupts = <GIC_SPI 118 IRQ_ 443 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&topckgen CLK_TOP_SY 444 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SP 445 <&topckgen CLK_TOP_SPI0_SEL>,
500 <&pericfg CLK_PERI_SP 446 <&pericfg CLK_PERI_SPI0_PD>;
501 clock-names = "parent-clk", "s 447 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>; 448 #address-cells = <1>;
503 #size-cells = <0>; 449 #size-cells = <0>;
504 status = "disabled"; 450 status = "disabled";
505 }; 451 };
506 452
507 thermal: thermal@1100b000 { 453 thermal: thermal@1100b000 {
508 #thermal-sensor-cells = <1>; 454 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622- 455 compatible = "mediatek,mt7622-thermal";
510 reg = <0 0x1100b000 0 0x1000>; 456 reg = <0 0x1100b000 0 0x1000>;
511 interrupts = <0 78 IRQ_TYPE_LE 457 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_TH 458 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AU 459 <&pericfg CLK_PERI_AUXADC_PD>;
514 clock-names = "therm", "auxadc 460 clock-names = "therm", "auxadc";
515 resets = <&pericfg MT7622_PERI 461 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
516 mediatek,auxadc = <&auxadc>; 462 mediatek,auxadc = <&auxadc>;
517 mediatek,apmixedsys = <&apmixe 463 mediatek,apmixedsys = <&apmixedsys>;
518 nvmem-cells = <&thermal_calibr 464 nvmem-cells = <&thermal_calibration>;
519 nvmem-cell-names = "calibratio 465 nvmem-cell-names = "calibration-data";
520 }; 466 };
521 467
522 btif: serial@1100c000 { 468 btif: serial@1100c000 {
523 compatible = "mediatek,mt7622- 469 compatible = "mediatek,mt7622-btif",
524 "mediatek,mtk-bti 470 "mediatek,mtk-btif";
525 reg = <0 0x1100c000 0 0x1000>; 471 reg = <0 0x1100c000 0 0x1000>;
526 interrupts = <GIC_SPI 90 IRQ_T 472 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&pericfg CLK_PERI_BT 473 clocks = <&pericfg CLK_PERI_BTIF_PD>;
>> 474 clock-names = "main";
528 reg-shift = <2>; 475 reg-shift = <2>;
529 reg-io-width = <4>; 476 reg-io-width = <4>;
530 status = "disabled"; 477 status = "disabled";
531 <<
532 bluetooth { <<
533 compatible = "mediatek <<
534 power-domains = <&scps <<
535 clocks = <&clk25m>; <<
536 clock-names = "ref"; <<
537 }; <<
538 }; 478 };
539 479
540 nandc: nand-controller@1100d000 { !! 480 nandc: nfi@1100d000 {
541 compatible = "mediatek,mt7622- 481 compatible = "mediatek,mt7622-nfc";
542 reg = <0 0x1100D000 0 0x1000>; 482 reg = <0 0x1100D000 0 0x1000>;
543 interrupts = <GIC_SPI 96 IRQ_T 483 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_NF 484 clocks = <&pericfg CLK_PERI_NFI_PD>,
545 <&pericfg CLK_PERI_SN 485 <&pericfg CLK_PERI_SNFI_PD>;
546 clock-names = "nfi_clk", "pad_ 486 clock-names = "nfi_clk", "pad_clk";
547 ecc-engine = <&bch>; 487 ecc-engine = <&bch>;
548 #address-cells = <1>; 488 #address-cells = <1>;
549 #size-cells = <0>; 489 #size-cells = <0>;
550 status = "disabled"; 490 status = "disabled";
551 }; 491 };
552 492
553 snfi: spi@1100d000 { <<
554 compatible = "mediatek,mt7622- <<
555 reg = <0 0x1100d000 0 0x1000>; <<
556 interrupts = <GIC_SPI 96 IRQ_T <<
557 clocks = <&pericfg CLK_PERI_NF <<
558 clock-names = "nfi_clk", "pad_ <<
559 nand-ecc-engine = <&bch>; <<
560 #address-cells = <1>; <<
561 #size-cells = <0>; <<
562 status = "disabled"; <<
563 }; <<
564 <<
565 bch: ecc@1100e000 { 493 bch: ecc@1100e000 {
566 compatible = "mediatek,mt7622- 494 compatible = "mediatek,mt7622-ecc";
567 reg = <0 0x1100e000 0 0x1000>; 495 reg = <0 0x1100e000 0 0x1000>;
568 interrupts = <GIC_SPI 95 IRQ_T 496 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
569 clocks = <&pericfg CLK_PERI_NF 497 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
570 clock-names = "nfiecc_clk"; 498 clock-names = "nfiecc_clk";
571 status = "disabled"; 499 status = "disabled";
572 }; 500 };
573 501
574 nor_flash: spi@11014000 { 502 nor_flash: spi@11014000 {
575 compatible = "mediatek,mt7622- 503 compatible = "mediatek,mt7622-nor",
576 "mediatek,mt8173- 504 "mediatek,mt8173-nor";
577 reg = <0 0x11014000 0 0xe0>; 505 reg = <0 0x11014000 0 0xe0>;
578 clocks = <&pericfg CLK_PERI_FL 506 clocks = <&pericfg CLK_PERI_FLASH_PD>,
579 <&topckgen CLK_TOP_FL 507 <&topckgen CLK_TOP_FLASH_SEL>;
580 clock-names = "spi", "sf"; 508 clock-names = "spi", "sf";
581 #address-cells = <1>; 509 #address-cells = <1>;
582 #size-cells = <0>; 510 #size-cells = <0>;
583 status = "disabled"; 511 status = "disabled";
584 }; 512 };
585 513
586 spi1: spi@11016000 { 514 spi1: spi@11016000 {
587 compatible = "mediatek,mt7622- 515 compatible = "mediatek,mt7622-spi";
588 reg = <0 0x11016000 0 0x100>; 516 reg = <0 0x11016000 0 0x100>;
589 interrupts = <GIC_SPI 122 IRQ_ 517 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&topckgen CLK_TOP_SY 518 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SP 519 <&topckgen CLK_TOP_SPI1_SEL>,
592 <&pericfg CLK_PERI_SP 520 <&pericfg CLK_PERI_SPI1_PD>;
593 clock-names = "parent-clk", "s 521 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 #address-cells = <1>; 522 #address-cells = <1>;
595 #size-cells = <0>; 523 #size-cells = <0>;
596 status = "disabled"; 524 status = "disabled";
597 }; 525 };
598 526
599 uart4: serial@11019000 { 527 uart4: serial@11019000 {
600 compatible = "mediatek,mt7622- 528 compatible = "mediatek,mt7622-uart",
601 "mediatek,mt6577- 529 "mediatek,mt6577-uart";
602 reg = <0 0x11019000 0 0x400>; 530 reg = <0 0x11019000 0 0x400>;
603 interrupts = <GIC_SPI 89 IRQ_T 531 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CLK_TOP_UA 532 clocks = <&topckgen CLK_TOP_UART_SEL>,
605 <&pericfg CLK_PERI_UA 533 <&pericfg CLK_PERI_UART4_PD>;
606 clock-names = "baud", "bus"; 534 clock-names = "baud", "bus";
607 status = "disabled"; 535 status = "disabled";
608 }; 536 };
609 537
610 audsys: clock-controller@11220000 { 538 audsys: clock-controller@11220000 {
611 compatible = "mediatek,mt7622- 539 compatible = "mediatek,mt7622-audsys", "syscon";
612 reg = <0 0x11220000 0 0x2000>; 540 reg = <0 0x11220000 0 0x2000>;
613 #clock-cells = <1>; 541 #clock-cells = <1>;
614 542
615 afe: audio-controller { 543 afe: audio-controller {
616 compatible = "mediatek 544 compatible = "mediatek,mt7622-audio";
617 interrupts = <GIC_SPI !! 545 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
618 <GIC_SPI !! 546 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
619 interrupt-names = "afe !! 547 interrupt-names = "afe", "asys";
620 548
621 clocks = <&infracfg CL 549 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
622 <&topckgen CL 550 <&topckgen CLK_TOP_AUD1_SEL>,
623 <&topckgen CL 551 <&topckgen CLK_TOP_AUD2_SEL>,
624 <&topckgen CL 552 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
625 <&topckgen CL 553 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
626 <&topckgen CL 554 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
627 <&topckgen CL 555 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
628 <&topckgen CL 556 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
629 <&topckgen CL 557 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
630 <&topckgen CL 558 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
631 <&topckgen CL 559 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
632 <&topckgen CL 560 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
633 <&topckgen CL 561 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
634 <&topckgen CL 562 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
635 <&topckgen CL 563 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
636 <&topckgen CL 564 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
637 <&topckgen CL 565 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
638 <&audsys CLK_ 566 <&audsys CLK_AUDIO_I2SO1>,
639 <&audsys CLK_ 567 <&audsys CLK_AUDIO_I2SO2>,
640 <&audsys CLK_ 568 <&audsys CLK_AUDIO_I2SO3>,
641 <&audsys CLK_ 569 <&audsys CLK_AUDIO_I2SO4>,
642 <&audsys CLK_ 570 <&audsys CLK_AUDIO_I2SIN1>,
643 <&audsys CLK_ 571 <&audsys CLK_AUDIO_I2SIN2>,
644 <&audsys CLK_ 572 <&audsys CLK_AUDIO_I2SIN3>,
645 <&audsys CLK_ 573 <&audsys CLK_AUDIO_I2SIN4>,
646 <&audsys CLK_ 574 <&audsys CLK_AUDIO_ASRCO1>,
647 <&audsys CLK_ 575 <&audsys CLK_AUDIO_ASRCO2>,
648 <&audsys CLK_ 576 <&audsys CLK_AUDIO_ASRCO3>,
649 <&audsys CLK_ 577 <&audsys CLK_AUDIO_ASRCO4>,
650 <&audsys CLK_ 578 <&audsys CLK_AUDIO_AFE>,
651 <&audsys CLK_ 579 <&audsys CLK_AUDIO_AFE_CONN>,
652 <&audsys CLK_ 580 <&audsys CLK_AUDIO_A1SYS>,
653 <&audsys CLK_ 581 <&audsys CLK_AUDIO_A2SYS>;
654 582
655 clock-names = "infra_s 583 clock-names = "infra_sys_audio_clk",
656 "top_aud 584 "top_audio_mux1_sel",
657 "top_aud 585 "top_audio_mux2_sel",
658 "top_aud 586 "top_audio_a1sys_hp",
659 "top_aud 587 "top_audio_a2sys_hp",
660 "i2s0_sr 588 "i2s0_src_sel",
661 "i2s1_sr 589 "i2s1_src_sel",
662 "i2s2_sr 590 "i2s2_src_sel",
663 "i2s3_sr 591 "i2s3_src_sel",
664 "i2s0_sr 592 "i2s0_src_div",
665 "i2s1_sr 593 "i2s1_src_div",
666 "i2s2_sr 594 "i2s2_src_div",
667 "i2s3_sr 595 "i2s3_src_div",
668 "i2s0_mc 596 "i2s0_mclk_en",
669 "i2s1_mc 597 "i2s1_mclk_en",
670 "i2s2_mc 598 "i2s2_mclk_en",
671 "i2s3_mc 599 "i2s3_mclk_en",
672 "i2so0_h 600 "i2so0_hop_ck",
673 "i2so1_h 601 "i2so1_hop_ck",
674 "i2so2_h 602 "i2so2_hop_ck",
675 "i2so3_h 603 "i2so3_hop_ck",
676 "i2si0_h 604 "i2si0_hop_ck",
677 "i2si1_h 605 "i2si1_hop_ck",
678 "i2si2_h 606 "i2si2_hop_ck",
679 "i2si3_h 607 "i2si3_hop_ck",
680 "asrc0_o 608 "asrc0_out_ck",
681 "asrc1_o 609 "asrc1_out_ck",
682 "asrc2_o 610 "asrc2_out_ck",
683 "asrc3_o 611 "asrc3_out_ck",
684 "audio_a 612 "audio_afe_pd",
685 "audio_a 613 "audio_afe_conn_pd",
686 "audio_a 614 "audio_a1sys_pd",
687 "audio_a 615 "audio_a2sys_pd";
688 616
689 assigned-clocks = <&to 617 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
690 <&to 618 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
691 <&to 619 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
692 <&to 620 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
693 assigned-clock-parents 621 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
694 622 <&topckgen CLK_TOP_AUD2PLL>;
695 assigned-clock-rates = 623 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
696 }; 624 };
697 }; 625 };
698 626
699 mmc0: mmc@11230000 { 627 mmc0: mmc@11230000 {
700 compatible = "mediatek,mt7622- 628 compatible = "mediatek,mt7622-mmc";
701 reg = <0 0x11230000 0 0x1000>; 629 reg = <0 0x11230000 0 0x1000>;
702 interrupts = <GIC_SPI 79 IRQ_T 630 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK_PERI_MS 631 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
704 <&topckgen CLK_TOP_MS 632 <&topckgen CLK_TOP_MSDC50_0_SEL>;
705 clock-names = "source", "hclk" 633 clock-names = "source", "hclk";
706 resets = <&pericfg MT7622_PERI <<
707 reset-names = "hrst"; <<
708 status = "disabled"; 634 status = "disabled";
709 }; 635 };
710 636
711 mmc1: mmc@11240000 { 637 mmc1: mmc@11240000 {
712 compatible = "mediatek,mt7622- 638 compatible = "mediatek,mt7622-mmc";
713 reg = <0 0x11240000 0 0x1000>; 639 reg = <0 0x11240000 0 0x1000>;
714 interrupts = <GIC_SPI 80 IRQ_T 640 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
715 clocks = <&pericfg CLK_PERI_MS 641 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
716 <&topckgen CLK_TOP_AX 642 <&topckgen CLK_TOP_AXI_SEL>;
717 clock-names = "source", "hclk" 643 clock-names = "source", "hclk";
718 resets = <&pericfg MT7622_PERI 644 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
719 reset-names = "hrst"; 645 reset-names = "hrst";
720 status = "disabled"; 646 status = "disabled";
721 }; 647 };
722 648
723 wmac: wmac@18000000 { !! 649 ssusbsys: ssusbsys@1a000000 {
724 compatible = "mediatek,mt7622- !! 650 compatible = "mediatek,mt7622-ssusbsys",
725 reg = <0 0x18000000 0 0x100000 !! 651 "syscon";
726 interrupts = <GIC_SPI 211 IRQ_ <<
727 <<
728 mediatek,infracfg = <&infracfg <<
729 status = "disabled"; <<
730 <<
731 power-domains = <&scpsys MT762 <<
732 }; <<
733 <<
734 ssusbsys: clock-controller@1a000000 { <<
735 compatible = "mediatek,mt7622- <<
736 reg = <0 0x1a000000 0 0x1000>; 652 reg = <0 0x1a000000 0 0x1000>;
737 #clock-cells = <1>; 653 #clock-cells = <1>;
738 #reset-cells = <1>; 654 #reset-cells = <1>;
739 }; 655 };
740 656
741 ssusb: usb@1a0c0000 { 657 ssusb: usb@1a0c0000 {
742 compatible = "mediatek,mt7622- 658 compatible = "mediatek,mt7622-xhci",
743 "mediatek,mtk-xhc 659 "mediatek,mtk-xhci";
744 reg = <0 0x1a0c0000 0 0x01000> 660 reg = <0 0x1a0c0000 0 0x01000>,
745 <0 0x1a0c4700 0 0x0100>; 661 <0 0x1a0c4700 0 0x0100>;
746 reg-names = "mac", "ippc"; 662 reg-names = "mac", "ippc";
747 interrupts = <GIC_SPI 232 IRQ_ 663 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
748 power-domains = <&scpsys MT762 664 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
749 clocks = <&ssusbsys CLK_SSUSB_ 665 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
750 <&ssusbsys CLK_SSUSB_ 666 <&ssusbsys CLK_SSUSB_REF_EN>,
751 <&ssusbsys CLK_SSUSB_ 667 <&ssusbsys CLK_SSUSB_MCU_EN>,
752 <&ssusbsys CLK_SSUSB_ 668 <&ssusbsys CLK_SSUSB_DMA_EN>;
753 clock-names = "sys_ck", "ref_c 669 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
754 phys = <&u2port0 PHY_TYPE_USB2 670 phys = <&u2port0 PHY_TYPE_USB2>,
755 <&u3port0 PHY_TYPE_USB3 671 <&u3port0 PHY_TYPE_USB3>,
756 <&u2port1 PHY_TYPE_USB2 672 <&u2port1 PHY_TYPE_USB2>;
757 673
758 status = "disabled"; 674 status = "disabled";
759 }; 675 };
760 676
761 u3phy: t-phy@1a0c4000 { !! 677 u3phy: usb-phy@1a0c4000 {
762 compatible = "mediatek,mt7622- !! 678 compatible = "mediatek,mt7622-u3phy",
763 "mediatek,generic 679 "mediatek,generic-tphy-v1";
764 reg = <0 0x1a0c4000 0 0x700>; 680 reg = <0 0x1a0c4000 0 0x700>;
765 #address-cells = <2>; 681 #address-cells = <2>;
766 #size-cells = <2>; 682 #size-cells = <2>;
767 ranges; 683 ranges;
768 status = "disabled"; 684 status = "disabled";
769 685
770 u2port0: usb-phy@1a0c4800 { 686 u2port0: usb-phy@1a0c4800 {
771 reg = <0 0x1a0c4800 0 687 reg = <0 0x1a0c4800 0 0x0100>;
772 #phy-cells = <1>; 688 #phy-cells = <1>;
773 clocks = <&ssusbsys CL 689 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
774 clock-names = "ref"; 690 clock-names = "ref";
775 }; 691 };
776 692
777 u3port0: usb-phy@1a0c4900 { 693 u3port0: usb-phy@1a0c4900 {
778 reg = <0 0x1a0c4900 0 694 reg = <0 0x1a0c4900 0 0x0700>;
779 #phy-cells = <1>; 695 #phy-cells = <1>;
780 clocks = <&clk25m>; 696 clocks = <&clk25m>;
781 clock-names = "ref"; 697 clock-names = "ref";
782 }; 698 };
783 699
784 u2port1: usb-phy@1a0c5000 { 700 u2port1: usb-phy@1a0c5000 {
785 reg = <0 0x1a0c5000 0 701 reg = <0 0x1a0c5000 0 0x0100>;
786 #phy-cells = <1>; 702 #phy-cells = <1>;
787 clocks = <&ssusbsys CL 703 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
788 clock-names = "ref"; 704 clock-names = "ref";
789 }; 705 };
790 }; 706 };
791 707
792 pciesys: clock-controller@1a100800 { !! 708 pciesys: pciesys@1a100800 {
793 compatible = "mediatek,mt7622- !! 709 compatible = "mediatek,mt7622-pciesys",
>> 710 "syscon";
794 reg = <0 0x1a100800 0 0x1000>; 711 reg = <0 0x1a100800 0 0x1000>;
795 #clock-cells = <1>; 712 #clock-cells = <1>;
796 #reset-cells = <1>; 713 #reset-cells = <1>;
797 }; 714 };
798 715
799 pciecfg: pciecfg@1a140000 { !! 716 pcie: pcie@1a140000 {
800 compatible = "mediatek,generic <<
801 reg = <0 0x1a140000 0 0x1000>; <<
802 }; <<
803 <<
804 pcie0: pcie@1a143000 { <<
805 compatible = "mediatek,mt7622- 717 compatible = "mediatek,mt7622-pcie";
806 device_type = "pci"; 718 device_type = "pci";
807 reg = <0 0x1a143000 0 0x1000>; !! 719 reg = <0 0x1a140000 0 0x1000>,
808 reg-names = "port0"; !! 720 <0 0x1a143000 0 0x1000>,
809 linux,pci-domain = <0>; !! 721 <0 0x1a145000 0 0x1000>;
>> 722 reg-names = "subsys", "port0", "port1";
810 #address-cells = <3>; 723 #address-cells = <3>;
811 #size-cells = <2>; 724 #size-cells = <2>;
812 interrupts = <GIC_SPI 228 IRQ_ !! 725 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
813 interrupt-names = "pcie_irq"; !! 726 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
814 clocks = <&pciesys CLK_PCIE_P0 727 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
>> 728 <&pciesys CLK_PCIE_P1_MAC_EN>,
>> 729 <&pciesys CLK_PCIE_P0_AHB_EN>,
815 <&pciesys CLK_PCIE_P0 730 <&pciesys CLK_PCIE_P0_AHB_EN>,
816 <&pciesys CLK_PCIE_P0 731 <&pciesys CLK_PCIE_P0_AUX_EN>,
>> 732 <&pciesys CLK_PCIE_P1_AUX_EN>,
817 <&pciesys CLK_PCIE_P0 733 <&pciesys CLK_PCIE_P0_AXI_EN>,
>> 734 <&pciesys CLK_PCIE_P1_AXI_EN>,
818 <&pciesys CLK_PCIE_P0 735 <&pciesys CLK_PCIE_P0_OBFF_EN>,
819 <&pciesys CLK_PCIE_P0 !! 736 <&pciesys CLK_PCIE_P1_OBFF_EN>,
820 clock-names = "sys_ck0", "ahb_ !! 737 <&pciesys CLK_PCIE_P0_PIPE_EN>,
821 "axi_ck0", "obff !! 738 <&pciesys CLK_PCIE_P1_PIPE_EN>;
822 !! 739 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
>> 740 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
>> 741 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
823 power-domains = <&scpsys MT762 742 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
824 bus-range = <0x00 0xff>; 743 bus-range = <0x00 0xff>;
825 ranges = <0x82000000 0 0x20000 !! 744 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
826 status = "disabled"; 745 status = "disabled";
827 746
828 #interrupt-cells = <1>; !! 747 pcie0: pcie@0,0 {
829 interrupt-map-mask = <0 0 0 7> !! 748 reg = <0x0000 0 0 0 0>;
830 interrupt-map = <0 0 0 1 &pcie !! 749 #address-cells = <3>;
831 <0 0 0 2 &pcie !! 750 #size-cells = <2>;
832 <0 0 0 3 &pcie <<
833 <0 0 0 4 &pcie <<
834 pcie_intc0: interrupt-controll <<
835 interrupt-controller; <<
836 #address-cells = <0>; <<
837 #interrupt-cells = <1> 751 #interrupt-cells = <1>;
838 }; !! 752 ranges;
839 }; !! 753 status = "disabled";
840 <<
841 pcie1: pcie@1a145000 { <<
842 compatible = "mediatek,mt7622- <<
843 device_type = "pci"; <<
844 reg = <0 0x1a145000 0 0x1000>; <<
845 reg-names = "port1"; <<
846 linux,pci-domain = <1>; <<
847 #address-cells = <3>; <<
848 #size-cells = <2>; <<
849 interrupts = <GIC_SPI 229 IRQ_ <<
850 interrupt-names = "pcie_irq"; <<
851 clocks = <&pciesys CLK_PCIE_P1 <<
852 /* designer has conne <<
853 <&pciesys CLK_PCIE_P0 <<
854 <&pciesys CLK_PCIE_P1 <<
855 <&pciesys CLK_PCIE_P1 <<
856 <&pciesys CLK_PCIE_P1 <<
857 <&pciesys CLK_PCIE_P1 <<
858 clock-names = "sys_ck1", "ahb_ <<
859 "axi_ck1", "obff <<
860 754
861 power-domains = <&scpsys MT762 !! 755 num-lanes = <1>;
862 bus-range = <0x00 0xff>; !! 756 interrupt-map-mask = <0 0 0 7>;
863 ranges = <0x82000000 0 0x28000 !! 757 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
864 status = "disabled"; !! 758 <0 0 0 2 &pcie_intc0 1>,
>> 759 <0 0 0 3 &pcie_intc0 2>,
>> 760 <0 0 0 4 &pcie_intc0 3>;
>> 761 pcie_intc0: interrupt-controller {
>> 762 interrupt-controller;
>> 763 #address-cells = <0>;
>> 764 #interrupt-cells = <1>;
>> 765 };
>> 766 };
865 767
866 #interrupt-cells = <1>; !! 768 pcie1: pcie@1,0 {
867 interrupt-map-mask = <0 0 0 7> !! 769 reg = <0x0800 0 0 0 0>;
868 interrupt-map = <0 0 0 1 &pcie !! 770 #address-cells = <3>;
869 <0 0 0 2 &pcie !! 771 #size-cells = <2>;
870 <0 0 0 3 &pcie <<
871 <0 0 0 4 &pcie <<
872 pcie_intc1: interrupt-controll <<
873 interrupt-controller; <<
874 #address-cells = <0>; <<
875 #interrupt-cells = <1> 772 #interrupt-cells = <1>;
>> 773 ranges;
>> 774 status = "disabled";
>> 775
>> 776 num-lanes = <1>;
>> 777 interrupt-map-mask = <0 0 0 7>;
>> 778 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
>> 779 <0 0 0 2 &pcie_intc1 1>,
>> 780 <0 0 0 3 &pcie_intc1 2>,
>> 781 <0 0 0 4 &pcie_intc1 3>;
>> 782 pcie_intc1: interrupt-controller {
>> 783 interrupt-controller;
>> 784 #address-cells = <0>;
>> 785 #interrupt-cells = <1>;
>> 786 };
876 }; 787 };
877 }; 788 };
878 789
879 sata: sata@1a200000 { 790 sata: sata@1a200000 {
880 compatible = "mediatek,mt7622- 791 compatible = "mediatek,mt7622-ahci",
881 "mediatek,mtk-ahc 792 "mediatek,mtk-ahci";
882 reg = <0 0x1a200000 0 0x1100>; 793 reg = <0 0x1a200000 0 0x1100>;
883 interrupts = <GIC_SPI 233 IRQ_ 794 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "hostc"; 795 interrupt-names = "hostc";
885 clocks = <&pciesys CLK_SATA_AH 796 clocks = <&pciesys CLK_SATA_AHB_EN>,
886 <&pciesys CLK_SATA_AX 797 <&pciesys CLK_SATA_AXI_EN>,
887 <&pciesys CLK_SATA_AS 798 <&pciesys CLK_SATA_ASIC_EN>,
888 <&pciesys CLK_SATA_RB 799 <&pciesys CLK_SATA_RBC_EN>,
889 <&pciesys CLK_SATA_PM 800 <&pciesys CLK_SATA_PM_EN>;
890 clock-names = "ahb", "axi", "a 801 clock-names = "ahb", "axi", "asic", "rbc", "pm";
891 phys = <&sata_port PHY_TYPE_SA 802 phys = <&sata_port PHY_TYPE_SATA>;
892 phy-names = "sata-phy"; 803 phy-names = "sata-phy";
893 ports-implemented = <0x1>; 804 ports-implemented = <0x1>;
894 power-domains = <&scpsys MT762 805 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
895 resets = <&pciesys MT7622_SATA 806 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
896 <&pciesys MT7622_SATA 807 <&pciesys MT7622_SATA_PHY_SW_RST>,
897 <&pciesys MT7622_SATA 808 <&pciesys MT7622_SATA_PHY_REG_RST>;
898 reset-names = "axi", "sw", "re 809 reset-names = "axi", "sw", "reg";
899 mediatek,phy-mode = <&pciesys> 810 mediatek,phy-mode = <&pciesys>;
900 status = "disabled"; 811 status = "disabled";
901 }; 812 };
902 813
903 sata_phy: t-phy { !! 814 sata_phy: sata-phy@1a243000 {
904 compatible = "mediatek,mt7622- !! 815 compatible = "mediatek,generic-tphy-v1";
905 "mediatek,generic <<
906 #address-cells = <2>; 816 #address-cells = <2>;
907 #size-cells = <2>; 817 #size-cells = <2>;
908 ranges; 818 ranges;
909 status = "disabled"; 819 status = "disabled";
910 820
911 sata_port: sata-phy@1a243000 { 821 sata_port: sata-phy@1a243000 {
912 reg = <0 0x1a243000 0 822 reg = <0 0x1a243000 0 0x0100>;
913 clocks = <&topckgen CL 823 clocks = <&topckgen CLK_TOP_ETH_500M>;
914 clock-names = "ref"; 824 clock-names = "ref";
915 #phy-cells = <1>; 825 #phy-cells = <1>;
916 }; 826 };
917 }; 827 };
918 828
919 hifsys: clock-controller@1af00000 { !! 829 ethsys: syscon@1b000000 {
920 compatible = "mediatek,mt7622- <<
921 reg = <0 0x1af00000 0 0x70>; <<
922 #clock-cells = <1>; <<
923 }; <<
924 <<
925 ethsys: clock-controller@1b000000 { <<
926 compatible = "mediatek,mt7622- 830 compatible = "mediatek,mt7622-ethsys",
927 "syscon"; 831 "syscon";
928 reg = <0 0x1b000000 0 0x1000>; 832 reg = <0 0x1b000000 0 0x1000>;
929 #clock-cells = <1>; 833 #clock-cells = <1>;
930 #reset-cells = <1>; 834 #reset-cells = <1>;
931 }; 835 };
932 836
933 hsdma: dma-controller@1b007000 { 837 hsdma: dma-controller@1b007000 {
934 compatible = "mediatek,mt7622- 838 compatible = "mediatek,mt7622-hsdma";
935 reg = <0 0x1b007000 0 0x1000>; 839 reg = <0 0x1b007000 0 0x1000>;
936 interrupts = <GIC_SPI 219 IRQ_ 840 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
937 clocks = <ðsys CLK_ETH_HSDM 841 clocks = <ðsys CLK_ETH_HSDMA_EN>;
938 clock-names = "hsdma"; 842 clock-names = "hsdma";
939 power-domains = <&scpsys MT762 843 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
940 #dma-cells = <1>; 844 #dma-cells = <1>;
941 dma-requests = <3>; <<
942 }; <<
943 <<
944 pcie_mirror: pcie-mirror@10000400 { <<
945 compatible = "mediatek,mt7622- <<
946 "syscon"; <<
947 reg = <0 0x10000400 0 0x10>; <<
948 }; <<
949 <<
950 wed0: wed@1020a000 { <<
951 compatible = "mediatek,mt7622- <<
952 "syscon"; <<
953 reg = <0 0x1020a000 0 0x1000>; <<
954 interrupts = <GIC_SPI 214 IRQ_ <<
955 }; <<
956 <<
957 wed1: wed@1020b000 { <<
958 compatible = "mediatek,mt7622- <<
959 "syscon"; <<
960 reg = <0 0x1020b000 0 0x1000>; <<
961 interrupts = <GIC_SPI 215 IRQ_ <<
962 }; 845 };
963 846
964 eth: ethernet@1b100000 { 847 eth: ethernet@1b100000 {
965 compatible = "mediatek,mt7622- 848 compatible = "mediatek,mt7622-eth";
966 reg = <0 0x1b100000 0 0x20000> 849 reg = <0 0x1b100000 0 0x20000>;
967 interrupts = <GIC_SPI 223 IRQ_ 850 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
968 <GIC_SPI 224 IRQ_ 851 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
969 <GIC_SPI 225 IRQ_ 852 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
970 clocks = <&topckgen CLK_TOP_ET 853 clocks = <&topckgen CLK_TOP_ETH_SEL>,
971 <ðsys CLK_ETH_ESW_ 854 <ðsys CLK_ETH_ESW_EN>,
972 <ðsys CLK_ETH_GP0_ 855 <ðsys CLK_ETH_GP0_EN>,
973 <ðsys CLK_ETH_GP1_ 856 <ðsys CLK_ETH_GP1_EN>,
974 <ðsys CLK_ETH_GP2_ 857 <ðsys CLK_ETH_GP2_EN>,
975 <&sgmiisys CLK_SGMII_ 858 <&sgmiisys CLK_SGMII_TX250M_EN>,
976 <&sgmiisys CLK_SGMII_ 859 <&sgmiisys CLK_SGMII_RX250M_EN>,
977 <&sgmiisys CLK_SGMII_ 860 <&sgmiisys CLK_SGMII_CDR_REF>,
978 <&sgmiisys CLK_SGMII_ 861 <&sgmiisys CLK_SGMII_CDR_FB>,
979 <&topckgen CLK_TOP_SG 862 <&topckgen CLK_TOP_SGMIIPLL>,
980 <&apmixedsys CLK_APMI 863 <&apmixedsys CLK_APMIXED_ETH2PLL>;
981 clock-names = "ethif", "esw", 864 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
982 "sgmii_tx250m", 865 "sgmii_tx250m", "sgmii_rx250m",
983 "sgmii_cdr_ref", 866 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
984 "eth2pll"; 867 "eth2pll";
985 power-domains = <&scpsys MT762 868 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
986 mediatek,ethsys = <ðsys>; 869 mediatek,ethsys = <ðsys>;
987 mediatek,sgmiisys = <&sgmiisys 870 mediatek,sgmiisys = <&sgmiisys>;
988 cci-control-port = <&cci_contr <<
989 mediatek,wed = <&wed0>, <&wed1 <<
990 mediatek,pcie-mirror = <&pcie_ <<
991 mediatek,hifsys = <&hifsys>; <<
992 dma-coherent; <<
993 #address-cells = <1>; 871 #address-cells = <1>;
994 #size-cells = <0>; 872 #size-cells = <0>;
995 status = "disabled"; 873 status = "disabled";
996 }; 874 };
997 875
998 sgmiisys: sgmiisys@1b128000 { 876 sgmiisys: sgmiisys@1b128000 {
999 compatible = "mediatek,mt7622- 877 compatible = "mediatek,mt7622-sgmiisys",
1000 "syscon"; 878 "syscon";
1001 reg = <0 0x1b128000 0 0x3000> !! 879 reg = <0 0x1b128000 0 0x1000>;
1002 #clock-cells = <1>; 880 #clock-cells = <1>;
1003 }; 881 };
1004 }; 882 };
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