1 /* 1 /*
2 * Copyright (c) 2017 MediaTek Inc. 2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com> 3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com>
5 * 5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h> 11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h> 13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h> 14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 compatible = "mediatek,mt7622"; 18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>; 19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 cpu_opp_table: opp-table { 23 cpu_opp_table: opp-table {
24 compatible = "operating-points 24 compatible = "operating-points-v2";
25 opp-shared; 25 opp-shared;
26 opp-300000000 { 26 opp-300000000 {
27 opp-hz = /bits/ 64 <30 27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <95000 28 opp-microvolt = <950000>;
29 }; 29 };
30 30
31 opp-437500000 { 31 opp-437500000 {
32 opp-hz = /bits/ 64 <43 32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <10000 33 opp-microvolt = <1000000>;
34 }; 34 };
35 35
36 opp-600000000 { 36 opp-600000000 {
37 opp-hz = /bits/ 64 <60 37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <10500 38 opp-microvolt = <1050000>;
39 }; 39 };
40 40
41 opp-812500000 { 41 opp-812500000 {
42 opp-hz = /bits/ 64 <81 42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <11000 43 opp-microvolt = <1100000>;
44 }; 44 };
45 45
46 opp-1025000000 { 46 opp-1025000000 {
47 opp-hz = /bits/ 64 <10 47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <11500 48 opp-microvolt = <1150000>;
49 }; 49 };
50 50
51 opp-1137500000 { 51 opp-1137500000 {
52 opp-hz = /bits/ 64 <11 52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <12000 53 opp-microvolt = <1200000>;
54 }; 54 };
55 55
56 opp-1262500000 { 56 opp-1262500000 {
57 opp-hz = /bits/ 64 <12 57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <12500 58 opp-microvolt = <1250000>;
59 }; 59 };
60 60
61 opp-1350000000 { 61 opp-1350000000 {
62 opp-hz = /bits/ 64 <13 62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <13100 63 opp-microvolt = <1310000>;
64 }; 64 };
65 }; 65 };
66 66
67 cpus { 67 cpus {
68 #address-cells = <2>; 68 #address-cells = <2>;
69 #size-cells = <0>; 69 #size-cells = <0>;
70 70
71 cpu0: cpu@0 { 71 cpu0: cpu@0 {
72 device_type = "cpu"; 72 device_type = "cpu";
73 compatible = "arm,cort !! 73 compatible = "arm,cortex-a53", "arm,armv8";
74 reg = <0x0 0x0>; 74 reg = <0x0 0x0>;
75 clocks = <&infracfg CL 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", " 77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = 78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 enable-method = "psci" 80 enable-method = "psci";
81 clock-frequency = <130 81 clock-frequency = <1300000000>;
82 cci-control-port = <&c 82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L <<
84 }; 83 };
85 84
86 cpu1: cpu@1 { 85 cpu1: cpu@1 {
87 device_type = "cpu"; 86 device_type = "cpu";
88 compatible = "arm,cort !! 87 compatible = "arm,cortex-a53", "arm,armv8";
89 reg = <0x0 0x1>; 88 reg = <0x0 0x1>;
90 clocks = <&infracfg CL 89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys 90 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", " 91 clock-names = "cpu", "intermediate";
93 operating-points-v2 = 92 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; 93 #cooling-cells = <2>;
95 enable-method = "psci" 94 enable-method = "psci";
96 clock-frequency = <130 95 clock-frequency = <1300000000>;
97 cci-control-port = <&c 96 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L <<
99 }; <<
100 <<
101 L2: l2-cache { <<
102 compatible = "cache"; <<
103 cache-level = <2>; <<
104 cache-unified; <<
105 }; 97 };
106 }; 98 };
107 99
108 pwrap_clk: dummy40m { 100 pwrap_clk: dummy40m {
109 compatible = "fixed-clock"; 101 compatible = "fixed-clock";
110 clock-frequency = <40000000>; 102 clock-frequency = <40000000>;
111 #clock-cells = <0>; 103 #clock-cells = <0>;
112 }; 104 };
113 105
114 clk25m: oscillator { 106 clk25m: oscillator {
115 compatible = "fixed-clock"; 107 compatible = "fixed-clock";
116 #clock-cells = <0>; 108 #clock-cells = <0>;
117 clock-frequency = <25000000>; 109 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal" 110 clock-output-names = "clkxtal";
119 }; 111 };
120 112
121 psci { 113 psci {
122 compatible = "arm,psci-0.2"; !! 114 compatible = "arm,psci-0.2";
123 method = "smc"; !! 115 method = "smc";
124 }; 116 };
125 117
126 pmu { 118 pmu {
127 compatible = "arm,cortex-a53-p 119 compatible = "arm,cortex-a53-pmu";
128 interrupts = <GIC_SPI 8 IRQ_TY 120 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 9 IRQ_TY 121 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
130 interrupt-affinity = <&cpu0>, 122 interrupt-affinity = <&cpu0>, <&cpu1>;
131 }; 123 };
132 124
133 reserved-memory { 125 reserved-memory {
134 #address-cells = <2>; 126 #address-cells = <2>;
135 #size-cells = <2>; 127 #size-cells = <2>;
136 ranges; 128 ranges;
137 129
138 /* 192 KiB reserved for ARM Tr 130 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
139 secmon_reserved: secmon@430000 131 secmon_reserved: secmon@43000000 {
140 reg = <0 0x43000000 0 132 reg = <0 0x43000000 0 0x30000>;
141 no-map; 133 no-map;
142 }; 134 };
143 }; 135 };
144 136
145 thermal-zones { 137 thermal-zones {
146 cpu_thermal: cpu-thermal { 138 cpu_thermal: cpu-thermal {
147 polling-delay-passive 139 polling-delay-passive = <1000>;
148 polling-delay = <1000> 140 polling-delay = <1000>;
149 141
150 thermal-sensors = <&th 142 thermal-sensors = <&thermal 0>;
151 143
152 trips { 144 trips {
153 cpu_passive: c 145 cpu_passive: cpu-passive {
154 temper 146 temperature = <47000>;
155 hyster 147 hysteresis = <2000>;
156 type = 148 type = "passive";
157 }; 149 };
158 150
159 cpu_active: cp 151 cpu_active: cpu-active {
160 temper 152 temperature = <67000>;
161 hyster 153 hysteresis = <2000>;
162 type = 154 type = "active";
163 }; 155 };
164 156
165 cpu_hot: cpu-h 157 cpu_hot: cpu-hot {
166 temper 158 temperature = <87000>;
167 hyster 159 hysteresis = <2000>;
168 type = 160 type = "hot";
169 }; 161 };
170 162
171 cpu-crit { 163 cpu-crit {
172 temper 164 temperature = <107000>;
173 hyster 165 hysteresis = <2000>;
174 type = 166 type = "critical";
175 }; 167 };
176 }; 168 };
177 169
178 cooling-maps { 170 cooling-maps {
179 map0 { 171 map0 {
180 trip = 172 trip = <&cpu_passive>;
181 coolin !! 173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 <<
183 }; 174 };
184 175
185 map1 { 176 map1 {
186 trip = 177 trip = <&cpu_active>;
187 coolin !! 178 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
188 <<
189 }; 179 };
190 180
191 map2 { 181 map2 {
192 trip = 182 trip = <&cpu_hot>;
193 coolin !! 183 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 <<
195 }; 184 };
196 }; 185 };
197 }; 186 };
198 }; 187 };
199 188
200 timer { 189 timer {
201 compatible = "arm,armv8-timer" 190 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>; 191 interrupt-parent = <&gic>;
203 interrupts = <GIC_PPI 13 (GIC_ 192 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_LEVEL_H 193 IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_ 194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_LEVEL_H 195 IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 (GIC_ 196 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_LEVEL_H 197 IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 (GIC_ 198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_LEVEL_H 199 IRQ_TYPE_LEVEL_HIGH)>;
211 }; 200 };
212 201
213 infracfg: infracfg@10000000 { 202 infracfg: infracfg@10000000 {
214 compatible = "mediatek,mt7622- 203 compatible = "mediatek,mt7622-infracfg",
215 "syscon"; 204 "syscon";
216 reg = <0 0x10000000 0 0x1000>; 205 reg = <0 0x10000000 0 0x1000>;
217 #clock-cells = <1>; 206 #clock-cells = <1>;
218 #reset-cells = <1>; 207 #reset-cells = <1>;
219 }; 208 };
220 209
221 pwrap: pwrap@10001000 { 210 pwrap: pwrap@10001000 {
222 compatible = "mediatek,mt7622- 211 compatible = "mediatek,mt7622-pwrap";
223 reg = <0 0x10001000 0 0x250>; 212 reg = <0 0x10001000 0 0x250>;
224 reg-names = "pwrap"; 213 reg-names = "pwrap";
225 clocks = <&infracfg CLK_INFRA_ 214 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
226 clock-names = "spi", "wrap"; 215 clock-names = "spi", "wrap";
227 resets = <&infracfg MT7622_INF 216 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
228 reset-names = "pwrap"; 217 reset-names = "pwrap";
229 interrupts = <GIC_SPI 163 IRQ_ 218 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
230 status = "disabled"; 219 status = "disabled";
231 }; 220 };
232 221
233 pericfg: pericfg@10002000 { 222 pericfg: pericfg@10002000 {
234 compatible = "mediatek,mt7622- 223 compatible = "mediatek,mt7622-pericfg",
235 "syscon"; 224 "syscon";
236 reg = <0 0x10002000 0 0x1000>; 225 reg = <0 0x10002000 0 0x1000>;
237 #clock-cells = <1>; 226 #clock-cells = <1>;
238 #reset-cells = <1>; 227 #reset-cells = <1>;
239 }; 228 };
240 229
241 scpsys: power-controller@10006000 { !! 230 scpsys: scpsys@10006000 {
242 compatible = "mediatek,mt7622- 231 compatible = "mediatek,mt7622-scpsys",
243 "syscon"; 232 "syscon";
244 #power-domain-cells = <1>; 233 #power-domain-cells = <1>;
245 reg = <0 0x10006000 0 0x1000>; 234 reg = <0 0x10006000 0 0x1000>;
246 interrupts = <GIC_SPI 165 IRQ_ 235 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 166 IRQ_ 236 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 167 IRQ_ 237 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
249 <GIC_SPI 168 IRQ_ 238 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
250 infracfg = <&infracfg>; 239 infracfg = <&infracfg>;
251 clocks = <&topckgen CLK_TOP_HI 240 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 clock-names = "hif_sel"; 241 clock-names = "hif_sel";
253 }; 242 };
254 243
255 cir: ir-receiver@10009000 { !! 244 cir: cir@10009000 {
256 compatible = "mediatek,mt7622- 245 compatible = "mediatek,mt7622-cir";
257 reg = <0 0x10009000 0 0x1000>; 246 reg = <0 0x10009000 0 0x1000>;
258 interrupts = <GIC_SPI 175 IRQ_ 247 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
259 clocks = <&infracfg CLK_INFRA_ 248 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
260 <&topckgen CLK_TOP_AX 249 <&topckgen CLK_TOP_AXI_SEL>;
261 clock-names = "clk", "bus"; 250 clock-names = "clk", "bus";
262 status = "disabled"; 251 status = "disabled";
263 }; 252 };
264 253
265 sysirq: interrupt-controller@10200620 254 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622- 255 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577- 256 "mediatek,mt6577-sysirq";
268 interrupt-controller; 257 interrupt-controller;
269 #interrupt-cells = <3>; 258 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>; 259 interrupt-parent = <&gic>;
271 reg = <0 0x10200620 0 0x20>; 260 reg = <0 0x10200620 0 0x20>;
272 }; 261 };
273 262
274 efuse: efuse@10206000 { 263 efuse: efuse@10206000 {
275 compatible = "mediatek,mt7622- 264 compatible = "mediatek,mt7622-efuse",
276 "mediatek,efuse"; 265 "mediatek,efuse";
277 reg = <0 0x10206000 0 0x1000>; 266 reg = <0 0x10206000 0 0x1000>;
278 #address-cells = <1>; 267 #address-cells = <1>;
279 #size-cells = <1>; 268 #size-cells = <1>;
280 269
281 thermal_calibration: calib@198 270 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>; 271 reg = <0x198 0xc>;
283 }; 272 };
284 }; 273 };
285 274
286 apmixedsys: clock-controller@10209000 !! 275 apmixedsys: apmixedsys@10209000 {
287 compatible = "mediatek,mt7622- !! 276 compatible = "mediatek,mt7622-apmixedsys",
>> 277 "syscon";
288 reg = <0 0x10209000 0 0x1000>; 278 reg = <0 0x10209000 0 0x1000>;
289 #clock-cells = <1>; 279 #clock-cells = <1>;
290 }; 280 };
291 281
292 topckgen: clock-controller@10210000 { !! 282 topckgen: topckgen@10210000 {
293 compatible = "mediatek,mt7622- !! 283 compatible = "mediatek,mt7622-topckgen",
>> 284 "syscon";
294 reg = <0 0x10210000 0 0x1000>; 285 reg = <0 0x10210000 0 0x1000>;
295 #clock-cells = <1>; 286 #clock-cells = <1>;
296 }; 287 };
297 288
298 rng: rng@1020f000 { 289 rng: rng@1020f000 {
299 compatible = "mediatek,mt7622- 290 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623- 291 "mediatek,mt7623-rng";
301 reg = <0 0x1020f000 0 0x1000>; 292 reg = <0 0x1020f000 0 0x1000>;
302 clocks = <&infracfg CLK_INFRA_ 293 clocks = <&infracfg CLK_INFRA_TRNG>;
303 clock-names = "rng"; 294 clock-names = "rng";
304 }; 295 };
305 296
306 pio: pinctrl@10211000 { 297 pio: pinctrl@10211000 {
307 compatible = "mediatek,mt7622- 298 compatible = "mediatek,mt7622-pinctrl";
308 reg = <0 0x10211000 0 0x1000>, 299 reg = <0 0x10211000 0 0x1000>,
309 <0 0x10005000 0 0x1000>; 300 <0 0x10005000 0 0x1000>;
310 reg-names = "base", "eint"; 301 reg-names = "base", "eint";
311 gpio-controller; 302 gpio-controller;
312 #gpio-cells = <2>; 303 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 103>; 304 gpio-ranges = <&pio 0 0 103>;
314 interrupt-controller; 305 interrupt-controller;
315 interrupts = <GIC_SPI 153 IRQ_ 306 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-parent = <&gic>; 307 interrupt-parent = <&gic>;
317 #interrupt-cells = <2>; 308 #interrupt-cells = <2>;
318 }; 309 };
319 310
320 watchdog: watchdog@10212000 { 311 watchdog: watchdog@10212000 {
321 compatible = "mediatek,mt7622- 312 compatible = "mediatek,mt7622-wdt",
322 "mediatek,mt6589- 313 "mediatek,mt6589-wdt";
323 reg = <0 0x10212000 0 0x800>; 314 reg = <0 0x10212000 0 0x800>;
324 }; 315 };
325 316
326 rtc: rtc@10212800 { 317 rtc: rtc@10212800 {
327 compatible = "mediatek,mt7622- 318 compatible = "mediatek,mt7622-rtc",
328 "mediatek,soc-rtc 319 "mediatek,soc-rtc";
329 reg = <0 0x10212800 0 0x200>; 320 reg = <0 0x10212800 0 0x200>;
330 interrupts = <GIC_SPI 129 IRQ_ 321 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
331 clocks = <&topckgen CLK_TOP_RT 322 clocks = <&topckgen CLK_TOP_RTC>;
332 clock-names = "rtc"; 323 clock-names = "rtc";
333 }; 324 };
334 325
335 gic: interrupt-controller@10300000 { 326 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400"; 327 compatible = "arm,gic-400";
337 interrupt-controller; 328 interrupt-controller;
338 #interrupt-cells = <3>; 329 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>; 330 interrupt-parent = <&gic>;
340 reg = <0 0x10310000 0 0x1000>, 331 reg = <0 0x10310000 0 0x1000>,
341 <0 0x10320000 0 0x1000>, 332 <0 0x10320000 0 0x1000>,
342 <0 0x10340000 0 0x2000>, 333 <0 0x10340000 0 0x2000>,
343 <0 0x10360000 0 0x2000>; 334 <0 0x10360000 0 0x2000>;
344 }; 335 };
345 336
346 cci: cci@10390000 { 337 cci: cci@10390000 {
347 compatible = "arm,cci-400"; 338 compatible = "arm,cci-400";
348 #address-cells = <1>; 339 #address-cells = <1>;
349 #size-cells = <1>; 340 #size-cells = <1>;
350 reg = <0 0x10390000 0 0x1000>; 341 reg = <0 0x10390000 0 0x1000>;
351 ranges = <0 0 0x10390000 0x100 342 ranges = <0 0 0x10390000 0x10000>;
352 343
353 cci_control0: slave-if@1000 { 344 cci_control0: slave-if@1000 {
354 compatible = "arm,cci- 345 compatible = "arm,cci-400-ctrl-if";
355 interface-type = "ace- 346 interface-type = "ace-lite";
356 reg = <0x1000 0x1000>; 347 reg = <0x1000 0x1000>;
357 }; 348 };
358 349
359 cci_control1: slave-if@4000 { 350 cci_control1: slave-if@4000 {
360 compatible = "arm,cci- 351 compatible = "arm,cci-400-ctrl-if";
361 interface-type = "ace" 352 interface-type = "ace";
362 reg = <0x4000 0x1000>; 353 reg = <0x4000 0x1000>;
363 }; 354 };
364 355
365 cci_control2: slave-if@5000 { 356 cci_control2: slave-if@5000 {
366 compatible = "arm,cci- !! 357 compatible = "arm,cci-400-ctrl-if";
367 interface-type = "ace" 358 interface-type = "ace";
368 reg = <0x5000 0x1000>; 359 reg = <0x5000 0x1000>;
369 }; 360 };
370 361
371 pmu@9000 { 362 pmu@9000 {
372 compatible = "arm,cci- 363 compatible = "arm,cci-400-pmu,r1";
373 reg = <0x9000 0x5000>; 364 reg = <0x9000 0x5000>;
374 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 366 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 367 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 368 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 369 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
379 }; 370 };
380 }; 371 };
381 372
382 auxadc: adc@11001000 { 373 auxadc: adc@11001000 {
383 compatible = "mediatek,mt7622- 374 compatible = "mediatek,mt7622-auxadc";
384 reg = <0 0x11001000 0 0x1000>; 375 reg = <0 0x11001000 0 0x1000>;
385 clocks = <&pericfg CLK_PERI_AU 376 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
386 clock-names = "main"; 377 clock-names = "main";
387 #io-channel-cells = <1>; 378 #io-channel-cells = <1>;
388 }; 379 };
389 380
390 uart0: serial@11002000 { 381 uart0: serial@11002000 {
391 compatible = "mediatek,mt7622- 382 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577- 383 "mediatek,mt6577-uart";
393 reg = <0 0x11002000 0 0x400>; 384 reg = <0 0x11002000 0 0x400>;
394 interrupts = <GIC_SPI 91 IRQ_T 385 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&topckgen CLK_TOP_UA 386 clocks = <&topckgen CLK_TOP_UART_SEL>,
396 <&pericfg CLK_PERI_UA 387 <&pericfg CLK_PERI_UART0_PD>;
397 clock-names = "baud", "bus"; 388 clock-names = "baud", "bus";
398 status = "disabled"; 389 status = "disabled";
399 }; 390 };
400 391
401 uart1: serial@11003000 { 392 uart1: serial@11003000 {
402 compatible = "mediatek,mt7622- 393 compatible = "mediatek,mt7622-uart",
403 "mediatek,mt6577- 394 "mediatek,mt6577-uart";
404 reg = <0 0x11003000 0 0x400>; 395 reg = <0 0x11003000 0 0x400>;
405 interrupts = <GIC_SPI 92 IRQ_T 396 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
406 clocks = <&topckgen CLK_TOP_UA 397 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 <&pericfg CLK_PERI_UA 398 <&pericfg CLK_PERI_UART1_PD>;
408 clock-names = "baud", "bus"; 399 clock-names = "baud", "bus";
409 status = "disabled"; 400 status = "disabled";
410 }; 401 };
411 402
412 uart2: serial@11004000 { 403 uart2: serial@11004000 {
413 compatible = "mediatek,mt7622- 404 compatible = "mediatek,mt7622-uart",
414 "mediatek,mt6577- 405 "mediatek,mt6577-uart";
415 reg = <0 0x11004000 0 0x400>; 406 reg = <0 0x11004000 0 0x400>;
416 interrupts = <GIC_SPI 93 IRQ_T 407 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&topckgen CLK_TOP_UA 408 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 <&pericfg CLK_PERI_UA 409 <&pericfg CLK_PERI_UART2_PD>;
419 clock-names = "baud", "bus"; 410 clock-names = "baud", "bus";
420 status = "disabled"; 411 status = "disabled";
421 }; 412 };
422 413
423 uart3: serial@11005000 { 414 uart3: serial@11005000 {
424 compatible = "mediatek,mt7622- 415 compatible = "mediatek,mt7622-uart",
425 "mediatek,mt6577- 416 "mediatek,mt6577-uart";
426 reg = <0 0x11005000 0 0x400>; 417 reg = <0 0x11005000 0 0x400>;
427 interrupts = <GIC_SPI 94 IRQ_T 418 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
428 clocks = <&topckgen CLK_TOP_UA 419 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 <&pericfg CLK_PERI_UA 420 <&pericfg CLK_PERI_UART3_PD>;
430 clock-names = "baud", "bus"; 421 clock-names = "baud", "bus";
431 status = "disabled"; 422 status = "disabled";
432 }; 423 };
433 424
434 pwm: pwm@11006000 { 425 pwm: pwm@11006000 {
435 compatible = "mediatek,mt7622- 426 compatible = "mediatek,mt7622-pwm";
436 reg = <0 0x11006000 0 0x1000>; 427 reg = <0 0x11006000 0 0x1000>;
437 #pwm-cells = <2>; <<
438 interrupts = <GIC_SPI 77 IRQ_T 428 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_PW 429 clocks = <&topckgen CLK_TOP_PWM_SEL>,
440 <&pericfg CLK_PERI_PW 430 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PW 431 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PW 432 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PW 433 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PW 434 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PW 435 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PW 436 <&pericfg CLK_PERI_PWM6_PD>;
447 clock-names = "top", "main", " 437 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
448 "pwm5", "pwm6"; 438 "pwm5", "pwm6";
449 status = "disabled"; 439 status = "disabled";
450 }; 440 };
451 441
452 i2c0: i2c@11007000 { 442 i2c0: i2c@11007000 {
453 compatible = "mediatek,mt7622- 443 compatible = "mediatek,mt7622-i2c";
454 reg = <0 0x11007000 0 0x90>, 444 reg = <0 0x11007000 0 0x90>,
455 <0 0x11000100 0 0x80>; 445 <0 0x11000100 0 0x80>;
456 interrupts = <GIC_SPI 84 IRQ_T 446 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>; 447 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2 448 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP 449 <&pericfg CLK_PERI_AP_DMA_PD>;
460 clock-names = "main", "dma"; 450 clock-names = "main", "dma";
461 #address-cells = <1>; 451 #address-cells = <1>;
462 #size-cells = <0>; 452 #size-cells = <0>;
463 status = "disabled"; 453 status = "disabled";
464 }; 454 };
465 455
466 i2c1: i2c@11008000 { 456 i2c1: i2c@11008000 {
467 compatible = "mediatek,mt7622- 457 compatible = "mediatek,mt7622-i2c";
468 reg = <0 0x11008000 0 0x90>, 458 reg = <0 0x11008000 0 0x90>,
469 <0 0x11000180 0 0x80>; 459 <0 0x11000180 0 0x80>;
470 interrupts = <GIC_SPI 85 IRQ_T 460 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
471 clock-div = <16>; 461 clock-div = <16>;
472 clocks = <&pericfg CLK_PERI_I2 462 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP 463 <&pericfg CLK_PERI_AP_DMA_PD>;
474 clock-names = "main", "dma"; 464 clock-names = "main", "dma";
475 #address-cells = <1>; 465 #address-cells = <1>;
476 #size-cells = <0>; 466 #size-cells = <0>;
477 status = "disabled"; 467 status = "disabled";
478 }; 468 };
479 469
480 i2c2: i2c@11009000 { 470 i2c2: i2c@11009000 {
481 compatible = "mediatek,mt7622- 471 compatible = "mediatek,mt7622-i2c";
482 reg = <0 0x11009000 0 0x90>, 472 reg = <0 0x11009000 0 0x90>,
483 <0 0x11000200 0 0x80>; 473 <0 0x11000200 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_T 474 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
485 clock-div = <16>; 475 clock-div = <16>;
486 clocks = <&pericfg CLK_PERI_I2 476 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP 477 <&pericfg CLK_PERI_AP_DMA_PD>;
488 clock-names = "main", "dma"; 478 clock-names = "main", "dma";
489 #address-cells = <1>; 479 #address-cells = <1>;
490 #size-cells = <0>; 480 #size-cells = <0>;
491 status = "disabled"; 481 status = "disabled";
492 }; 482 };
493 483
494 spi0: spi@1100a000 { 484 spi0: spi@1100a000 {
495 compatible = "mediatek,mt7622- 485 compatible = "mediatek,mt7622-spi";
496 reg = <0 0x1100a000 0 0x100>; 486 reg = <0 0x1100a000 0 0x100>;
497 interrupts = <GIC_SPI 118 IRQ_ 487 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&topckgen CLK_TOP_SY 488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SP 489 <&topckgen CLK_TOP_SPI0_SEL>,
500 <&pericfg CLK_PERI_SP 490 <&pericfg CLK_PERI_SPI0_PD>;
501 clock-names = "parent-clk", "s 491 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>; 492 #address-cells = <1>;
503 #size-cells = <0>; 493 #size-cells = <0>;
504 status = "disabled"; 494 status = "disabled";
505 }; 495 };
506 496
507 thermal: thermal@1100b000 { 497 thermal: thermal@1100b000 {
508 #thermal-sensor-cells = <1>; 498 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622- 499 compatible = "mediatek,mt7622-thermal";
510 reg = <0 0x1100b000 0 0x1000>; 500 reg = <0 0x1100b000 0 0x1000>;
511 interrupts = <0 78 IRQ_TYPE_LE 501 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_TH 502 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AU 503 <&pericfg CLK_PERI_AUXADC_PD>;
514 clock-names = "therm", "auxadc 504 clock-names = "therm", "auxadc";
515 resets = <&pericfg MT7622_PERI 505 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
>> 506 reset-names = "therm";
516 mediatek,auxadc = <&auxadc>; 507 mediatek,auxadc = <&auxadc>;
517 mediatek,apmixedsys = <&apmixe 508 mediatek,apmixedsys = <&apmixedsys>;
518 nvmem-cells = <&thermal_calibr 509 nvmem-cells = <&thermal_calibration>;
519 nvmem-cell-names = "calibratio 510 nvmem-cell-names = "calibration-data";
520 }; 511 };
521 512
522 btif: serial@1100c000 { 513 btif: serial@1100c000 {
523 compatible = "mediatek,mt7622- 514 compatible = "mediatek,mt7622-btif",
524 "mediatek,mtk-bti 515 "mediatek,mtk-btif";
525 reg = <0 0x1100c000 0 0x1000>; 516 reg = <0 0x1100c000 0 0x1000>;
526 interrupts = <GIC_SPI 90 IRQ_T 517 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&pericfg CLK_PERI_BT 518 clocks = <&pericfg CLK_PERI_BTIF_PD>;
>> 519 clock-names = "main";
528 reg-shift = <2>; 520 reg-shift = <2>;
529 reg-io-width = <4>; 521 reg-io-width = <4>;
530 status = "disabled"; 522 status = "disabled";
531 523
532 bluetooth { 524 bluetooth {
533 compatible = "mediatek 525 compatible = "mediatek,mt7622-bluetooth";
534 power-domains = <&scps 526 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
535 clocks = <&clk25m>; 527 clocks = <&clk25m>;
536 clock-names = "ref"; 528 clock-names = "ref";
537 }; 529 };
538 }; 530 };
539 531
540 nandc: nand-controller@1100d000 { !! 532 nandc: nfi@1100d000 {
541 compatible = "mediatek,mt7622- 533 compatible = "mediatek,mt7622-nfc";
542 reg = <0 0x1100D000 0 0x1000>; 534 reg = <0 0x1100D000 0 0x1000>;
543 interrupts = <GIC_SPI 96 IRQ_T 535 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_NF 536 clocks = <&pericfg CLK_PERI_NFI_PD>,
545 <&pericfg CLK_PERI_SN 537 <&pericfg CLK_PERI_SNFI_PD>;
546 clock-names = "nfi_clk", "pad_ 538 clock-names = "nfi_clk", "pad_clk";
547 ecc-engine = <&bch>; 539 ecc-engine = <&bch>;
548 #address-cells = <1>; 540 #address-cells = <1>;
549 #size-cells = <0>; 541 #size-cells = <0>;
550 status = "disabled"; 542 status = "disabled";
551 }; 543 };
552 544
553 snfi: spi@1100d000 { <<
554 compatible = "mediatek,mt7622- <<
555 reg = <0 0x1100d000 0 0x1000>; <<
556 interrupts = <GIC_SPI 96 IRQ_T <<
557 clocks = <&pericfg CLK_PERI_NF <<
558 clock-names = "nfi_clk", "pad_ <<
559 nand-ecc-engine = <&bch>; <<
560 #address-cells = <1>; <<
561 #size-cells = <0>; <<
562 status = "disabled"; <<
563 }; <<
564 <<
565 bch: ecc@1100e000 { 545 bch: ecc@1100e000 {
566 compatible = "mediatek,mt7622- 546 compatible = "mediatek,mt7622-ecc";
567 reg = <0 0x1100e000 0 0x1000>; 547 reg = <0 0x1100e000 0 0x1000>;
568 interrupts = <GIC_SPI 95 IRQ_T 548 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
569 clocks = <&pericfg CLK_PERI_NF 549 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
570 clock-names = "nfiecc_clk"; 550 clock-names = "nfiecc_clk";
571 status = "disabled"; 551 status = "disabled";
572 }; 552 };
573 553
574 nor_flash: spi@11014000 { 554 nor_flash: spi@11014000 {
575 compatible = "mediatek,mt7622- 555 compatible = "mediatek,mt7622-nor",
576 "mediatek,mt8173- 556 "mediatek,mt8173-nor";
577 reg = <0 0x11014000 0 0xe0>; 557 reg = <0 0x11014000 0 0xe0>;
578 clocks = <&pericfg CLK_PERI_FL 558 clocks = <&pericfg CLK_PERI_FLASH_PD>,
579 <&topckgen CLK_TOP_FL 559 <&topckgen CLK_TOP_FLASH_SEL>;
580 clock-names = "spi", "sf"; 560 clock-names = "spi", "sf";
581 #address-cells = <1>; 561 #address-cells = <1>;
582 #size-cells = <0>; 562 #size-cells = <0>;
583 status = "disabled"; 563 status = "disabled";
584 }; 564 };
585 565
586 spi1: spi@11016000 { 566 spi1: spi@11016000 {
587 compatible = "mediatek,mt7622- 567 compatible = "mediatek,mt7622-spi";
588 reg = <0 0x11016000 0 0x100>; 568 reg = <0 0x11016000 0 0x100>;
589 interrupts = <GIC_SPI 122 IRQ_ 569 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&topckgen CLK_TOP_SY 570 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SP 571 <&topckgen CLK_TOP_SPI1_SEL>,
592 <&pericfg CLK_PERI_SP 572 <&pericfg CLK_PERI_SPI1_PD>;
593 clock-names = "parent-clk", "s 573 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 #address-cells = <1>; 574 #address-cells = <1>;
595 #size-cells = <0>; 575 #size-cells = <0>;
596 status = "disabled"; 576 status = "disabled";
597 }; 577 };
598 578
599 uart4: serial@11019000 { 579 uart4: serial@11019000 {
600 compatible = "mediatek,mt7622- 580 compatible = "mediatek,mt7622-uart",
601 "mediatek,mt6577- 581 "mediatek,mt6577-uart";
602 reg = <0 0x11019000 0 0x400>; 582 reg = <0 0x11019000 0 0x400>;
603 interrupts = <GIC_SPI 89 IRQ_T 583 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CLK_TOP_UA 584 clocks = <&topckgen CLK_TOP_UART_SEL>,
605 <&pericfg CLK_PERI_UA 585 <&pericfg CLK_PERI_UART4_PD>;
606 clock-names = "baud", "bus"; 586 clock-names = "baud", "bus";
607 status = "disabled"; 587 status = "disabled";
608 }; 588 };
609 589
610 audsys: clock-controller@11220000 { 590 audsys: clock-controller@11220000 {
611 compatible = "mediatek,mt7622- 591 compatible = "mediatek,mt7622-audsys", "syscon";
612 reg = <0 0x11220000 0 0x2000>; 592 reg = <0 0x11220000 0 0x2000>;
613 #clock-cells = <1>; 593 #clock-cells = <1>;
614 594
615 afe: audio-controller { 595 afe: audio-controller {
616 compatible = "mediatek 596 compatible = "mediatek,mt7622-audio";
617 interrupts = <GIC_SPI !! 597 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
618 <GIC_SPI !! 598 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
619 interrupt-names = "afe !! 599 interrupt-names = "afe", "asys";
620 600
621 clocks = <&infracfg CL 601 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
622 <&topckgen CL 602 <&topckgen CLK_TOP_AUD1_SEL>,
623 <&topckgen CL 603 <&topckgen CLK_TOP_AUD2_SEL>,
624 <&topckgen CL 604 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
625 <&topckgen CL 605 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
626 <&topckgen CL 606 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
627 <&topckgen CL 607 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
628 <&topckgen CL 608 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
629 <&topckgen CL 609 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
630 <&topckgen CL 610 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
631 <&topckgen CL 611 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
632 <&topckgen CL 612 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
633 <&topckgen CL 613 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
634 <&topckgen CL 614 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
635 <&topckgen CL 615 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
636 <&topckgen CL 616 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
637 <&topckgen CL 617 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
638 <&audsys CLK_ 618 <&audsys CLK_AUDIO_I2SO1>,
639 <&audsys CLK_ 619 <&audsys CLK_AUDIO_I2SO2>,
640 <&audsys CLK_ 620 <&audsys CLK_AUDIO_I2SO3>,
641 <&audsys CLK_ 621 <&audsys CLK_AUDIO_I2SO4>,
642 <&audsys CLK_ 622 <&audsys CLK_AUDIO_I2SIN1>,
643 <&audsys CLK_ 623 <&audsys CLK_AUDIO_I2SIN2>,
644 <&audsys CLK_ 624 <&audsys CLK_AUDIO_I2SIN3>,
645 <&audsys CLK_ 625 <&audsys CLK_AUDIO_I2SIN4>,
646 <&audsys CLK_ 626 <&audsys CLK_AUDIO_ASRCO1>,
647 <&audsys CLK_ 627 <&audsys CLK_AUDIO_ASRCO2>,
648 <&audsys CLK_ 628 <&audsys CLK_AUDIO_ASRCO3>,
649 <&audsys CLK_ 629 <&audsys CLK_AUDIO_ASRCO4>,
650 <&audsys CLK_ 630 <&audsys CLK_AUDIO_AFE>,
651 <&audsys CLK_ 631 <&audsys CLK_AUDIO_AFE_CONN>,
652 <&audsys CLK_ 632 <&audsys CLK_AUDIO_A1SYS>,
653 <&audsys CLK_ 633 <&audsys CLK_AUDIO_A2SYS>;
654 634
655 clock-names = "infra_s 635 clock-names = "infra_sys_audio_clk",
656 "top_aud 636 "top_audio_mux1_sel",
657 "top_aud 637 "top_audio_mux2_sel",
658 "top_aud 638 "top_audio_a1sys_hp",
659 "top_aud 639 "top_audio_a2sys_hp",
660 "i2s0_sr 640 "i2s0_src_sel",
661 "i2s1_sr 641 "i2s1_src_sel",
662 "i2s2_sr 642 "i2s2_src_sel",
663 "i2s3_sr 643 "i2s3_src_sel",
664 "i2s0_sr 644 "i2s0_src_div",
665 "i2s1_sr 645 "i2s1_src_div",
666 "i2s2_sr 646 "i2s2_src_div",
667 "i2s3_sr 647 "i2s3_src_div",
668 "i2s0_mc 648 "i2s0_mclk_en",
669 "i2s1_mc 649 "i2s1_mclk_en",
670 "i2s2_mc 650 "i2s2_mclk_en",
671 "i2s3_mc 651 "i2s3_mclk_en",
672 "i2so0_h 652 "i2so0_hop_ck",
673 "i2so1_h 653 "i2so1_hop_ck",
674 "i2so2_h 654 "i2so2_hop_ck",
675 "i2so3_h 655 "i2so3_hop_ck",
676 "i2si0_h 656 "i2si0_hop_ck",
677 "i2si1_h 657 "i2si1_hop_ck",
678 "i2si2_h 658 "i2si2_hop_ck",
679 "i2si3_h 659 "i2si3_hop_ck",
680 "asrc0_o 660 "asrc0_out_ck",
681 "asrc1_o 661 "asrc1_out_ck",
682 "asrc2_o 662 "asrc2_out_ck",
683 "asrc3_o 663 "asrc3_out_ck",
684 "audio_a 664 "audio_afe_pd",
685 "audio_a 665 "audio_afe_conn_pd",
686 "audio_a 666 "audio_a1sys_pd",
687 "audio_a 667 "audio_a2sys_pd";
688 668
689 assigned-clocks = <&to 669 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
690 <&to 670 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
691 <&to 671 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
692 <&to 672 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
693 assigned-clock-parents 673 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
694 674 <&topckgen CLK_TOP_AUD2PLL>;
695 assigned-clock-rates = 675 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
696 }; 676 };
697 }; 677 };
698 678
699 mmc0: mmc@11230000 { 679 mmc0: mmc@11230000 {
700 compatible = "mediatek,mt7622- 680 compatible = "mediatek,mt7622-mmc";
701 reg = <0 0x11230000 0 0x1000>; 681 reg = <0 0x11230000 0 0x1000>;
702 interrupts = <GIC_SPI 79 IRQ_T 682 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK_PERI_MS 683 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
704 <&topckgen CLK_TOP_MS 684 <&topckgen CLK_TOP_MSDC50_0_SEL>;
705 clock-names = "source", "hclk" 685 clock-names = "source", "hclk";
706 resets = <&pericfg MT7622_PERI <<
707 reset-names = "hrst"; <<
708 status = "disabled"; 686 status = "disabled";
709 }; 687 };
710 688
711 mmc1: mmc@11240000 { 689 mmc1: mmc@11240000 {
712 compatible = "mediatek,mt7622- 690 compatible = "mediatek,mt7622-mmc";
713 reg = <0 0x11240000 0 0x1000>; 691 reg = <0 0x11240000 0 0x1000>;
714 interrupts = <GIC_SPI 80 IRQ_T 692 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
715 clocks = <&pericfg CLK_PERI_MS 693 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
716 <&topckgen CLK_TOP_AX 694 <&topckgen CLK_TOP_AXI_SEL>;
717 clock-names = "source", "hclk" 695 clock-names = "source", "hclk";
718 resets = <&pericfg MT7622_PERI <<
719 reset-names = "hrst"; <<
720 status = "disabled"; 696 status = "disabled";
721 }; 697 };
722 698
723 wmac: wmac@18000000 { !! 699 ssusbsys: ssusbsys@1a000000 {
724 compatible = "mediatek,mt7622- !! 700 compatible = "mediatek,mt7622-ssusbsys",
725 reg = <0 0x18000000 0 0x100000 !! 701 "syscon";
726 interrupts = <GIC_SPI 211 IRQ_ <<
727 <<
728 mediatek,infracfg = <&infracfg <<
729 status = "disabled"; <<
730 <<
731 power-domains = <&scpsys MT762 <<
732 }; <<
733 <<
734 ssusbsys: clock-controller@1a000000 { <<
735 compatible = "mediatek,mt7622- <<
736 reg = <0 0x1a000000 0 0x1000>; 702 reg = <0 0x1a000000 0 0x1000>;
737 #clock-cells = <1>; 703 #clock-cells = <1>;
738 #reset-cells = <1>; 704 #reset-cells = <1>;
739 }; 705 };
740 706
741 ssusb: usb@1a0c0000 { 707 ssusb: usb@1a0c0000 {
742 compatible = "mediatek,mt7622- 708 compatible = "mediatek,mt7622-xhci",
743 "mediatek,mtk-xhc 709 "mediatek,mtk-xhci";
744 reg = <0 0x1a0c0000 0 0x01000> 710 reg = <0 0x1a0c0000 0 0x01000>,
745 <0 0x1a0c4700 0 0x0100>; 711 <0 0x1a0c4700 0 0x0100>;
746 reg-names = "mac", "ippc"; 712 reg-names = "mac", "ippc";
747 interrupts = <GIC_SPI 232 IRQ_ 713 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
748 power-domains = <&scpsys MT762 714 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
749 clocks = <&ssusbsys CLK_SSUSB_ 715 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
750 <&ssusbsys CLK_SSUSB_ 716 <&ssusbsys CLK_SSUSB_REF_EN>,
751 <&ssusbsys CLK_SSUSB_ 717 <&ssusbsys CLK_SSUSB_MCU_EN>,
752 <&ssusbsys CLK_SSUSB_ 718 <&ssusbsys CLK_SSUSB_DMA_EN>;
753 clock-names = "sys_ck", "ref_c 719 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
754 phys = <&u2port0 PHY_TYPE_USB2 720 phys = <&u2port0 PHY_TYPE_USB2>,
755 <&u3port0 PHY_TYPE_USB3 721 <&u3port0 PHY_TYPE_USB3>,
756 <&u2port1 PHY_TYPE_USB2 722 <&u2port1 PHY_TYPE_USB2>;
757 723
758 status = "disabled"; 724 status = "disabled";
759 }; 725 };
760 726
761 u3phy: t-phy@1a0c4000 { !! 727 u3phy: usb-phy@1a0c4000 {
762 compatible = "mediatek,mt7622- !! 728 compatible = "mediatek,mt7622-u3phy",
763 "mediatek,generic 729 "mediatek,generic-tphy-v1";
764 reg = <0 0x1a0c4000 0 0x700>; 730 reg = <0 0x1a0c4000 0 0x700>;
765 #address-cells = <2>; 731 #address-cells = <2>;
766 #size-cells = <2>; 732 #size-cells = <2>;
767 ranges; 733 ranges;
768 status = "disabled"; 734 status = "disabled";
769 735
770 u2port0: usb-phy@1a0c4800 { 736 u2port0: usb-phy@1a0c4800 {
771 reg = <0 0x1a0c4800 0 737 reg = <0 0x1a0c4800 0 0x0100>;
772 #phy-cells = <1>; 738 #phy-cells = <1>;
773 clocks = <&ssusbsys CL 739 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
774 clock-names = "ref"; 740 clock-names = "ref";
775 }; 741 };
776 742
777 u3port0: usb-phy@1a0c4900 { 743 u3port0: usb-phy@1a0c4900 {
778 reg = <0 0x1a0c4900 0 744 reg = <0 0x1a0c4900 0 0x0700>;
779 #phy-cells = <1>; 745 #phy-cells = <1>;
780 clocks = <&clk25m>; 746 clocks = <&clk25m>;
781 clock-names = "ref"; 747 clock-names = "ref";
782 }; 748 };
783 749
784 u2port1: usb-phy@1a0c5000 { 750 u2port1: usb-phy@1a0c5000 {
785 reg = <0 0x1a0c5000 0 751 reg = <0 0x1a0c5000 0 0x0100>;
786 #phy-cells = <1>; 752 #phy-cells = <1>;
787 clocks = <&ssusbsys CL 753 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
788 clock-names = "ref"; 754 clock-names = "ref";
789 }; 755 };
790 }; 756 };
791 757
792 pciesys: clock-controller@1a100800 { !! 758 pciesys: pciesys@1a100800 {
793 compatible = "mediatek,mt7622- !! 759 compatible = "mediatek,mt7622-pciesys",
>> 760 "syscon";
794 reg = <0 0x1a100800 0 0x1000>; 761 reg = <0 0x1a100800 0 0x1000>;
795 #clock-cells = <1>; 762 #clock-cells = <1>;
796 #reset-cells = <1>; 763 #reset-cells = <1>;
797 }; 764 };
798 765
799 pciecfg: pciecfg@1a140000 { !! 766 pcie: pcie@1a140000 {
800 compatible = "mediatek,generic <<
801 reg = <0 0x1a140000 0 0x1000>; <<
802 }; <<
803 <<
804 pcie0: pcie@1a143000 { <<
805 compatible = "mediatek,mt7622- 767 compatible = "mediatek,mt7622-pcie";
806 device_type = "pci"; 768 device_type = "pci";
807 reg = <0 0x1a143000 0 0x1000>; !! 769 reg = <0 0x1a140000 0 0x1000>,
808 reg-names = "port0"; !! 770 <0 0x1a143000 0 0x1000>,
809 linux,pci-domain = <0>; !! 771 <0 0x1a145000 0 0x1000>;
>> 772 reg-names = "subsys", "port0", "port1";
810 #address-cells = <3>; 773 #address-cells = <3>;
811 #size-cells = <2>; 774 #size-cells = <2>;
812 interrupts = <GIC_SPI 228 IRQ_ !! 775 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
813 interrupt-names = "pcie_irq"; !! 776 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
814 clocks = <&pciesys CLK_PCIE_P0 777 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
>> 778 <&pciesys CLK_PCIE_P1_MAC_EN>,
>> 779 <&pciesys CLK_PCIE_P0_AHB_EN>,
815 <&pciesys CLK_PCIE_P0 780 <&pciesys CLK_PCIE_P0_AHB_EN>,
816 <&pciesys CLK_PCIE_P0 781 <&pciesys CLK_PCIE_P0_AUX_EN>,
>> 782 <&pciesys CLK_PCIE_P1_AUX_EN>,
817 <&pciesys CLK_PCIE_P0 783 <&pciesys CLK_PCIE_P0_AXI_EN>,
>> 784 <&pciesys CLK_PCIE_P1_AXI_EN>,
818 <&pciesys CLK_PCIE_P0 785 <&pciesys CLK_PCIE_P0_OBFF_EN>,
819 <&pciesys CLK_PCIE_P0 !! 786 <&pciesys CLK_PCIE_P1_OBFF_EN>,
820 clock-names = "sys_ck0", "ahb_ !! 787 <&pciesys CLK_PCIE_P0_PIPE_EN>,
821 "axi_ck0", "obff !! 788 <&pciesys CLK_PCIE_P1_PIPE_EN>;
822 !! 789 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
>> 790 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
>> 791 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
823 power-domains = <&scpsys MT762 792 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
824 bus-range = <0x00 0xff>; 793 bus-range = <0x00 0xff>;
825 ranges = <0x82000000 0 0x20000 !! 794 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
826 status = "disabled"; 795 status = "disabled";
827 796
828 #interrupt-cells = <1>; !! 797 pcie0: pcie@0,0 {
829 interrupt-map-mask = <0 0 0 7> !! 798 reg = <0x0000 0 0 0 0>;
830 interrupt-map = <0 0 0 1 &pcie !! 799 #address-cells = <3>;
831 <0 0 0 2 &pcie !! 800 #size-cells = <2>;
832 <0 0 0 3 &pcie <<
833 <0 0 0 4 &pcie <<
834 pcie_intc0: interrupt-controll <<
835 interrupt-controller; <<
836 #address-cells = <0>; <<
837 #interrupt-cells = <1> 801 #interrupt-cells = <1>;
838 }; !! 802 ranges;
839 }; !! 803 status = "disabled";
840 804
841 pcie1: pcie@1a145000 { !! 805 interrupt-map-mask = <0 0 0 7>;
842 compatible = "mediatek,mt7622- !! 806 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
843 device_type = "pci"; !! 807 <0 0 0 2 &pcie_intc0 1>,
844 reg = <0 0x1a145000 0 0x1000>; !! 808 <0 0 0 3 &pcie_intc0 2>,
845 reg-names = "port1"; !! 809 <0 0 0 4 &pcie_intc0 3>;
846 linux,pci-domain = <1>; !! 810 pcie_intc0: interrupt-controller {
847 #address-cells = <3>; !! 811 interrupt-controller;
848 #size-cells = <2>; !! 812 #address-cells = <0>;
849 interrupts = <GIC_SPI 229 IRQ_ !! 813 #interrupt-cells = <1>;
850 interrupt-names = "pcie_irq"; !! 814 };
851 clocks = <&pciesys CLK_PCIE_P1 !! 815 };
852 /* designer has conne <<
853 <&pciesys CLK_PCIE_P0 <<
854 <&pciesys CLK_PCIE_P1 <<
855 <&pciesys CLK_PCIE_P1 <<
856 <&pciesys CLK_PCIE_P1 <<
857 <&pciesys CLK_PCIE_P1 <<
858 clock-names = "sys_ck1", "ahb_ <<
859 "axi_ck1", "obff <<
860 <<
861 power-domains = <&scpsys MT762 <<
862 bus-range = <0x00 0xff>; <<
863 ranges = <0x82000000 0 0x28000 <<
864 status = "disabled"; <<
865 816
866 #interrupt-cells = <1>; !! 817 pcie1: pcie@1,0 {
867 interrupt-map-mask = <0 0 0 7> !! 818 reg = <0x0800 0 0 0 0>;
868 interrupt-map = <0 0 0 1 &pcie !! 819 #address-cells = <3>;
869 <0 0 0 2 &pcie !! 820 #size-cells = <2>;
870 <0 0 0 3 &pcie <<
871 <0 0 0 4 &pcie <<
872 pcie_intc1: interrupt-controll <<
873 interrupt-controller; <<
874 #address-cells = <0>; <<
875 #interrupt-cells = <1> 821 #interrupt-cells = <1>;
>> 822 ranges;
>> 823 status = "disabled";
>> 824
>> 825 interrupt-map-mask = <0 0 0 7>;
>> 826 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
>> 827 <0 0 0 2 &pcie_intc1 1>,
>> 828 <0 0 0 3 &pcie_intc1 2>,
>> 829 <0 0 0 4 &pcie_intc1 3>;
>> 830 pcie_intc1: interrupt-controller {
>> 831 interrupt-controller;
>> 832 #address-cells = <0>;
>> 833 #interrupt-cells = <1>;
>> 834 };
876 }; 835 };
877 }; 836 };
878 837
879 sata: sata@1a200000 { 838 sata: sata@1a200000 {
880 compatible = "mediatek,mt7622- 839 compatible = "mediatek,mt7622-ahci",
881 "mediatek,mtk-ahc 840 "mediatek,mtk-ahci";
882 reg = <0 0x1a200000 0 0x1100>; 841 reg = <0 0x1a200000 0 0x1100>;
883 interrupts = <GIC_SPI 233 IRQ_ 842 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "hostc"; 843 interrupt-names = "hostc";
885 clocks = <&pciesys CLK_SATA_AH 844 clocks = <&pciesys CLK_SATA_AHB_EN>,
886 <&pciesys CLK_SATA_AX 845 <&pciesys CLK_SATA_AXI_EN>,
887 <&pciesys CLK_SATA_AS 846 <&pciesys CLK_SATA_ASIC_EN>,
888 <&pciesys CLK_SATA_RB 847 <&pciesys CLK_SATA_RBC_EN>,
889 <&pciesys CLK_SATA_PM 848 <&pciesys CLK_SATA_PM_EN>;
890 clock-names = "ahb", "axi", "a 849 clock-names = "ahb", "axi", "asic", "rbc", "pm";
891 phys = <&sata_port PHY_TYPE_SA 850 phys = <&sata_port PHY_TYPE_SATA>;
892 phy-names = "sata-phy"; 851 phy-names = "sata-phy";
893 ports-implemented = <0x1>; 852 ports-implemented = <0x1>;
894 power-domains = <&scpsys MT762 853 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
895 resets = <&pciesys MT7622_SATA 854 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
896 <&pciesys MT7622_SATA 855 <&pciesys MT7622_SATA_PHY_SW_RST>,
897 <&pciesys MT7622_SATA 856 <&pciesys MT7622_SATA_PHY_REG_RST>;
898 reset-names = "axi", "sw", "re 857 reset-names = "axi", "sw", "reg";
899 mediatek,phy-mode = <&pciesys> 858 mediatek,phy-mode = <&pciesys>;
900 status = "disabled"; 859 status = "disabled";
901 }; 860 };
902 861
903 sata_phy: t-phy { !! 862 sata_phy: sata-phy@1a243000 {
904 compatible = "mediatek,mt7622- !! 863 compatible = "mediatek,generic-tphy-v1";
905 "mediatek,generic <<
906 #address-cells = <2>; 864 #address-cells = <2>;
907 #size-cells = <2>; 865 #size-cells = <2>;
908 ranges; 866 ranges;
909 status = "disabled"; 867 status = "disabled";
910 868
911 sata_port: sata-phy@1a243000 { 869 sata_port: sata-phy@1a243000 {
912 reg = <0 0x1a243000 0 870 reg = <0 0x1a243000 0 0x0100>;
913 clocks = <&topckgen CL 871 clocks = <&topckgen CLK_TOP_ETH_500M>;
914 clock-names = "ref"; 872 clock-names = "ref";
915 #phy-cells = <1>; 873 #phy-cells = <1>;
916 }; 874 };
917 }; 875 };
918 876
919 hifsys: clock-controller@1af00000 { !! 877 ethsys: syscon@1b000000 {
920 compatible = "mediatek,mt7622- <<
921 reg = <0 0x1af00000 0 0x70>; <<
922 #clock-cells = <1>; <<
923 }; <<
924 <<
925 ethsys: clock-controller@1b000000 { <<
926 compatible = "mediatek,mt7622- 878 compatible = "mediatek,mt7622-ethsys",
927 "syscon"; 879 "syscon";
928 reg = <0 0x1b000000 0 0x1000>; 880 reg = <0 0x1b000000 0 0x1000>;
929 #clock-cells = <1>; 881 #clock-cells = <1>;
930 #reset-cells = <1>; 882 #reset-cells = <1>;
931 }; 883 };
932 884
933 hsdma: dma-controller@1b007000 { 885 hsdma: dma-controller@1b007000 {
934 compatible = "mediatek,mt7622- 886 compatible = "mediatek,mt7622-hsdma";
935 reg = <0 0x1b007000 0 0x1000>; 887 reg = <0 0x1b007000 0 0x1000>;
936 interrupts = <GIC_SPI 219 IRQ_ 888 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
937 clocks = <ðsys CLK_ETH_HSDM 889 clocks = <ðsys CLK_ETH_HSDMA_EN>;
938 clock-names = "hsdma"; 890 clock-names = "hsdma";
939 power-domains = <&scpsys MT762 891 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
940 #dma-cells = <1>; 892 #dma-cells = <1>;
941 dma-requests = <3>; <<
942 }; <<
943 <<
944 pcie_mirror: pcie-mirror@10000400 { <<
945 compatible = "mediatek,mt7622- <<
946 "syscon"; <<
947 reg = <0 0x10000400 0 0x10>; <<
948 }; <<
949 <<
950 wed0: wed@1020a000 { <<
951 compatible = "mediatek,mt7622- <<
952 "syscon"; <<
953 reg = <0 0x1020a000 0 0x1000>; <<
954 interrupts = <GIC_SPI 214 IRQ_ <<
955 }; <<
956 <<
957 wed1: wed@1020b000 { <<
958 compatible = "mediatek,mt7622- <<
959 "syscon"; <<
960 reg = <0 0x1020b000 0 0x1000>; <<
961 interrupts = <GIC_SPI 215 IRQ_ <<
962 }; 893 };
963 894
964 eth: ethernet@1b100000 { 895 eth: ethernet@1b100000 {
965 compatible = "mediatek,mt7622- !! 896 compatible = "mediatek,mt7622-eth",
>> 897 "mediatek,mt2701-eth",
>> 898 "syscon";
966 reg = <0 0x1b100000 0 0x20000> 899 reg = <0 0x1b100000 0 0x20000>;
967 interrupts = <GIC_SPI 223 IRQ_ 900 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
968 <GIC_SPI 224 IRQ_ 901 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
969 <GIC_SPI 225 IRQ_ 902 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
970 clocks = <&topckgen CLK_TOP_ET 903 clocks = <&topckgen CLK_TOP_ETH_SEL>,
971 <ðsys CLK_ETH_ESW_ 904 <ðsys CLK_ETH_ESW_EN>,
972 <ðsys CLK_ETH_GP0_ 905 <ðsys CLK_ETH_GP0_EN>,
973 <ðsys CLK_ETH_GP1_ 906 <ðsys CLK_ETH_GP1_EN>,
974 <ðsys CLK_ETH_GP2_ 907 <ðsys CLK_ETH_GP2_EN>,
975 <&sgmiisys CLK_SGMII_ 908 <&sgmiisys CLK_SGMII_TX250M_EN>,
976 <&sgmiisys CLK_SGMII_ 909 <&sgmiisys CLK_SGMII_RX250M_EN>,
977 <&sgmiisys CLK_SGMII_ 910 <&sgmiisys CLK_SGMII_CDR_REF>,
978 <&sgmiisys CLK_SGMII_ 911 <&sgmiisys CLK_SGMII_CDR_FB>,
979 <&topckgen CLK_TOP_SG 912 <&topckgen CLK_TOP_SGMIIPLL>,
980 <&apmixedsys CLK_APMI 913 <&apmixedsys CLK_APMIXED_ETH2PLL>;
981 clock-names = "ethif", "esw", 914 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
982 "sgmii_tx250m", 915 "sgmii_tx250m", "sgmii_rx250m",
983 "sgmii_cdr_ref", 916 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
984 "eth2pll"; 917 "eth2pll";
985 power-domains = <&scpsys MT762 918 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
986 mediatek,ethsys = <ðsys>; 919 mediatek,ethsys = <ðsys>;
987 mediatek,sgmiisys = <&sgmiisys 920 mediatek,sgmiisys = <&sgmiisys>;
988 cci-control-port = <&cci_contr <<
989 mediatek,wed = <&wed0>, <&wed1 <<
990 mediatek,pcie-mirror = <&pcie_ <<
991 mediatek,hifsys = <&hifsys>; <<
992 dma-coherent; <<
993 #address-cells = <1>; 921 #address-cells = <1>;
994 #size-cells = <0>; 922 #size-cells = <0>;
995 status = "disabled"; 923 status = "disabled";
996 }; 924 };
997 925
998 sgmiisys: sgmiisys@1b128000 { 926 sgmiisys: sgmiisys@1b128000 {
999 compatible = "mediatek,mt7622- 927 compatible = "mediatek,mt7622-sgmiisys",
1000 "syscon"; 928 "syscon";
1001 reg = <0 0x1b128000 0 0x3000> !! 929 reg = <0 0x1b128000 0 0x1000>;
1002 #clock-cells = <1>; 930 #clock-cells = <1>;
1003 }; 931 };
1004 }; 932 };
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