1 /* 1 /*
2 * Copyright (c) 2017 MediaTek Inc. 2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com> 3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com>
5 * 5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h> 11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h> 13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h> 14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 compatible = "mediatek,mt7622"; 18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>; 19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 cpu_opp_table: opp-table { 23 cpu_opp_table: opp-table {
24 compatible = "operating-points 24 compatible = "operating-points-v2";
25 opp-shared; 25 opp-shared;
26 opp-300000000 { 26 opp-300000000 {
27 opp-hz = /bits/ 64 <30 27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <95000 28 opp-microvolt = <950000>;
29 }; 29 };
30 30
31 opp-437500000 { 31 opp-437500000 {
32 opp-hz = /bits/ 64 <43 32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <10000 33 opp-microvolt = <1000000>;
34 }; 34 };
35 35
36 opp-600000000 { 36 opp-600000000 {
37 opp-hz = /bits/ 64 <60 37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <10500 38 opp-microvolt = <1050000>;
39 }; 39 };
40 40
41 opp-812500000 { 41 opp-812500000 {
42 opp-hz = /bits/ 64 <81 42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <11000 43 opp-microvolt = <1100000>;
44 }; 44 };
45 45
46 opp-1025000000 { 46 opp-1025000000 {
47 opp-hz = /bits/ 64 <10 47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <11500 48 opp-microvolt = <1150000>;
49 }; 49 };
50 50
51 opp-1137500000 { 51 opp-1137500000 {
52 opp-hz = /bits/ 64 <11 52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <12000 53 opp-microvolt = <1200000>;
54 }; 54 };
55 55
56 opp-1262500000 { 56 opp-1262500000 {
57 opp-hz = /bits/ 64 <12 57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <12500 58 opp-microvolt = <1250000>;
59 }; 59 };
60 60
61 opp-1350000000 { 61 opp-1350000000 {
62 opp-hz = /bits/ 64 <13 62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <13100 63 opp-microvolt = <1310000>;
64 }; 64 };
65 }; 65 };
66 66
67 cpus { 67 cpus {
68 #address-cells = <2>; 68 #address-cells = <2>;
69 #size-cells = <0>; 69 #size-cells = <0>;
70 70
71 cpu0: cpu@0 { 71 cpu0: cpu@0 {
72 device_type = "cpu"; 72 device_type = "cpu";
73 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
74 reg = <0x0 0x0>; 74 reg = <0x0 0x0>;
75 clocks = <&infracfg CL 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", " 77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = 78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 enable-method = "psci" 80 enable-method = "psci";
81 clock-frequency = <130 81 clock-frequency = <1300000000>;
82 cci-control-port = <&c 82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L 83 next-level-cache = <&L2>;
84 }; 84 };
85 85
86 cpu1: cpu@1 { 86 cpu1: cpu@1 {
87 device_type = "cpu"; 87 device_type = "cpu";
88 compatible = "arm,cort 88 compatible = "arm,cortex-a53";
89 reg = <0x0 0x1>; 89 reg = <0x0 0x1>;
90 clocks = <&infracfg CL 90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys 91 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", " 92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = 93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; 94 #cooling-cells = <2>;
95 enable-method = "psci" 95 enable-method = "psci";
96 clock-frequency = <130 96 clock-frequency = <1300000000>;
97 cci-control-port = <&c 97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L 98 next-level-cache = <&L2>;
99 }; 99 };
100 100
101 L2: l2-cache { 101 L2: l2-cache {
102 compatible = "cache"; 102 compatible = "cache";
103 cache-level = <2>; 103 cache-level = <2>;
104 cache-unified; 104 cache-unified;
105 }; 105 };
106 }; 106 };
107 107
108 pwrap_clk: dummy40m { 108 pwrap_clk: dummy40m {
109 compatible = "fixed-clock"; 109 compatible = "fixed-clock";
110 clock-frequency = <40000000>; 110 clock-frequency = <40000000>;
111 #clock-cells = <0>; 111 #clock-cells = <0>;
112 }; 112 };
113 113
114 clk25m: oscillator { 114 clk25m: oscillator {
115 compatible = "fixed-clock"; 115 compatible = "fixed-clock";
116 #clock-cells = <0>; 116 #clock-cells = <0>;
117 clock-frequency = <25000000>; 117 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal" 118 clock-output-names = "clkxtal";
119 }; 119 };
120 120
121 psci { 121 psci {
122 compatible = "arm,psci-0.2"; 122 compatible = "arm,psci-0.2";
123 method = "smc"; 123 method = "smc";
124 }; 124 };
125 125
126 pmu { 126 pmu {
127 compatible = "arm,cortex-a53-p 127 compatible = "arm,cortex-a53-pmu";
128 interrupts = <GIC_SPI 8 IRQ_TY 128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 9 IRQ_TY 129 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
130 interrupt-affinity = <&cpu0>, 130 interrupt-affinity = <&cpu0>, <&cpu1>;
131 }; 131 };
132 132
133 reserved-memory { 133 reserved-memory {
134 #address-cells = <2>; 134 #address-cells = <2>;
135 #size-cells = <2>; 135 #size-cells = <2>;
136 ranges; 136 ranges;
137 137
138 /* 192 KiB reserved for ARM Tr 138 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
139 secmon_reserved: secmon@430000 139 secmon_reserved: secmon@43000000 {
140 reg = <0 0x43000000 0 140 reg = <0 0x43000000 0 0x30000>;
141 no-map; 141 no-map;
142 }; 142 };
143 }; 143 };
144 144
145 thermal-zones { 145 thermal-zones {
146 cpu_thermal: cpu-thermal { 146 cpu_thermal: cpu-thermal {
147 polling-delay-passive 147 polling-delay-passive = <1000>;
148 polling-delay = <1000> 148 polling-delay = <1000>;
149 149
150 thermal-sensors = <&th 150 thermal-sensors = <&thermal 0>;
151 151
152 trips { 152 trips {
153 cpu_passive: c 153 cpu_passive: cpu-passive {
154 temper 154 temperature = <47000>;
155 hyster 155 hysteresis = <2000>;
156 type = 156 type = "passive";
157 }; 157 };
158 158
159 cpu_active: cp 159 cpu_active: cpu-active {
160 temper 160 temperature = <67000>;
161 hyster 161 hysteresis = <2000>;
162 type = 162 type = "active";
163 }; 163 };
164 164
165 cpu_hot: cpu-h 165 cpu_hot: cpu-hot {
166 temper 166 temperature = <87000>;
167 hyster 167 hysteresis = <2000>;
168 type = 168 type = "hot";
169 }; 169 };
170 170
171 cpu-crit { 171 cpu-crit {
172 temper 172 temperature = <107000>;
173 hyster 173 hysteresis = <2000>;
174 type = 174 type = "critical";
175 }; 175 };
176 }; 176 };
177 177
178 cooling-maps { 178 cooling-maps {
179 map0 { 179 map0 {
180 trip = 180 trip = <&cpu_passive>;
181 coolin 181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182 182 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
183 }; 183 };
184 184
185 map1 { 185 map1 {
186 trip = 186 trip = <&cpu_active>;
187 coolin 187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189 }; 189 };
190 190
191 map2 { 191 map2 {
192 trip = 192 trip = <&cpu_hot>;
193 coolin 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
195 }; 195 };
196 }; 196 };
197 }; 197 };
198 }; 198 };
199 199
200 timer { 200 timer {
201 compatible = "arm,armv8-timer" 201 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>; 202 interrupt-parent = <&gic>;
203 interrupts = <GIC_PPI 13 (GIC_ 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_LEVEL_H 204 IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_ 205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_LEVEL_H 206 IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 (GIC_ 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_LEVEL_H 208 IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 (GIC_ 209 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_LEVEL_H 210 IRQ_TYPE_LEVEL_HIGH)>;
211 }; 211 };
212 212
213 infracfg: infracfg@10000000 { 213 infracfg: infracfg@10000000 {
214 compatible = "mediatek,mt7622- 214 compatible = "mediatek,mt7622-infracfg",
215 "syscon"; 215 "syscon";
216 reg = <0 0x10000000 0 0x1000>; 216 reg = <0 0x10000000 0 0x1000>;
217 #clock-cells = <1>; 217 #clock-cells = <1>;
218 #reset-cells = <1>; 218 #reset-cells = <1>;
219 }; 219 };
220 220
221 pwrap: pwrap@10001000 { 221 pwrap: pwrap@10001000 {
222 compatible = "mediatek,mt7622- 222 compatible = "mediatek,mt7622-pwrap";
223 reg = <0 0x10001000 0 0x250>; 223 reg = <0 0x10001000 0 0x250>;
224 reg-names = "pwrap"; 224 reg-names = "pwrap";
225 clocks = <&infracfg CLK_INFRA_ 225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
226 clock-names = "spi", "wrap"; 226 clock-names = "spi", "wrap";
227 resets = <&infracfg MT7622_INF 227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
228 reset-names = "pwrap"; 228 reset-names = "pwrap";
229 interrupts = <GIC_SPI 163 IRQ_ 229 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
230 status = "disabled"; 230 status = "disabled";
231 }; 231 };
232 232
233 pericfg: pericfg@10002000 { 233 pericfg: pericfg@10002000 {
234 compatible = "mediatek,mt7622- 234 compatible = "mediatek,mt7622-pericfg",
235 "syscon"; 235 "syscon";
236 reg = <0 0x10002000 0 0x1000>; 236 reg = <0 0x10002000 0 0x1000>;
237 #clock-cells = <1>; 237 #clock-cells = <1>;
238 #reset-cells = <1>; 238 #reset-cells = <1>;
239 }; 239 };
240 240
241 scpsys: power-controller@10006000 { 241 scpsys: power-controller@10006000 {
242 compatible = "mediatek,mt7622- 242 compatible = "mediatek,mt7622-scpsys",
243 "syscon"; 243 "syscon";
244 #power-domain-cells = <1>; 244 #power-domain-cells = <1>;
245 reg = <0 0x10006000 0 0x1000>; 245 reg = <0 0x10006000 0 0x1000>;
246 interrupts = <GIC_SPI 165 IRQ_ 246 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 166 IRQ_ 247 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 167 IRQ_ 248 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
249 <GIC_SPI 168 IRQ_ 249 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
250 infracfg = <&infracfg>; 250 infracfg = <&infracfg>;
251 clocks = <&topckgen CLK_TOP_HI 251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 clock-names = "hif_sel"; 252 clock-names = "hif_sel";
253 }; 253 };
254 254
255 cir: ir-receiver@10009000 { 255 cir: ir-receiver@10009000 {
256 compatible = "mediatek,mt7622- 256 compatible = "mediatek,mt7622-cir";
257 reg = <0 0x10009000 0 0x1000>; 257 reg = <0 0x10009000 0 0x1000>;
258 interrupts = <GIC_SPI 175 IRQ_ 258 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
259 clocks = <&infracfg CLK_INFRA_ 259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
260 <&topckgen CLK_TOP_AX 260 <&topckgen CLK_TOP_AXI_SEL>;
261 clock-names = "clk", "bus"; 261 clock-names = "clk", "bus";
262 status = "disabled"; 262 status = "disabled";
263 }; 263 };
264 264
265 sysirq: interrupt-controller@10200620 265 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622- 266 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577- 267 "mediatek,mt6577-sysirq";
268 interrupt-controller; 268 interrupt-controller;
269 #interrupt-cells = <3>; 269 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>; 270 interrupt-parent = <&gic>;
271 reg = <0 0x10200620 0 0x20>; 271 reg = <0 0x10200620 0 0x20>;
272 }; 272 };
273 273
274 efuse: efuse@10206000 { 274 efuse: efuse@10206000 {
275 compatible = "mediatek,mt7622- 275 compatible = "mediatek,mt7622-efuse",
276 "mediatek,efuse"; 276 "mediatek,efuse";
277 reg = <0 0x10206000 0 0x1000>; 277 reg = <0 0x10206000 0 0x1000>;
278 #address-cells = <1>; 278 #address-cells = <1>;
279 #size-cells = <1>; 279 #size-cells = <1>;
280 280
281 thermal_calibration: calib@198 281 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>; 282 reg = <0x198 0xc>;
283 }; 283 };
284 }; 284 };
285 285
286 apmixedsys: clock-controller@10209000 286 apmixedsys: clock-controller@10209000 {
287 compatible = "mediatek,mt7622- 287 compatible = "mediatek,mt7622-apmixedsys";
288 reg = <0 0x10209000 0 0x1000>; 288 reg = <0 0x10209000 0 0x1000>;
289 #clock-cells = <1>; 289 #clock-cells = <1>;
290 }; 290 };
291 291
292 topckgen: clock-controller@10210000 { 292 topckgen: clock-controller@10210000 {
293 compatible = "mediatek,mt7622- 293 compatible = "mediatek,mt7622-topckgen";
294 reg = <0 0x10210000 0 0x1000>; 294 reg = <0 0x10210000 0 0x1000>;
295 #clock-cells = <1>; 295 #clock-cells = <1>;
296 }; 296 };
297 297
298 rng: rng@1020f000 { 298 rng: rng@1020f000 {
299 compatible = "mediatek,mt7622- 299 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623- 300 "mediatek,mt7623-rng";
301 reg = <0 0x1020f000 0 0x1000>; 301 reg = <0 0x1020f000 0 0x1000>;
302 clocks = <&infracfg CLK_INFRA_ 302 clocks = <&infracfg CLK_INFRA_TRNG>;
303 clock-names = "rng"; 303 clock-names = "rng";
304 }; 304 };
305 305
306 pio: pinctrl@10211000 { 306 pio: pinctrl@10211000 {
307 compatible = "mediatek,mt7622- 307 compatible = "mediatek,mt7622-pinctrl";
308 reg = <0 0x10211000 0 0x1000>, 308 reg = <0 0x10211000 0 0x1000>,
309 <0 0x10005000 0 0x1000>; 309 <0 0x10005000 0 0x1000>;
310 reg-names = "base", "eint"; 310 reg-names = "base", "eint";
311 gpio-controller; 311 gpio-controller;
312 #gpio-cells = <2>; 312 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 103>; 313 gpio-ranges = <&pio 0 0 103>;
314 interrupt-controller; 314 interrupt-controller;
315 interrupts = <GIC_SPI 153 IRQ_ 315 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-parent = <&gic>; 316 interrupt-parent = <&gic>;
317 #interrupt-cells = <2>; 317 #interrupt-cells = <2>;
318 }; 318 };
319 319
320 watchdog: watchdog@10212000 { 320 watchdog: watchdog@10212000 {
321 compatible = "mediatek,mt7622- 321 compatible = "mediatek,mt7622-wdt",
322 "mediatek,mt6589- 322 "mediatek,mt6589-wdt";
323 reg = <0 0x10212000 0 0x800>; 323 reg = <0 0x10212000 0 0x800>;
324 }; 324 };
325 325
326 rtc: rtc@10212800 { 326 rtc: rtc@10212800 {
327 compatible = "mediatek,mt7622- 327 compatible = "mediatek,mt7622-rtc",
328 "mediatek,soc-rtc 328 "mediatek,soc-rtc";
329 reg = <0 0x10212800 0 0x200>; 329 reg = <0 0x10212800 0 0x200>;
330 interrupts = <GIC_SPI 129 IRQ_ 330 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
331 clocks = <&topckgen CLK_TOP_RT 331 clocks = <&topckgen CLK_TOP_RTC>;
332 clock-names = "rtc"; 332 clock-names = "rtc";
333 }; 333 };
334 334
335 gic: interrupt-controller@10300000 { 335 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400"; 336 compatible = "arm,gic-400";
337 interrupt-controller; 337 interrupt-controller;
338 #interrupt-cells = <3>; 338 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>; 339 interrupt-parent = <&gic>;
340 reg = <0 0x10310000 0 0x1000>, 340 reg = <0 0x10310000 0 0x1000>,
341 <0 0x10320000 0 0x1000>, 341 <0 0x10320000 0 0x1000>,
342 <0 0x10340000 0 0x2000>, 342 <0 0x10340000 0 0x2000>,
343 <0 0x10360000 0 0x2000>; 343 <0 0x10360000 0 0x2000>;
344 }; 344 };
345 345
346 cci: cci@10390000 { 346 cci: cci@10390000 {
347 compatible = "arm,cci-400"; 347 compatible = "arm,cci-400";
348 #address-cells = <1>; 348 #address-cells = <1>;
349 #size-cells = <1>; 349 #size-cells = <1>;
350 reg = <0 0x10390000 0 0x1000>; 350 reg = <0 0x10390000 0 0x1000>;
351 ranges = <0 0 0x10390000 0x100 351 ranges = <0 0 0x10390000 0x10000>;
352 352
353 cci_control0: slave-if@1000 { 353 cci_control0: slave-if@1000 {
354 compatible = "arm,cci- 354 compatible = "arm,cci-400-ctrl-if";
355 interface-type = "ace- 355 interface-type = "ace-lite";
356 reg = <0x1000 0x1000>; 356 reg = <0x1000 0x1000>;
357 }; 357 };
358 358
359 cci_control1: slave-if@4000 { 359 cci_control1: slave-if@4000 {
360 compatible = "arm,cci- 360 compatible = "arm,cci-400-ctrl-if";
361 interface-type = "ace" 361 interface-type = "ace";
362 reg = <0x4000 0x1000>; 362 reg = <0x4000 0x1000>;
363 }; 363 };
364 364
365 cci_control2: slave-if@5000 { 365 cci_control2: slave-if@5000 {
366 compatible = "arm,cci- 366 compatible = "arm,cci-400-ctrl-if", "syscon";
367 interface-type = "ace" 367 interface-type = "ace";
368 reg = <0x5000 0x1000>; 368 reg = <0x5000 0x1000>;
369 }; 369 };
370 370
371 pmu@9000 { 371 pmu@9000 {
372 compatible = "arm,cci- 372 compatible = "arm,cci-400-pmu,r1";
373 reg = <0x9000 0x5000>; 373 reg = <0x9000 0x5000>;
374 interrupts = <GIC_SPI 374 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 375 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 376 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 377 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 378 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
379 }; 379 };
380 }; 380 };
381 381
382 auxadc: adc@11001000 { 382 auxadc: adc@11001000 {
383 compatible = "mediatek,mt7622- 383 compatible = "mediatek,mt7622-auxadc";
384 reg = <0 0x11001000 0 0x1000>; 384 reg = <0 0x11001000 0 0x1000>;
385 clocks = <&pericfg CLK_PERI_AU 385 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
386 clock-names = "main"; 386 clock-names = "main";
387 #io-channel-cells = <1>; 387 #io-channel-cells = <1>;
388 }; 388 };
389 389
390 uart0: serial@11002000 { 390 uart0: serial@11002000 {
391 compatible = "mediatek,mt7622- 391 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577- 392 "mediatek,mt6577-uart";
393 reg = <0 0x11002000 0 0x400>; 393 reg = <0 0x11002000 0 0x400>;
394 interrupts = <GIC_SPI 91 IRQ_T 394 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&topckgen CLK_TOP_UA 395 clocks = <&topckgen CLK_TOP_UART_SEL>,
396 <&pericfg CLK_PERI_UA 396 <&pericfg CLK_PERI_UART0_PD>;
397 clock-names = "baud", "bus"; 397 clock-names = "baud", "bus";
398 status = "disabled"; 398 status = "disabled";
399 }; 399 };
400 400
401 uart1: serial@11003000 { 401 uart1: serial@11003000 {
402 compatible = "mediatek,mt7622- 402 compatible = "mediatek,mt7622-uart",
403 "mediatek,mt6577- 403 "mediatek,mt6577-uart";
404 reg = <0 0x11003000 0 0x400>; 404 reg = <0 0x11003000 0 0x400>;
405 interrupts = <GIC_SPI 92 IRQ_T 405 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
406 clocks = <&topckgen CLK_TOP_UA 406 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 <&pericfg CLK_PERI_UA 407 <&pericfg CLK_PERI_UART1_PD>;
408 clock-names = "baud", "bus"; 408 clock-names = "baud", "bus";
409 status = "disabled"; 409 status = "disabled";
410 }; 410 };
411 411
412 uart2: serial@11004000 { 412 uart2: serial@11004000 {
413 compatible = "mediatek,mt7622- 413 compatible = "mediatek,mt7622-uart",
414 "mediatek,mt6577- 414 "mediatek,mt6577-uart";
415 reg = <0 0x11004000 0 0x400>; 415 reg = <0 0x11004000 0 0x400>;
416 interrupts = <GIC_SPI 93 IRQ_T 416 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&topckgen CLK_TOP_UA 417 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 <&pericfg CLK_PERI_UA 418 <&pericfg CLK_PERI_UART2_PD>;
419 clock-names = "baud", "bus"; 419 clock-names = "baud", "bus";
420 status = "disabled"; 420 status = "disabled";
421 }; 421 };
422 422
423 uart3: serial@11005000 { 423 uart3: serial@11005000 {
424 compatible = "mediatek,mt7622- 424 compatible = "mediatek,mt7622-uart",
425 "mediatek,mt6577- 425 "mediatek,mt6577-uart";
426 reg = <0 0x11005000 0 0x400>; 426 reg = <0 0x11005000 0 0x400>;
427 interrupts = <GIC_SPI 94 IRQ_T 427 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
428 clocks = <&topckgen CLK_TOP_UA 428 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 <&pericfg CLK_PERI_UA 429 <&pericfg CLK_PERI_UART3_PD>;
430 clock-names = "baud", "bus"; 430 clock-names = "baud", "bus";
431 status = "disabled"; 431 status = "disabled";
432 }; 432 };
433 433
434 pwm: pwm@11006000 { 434 pwm: pwm@11006000 {
435 compatible = "mediatek,mt7622- 435 compatible = "mediatek,mt7622-pwm";
436 reg = <0 0x11006000 0 0x1000>; 436 reg = <0 0x11006000 0 0x1000>;
437 #pwm-cells = <2>; 437 #pwm-cells = <2>;
438 interrupts = <GIC_SPI 77 IRQ_T 438 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_PW 439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
440 <&pericfg CLK_PERI_PW 440 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PW 441 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PW 442 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PW 443 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PW 444 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PW 445 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PW 446 <&pericfg CLK_PERI_PWM6_PD>;
447 clock-names = "top", "main", " 447 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
448 "pwm5", "pwm6"; 448 "pwm5", "pwm6";
449 status = "disabled"; 449 status = "disabled";
450 }; 450 };
451 451
452 i2c0: i2c@11007000 { 452 i2c0: i2c@11007000 {
453 compatible = "mediatek,mt7622- 453 compatible = "mediatek,mt7622-i2c";
454 reg = <0 0x11007000 0 0x90>, 454 reg = <0 0x11007000 0 0x90>,
455 <0 0x11000100 0 0x80>; 455 <0 0x11000100 0 0x80>;
456 interrupts = <GIC_SPI 84 IRQ_T 456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
457 clock-div = <16>; 457 clock-div = <16>;
458 clocks = <&pericfg CLK_PERI_I2 458 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP 459 <&pericfg CLK_PERI_AP_DMA_PD>;
460 clock-names = "main", "dma"; 460 clock-names = "main", "dma";
461 #address-cells = <1>; 461 #address-cells = <1>;
462 #size-cells = <0>; 462 #size-cells = <0>;
463 status = "disabled"; 463 status = "disabled";
464 }; 464 };
465 465
466 i2c1: i2c@11008000 { 466 i2c1: i2c@11008000 {
467 compatible = "mediatek,mt7622- 467 compatible = "mediatek,mt7622-i2c";
468 reg = <0 0x11008000 0 0x90>, 468 reg = <0 0x11008000 0 0x90>,
469 <0 0x11000180 0 0x80>; 469 <0 0x11000180 0 0x80>;
470 interrupts = <GIC_SPI 85 IRQ_T 470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
471 clock-div = <16>; 471 clock-div = <16>;
472 clocks = <&pericfg CLK_PERI_I2 472 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP 473 <&pericfg CLK_PERI_AP_DMA_PD>;
474 clock-names = "main", "dma"; 474 clock-names = "main", "dma";
475 #address-cells = <1>; 475 #address-cells = <1>;
476 #size-cells = <0>; 476 #size-cells = <0>;
477 status = "disabled"; 477 status = "disabled";
478 }; 478 };
479 479
480 i2c2: i2c@11009000 { 480 i2c2: i2c@11009000 {
481 compatible = "mediatek,mt7622- 481 compatible = "mediatek,mt7622-i2c";
482 reg = <0 0x11009000 0 0x90>, 482 reg = <0 0x11009000 0 0x90>,
483 <0 0x11000200 0 0x80>; 483 <0 0x11000200 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_T 484 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
485 clock-div = <16>; 485 clock-div = <16>;
486 clocks = <&pericfg CLK_PERI_I2 486 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP 487 <&pericfg CLK_PERI_AP_DMA_PD>;
488 clock-names = "main", "dma"; 488 clock-names = "main", "dma";
489 #address-cells = <1>; 489 #address-cells = <1>;
490 #size-cells = <0>; 490 #size-cells = <0>;
491 status = "disabled"; 491 status = "disabled";
492 }; 492 };
493 493
494 spi0: spi@1100a000 { 494 spi0: spi@1100a000 {
495 compatible = "mediatek,mt7622- 495 compatible = "mediatek,mt7622-spi";
496 reg = <0 0x1100a000 0 0x100>; 496 reg = <0 0x1100a000 0 0x100>;
497 interrupts = <GIC_SPI 118 IRQ_ 497 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&topckgen CLK_TOP_SY 498 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SP 499 <&topckgen CLK_TOP_SPI0_SEL>,
500 <&pericfg CLK_PERI_SP 500 <&pericfg CLK_PERI_SPI0_PD>;
501 clock-names = "parent-clk", "s 501 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>; 502 #address-cells = <1>;
503 #size-cells = <0>; 503 #size-cells = <0>;
504 status = "disabled"; 504 status = "disabled";
505 }; 505 };
506 506
507 thermal: thermal@1100b000 { 507 thermal: thermal@1100b000 {
508 #thermal-sensor-cells = <1>; 508 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622- 509 compatible = "mediatek,mt7622-thermal";
510 reg = <0 0x1100b000 0 0x1000>; 510 reg = <0 0x1100b000 0 0x1000>;
511 interrupts = <0 78 IRQ_TYPE_LE 511 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_TH 512 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AU 513 <&pericfg CLK_PERI_AUXADC_PD>;
514 clock-names = "therm", "auxadc 514 clock-names = "therm", "auxadc";
515 resets = <&pericfg MT7622_PERI 515 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
516 mediatek,auxadc = <&auxadc>; 516 mediatek,auxadc = <&auxadc>;
517 mediatek,apmixedsys = <&apmixe 517 mediatek,apmixedsys = <&apmixedsys>;
518 nvmem-cells = <&thermal_calibr 518 nvmem-cells = <&thermal_calibration>;
519 nvmem-cell-names = "calibratio 519 nvmem-cell-names = "calibration-data";
520 }; 520 };
521 521
522 btif: serial@1100c000 { 522 btif: serial@1100c000 {
523 compatible = "mediatek,mt7622- 523 compatible = "mediatek,mt7622-btif",
524 "mediatek,mtk-bti 524 "mediatek,mtk-btif";
525 reg = <0 0x1100c000 0 0x1000>; 525 reg = <0 0x1100c000 0 0x1000>;
526 interrupts = <GIC_SPI 90 IRQ_T 526 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&pericfg CLK_PERI_BT 527 clocks = <&pericfg CLK_PERI_BTIF_PD>;
528 reg-shift = <2>; 528 reg-shift = <2>;
529 reg-io-width = <4>; 529 reg-io-width = <4>;
530 status = "disabled"; 530 status = "disabled";
531 531
532 bluetooth { 532 bluetooth {
533 compatible = "mediatek 533 compatible = "mediatek,mt7622-bluetooth";
534 power-domains = <&scps 534 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
535 clocks = <&clk25m>; 535 clocks = <&clk25m>;
536 clock-names = "ref"; 536 clock-names = "ref";
537 }; 537 };
538 }; 538 };
539 539
540 nandc: nand-controller@1100d000 { 540 nandc: nand-controller@1100d000 {
541 compatible = "mediatek,mt7622- 541 compatible = "mediatek,mt7622-nfc";
542 reg = <0 0x1100D000 0 0x1000>; 542 reg = <0 0x1100D000 0 0x1000>;
543 interrupts = <GIC_SPI 96 IRQ_T 543 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
544 clocks = <&pericfg CLK_PERI_NF 544 clocks = <&pericfg CLK_PERI_NFI_PD>,
545 <&pericfg CLK_PERI_SN 545 <&pericfg CLK_PERI_SNFI_PD>;
546 clock-names = "nfi_clk", "pad_ 546 clock-names = "nfi_clk", "pad_clk";
547 ecc-engine = <&bch>; 547 ecc-engine = <&bch>;
548 #address-cells = <1>; 548 #address-cells = <1>;
549 #size-cells = <0>; 549 #size-cells = <0>;
550 status = "disabled"; 550 status = "disabled";
551 }; 551 };
552 552
553 snfi: spi@1100d000 { 553 snfi: spi@1100d000 {
554 compatible = "mediatek,mt7622- 554 compatible = "mediatek,mt7622-snand";
555 reg = <0 0x1100d000 0 0x1000>; 555 reg = <0 0x1100d000 0 0x1000>;
556 interrupts = <GIC_SPI 96 IRQ_T 556 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
557 clocks = <&pericfg CLK_PERI_NF 557 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
558 clock-names = "nfi_clk", "pad_ 558 clock-names = "nfi_clk", "pad_clk";
559 nand-ecc-engine = <&bch>; 559 nand-ecc-engine = <&bch>;
560 #address-cells = <1>; 560 #address-cells = <1>;
561 #size-cells = <0>; 561 #size-cells = <0>;
562 status = "disabled"; 562 status = "disabled";
563 }; 563 };
564 564
565 bch: ecc@1100e000 { 565 bch: ecc@1100e000 {
566 compatible = "mediatek,mt7622- 566 compatible = "mediatek,mt7622-ecc";
567 reg = <0 0x1100e000 0 0x1000>; 567 reg = <0 0x1100e000 0 0x1000>;
568 interrupts = <GIC_SPI 95 IRQ_T 568 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
569 clocks = <&pericfg CLK_PERI_NF 569 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
570 clock-names = "nfiecc_clk"; 570 clock-names = "nfiecc_clk";
571 status = "disabled"; 571 status = "disabled";
572 }; 572 };
573 573
574 nor_flash: spi@11014000 { 574 nor_flash: spi@11014000 {
575 compatible = "mediatek,mt7622- 575 compatible = "mediatek,mt7622-nor",
576 "mediatek,mt8173- 576 "mediatek,mt8173-nor";
577 reg = <0 0x11014000 0 0xe0>; 577 reg = <0 0x11014000 0 0xe0>;
578 clocks = <&pericfg CLK_PERI_FL 578 clocks = <&pericfg CLK_PERI_FLASH_PD>,
579 <&topckgen CLK_TOP_FL 579 <&topckgen CLK_TOP_FLASH_SEL>;
580 clock-names = "spi", "sf"; 580 clock-names = "spi", "sf";
581 #address-cells = <1>; 581 #address-cells = <1>;
582 #size-cells = <0>; 582 #size-cells = <0>;
583 status = "disabled"; 583 status = "disabled";
584 }; 584 };
585 585
586 spi1: spi@11016000 { 586 spi1: spi@11016000 {
587 compatible = "mediatek,mt7622- 587 compatible = "mediatek,mt7622-spi";
588 reg = <0 0x11016000 0 0x100>; 588 reg = <0 0x11016000 0 0x100>;
589 interrupts = <GIC_SPI 122 IRQ_ 589 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&topckgen CLK_TOP_SY 590 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SP 591 <&topckgen CLK_TOP_SPI1_SEL>,
592 <&pericfg CLK_PERI_SP 592 <&pericfg CLK_PERI_SPI1_PD>;
593 clock-names = "parent-clk", "s 593 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 #address-cells = <1>; 594 #address-cells = <1>;
595 #size-cells = <0>; 595 #size-cells = <0>;
596 status = "disabled"; 596 status = "disabled";
597 }; 597 };
598 598
599 uart4: serial@11019000 { 599 uart4: serial@11019000 {
600 compatible = "mediatek,mt7622- 600 compatible = "mediatek,mt7622-uart",
601 "mediatek,mt6577- 601 "mediatek,mt6577-uart";
602 reg = <0 0x11019000 0 0x400>; 602 reg = <0 0x11019000 0 0x400>;
603 interrupts = <GIC_SPI 89 IRQ_T 603 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CLK_TOP_UA 604 clocks = <&topckgen CLK_TOP_UART_SEL>,
605 <&pericfg CLK_PERI_UA 605 <&pericfg CLK_PERI_UART4_PD>;
606 clock-names = "baud", "bus"; 606 clock-names = "baud", "bus";
607 status = "disabled"; 607 status = "disabled";
608 }; 608 };
609 609
610 audsys: clock-controller@11220000 { 610 audsys: clock-controller@11220000 {
611 compatible = "mediatek,mt7622- 611 compatible = "mediatek,mt7622-audsys", "syscon";
612 reg = <0 0x11220000 0 0x2000>; 612 reg = <0 0x11220000 0 0x2000>;
613 #clock-cells = <1>; 613 #clock-cells = <1>;
614 614
615 afe: audio-controller { 615 afe: audio-controller {
616 compatible = "mediatek 616 compatible = "mediatek,mt7622-audio";
617 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
618 <GIC_SPI 618 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
619 interrupt-names = "afe 619 interrupt-names = "afe", "asys";
620 620
621 clocks = <&infracfg CL 621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
622 <&topckgen CL 622 <&topckgen CLK_TOP_AUD1_SEL>,
623 <&topckgen CL 623 <&topckgen CLK_TOP_AUD2_SEL>,
624 <&topckgen CL 624 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
625 <&topckgen CL 625 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
626 <&topckgen CL 626 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
627 <&topckgen CL 627 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
628 <&topckgen CL 628 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
629 <&topckgen CL 629 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
630 <&topckgen CL 630 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
631 <&topckgen CL 631 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
632 <&topckgen CL 632 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
633 <&topckgen CL 633 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
634 <&topckgen CL 634 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
635 <&topckgen CL 635 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
636 <&topckgen CL 636 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
637 <&topckgen CL 637 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
638 <&audsys CLK_ 638 <&audsys CLK_AUDIO_I2SO1>,
639 <&audsys CLK_ 639 <&audsys CLK_AUDIO_I2SO2>,
640 <&audsys CLK_ 640 <&audsys CLK_AUDIO_I2SO3>,
641 <&audsys CLK_ 641 <&audsys CLK_AUDIO_I2SO4>,
642 <&audsys CLK_ 642 <&audsys CLK_AUDIO_I2SIN1>,
643 <&audsys CLK_ 643 <&audsys CLK_AUDIO_I2SIN2>,
644 <&audsys CLK_ 644 <&audsys CLK_AUDIO_I2SIN3>,
645 <&audsys CLK_ 645 <&audsys CLK_AUDIO_I2SIN4>,
646 <&audsys CLK_ 646 <&audsys CLK_AUDIO_ASRCO1>,
647 <&audsys CLK_ 647 <&audsys CLK_AUDIO_ASRCO2>,
648 <&audsys CLK_ 648 <&audsys CLK_AUDIO_ASRCO3>,
649 <&audsys CLK_ 649 <&audsys CLK_AUDIO_ASRCO4>,
650 <&audsys CLK_ 650 <&audsys CLK_AUDIO_AFE>,
651 <&audsys CLK_ 651 <&audsys CLK_AUDIO_AFE_CONN>,
652 <&audsys CLK_ 652 <&audsys CLK_AUDIO_A1SYS>,
653 <&audsys CLK_ 653 <&audsys CLK_AUDIO_A2SYS>;
654 654
655 clock-names = "infra_s 655 clock-names = "infra_sys_audio_clk",
656 "top_aud 656 "top_audio_mux1_sel",
657 "top_aud 657 "top_audio_mux2_sel",
658 "top_aud 658 "top_audio_a1sys_hp",
659 "top_aud 659 "top_audio_a2sys_hp",
660 "i2s0_sr 660 "i2s0_src_sel",
661 "i2s1_sr 661 "i2s1_src_sel",
662 "i2s2_sr 662 "i2s2_src_sel",
663 "i2s3_sr 663 "i2s3_src_sel",
664 "i2s0_sr 664 "i2s0_src_div",
665 "i2s1_sr 665 "i2s1_src_div",
666 "i2s2_sr 666 "i2s2_src_div",
667 "i2s3_sr 667 "i2s3_src_div",
668 "i2s0_mc 668 "i2s0_mclk_en",
669 "i2s1_mc 669 "i2s1_mclk_en",
670 "i2s2_mc 670 "i2s2_mclk_en",
671 "i2s3_mc 671 "i2s3_mclk_en",
672 "i2so0_h 672 "i2so0_hop_ck",
673 "i2so1_h 673 "i2so1_hop_ck",
674 "i2so2_h 674 "i2so2_hop_ck",
675 "i2so3_h 675 "i2so3_hop_ck",
676 "i2si0_h 676 "i2si0_hop_ck",
677 "i2si1_h 677 "i2si1_hop_ck",
678 "i2si2_h 678 "i2si2_hop_ck",
679 "i2si3_h 679 "i2si3_hop_ck",
680 "asrc0_o 680 "asrc0_out_ck",
681 "asrc1_o 681 "asrc1_out_ck",
682 "asrc2_o 682 "asrc2_out_ck",
683 "asrc3_o 683 "asrc3_out_ck",
684 "audio_a 684 "audio_afe_pd",
685 "audio_a 685 "audio_afe_conn_pd",
686 "audio_a 686 "audio_a1sys_pd",
687 "audio_a 687 "audio_a2sys_pd";
688 688
689 assigned-clocks = <&to 689 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
690 <&to 690 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
691 <&to 691 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
692 <&to 692 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
693 assigned-clock-parents 693 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
694 694 <&topckgen CLK_TOP_AUD2PLL>;
695 assigned-clock-rates = 695 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
696 }; 696 };
697 }; 697 };
698 698
699 mmc0: mmc@11230000 { 699 mmc0: mmc@11230000 {
700 compatible = "mediatek,mt7622- 700 compatible = "mediatek,mt7622-mmc";
701 reg = <0 0x11230000 0 0x1000>; 701 reg = <0 0x11230000 0 0x1000>;
702 interrupts = <GIC_SPI 79 IRQ_T 702 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
703 clocks = <&pericfg CLK_PERI_MS 703 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
704 <&topckgen CLK_TOP_MS 704 <&topckgen CLK_TOP_MSDC50_0_SEL>;
705 clock-names = "source", "hclk" 705 clock-names = "source", "hclk";
706 resets = <&pericfg MT7622_PERI 706 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
707 reset-names = "hrst"; 707 reset-names = "hrst";
708 status = "disabled"; 708 status = "disabled";
709 }; 709 };
710 710
711 mmc1: mmc@11240000 { 711 mmc1: mmc@11240000 {
712 compatible = "mediatek,mt7622- 712 compatible = "mediatek,mt7622-mmc";
713 reg = <0 0x11240000 0 0x1000>; 713 reg = <0 0x11240000 0 0x1000>;
714 interrupts = <GIC_SPI 80 IRQ_T 714 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
715 clocks = <&pericfg CLK_PERI_MS 715 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
716 <&topckgen CLK_TOP_AX 716 <&topckgen CLK_TOP_AXI_SEL>;
717 clock-names = "source", "hclk" 717 clock-names = "source", "hclk";
718 resets = <&pericfg MT7622_PERI 718 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
719 reset-names = "hrst"; 719 reset-names = "hrst";
720 status = "disabled"; 720 status = "disabled";
721 }; 721 };
722 722
723 wmac: wmac@18000000 { 723 wmac: wmac@18000000 {
724 compatible = "mediatek,mt7622- 724 compatible = "mediatek,mt7622-wmac";
725 reg = <0 0x18000000 0 0x100000 725 reg = <0 0x18000000 0 0x100000>;
726 interrupts = <GIC_SPI 211 IRQ_ 726 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
727 727
728 mediatek,infracfg = <&infracfg 728 mediatek,infracfg = <&infracfg>;
729 status = "disabled"; 729 status = "disabled";
730 730
731 power-domains = <&scpsys MT762 731 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
732 }; 732 };
733 733
734 ssusbsys: clock-controller@1a000000 { 734 ssusbsys: clock-controller@1a000000 {
735 compatible = "mediatek,mt7622- 735 compatible = "mediatek,mt7622-ssusbsys";
736 reg = <0 0x1a000000 0 0x1000>; 736 reg = <0 0x1a000000 0 0x1000>;
737 #clock-cells = <1>; 737 #clock-cells = <1>;
738 #reset-cells = <1>; 738 #reset-cells = <1>;
739 }; 739 };
740 740
741 ssusb: usb@1a0c0000 { 741 ssusb: usb@1a0c0000 {
742 compatible = "mediatek,mt7622- 742 compatible = "mediatek,mt7622-xhci",
743 "mediatek,mtk-xhc 743 "mediatek,mtk-xhci";
744 reg = <0 0x1a0c0000 0 0x01000> 744 reg = <0 0x1a0c0000 0 0x01000>,
745 <0 0x1a0c4700 0 0x0100>; 745 <0 0x1a0c4700 0 0x0100>;
746 reg-names = "mac", "ippc"; 746 reg-names = "mac", "ippc";
747 interrupts = <GIC_SPI 232 IRQ_ 747 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
748 power-domains = <&scpsys MT762 748 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
749 clocks = <&ssusbsys CLK_SSUSB_ 749 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
750 <&ssusbsys CLK_SSUSB_ 750 <&ssusbsys CLK_SSUSB_REF_EN>,
751 <&ssusbsys CLK_SSUSB_ 751 <&ssusbsys CLK_SSUSB_MCU_EN>,
752 <&ssusbsys CLK_SSUSB_ 752 <&ssusbsys CLK_SSUSB_DMA_EN>;
753 clock-names = "sys_ck", "ref_c 753 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
754 phys = <&u2port0 PHY_TYPE_USB2 754 phys = <&u2port0 PHY_TYPE_USB2>,
755 <&u3port0 PHY_TYPE_USB3 755 <&u3port0 PHY_TYPE_USB3>,
756 <&u2port1 PHY_TYPE_USB2 756 <&u2port1 PHY_TYPE_USB2>;
757 757
758 status = "disabled"; 758 status = "disabled";
759 }; 759 };
760 760
761 u3phy: t-phy@1a0c4000 { 761 u3phy: t-phy@1a0c4000 {
762 compatible = "mediatek,mt7622- 762 compatible = "mediatek,mt7622-tphy",
763 "mediatek,generic 763 "mediatek,generic-tphy-v1";
764 reg = <0 0x1a0c4000 0 0x700>; 764 reg = <0 0x1a0c4000 0 0x700>;
765 #address-cells = <2>; 765 #address-cells = <2>;
766 #size-cells = <2>; 766 #size-cells = <2>;
767 ranges; 767 ranges;
768 status = "disabled"; 768 status = "disabled";
769 769
770 u2port0: usb-phy@1a0c4800 { 770 u2port0: usb-phy@1a0c4800 {
771 reg = <0 0x1a0c4800 0 771 reg = <0 0x1a0c4800 0 0x0100>;
772 #phy-cells = <1>; 772 #phy-cells = <1>;
773 clocks = <&ssusbsys CL 773 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
774 clock-names = "ref"; 774 clock-names = "ref";
775 }; 775 };
776 776
777 u3port0: usb-phy@1a0c4900 { 777 u3port0: usb-phy@1a0c4900 {
778 reg = <0 0x1a0c4900 0 778 reg = <0 0x1a0c4900 0 0x0700>;
779 #phy-cells = <1>; 779 #phy-cells = <1>;
780 clocks = <&clk25m>; 780 clocks = <&clk25m>;
781 clock-names = "ref"; 781 clock-names = "ref";
782 }; 782 };
783 783
784 u2port1: usb-phy@1a0c5000 { 784 u2port1: usb-phy@1a0c5000 {
785 reg = <0 0x1a0c5000 0 785 reg = <0 0x1a0c5000 0 0x0100>;
786 #phy-cells = <1>; 786 #phy-cells = <1>;
787 clocks = <&ssusbsys CL 787 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
788 clock-names = "ref"; 788 clock-names = "ref";
789 }; 789 };
790 }; 790 };
791 791
792 pciesys: clock-controller@1a100800 { 792 pciesys: clock-controller@1a100800 {
793 compatible = "mediatek,mt7622- 793 compatible = "mediatek,mt7622-pciesys";
794 reg = <0 0x1a100800 0 0x1000>; 794 reg = <0 0x1a100800 0 0x1000>;
795 #clock-cells = <1>; 795 #clock-cells = <1>;
796 #reset-cells = <1>; 796 #reset-cells = <1>;
797 }; 797 };
798 798
799 pciecfg: pciecfg@1a140000 { 799 pciecfg: pciecfg@1a140000 {
800 compatible = "mediatek,generic 800 compatible = "mediatek,generic-pciecfg", "syscon";
801 reg = <0 0x1a140000 0 0x1000>; 801 reg = <0 0x1a140000 0 0x1000>;
802 }; 802 };
803 803
804 pcie0: pcie@1a143000 { 804 pcie0: pcie@1a143000 {
805 compatible = "mediatek,mt7622- 805 compatible = "mediatek,mt7622-pcie";
806 device_type = "pci"; 806 device_type = "pci";
807 reg = <0 0x1a143000 0 0x1000>; 807 reg = <0 0x1a143000 0 0x1000>;
808 reg-names = "port0"; 808 reg-names = "port0";
809 linux,pci-domain = <0>; 809 linux,pci-domain = <0>;
810 #address-cells = <3>; 810 #address-cells = <3>;
811 #size-cells = <2>; 811 #size-cells = <2>;
812 interrupts = <GIC_SPI 228 IRQ_ 812 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
813 interrupt-names = "pcie_irq"; 813 interrupt-names = "pcie_irq";
814 clocks = <&pciesys CLK_PCIE_P0 814 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
815 <&pciesys CLK_PCIE_P0 815 <&pciesys CLK_PCIE_P0_AHB_EN>,
816 <&pciesys CLK_PCIE_P0 816 <&pciesys CLK_PCIE_P0_AUX_EN>,
817 <&pciesys CLK_PCIE_P0 817 <&pciesys CLK_PCIE_P0_AXI_EN>,
818 <&pciesys CLK_PCIE_P0 818 <&pciesys CLK_PCIE_P0_OBFF_EN>,
819 <&pciesys CLK_PCIE_P0 819 <&pciesys CLK_PCIE_P0_PIPE_EN>;
820 clock-names = "sys_ck0", "ahb_ 820 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
821 "axi_ck0", "obff 821 "axi_ck0", "obff_ck0", "pipe_ck0";
822 822
823 power-domains = <&scpsys MT762 823 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
824 bus-range = <0x00 0xff>; 824 bus-range = <0x00 0xff>;
825 ranges = <0x82000000 0 0x20000 825 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
826 status = "disabled"; 826 status = "disabled";
827 827
828 #interrupt-cells = <1>; 828 #interrupt-cells = <1>;
829 interrupt-map-mask = <0 0 0 7> 829 interrupt-map-mask = <0 0 0 7>;
830 interrupt-map = <0 0 0 1 &pcie 830 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
831 <0 0 0 2 &pcie 831 <0 0 0 2 &pcie_intc0 1>,
832 <0 0 0 3 &pcie 832 <0 0 0 3 &pcie_intc0 2>,
833 <0 0 0 4 &pcie 833 <0 0 0 4 &pcie_intc0 3>;
834 pcie_intc0: interrupt-controll 834 pcie_intc0: interrupt-controller {
835 interrupt-controller; 835 interrupt-controller;
836 #address-cells = <0>; 836 #address-cells = <0>;
837 #interrupt-cells = <1> 837 #interrupt-cells = <1>;
838 }; 838 };
839 }; 839 };
840 840
841 pcie1: pcie@1a145000 { 841 pcie1: pcie@1a145000 {
842 compatible = "mediatek,mt7622- 842 compatible = "mediatek,mt7622-pcie";
843 device_type = "pci"; 843 device_type = "pci";
844 reg = <0 0x1a145000 0 0x1000>; 844 reg = <0 0x1a145000 0 0x1000>;
845 reg-names = "port1"; 845 reg-names = "port1";
846 linux,pci-domain = <1>; 846 linux,pci-domain = <1>;
847 #address-cells = <3>; 847 #address-cells = <3>;
848 #size-cells = <2>; 848 #size-cells = <2>;
849 interrupts = <GIC_SPI 229 IRQ_ 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
850 interrupt-names = "pcie_irq"; 850 interrupt-names = "pcie_irq";
851 clocks = <&pciesys CLK_PCIE_P1 851 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
852 /* designer has conne 852 /* designer has connect RC1 with p0_ahb clock */
853 <&pciesys CLK_PCIE_P0 853 <&pciesys CLK_PCIE_P0_AHB_EN>,
854 <&pciesys CLK_PCIE_P1 854 <&pciesys CLK_PCIE_P1_AUX_EN>,
855 <&pciesys CLK_PCIE_P1 855 <&pciesys CLK_PCIE_P1_AXI_EN>,
856 <&pciesys CLK_PCIE_P1 856 <&pciesys CLK_PCIE_P1_OBFF_EN>,
857 <&pciesys CLK_PCIE_P1 857 <&pciesys CLK_PCIE_P1_PIPE_EN>;
858 clock-names = "sys_ck1", "ahb_ 858 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
859 "axi_ck1", "obff 859 "axi_ck1", "obff_ck1", "pipe_ck1";
860 860
861 power-domains = <&scpsys MT762 861 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
862 bus-range = <0x00 0xff>; 862 bus-range = <0x00 0xff>;
863 ranges = <0x82000000 0 0x28000 863 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
864 status = "disabled"; 864 status = "disabled";
865 865
866 #interrupt-cells = <1>; 866 #interrupt-cells = <1>;
867 interrupt-map-mask = <0 0 0 7> 867 interrupt-map-mask = <0 0 0 7>;
868 interrupt-map = <0 0 0 1 &pcie 868 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
869 <0 0 0 2 &pcie 869 <0 0 0 2 &pcie_intc1 1>,
870 <0 0 0 3 &pcie 870 <0 0 0 3 &pcie_intc1 2>,
871 <0 0 0 4 &pcie 871 <0 0 0 4 &pcie_intc1 3>;
872 pcie_intc1: interrupt-controll 872 pcie_intc1: interrupt-controller {
873 interrupt-controller; 873 interrupt-controller;
874 #address-cells = <0>; 874 #address-cells = <0>;
875 #interrupt-cells = <1> 875 #interrupt-cells = <1>;
876 }; 876 };
877 }; 877 };
878 878
879 sata: sata@1a200000 { 879 sata: sata@1a200000 {
880 compatible = "mediatek,mt7622- 880 compatible = "mediatek,mt7622-ahci",
881 "mediatek,mtk-ahc 881 "mediatek,mtk-ahci";
882 reg = <0 0x1a200000 0 0x1100>; 882 reg = <0 0x1a200000 0 0x1100>;
883 interrupts = <GIC_SPI 233 IRQ_ 883 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "hostc"; 884 interrupt-names = "hostc";
885 clocks = <&pciesys CLK_SATA_AH 885 clocks = <&pciesys CLK_SATA_AHB_EN>,
886 <&pciesys CLK_SATA_AX 886 <&pciesys CLK_SATA_AXI_EN>,
887 <&pciesys CLK_SATA_AS 887 <&pciesys CLK_SATA_ASIC_EN>,
888 <&pciesys CLK_SATA_RB 888 <&pciesys CLK_SATA_RBC_EN>,
889 <&pciesys CLK_SATA_PM 889 <&pciesys CLK_SATA_PM_EN>;
890 clock-names = "ahb", "axi", "a 890 clock-names = "ahb", "axi", "asic", "rbc", "pm";
891 phys = <&sata_port PHY_TYPE_SA 891 phys = <&sata_port PHY_TYPE_SATA>;
892 phy-names = "sata-phy"; 892 phy-names = "sata-phy";
893 ports-implemented = <0x1>; 893 ports-implemented = <0x1>;
894 power-domains = <&scpsys MT762 894 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
895 resets = <&pciesys MT7622_SATA 895 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
896 <&pciesys MT7622_SATA 896 <&pciesys MT7622_SATA_PHY_SW_RST>,
897 <&pciesys MT7622_SATA 897 <&pciesys MT7622_SATA_PHY_REG_RST>;
898 reset-names = "axi", "sw", "re 898 reset-names = "axi", "sw", "reg";
899 mediatek,phy-mode = <&pciesys> 899 mediatek,phy-mode = <&pciesys>;
900 status = "disabled"; 900 status = "disabled";
901 }; 901 };
902 902
903 sata_phy: t-phy { 903 sata_phy: t-phy {
904 compatible = "mediatek,mt7622- 904 compatible = "mediatek,mt7622-tphy",
905 "mediatek,generic 905 "mediatek,generic-tphy-v1";
906 #address-cells = <2>; 906 #address-cells = <2>;
907 #size-cells = <2>; 907 #size-cells = <2>;
908 ranges; 908 ranges;
909 status = "disabled"; 909 status = "disabled";
910 910
911 sata_port: sata-phy@1a243000 { 911 sata_port: sata-phy@1a243000 {
912 reg = <0 0x1a243000 0 912 reg = <0 0x1a243000 0 0x0100>;
913 clocks = <&topckgen CL 913 clocks = <&topckgen CLK_TOP_ETH_500M>;
914 clock-names = "ref"; 914 clock-names = "ref";
915 #phy-cells = <1>; 915 #phy-cells = <1>;
916 }; 916 };
917 }; 917 };
918 918
919 hifsys: clock-controller@1af00000 { 919 hifsys: clock-controller@1af00000 {
920 compatible = "mediatek,mt7622- 920 compatible = "mediatek,mt7622-hifsys";
921 reg = <0 0x1af00000 0 0x70>; 921 reg = <0 0x1af00000 0 0x70>;
922 #clock-cells = <1>; 922 #clock-cells = <1>;
923 }; 923 };
924 924
925 ethsys: clock-controller@1b000000 { 925 ethsys: clock-controller@1b000000 {
926 compatible = "mediatek,mt7622- 926 compatible = "mediatek,mt7622-ethsys",
927 "syscon"; 927 "syscon";
928 reg = <0 0x1b000000 0 0x1000>; 928 reg = <0 0x1b000000 0 0x1000>;
929 #clock-cells = <1>; 929 #clock-cells = <1>;
930 #reset-cells = <1>; 930 #reset-cells = <1>;
931 }; 931 };
932 932
933 hsdma: dma-controller@1b007000 { 933 hsdma: dma-controller@1b007000 {
934 compatible = "mediatek,mt7622- 934 compatible = "mediatek,mt7622-hsdma";
935 reg = <0 0x1b007000 0 0x1000>; 935 reg = <0 0x1b007000 0 0x1000>;
936 interrupts = <GIC_SPI 219 IRQ_ 936 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
937 clocks = <ðsys CLK_ETH_HSDM 937 clocks = <ðsys CLK_ETH_HSDMA_EN>;
938 clock-names = "hsdma"; 938 clock-names = "hsdma";
939 power-domains = <&scpsys MT762 939 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
940 #dma-cells = <1>; 940 #dma-cells = <1>;
941 dma-requests = <3>; 941 dma-requests = <3>;
942 }; 942 };
943 943
944 pcie_mirror: pcie-mirror@10000400 { 944 pcie_mirror: pcie-mirror@10000400 {
945 compatible = "mediatek,mt7622- 945 compatible = "mediatek,mt7622-pcie-mirror",
946 "syscon"; 946 "syscon";
947 reg = <0 0x10000400 0 0x10>; 947 reg = <0 0x10000400 0 0x10>;
948 }; 948 };
949 949
950 wed0: wed@1020a000 { 950 wed0: wed@1020a000 {
951 compatible = "mediatek,mt7622- 951 compatible = "mediatek,mt7622-wed",
952 "syscon"; 952 "syscon";
953 reg = <0 0x1020a000 0 0x1000>; 953 reg = <0 0x1020a000 0 0x1000>;
954 interrupts = <GIC_SPI 214 IRQ_ 954 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
955 }; 955 };
956 956
957 wed1: wed@1020b000 { 957 wed1: wed@1020b000 {
958 compatible = "mediatek,mt7622- 958 compatible = "mediatek,mt7622-wed",
959 "syscon"; 959 "syscon";
960 reg = <0 0x1020b000 0 0x1000>; 960 reg = <0 0x1020b000 0 0x1000>;
961 interrupts = <GIC_SPI 215 IRQ_ 961 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
962 }; 962 };
963 963
964 eth: ethernet@1b100000 { 964 eth: ethernet@1b100000 {
965 compatible = "mediatek,mt7622- 965 compatible = "mediatek,mt7622-eth";
966 reg = <0 0x1b100000 0 0x20000> 966 reg = <0 0x1b100000 0 0x20000>;
967 interrupts = <GIC_SPI 223 IRQ_ 967 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
968 <GIC_SPI 224 IRQ_ 968 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
969 <GIC_SPI 225 IRQ_ 969 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
970 clocks = <&topckgen CLK_TOP_ET 970 clocks = <&topckgen CLK_TOP_ETH_SEL>,
971 <ðsys CLK_ETH_ESW_ 971 <ðsys CLK_ETH_ESW_EN>,
972 <ðsys CLK_ETH_GP0_ 972 <ðsys CLK_ETH_GP0_EN>,
973 <ðsys CLK_ETH_GP1_ 973 <ðsys CLK_ETH_GP1_EN>,
974 <ðsys CLK_ETH_GP2_ 974 <ðsys CLK_ETH_GP2_EN>,
975 <&sgmiisys CLK_SGMII_ 975 <&sgmiisys CLK_SGMII_TX250M_EN>,
976 <&sgmiisys CLK_SGMII_ 976 <&sgmiisys CLK_SGMII_RX250M_EN>,
977 <&sgmiisys CLK_SGMII_ 977 <&sgmiisys CLK_SGMII_CDR_REF>,
978 <&sgmiisys CLK_SGMII_ 978 <&sgmiisys CLK_SGMII_CDR_FB>,
979 <&topckgen CLK_TOP_SG 979 <&topckgen CLK_TOP_SGMIIPLL>,
980 <&apmixedsys CLK_APMI 980 <&apmixedsys CLK_APMIXED_ETH2PLL>;
981 clock-names = "ethif", "esw", 981 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
982 "sgmii_tx250m", 982 "sgmii_tx250m", "sgmii_rx250m",
983 "sgmii_cdr_ref", 983 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
984 "eth2pll"; 984 "eth2pll";
985 power-domains = <&scpsys MT762 985 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
986 mediatek,ethsys = <ðsys>; 986 mediatek,ethsys = <ðsys>;
987 mediatek,sgmiisys = <&sgmiisys 987 mediatek,sgmiisys = <&sgmiisys>;
988 cci-control-port = <&cci_contr 988 cci-control-port = <&cci_control2>;
989 mediatek,wed = <&wed0>, <&wed1 989 mediatek,wed = <&wed0>, <&wed1>;
990 mediatek,pcie-mirror = <&pcie_ 990 mediatek,pcie-mirror = <&pcie_mirror>;
991 mediatek,hifsys = <&hifsys>; 991 mediatek,hifsys = <&hifsys>;
992 dma-coherent; 992 dma-coherent;
993 #address-cells = <1>; 993 #address-cells = <1>;
994 #size-cells = <0>; 994 #size-cells = <0>;
995 status = "disabled"; 995 status = "disabled";
996 }; 996 };
997 997
998 sgmiisys: sgmiisys@1b128000 { 998 sgmiisys: sgmiisys@1b128000 {
999 compatible = "mediatek,mt7622- 999 compatible = "mediatek,mt7622-sgmiisys",
1000 "syscon"; 1000 "syscon";
1001 reg = <0 0x1b128000 0 0x3000> 1001 reg = <0 0x1b128000 0 0x3000>;
1002 #clock-cells = <1>; 1002 #clock-cells = <1>;
1003 }; 1003 };
1004 }; 1004 };
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