1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.
8 #include <dt-bindings/regulator/dlg,da9211-reg
9 #include <dt-bindings/gpio/gpio.h>
10 #include "mt8173.dtsi"
11
12 / {
13 aliases {
14 mmc0 = &mmc0;
15 mmc1 = &mmc1;
16 mmc2 = &mmc3;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0 0x40000000 0 0x800000
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm0 0 1000000>;
27 power-supply = <&bl_fixed_reg>
28 enable-gpios = <&pio 95 GPIO_A
29
30 pinctrl-names = "default";
31 pinctrl-0 = <&panel_backlight_
32 status = "okay";
33 };
34
35 bl_fixed_reg: fixedregulator2 {
36 compatible = "regulator-fixed"
37 regulator-name = "bl_fixed";
38 regulator-min-microvolt = <180
39 regulator-max-microvolt = <180
40 startup-delay-us = <1000>;
41 enable-active-high;
42 gpio = <&pio 32 GPIO_ACTIVE_HI
43 pinctrl-names = "default";
44 pinctrl-0 = <&bl_fixed_pins>;
45 };
46
47 chosen {
48 stdout-path = "serial0:115200n
49 };
50
51 gpio_keys: gpio-keys {
52 compatible = "gpio-keys";
53 pinctrl-names = "default";
54 pinctrl-0 = <&gpio_keys_pins>;
55
56 switch-lid {
57 label = "Lid";
58 gpios = <&pio 69 GPIO_
59 linux,code = <SW_LID>;
60 linux,input-type = <EV
61 wakeup-source;
62 };
63
64 switch-power {
65 label = "Power";
66 gpios = <&pio 14 GPIO_
67 linux,code = <KEY_POWE
68 debounce-interval = <3
69 wakeup-source;
70 };
71
72 switch-tablet-mode {
73 label = "Tablet_mode";
74 gpios = <&pio 121 GPIO
75 linux,code = <SW_TABLE
76 linux,input-type = <EV
77 wakeup-source;
78 };
79
80 switch-volume-down {
81 label = "Volume_down";
82 gpios = <&pio 123 GPIO
83 linux,code = <KEY_VOLU
84 };
85
86 switch-volume-up {
87 label = "Volume_up";
88 gpios = <&pio 124 GPIO
89 linux,code = <KEY_VOLU
90 };
91 };
92
93 panel_fixed_3v3: regulator1 {
94 compatible = "regulator-fixed"
95 regulator-name = "PANEL_3V3";
96 regulator-min-microvolt = <330
97 regulator-max-microvolt = <330
98 enable-active-high;
99 regulator-boot-on;
100 off-on-delay-us = <500000>;
101 gpio = <&pio 41 GPIO_ACTIVE_HI
102 pinctrl-names = "default";
103 pinctrl-0 = <&panel_fixed_pins
104 };
105
106 ps8640_fixed_1v2: regulator2 {
107 compatible = "regulator-fixed"
108 regulator-name = "PS8640_1V2";
109 regulator-min-microvolt = <120
110 regulator-max-microvolt = <120
111 regulator-enable-ramp-delay =
112 enable-active-high;
113 regulator-boot-on;
114 gpio = <&pio 30 GPIO_ACTIVE_HI
115 pinctrl-names = "default";
116 pinctrl-0 = <&ps8640_fixed_pin
117 };
118
119 sdio_fixed_3v3: fixedregulator0 {
120 compatible = "regulator-fixed"
121 regulator-name = "3V3";
122 regulator-min-microvolt = <330
123 regulator-max-microvolt = <330
124 gpio = <&pio 85 GPIO_ACTIVE_HI
125 pinctrl-names = "default";
126 pinctrl-0 = <&sdio_fixed_3v3_p
127 };
128
129 sound: sound {
130 compatible = "mediatek,mt8173-
131 mediatek,audio-codec = <&rt565
132 mediatek,platform = <&afe>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&aud_i2s2>;
135
136 mediatek,mclk = <1>;
137 codec-capture {
138 sound-dai = <&rt5650 1
139 };
140 };
141
142 hdmicon: connector {
143 compatible = "hdmi-connector";
144 label = "hdmi";
145 type = "a";
146 ddc-i2c-bus = <&hdmiddc0>;
147
148 port {
149 hdmi_connector_in: end
150 remote-endpoin
151 };
152 };
153 };
154
155 watchdog {
156 compatible = "arm,smc-wdt";
157 };
158 };
159
160 /*
161 * Disable the original MMIO watch dog and swi
162 * operates on the same MMIO.
163 */
164 &watchdog {
165 status = "disabled";
166 };
167
168 &mfg_async {
169 domain-supply = <&da9211_vgpu_reg>;
170 };
171
172 &cec {
173 status = "okay";
174 };
175
176 &cpu0 {
177 proc-supply = <&mt6397_vpca15_reg>;
178 };
179
180 &cpu1 {
181 proc-supply = <&mt6397_vpca15_reg>;
182 };
183
184 &cpu2 {
185 proc-supply = <&da9211_vcpu_reg>;
186 sram-supply = <&mt6397_vsramca7_reg>;
187 };
188
189 &cpu3 {
190 proc-supply = <&da9211_vcpu_reg>;
191 sram-supply = <&mt6397_vsramca7_reg>;
192 };
193
194 &cpu_thermal {
195 sustainable-power = <4500>; /* milliwa
196 trips {
197 threshold: trip-point0 {
198 temperature = <60000>;
199 };
200
201 target: trip-point1 {
202 temperature = <65000>;
203 };
204 };
205 };
206
207 &dsi0 {
208 status = "okay";
209 ports {
210 port {
211 dsi0_out: endpoint {
212 remote-endpoin
213 };
214 };
215 };
216 };
217
218 &dpi0 {
219 status = "okay";
220 };
221
222 &hdmi0 {
223 status = "okay";
224 ports {
225 port@1 {
226 reg = <1>;
227
228 hdmi0_out: endpoint {
229 remote-endpoin
230 };
231 };
232 };
233 };
234
235 &hdmi_phy {
236 status = "okay";
237 mediatek,ibias = <0xc>;
238 };
239
240 &i2c0 {
241 status = "okay";
242
243 rt5650: audio-codec@1a {
244 compatible = "realtek,rt5650";
245 reg = <0x1a>;
246 avdd-supply = <&mt6397_vgp1_re
247 cpvdd-supply = <&mt6397_vcama_
248 interrupts-extended = <&pio 3
249 pinctrl-names = "default";
250 pinctrl-0 = <&rt5650_irq>;
251 #sound-dai-cells = <1>;
252 realtek,dmic1-data-pin = <2>;
253 realtek,jd-mode = <2>;
254 };
255
256 ps8640: edp-bridge@8 {
257 compatible = "parade,ps8640";
258 reg = <0x8>;
259 powerdown-gpios = <&pio 127 GP
260 reset-gpios = <&pio 115 GPIO_A
261 pinctrl-names = "default";
262 pinctrl-0 = <&ps8640_pins>;
263 vdd12-supply = <&ps8640_fixed_
264 vdd33-supply = <&mt6397_vgp2_r
265
266 ports {
267 #address-cells = <1>;
268 #size-cells = <0>;
269
270 port@0 {
271 reg = <0>;
272
273 ps8640_in: end
274 remote
275 };
276 };
277
278 port@1 {
279 reg = <1>;
280
281 ps8640_out: en
282 remote
283 };
284 };
285 };
286
287 aux-bus {
288 panel: panel {
289 compatible = "
290 power-supply =
291 backlight = <&
292
293 port {
294 panel_
295
296 };
297 };
298 };
299 };
300 };
301 };
302
303 &i2c1 {
304 clock-frequency = <1500000>;
305 status = "okay";
306
307 da9211: da9211@68 {
308 compatible = "dlg,da9211";
309 reg = <0x68>;
310 interrupts-extended = <&pio 15
311
312 regulators {
313 da9211_vcpu_reg: BUCKA
314 regulator-name
315 regulator-min-
316 regulator-max-
317 regulator-min-
318 regulator-max-
319 regulator-ramp
320 regulator-alwa
321 regulator-allo
322
323 };
324
325 da9211_vgpu_reg: BUCKB
326 regulator-name
327 regulator-min-
328 regulator-max-
329 regulator-min-
330 regulator-max-
331 regulator-ramp
332 };
333 };
334 };
335 };
336
337 &i2c2 {
338 status = "okay";
339
340 tpm: tpm@20 {
341 compatible = "infineon,slb9645
342 reg = <0x20>;
343 powered-while-suspended;
344 };
345 };
346
347 &i2c3 {
348 clock-frequency = <400000>;
349 status = "okay";
350
351 touchscreen: touchscreen@10 {
352 compatible = "elan,ekth3500";
353 reg = <0x10>;
354 interrupts-extended = <&pio 88
355 };
356 };
357
358 &i2c4 {
359 clock-frequency = <400000>;
360 status = "okay";
361 pinctrl-names = "default";
362 pinctrl-0 = <&trackpad_irq>;
363
364 trackpad: trackpad@15 {
365 compatible = "elan,ekth3000";
366 interrupts-extended = <&pio 11
367 reg = <0x15>;
368 vcc-supply = <&mt6397_vgp6_reg
369 wakeup-source;
370 };
371 };
372
373 &mipi_tx0 {
374 status = "okay";
375 };
376
377 &mmc0 {
378 status = "okay";
379 pinctrl-names = "default", "state_uhs"
380 pinctrl-0 = <&mmc0_pins_default>;
381 pinctrl-1 = <&mmc0_pins_uhs>;
382 bus-width = <8>;
383 max-frequency = <200000000>;
384 cap-mmc-highspeed;
385 mmc-hs200-1_8v;
386 mmc-hs400-1_8v;
387 cap-mmc-hw-reset;
388 hs400-ds-delay = <0x14015>;
389 mediatek,hs200-cmd-int-delay = <30>;
390 mediatek,hs400-cmd-int-delay = <14>;
391 mediatek,hs400-cmd-resp-sel-rising;
392 vmmc-supply = <&mt6397_vemc_3v3_reg>;
393 vqmmc-supply = <&mt6397_vio18_reg>;
394 assigned-clocks = <&topckgen CLK_TOP_M
395 assigned-clock-parents = <&topckgen CL
396 non-removable;
397 };
398
399 &mmc1 {
400 status = "okay";
401 pinctrl-names = "default", "state_uhs"
402 pinctrl-0 = <&mmc1_pins_default>;
403 pinctrl-1 = <&mmc1_pins_uhs>;
404 bus-width = <4>;
405 max-frequency = <200000000>;
406 cap-sd-highspeed;
407 sd-uhs-sdr50;
408 sd-uhs-sdr104;
409 cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
410 vmmc-supply = <&mt6397_vmch_reg>;
411 vqmmc-supply = <&mt6397_vmc_reg>;
412 };
413
414 &mmc3 {
415 status = "okay";
416 pinctrl-names = "default", "state_uhs"
417 pinctrl-0 = <&mmc3_pins_default>;
418 pinctrl-1 = <&mmc3_pins_uhs>;
419 bus-width = <4>;
420 max-frequency = <200000000>;
421 cap-sd-highspeed;
422 sd-uhs-sdr50;
423 sd-uhs-sdr104;
424 keep-power-in-suspend;
425 wakeup-source;
426 cap-sdio-irq;
427 vmmc-supply = <&sdio_fixed_3v3>;
428 vqmmc-supply = <&mt6397_vgp3_reg>;
429 non-removable;
430 cap-power-off-card;
431
432 #address-cells = <1>;
433 #size-cells = <0>;
434
435 btmrvl: btmrvl@2 {
436 compatible = "marvell,sd8897-b
437 reg = <2>;
438 interrupts-extended = <&pio 11
439 marvell,wakeup-pin = /bits/ 16
440 marvell,wakeup-gap-ms = /bits/
441 };
442
443 mwifiex: mwifiex@1 {
444 compatible = "marvell,sd8897";
445 reg = <1>;
446 interrupts-extended = <&pio 38
447 marvell,wakeup-pin = <3>;
448 };
449 };
450
451 &nor_flash {
452 status = "okay";
453 pinctrl-names = "default";
454 pinctrl-0 = <&nor_gpio1_pins>;
455
456 flash@0 {
457 compatible = "jedec,spi-nor";
458 reg = <0>;
459 spi-max-frequency = <50000000>
460 };
461 };
462
463 &pio {
464 gpio-line-names = "EC_INT_1V8",
465 "SD_CD_L",
466 "ALC5514_IRQ",
467 "ALC5650_IRQ",
468 /*
469 * AP_FLASH_WP_L is
470 * call it SFWP_B.
471 */
472 "AP_FLASH_WP_L",
473 "SFIN",
474 "SFCS0",
475 "SFHOLD",
476 "SFOUT",
477 "SFCK",
478 "WRAP_EVENT_S_EINT10
479 "PMU_INT",
480 "I2S2_WS_ALC5650",
481 "I2S2_BCK_ALC5650",
482 "PWR_BTN_1V8",
483 "DA9212_IRQ",
484 "IDDIG",
485 "WATCHDOG",
486 "CEC",
487 "HDMISCK",
488 "HDMISD",
489 "HTPLG",
490 "MSDC3_DAT0",
491 "MSDC3_DAT1",
492 "MSDC3_DAT2",
493 "MSDC3_DAT3",
494 "MSDC3_CLK",
495 "MSDC3_CMD",
496 "USB_C0_OC_FLAGB",
497 "USBA_OC1_L",
498 "PS8640_1V2_ENABLE",
499 "THERM_ALERT_N",
500 "PANEL_LCD_POWER_EN"
501 "ANX7688_CHIP_PD_C",
502 "EC_IN_RW_1V8",
503 "ANX7688_1V_EN_C",
504 "USB_DP_HPD_C",
505 "TPM_DAVINT_N",
506 "MARVELL8897_IRQ",
507 "EN_USB_A0_PWR",
508 "USBA_A0_OC_L",
509 "EN_PP3300_DX_EDP",
510 "",
511 "SOC_I2C2_1V8_SDA_40
512 "SOC_I2C2_1V8_SCL_40
513 "SOC_I2C0_1V8_SDA_40
514 "SOC_I2C0_1V8_SCL_40
515 "EMMC_ID1",
516 "EMMC_ID0",
517 "MEM_CONFIG3",
518 "EMMC_ID2",
519 "MEM_CONFIG1",
520 "MEM_CONFIG2",
521 "BRD_ID2",
522 "MEM_CONFIG0",
523 "BRD_ID0",
524 "BRD_ID1",
525 "EMMC_DAT0",
526 "EMMC_DAT1",
527 "EMMC_DAT2",
528 "EMMC_DAT3",
529 "EMMC_DAT4",
530 "EMMC_DAT5",
531 "EMMC_DAT6",
532 "EMMC_DAT7",
533 "EMMC_CLK",
534 "EMMC_CMD",
535 "EMMC_RCLK",
536 "PLT_RST_L",
537 "LID_OPEN_1V8_L",
538 "AUDIO_SPI_MISO_R",
539 "",
540 "AC_OK_1V8",
541 "SD_DATA0",
542 "SD_DATA1",
543 "SD_DATA2",
544 "SD_DATA3",
545 "SD_CLK",
546 "SD_CMD",
547 "PWRAP_SPI0_MI",
548 "PWRAP_SPI0_MO",
549 "PWRAP_SPI0_CK",
550 "PWRAP_SPI0_CSN",
551 "",
552 "",
553 "WIFI_PDN",
554 "RTC32K_1V8",
555 "DISP_PWM0",
556 "TOUCHSCREEN_INT_L",
557 "",
558 "SRCLKENA0",
559 "SRCLKENA1",
560 "PS8640_MODE_CONF",
561 "TOUCHSCREEN_RESET_R
562 "PLATFORM_PROCHOT_L"
563 "PANEL_POWER_EN",
564 "REC_MODE_L",
565 "EC_FW_UPDATE_L",
566 "ACCEL2_INT_L",
567 "HDMI_DP_INT",
568 "ACCELGYRO3_INT_L",
569 "ACCELGYRO4_INT_L",
570 "SPI_EC_CLK",
571 "SPI_EC_MI",
572 "SPI_EC_MO",
573 "SPI_EC_CSN",
574 "SOC_I2C3_1V8_SDA_40
575 "SOC_I2C3_1V8_SCL_40
576 "",
577 "",
578 "",
579 "",
580 "",
581 "",
582 "",
583 "PS8640_SYSRSTN_1V8"
584 "APIN_MAX98090_DOUT2
585 "TP_INT_1V8_L_R",
586 "RST_USB_HUB_R",
587 "BT_WAKE_L",
588 "ACCEL1_INT_L",
589 "TABLET_MODE_L",
590 "",
591 "V_UP_IN_L_R",
592 "V_DOWN_IN_L_R",
593 "SOC_I2C1_1V8_SDA_1M
594 "SOC_I2C1_1V8_SCL_1M
595 "PS8640_PDN_1V8",
596 "MAX98090_LRCLK",
597 "MAX98090_BCLK",
598 "MAX98090_MCLK",
599 "APOUT_MAX98090_DIN"
600 "APIN_MAX98090_DOUT"
601 "SOC_I2C4_1V8_SDA_40
602 "SOC_I2C4_1V8_SCL_40
603
604 aud_i2s2: aud_i2s2 {
605 pins1 {
606 pinmux = <MT8173_PIN_1
607 <MT8173_PIN_1
608 <MT8173_PIN_1
609 <MT8173_PIN_1
610 <MT8173_PIN_1
611 <MT8173_PIN_1
612 <MT8173_PIN_1
613 bias-pull-down;
614 };
615 };
616
617 bl_fixed_pins: bl_fixed_pins {
618 pins1 {
619 pinmux = <MT8173_PIN_3
620 output-low;
621 };
622 };
623
624 bt_wake_pins: bt_wake_pins {
625 pins1 {
626 pinmux = <MT8173_PIN_1
627 bias-pull-up;
628 };
629 };
630
631 disp_pwm0_pins: disp_pwm0_pins {
632 pins1 {
633 pinmux = <MT8173_PIN_8
634 output-low;
635 };
636 };
637
638 gpio_keys_pins: gpio_keys_pins {
639 volume_pins {
640 pinmux = <MT8173_PIN_1
641 <MT8173_PIN_1
642 bias-pull-up;
643 };
644
645 tablet_mode_pins {
646 pinmux = <MT8173_PIN_1
647 bias-pull-up;
648 };
649 };
650
651 hdmi_mux_pins: hdmi_mux_pins {
652 pins1 {
653 pinmux = <MT8173_PIN_3
654 };
655 };
656
657 i2c1_pins_a: i2c1 {
658 da9211_pins {
659 pinmux = <MT8173_PIN_1
660 bias-pull-up;
661 };
662 };
663
664 mmc0_pins_default: mmc0default {
665 pins_cmd_dat {
666 pinmux = <MT8173_PIN_5
667 <MT8173_PIN_5
668 <MT8173_PIN_5
669 <MT8173_PIN_6
670 <MT8173_PIN_6
671 <MT8173_PIN_6
672 <MT8173_PIN_6
673 <MT8173_PIN_6
674 <MT8173_PIN_6
675 bias-pull-up;
676 };
677
678 pins_clk {
679 pinmux = <MT8173_PIN_6
680 bias-pull-down;
681 };
682
683 pins_rst {
684 pinmux = <MT8173_PIN_6
685 bias-pull-up;
686 };
687 };
688
689 mmc1_pins_default: mmc1default {
690 pins_cmd_dat {
691 pinmux = <MT8173_PIN_7
692 <MT8173_PIN_7
693 <MT8173_PIN_7
694 <MT8173_PIN_7
695 <MT8173_PIN_7
696 input-enable;
697 drive-strength = <MTK_
698 bias-pull-up = <MTK_PU
699 };
700
701 pins_clk {
702 pinmux = <MT8173_PIN_7
703 bias-pull-down;
704 drive-strength = <MTK_
705 };
706
707 pins_insert {
708 pinmux = <MT8173_PIN_1
709 bias-pull-up;
710 };
711 };
712
713 mmc3_pins_default: mmc3default {
714 pins_dat {
715 pinmux = <MT8173_PIN_2
716 <MT8173_PIN_2
717 <MT8173_PIN_2
718 <MT8173_PIN_2
719 input-enable;
720 drive-strength = <MTK_
721 bias-pull-up = <MTK_PU
722 };
723
724 pins_cmd {
725 pinmux = <MT8173_PIN_2
726 input-enable;
727 drive-strength = <MTK_
728 bias-pull-up = <MTK_PU
729 };
730
731 pins_clk {
732 pinmux = <MT8173_PIN_2
733 bias-pull-down;
734 drive-strength = <MTK_
735 };
736 };
737
738 mmc0_pins_uhs: mmc0 {
739 pins_cmd_dat {
740 pinmux = <MT8173_PIN_5
741 <MT8173_PIN_5
742 <MT8173_PIN_5
743 <MT8173_PIN_6
744 <MT8173_PIN_6
745 <MT8173_PIN_6
746 <MT8173_PIN_6
747 <MT8173_PIN_6
748 <MT8173_PIN_6
749 input-enable;
750 drive-strength = <MTK_
751 bias-pull-up = <MTK_PU
752 };
753
754 pins_clk {
755 pinmux = <MT8173_PIN_6
756 drive-strength = <MTK_
757 bias-pull-down = <MTK_
758 };
759
760 pins_ds {
761 pinmux = <MT8173_PIN_6
762 drive-strength = <MTK_
763 bias-pull-down = <MTK_
764 };
765
766 pins_rst {
767 pinmux = <MT8173_PIN_6
768 bias-pull-up;
769 };
770 };
771
772 mmc1_pins_uhs: mmc1 {
773 pins_cmd_dat {
774 pinmux = <MT8173_PIN_7
775 <MT8173_PIN_7
776 <MT8173_PIN_7
777 <MT8173_PIN_7
778 <MT8173_PIN_7
779 input-enable;
780 drive-strength = <MTK_
781 bias-pull-up = <MTK_PU
782 };
783
784 pins_clk {
785 pinmux = <MT8173_PIN_7
786 drive-strength = <MTK_
787 bias-pull-down = <MTK_
788 };
789 };
790
791 mmc3_pins_uhs: mmc3 {
792 pins_dat {
793 pinmux = <MT8173_PIN_2
794 <MT8173_PIN_2
795 <MT8173_PIN_2
796 <MT8173_PIN_2
797 input-enable;
798 drive-strength = <MTK_
799 bias-pull-up = <MTK_PU
800 };
801
802 pins_cmd {
803 pinmux = <MT8173_PIN_2
804 input-enable;
805 drive-strength = <MTK_
806 bias-pull-up = <MTK_PU
807 };
808
809 pins_clk {
810 pinmux = <MT8173_PIN_2
811 drive-strength = <MTK_
812 bias-pull-down = <MTK_
813 };
814 };
815
816 nor_gpio1_pins: nor {
817 pins1 {
818 pinmux = <MT8173_PIN_6
819 <MT8173_PIN_7
820 <MT8173_PIN_8
821 input-enable;
822 drive-strength = <MTK_
823 bias-pull-up;
824 };
825
826 pins2 {
827 pinmux = <MT8173_PIN_5
828 drive-strength = <MTK_
829 bias-pull-up;
830 };
831
832 pins_clk {
833 pinmux = <MT8173_PIN_9
834 input-enable;
835 drive-strength = <MTK_
836 bias-pull-up;
837 };
838 };
839
840 panel_backlight_en_pins: panel_backlig
841 pins1 {
842 pinmux = <MT8173_PIN_9
843 };
844 };
845
846 panel_fixed_pins: panel_fixed_pins {
847 pins1 {
848 pinmux = <MT8173_PIN_4
849 };
850 };
851
852 ps8640_pins: ps8640_pins {
853 pins1 {
854 pinmux = <MT8173_PIN_9
855 <MT8173_PIN_1
856 <MT8173_PIN_1
857 };
858 };
859
860 ps8640_fixed_pins: ps8640_fixed_pins {
861 pins1 {
862 pinmux = <MT8173_PIN_3
863 };
864 };
865
866 rt5650_irq: rt5650_irq {
867 pins1 {
868 pinmux = <MT8173_PIN_3
869 bias-pull-down;
870 };
871 };
872
873 sdio_fixed_3v3_pins: sdio_fixed_3v3_pi
874 pins1 {
875 pinmux = <MT8173_PIN_8
876 output-low;
877 };
878 };
879
880 spi_pins_a: spi1 {
881 pins1 {
882 pinmux = <MT8173_PIN_0
883 bias-pull-up;
884 };
885
886 pins_spi {
887 pinmux = <MT8173_PIN_1
888 <MT8173_PIN_1
889 <MT8173_PIN_1
890 <MT8173_PIN_1
891 bias-disable;
892 };
893 };
894
895 trackpad_irq: trackpad_irq {
896 pins1 {
897 pinmux = <MT8173_PIN_1
898 input-enable;
899 bias-pull-up;
900 };
901 };
902
903 usb_pins: usb {
904 pins1 {
905 pinmux = <MT8173_PIN_1
906 output-high;
907 bias-disable;
908 };
909 };
910
911 wifi_wake_pins: wifi_wake_pins {
912 pins1 {
913 pinmux = <MT8173_PIN_3
914 bias-pull-up;
915 };
916 };
917 };
918
919 &pwm0 {
920 pinctrl-names = "default";
921 pinctrl-0 = <&disp_pwm0_pins>;
922 status = "okay";
923 };
924
925 &pwrap {
926 pmic: pmic {
927 compatible = "mediatek,mt6397"
928 #address-cells = <1>;
929 #size-cells = <1>;
930 interrupts-extended = <&pio 11
931 interrupt-controller;
932 #interrupt-cells = <2>;
933
934 clock: mt6397clock {
935 compatible = "mediatek
936 #clock-cells = <1>;
937 };
938
939 pio6397: pinctrl {
940 compatible = "mediatek
941 gpio-controller;
942 #gpio-cells = <2>;
943 };
944
945 regulator: mt6397regulator {
946 compatible = "mediatek
947
948 mt6397_vpca15_reg: buc
949 regulator-comp
950 regulator-name
951 regulator-min-
952 regulator-max-
953 regulator-ramp
954 regulator-alwa
955 regulator-allo
956 };
957
958 mt6397_vpca7_reg: buck
959 regulator-comp
960 regulator-name
961 regulator-min-
962 regulator-max-
963 regulator-ramp
964 regulator-enab
965 regulator-alwa
966 };
967
968 mt6397_vsramca15_reg:
969 regulator-comp
970 regulator-name
971 regulator-min-
972 regulator-max-
973 regulator-ramp
974 regulator-alwa
975 };
976
977 mt6397_vsramca7_reg: b
978 regulator-comp
979 regulator-name
980 regulator-min-
981 regulator-max-
982 regulator-ramp
983 regulator-alwa
984 };
985
986 mt6397_vcore_reg: buck
987 regulator-comp
988 regulator-name
989 regulator-min-
990 regulator-max-
991 regulator-ramp
992 regulator-alwa
993 };
994
995 mt6397_vgpu_reg: buck_
996 regulator-comp
997 regulator-name
998 regulator-min-
999 regulator-max-
1000 regulator-ram
1001 regulator-ena
1002 };
1003
1004 mt6397_vdrm_reg: buck
1005 regulator-com
1006 regulator-nam
1007 regulator-min
1008 regulator-max
1009 regulator-ram
1010 regulator-alw
1011 };
1012
1013 mt6397_vio18_reg: buc
1014 regulator-com
1015 regulator-nam
1016 regulator-min
1017 regulator-max
1018 regulator-ram
1019 regulator-alw
1020 };
1021
1022 mt6397_vtcxo_reg: ldo
1023 regulator-com
1024 regulator-nam
1025 regulator-alw
1026 };
1027
1028 mt6397_va28_reg: ldo_
1029 regulator-com
1030 regulator-nam
1031 };
1032
1033 mt6397_vcama_reg: ldo
1034 regulator-com
1035 regulator-nam
1036 regulator-min
1037 regulator-max
1038 regulator-ena
1039 };
1040
1041 mt6397_vio28_reg: ldo
1042 regulator-com
1043 regulator-nam
1044 regulator-alw
1045 };
1046
1047 mt6397_vusb_reg: ldo_
1048 regulator-com
1049 regulator-nam
1050 };
1051
1052 mt6397_vmc_reg: ldo_v
1053 regulator-com
1054 regulator-nam
1055 regulator-min
1056 regulator-max
1057 regulator-ena
1058 };
1059
1060 mt6397_vmch_reg: ldo_
1061 regulator-com
1062 regulator-nam
1063 regulator-min
1064 regulator-max
1065 regulator-ena
1066 };
1067
1068 mt6397_vemc_3v3_reg:
1069 regulator-com
1070 regulator-nam
1071 regulator-min
1072 regulator-max
1073 regulator-ena
1074 };
1075
1076 mt6397_vgp1_reg: ldo_
1077 regulator-com
1078 regulator-nam
1079 regulator-min
1080 regulator-max
1081 regulator-ena
1082 };
1083
1084 mt6397_vgp2_reg: ldo_
1085 regulator-com
1086 regulator-nam
1087 regulator-min
1088 regulator-max
1089 regulator-ena
1090 };
1091
1092 mt6397_vgp3_reg: ldo_
1093 regulator-com
1094 regulator-nam
1095 regulator-min
1096 regulator-max
1097 regulator-ena
1098 };
1099
1100 mt6397_vgp4_reg: ldo_
1101 regulator-com
1102 regulator-nam
1103 regulator-min
1104 regulator-max
1105 regulator-ena
1106 };
1107
1108 mt6397_vgp5_reg: ldo_
1109 regulator-com
1110 regulator-nam
1111 regulator-min
1112 regulator-max
1113 regulator-ena
1114 };
1115
1116 mt6397_vgp6_reg: ldo_
1117 regulator-com
1118 regulator-nam
1119 regulator-min
1120 regulator-max
1121 regulator-ena
1122 regulator-alw
1123 };
1124
1125 mt6397_vibr_reg: ldo_
1126 regulator-com
1127 regulator-nam
1128 regulator-min
1129 regulator-max
1130 regulator-ena
1131 };
1132 };
1133
1134 rtc: mt6397rtc {
1135 compatible = "mediate
1136 };
1137 };
1138 };
1139
1140 &spi {
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&spi_pins_a>;
1143 mediatek,pad-select = <1>;
1144 status = "okay";
1145 /* clients */
1146 cros_ec: ec@0 {
1147 compatible = "google,cros-ec-
1148 reg = <0x0>;
1149 spi-max-frequency = <12000000
1150 interrupts-extended = <&pio 0
1151 google,cros-ec-spi-msg-delay
1152 wakeup-source;
1153
1154 i2c_tunnel: i2c-tunnel0 {
1155 compatible = "google,
1156 google,remote-bus = <
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159
1160 battery: sbs-battery@
1161 compatible =
1162 reg = <0xb>;
1163 sbs,i2c-retry
1164 sbs,poll-retr
1165 };
1166 };
1167 };
1168 };
1169
1170 &ssusb {
1171 dr_mode = "host";
1172 wakeup-source;
1173 vusb33-supply = <&mt6397_vusb_reg>;
1174 status = "okay";
1175 };
1176
1177 &thermal {
1178 bank0-supply = <&mt6397_vpca15_reg>;
1179 bank1-supply = <&da9211_vcpu_reg>;
1180 };
1181
1182 &uart0 {
1183 status = "okay";
1184 };
1185
1186 &usb_host {
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&usb_pins>;
1189 vusb33-supply = <&mt6397_vusb_reg>;
1190 status = "okay";
1191 };
1192
1193 #include <arm/cros-ec-keyboard.dtsi>
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