1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Copyright (C) 2022 MediaTek Inc. 3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@media 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
5 */ 5 */
6 /dts-v1/; 6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h> 7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h> 8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-por 11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h 12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h> 13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h> 15 #include <dt-bindings/reset/mt8186-resets.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/thermal/mediatek,lvts-th <<
18 16
19 / { 17 / {
20 compatible = "mediatek,mt8186"; 18 compatible = "mediatek,mt8186";
21 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
22 #address-cells = <2>; 20 #address-cells = <2>;
23 #size-cells = <2>; 21 #size-cells = <2>;
24 22
25 aliases { 23 aliases {
26 ovl0 = &ovl0; 24 ovl0 = &ovl0;
27 ovl-2l0 = &ovl_2l0; 25 ovl-2l0 = &ovl_2l0;
28 rdma0 = &rdma0; 26 rdma0 = &rdma0;
29 rdma1 = &rdma1; 27 rdma1 = &rdma1;
30 }; 28 };
31 29
32 cci: cci { 30 cci: cci {
33 compatible = "mediatek,mt8186- 31 compatible = "mediatek,mt8186-cci";
34 clocks = <&mcusys CLK_MCU_ARMP 32 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
35 <&apmixedsys CLK_APMI 33 <&apmixedsys CLK_APMIXED_MAINPLL>;
36 clock-names = "cci", "intermed 34 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_op 35 operating-points-v2 = <&cci_opp>;
38 }; 36 };
39 37
40 cci_opp: opp-table-cci { 38 cci_opp: opp-table-cci {
41 compatible = "operating-points 39 compatible = "operating-points-v2";
42 opp-shared; 40 opp-shared;
43 41
44 cci_opp_0: opp-500000000 { 42 cci_opp_0: opp-500000000 {
45 opp-hz = /bits/ 64 <50 43 opp-hz = /bits/ 64 <500000000>;
46 opp-microvolt = <60000 44 opp-microvolt = <600000>;
47 }; 45 };
48 46
49 cci_opp_1: opp-560000000 { 47 cci_opp_1: opp-560000000 {
50 opp-hz = /bits/ 64 <56 48 opp-hz = /bits/ 64 <560000000>;
51 opp-microvolt = <67500 49 opp-microvolt = <675000>;
52 }; 50 };
53 51
54 cci_opp_2: opp-612000000 { 52 cci_opp_2: opp-612000000 {
55 opp-hz = /bits/ 64 <61 53 opp-hz = /bits/ 64 <612000000>;
56 opp-microvolt = <69375 54 opp-microvolt = <693750>;
57 }; 55 };
58 56
59 cci_opp_3: opp-682000000 { 57 cci_opp_3: opp-682000000 {
60 opp-hz = /bits/ 64 <68 58 opp-hz = /bits/ 64 <682000000>;
61 opp-microvolt = <71875 59 opp-microvolt = <718750>;
62 }; 60 };
63 61
64 cci_opp_4: opp-752000000 { 62 cci_opp_4: opp-752000000 {
65 opp-hz = /bits/ 64 <75 63 opp-hz = /bits/ 64 <752000000>;
66 opp-microvolt = <74375 64 opp-microvolt = <743750>;
67 }; 65 };
68 66
69 cci_opp_5: opp-822000000 { 67 cci_opp_5: opp-822000000 {
70 opp-hz = /bits/ 64 <82 68 opp-hz = /bits/ 64 <822000000>;
71 opp-microvolt = <76875 69 opp-microvolt = <768750>;
72 }; 70 };
73 71
74 cci_opp_6: opp-875000000 { 72 cci_opp_6: opp-875000000 {
75 opp-hz = /bits/ 64 <87 73 opp-hz = /bits/ 64 <875000000>;
76 opp-microvolt = <78125 74 opp-microvolt = <781250>;
77 }; 75 };
78 76
79 cci_opp_7: opp-927000000 { 77 cci_opp_7: opp-927000000 {
80 opp-hz = /bits/ 64 <92 78 opp-hz = /bits/ 64 <927000000>;
81 opp-microvolt = <80000 79 opp-microvolt = <800000>;
82 }; 80 };
83 81
84 cci_opp_8: opp-980000000 { 82 cci_opp_8: opp-980000000 {
85 opp-hz = /bits/ 64 <98 83 opp-hz = /bits/ 64 <980000000>;
86 opp-microvolt = <81875 84 opp-microvolt = <818750>;
87 }; 85 };
88 86
89 cci_opp_9: opp-1050000000 { 87 cci_opp_9: opp-1050000000 {
90 opp-hz = /bits/ 64 <10 88 opp-hz = /bits/ 64 <1050000000>;
91 opp-microvolt = <84375 89 opp-microvolt = <843750>;
92 }; 90 };
93 91
94 cci_opp_10: opp-1120000000 { 92 cci_opp_10: opp-1120000000 {
95 opp-hz = /bits/ 64 <11 93 opp-hz = /bits/ 64 <1120000000>;
96 opp-microvolt = <86250 94 opp-microvolt = <862500>;
97 }; 95 };
98 96
99 cci_opp_11: opp-1155000000 { 97 cci_opp_11: opp-1155000000 {
100 opp-hz = /bits/ 64 <11 98 opp-hz = /bits/ 64 <1155000000>;
101 opp-microvolt = <88750 99 opp-microvolt = <887500>;
102 }; 100 };
103 101
104 cci_opp_12: opp-1190000000 { 102 cci_opp_12: opp-1190000000 {
105 opp-hz = /bits/ 64 <11 103 opp-hz = /bits/ 64 <1190000000>;
106 opp-microvolt = <90625 104 opp-microvolt = <906250>;
107 }; 105 };
108 106
109 cci_opp_13: opp-1260000000 { 107 cci_opp_13: opp-1260000000 {
110 opp-hz = /bits/ 64 <12 108 opp-hz = /bits/ 64 <1260000000>;
111 opp-microvolt = <95000 109 opp-microvolt = <950000>;
112 }; 110 };
113 111
114 cci_opp_14: opp-1330000000 { 112 cci_opp_14: opp-1330000000 {
115 opp-hz = /bits/ 64 <13 113 opp-hz = /bits/ 64 <1330000000>;
116 opp-microvolt = <99375 114 opp-microvolt = <993750>;
117 }; 115 };
118 116
119 cci_opp_15: opp-1400000000 { 117 cci_opp_15: opp-1400000000 {
120 opp-hz = /bits/ 64 <14 118 opp-hz = /bits/ 64 <1400000000>;
121 opp-microvolt = <10312 119 opp-microvolt = <1031250>;
122 }; 120 };
123 }; 121 };
124 122
125 cluster0_opp: opp-table-cluster0 { 123 cluster0_opp: opp-table-cluster0 {
126 compatible = "operating-points 124 compatible = "operating-points-v2";
127 opp-shared; 125 opp-shared;
128 126
129 opp-500000000 { 127 opp-500000000 {
130 opp-hz = /bits/ 64 <50 128 opp-hz = /bits/ 64 <500000000>;
131 opp-microvolt = <60000 129 opp-microvolt = <600000>;
132 required-opps = <&cci_ 130 required-opps = <&cci_opp_0>;
133 }; 131 };
134 132
135 opp-774000000 { 133 opp-774000000 {
136 opp-hz = /bits/ 64 <77 134 opp-hz = /bits/ 64 <774000000>;
137 opp-microvolt = <67500 135 opp-microvolt = <675000>;
138 required-opps = <&cci_ 136 required-opps = <&cci_opp_1>;
139 }; 137 };
140 138
141 opp-875000000 { 139 opp-875000000 {
142 opp-hz = /bits/ 64 <87 140 opp-hz = /bits/ 64 <875000000>;
143 opp-microvolt = <70000 141 opp-microvolt = <700000>;
144 required-opps = <&cci_ 142 required-opps = <&cci_opp_2>;
145 }; 143 };
146 144
147 opp-975000000 { 145 opp-975000000 {
148 opp-hz = /bits/ 64 <97 146 opp-hz = /bits/ 64 <975000000>;
149 opp-microvolt = <72500 147 opp-microvolt = <725000>;
150 required-opps = <&cci_ 148 required-opps = <&cci_opp_3>;
151 }; 149 };
152 150
153 opp-1075000000 { 151 opp-1075000000 {
154 opp-hz = /bits/ 64 <10 152 opp-hz = /bits/ 64 <1075000000>;
155 opp-microvolt = <75000 153 opp-microvolt = <750000>;
156 required-opps = <&cci_ 154 required-opps = <&cci_opp_4>;
157 }; 155 };
158 156
159 opp-1175000000 { 157 opp-1175000000 {
160 opp-hz = /bits/ 64 <11 158 opp-hz = /bits/ 64 <1175000000>;
161 opp-microvolt = <77500 159 opp-microvolt = <775000>;
162 required-opps = <&cci_ 160 required-opps = <&cci_opp_5>;
163 }; 161 };
164 162
165 opp-1275000000 { 163 opp-1275000000 {
166 opp-hz = /bits/ 64 <12 164 opp-hz = /bits/ 64 <1275000000>;
167 opp-microvolt = <80000 165 opp-microvolt = <800000>;
168 required-opps = <&cci_ 166 required-opps = <&cci_opp_6>;
169 }; 167 };
170 168
171 opp-1375000000 { 169 opp-1375000000 {
172 opp-hz = /bits/ 64 <13 170 opp-hz = /bits/ 64 <1375000000>;
173 opp-microvolt = <82500 171 opp-microvolt = <825000>;
174 required-opps = <&cci_ 172 required-opps = <&cci_opp_7>;
175 }; 173 };
176 174
177 opp-1500000000 { 175 opp-1500000000 {
178 opp-hz = /bits/ 64 <15 176 opp-hz = /bits/ 64 <1500000000>;
179 opp-microvolt = <85625 177 opp-microvolt = <856250>;
180 required-opps = <&cci_ 178 required-opps = <&cci_opp_8>;
181 }; 179 };
182 180
183 opp-1618000000 { 181 opp-1618000000 {
184 opp-hz = /bits/ 64 <16 182 opp-hz = /bits/ 64 <1618000000>;
185 opp-microvolt = <87500 183 opp-microvolt = <875000>;
186 required-opps = <&cci_ 184 required-opps = <&cci_opp_9>;
187 }; 185 };
188 186
189 opp-1666000000 { 187 opp-1666000000 {
190 opp-hz = /bits/ 64 <16 188 opp-hz = /bits/ 64 <1666000000>;
191 opp-microvolt = <90000 189 opp-microvolt = <900000>;
192 required-opps = <&cci_ 190 required-opps = <&cci_opp_10>;
193 }; 191 };
194 192
195 opp-1733000000 { 193 opp-1733000000 {
196 opp-hz = /bits/ 64 <17 194 opp-hz = /bits/ 64 <1733000000>;
197 opp-microvolt = <92500 195 opp-microvolt = <925000>;
198 required-opps = <&cci_ 196 required-opps = <&cci_opp_11>;
199 }; 197 };
200 198
201 opp-1800000000 { 199 opp-1800000000 {
202 opp-hz = /bits/ 64 <18 200 opp-hz = /bits/ 64 <1800000000>;
203 opp-microvolt = <95000 201 opp-microvolt = <950000>;
204 required-opps = <&cci_ 202 required-opps = <&cci_opp_12>;
205 }; 203 };
206 204
207 opp-1866000000 { 205 opp-1866000000 {
208 opp-hz = /bits/ 64 <18 206 opp-hz = /bits/ 64 <1866000000>;
209 opp-microvolt = <98125 207 opp-microvolt = <981250>;
210 required-opps = <&cci_ 208 required-opps = <&cci_opp_13>;
211 }; 209 };
212 210
213 opp-1933000000 { 211 opp-1933000000 {
214 opp-hz = /bits/ 64 <19 212 opp-hz = /bits/ 64 <1933000000>;
215 opp-microvolt = <10062 213 opp-microvolt = <1006250>;
216 required-opps = <&cci_ 214 required-opps = <&cci_opp_14>;
217 }; 215 };
218 216
219 opp-2000000000 { 217 opp-2000000000 {
220 opp-hz = /bits/ 64 <20 218 opp-hz = /bits/ 64 <2000000000>;
221 opp-microvolt = <10312 219 opp-microvolt = <1031250>;
222 required-opps = <&cci_ 220 required-opps = <&cci_opp_15>;
223 }; 221 };
224 }; 222 };
225 223
226 cluster1_opp: opp-table-cluster1 { 224 cluster1_opp: opp-table-cluster1 {
227 compatible = "operating-points 225 compatible = "operating-points-v2";
228 opp-shared; 226 opp-shared;
229 227
230 opp-774000000 { 228 opp-774000000 {
231 opp-hz = /bits/ 64 <77 229 opp-hz = /bits/ 64 <774000000>;
232 opp-microvolt = <67500 230 opp-microvolt = <675000>;
233 required-opps = <&cci_ 231 required-opps = <&cci_opp_0>;
234 }; 232 };
235 233
236 opp-835000000 { 234 opp-835000000 {
237 opp-hz = /bits/ 64 <83 235 opp-hz = /bits/ 64 <835000000>;
238 opp-microvolt = <69375 236 opp-microvolt = <693750>;
239 required-opps = <&cci_ 237 required-opps = <&cci_opp_1>;
240 }; 238 };
241 239
242 opp-919000000 { 240 opp-919000000 {
243 opp-hz = /bits/ 64 <91 241 opp-hz = /bits/ 64 <919000000>;
244 opp-microvolt = <71875 242 opp-microvolt = <718750>;
245 required-opps = <&cci_ 243 required-opps = <&cci_opp_2>;
246 }; 244 };
247 245
248 opp-1002000000 { 246 opp-1002000000 {
249 opp-hz = /bits/ 64 <10 247 opp-hz = /bits/ 64 <1002000000>;
250 opp-microvolt = <74375 248 opp-microvolt = <743750>;
251 required-opps = <&cci_ 249 required-opps = <&cci_opp_3>;
252 }; 250 };
253 251
254 opp-1085000000 { 252 opp-1085000000 {
255 opp-hz = /bits/ 64 <10 253 opp-hz = /bits/ 64 <1085000000>;
256 opp-microvolt = <77500 254 opp-microvolt = <775000>;
257 required-opps = <&cci_ 255 required-opps = <&cci_opp_4>;
258 }; 256 };
259 257
260 opp-1169000000 { 258 opp-1169000000 {
261 opp-hz = /bits/ 64 <11 259 opp-hz = /bits/ 64 <1169000000>;
262 opp-microvolt = <80000 260 opp-microvolt = <800000>;
263 required-opps = <&cci_ 261 required-opps = <&cci_opp_5>;
264 }; 262 };
265 263
266 opp-1308000000 { 264 opp-1308000000 {
267 opp-hz = /bits/ 64 <13 265 opp-hz = /bits/ 64 <1308000000>;
268 opp-microvolt = <84375 266 opp-microvolt = <843750>;
269 required-opps = <&cci_ 267 required-opps = <&cci_opp_6>;
270 }; 268 };
271 269
272 opp-1419000000 { 270 opp-1419000000 {
273 opp-hz = /bits/ 64 <14 271 opp-hz = /bits/ 64 <1419000000>;
274 opp-microvolt = <87500 272 opp-microvolt = <875000>;
275 required-opps = <&cci_ 273 required-opps = <&cci_opp_7>;
276 }; 274 };
277 275
278 opp-1530000000 { 276 opp-1530000000 {
279 opp-hz = /bits/ 64 <15 277 opp-hz = /bits/ 64 <1530000000>;
280 opp-microvolt = <91250 278 opp-microvolt = <912500>;
281 required-opps = <&cci_ 279 required-opps = <&cci_opp_8>;
282 }; 280 };
283 281
284 opp-1670000000 { 282 opp-1670000000 {
285 opp-hz = /bits/ 64 <16 283 opp-hz = /bits/ 64 <1670000000>;
286 opp-microvolt = <95625 284 opp-microvolt = <956250>;
287 required-opps = <&cci_ 285 required-opps = <&cci_opp_9>;
288 }; 286 };
289 287
290 opp-1733000000 { 288 opp-1733000000 {
291 opp-hz = /bits/ 64 <17 289 opp-hz = /bits/ 64 <1733000000>;
292 opp-microvolt = <98125 290 opp-microvolt = <981250>;
293 required-opps = <&cci_ 291 required-opps = <&cci_opp_10>;
294 }; 292 };
295 293
296 opp-1796000000 { 294 opp-1796000000 {
297 opp-hz = /bits/ 64 <17 295 opp-hz = /bits/ 64 <1796000000>;
298 opp-microvolt = <10125 296 opp-microvolt = <1012500>;
299 required-opps = <&cci_ 297 required-opps = <&cci_opp_11>;
300 }; 298 };
301 299
302 opp-1860000000 { 300 opp-1860000000 {
303 opp-hz = /bits/ 64 <18 301 opp-hz = /bits/ 64 <1860000000>;
304 opp-microvolt = <10375 302 opp-microvolt = <1037500>;
305 required-opps = <&cci_ 303 required-opps = <&cci_opp_12>;
306 }; 304 };
307 305
308 opp-1923000000 { 306 opp-1923000000 {
309 opp-hz = /bits/ 64 <19 307 opp-hz = /bits/ 64 <1923000000>;
310 opp-microvolt = <10625 308 opp-microvolt = <1062500>;
311 required-opps = <&cci_ 309 required-opps = <&cci_opp_13>;
312 }; 310 };
313 311
314 cluster1_opp_14: opp-198600000 312 cluster1_opp_14: opp-1986000000 {
315 opp-hz = /bits/ 64 <19 313 opp-hz = /bits/ 64 <1986000000>;
316 opp-microvolt = <10937 314 opp-microvolt = <1093750>;
317 required-opps = <&cci_ 315 required-opps = <&cci_opp_14>;
318 }; 316 };
319 317
320 cluster1_opp_15: opp-205000000 318 cluster1_opp_15: opp-2050000000 {
321 opp-hz = /bits/ 64 <20 319 opp-hz = /bits/ 64 <2050000000>;
322 opp-microvolt = <11187 320 opp-microvolt = <1118750>;
323 required-opps = <&cci_ 321 required-opps = <&cci_opp_15>;
324 }; 322 };
325 }; 323 };
326 324
327 cpus { 325 cpus {
328 #address-cells = <1>; 326 #address-cells = <1>;
329 #size-cells = <0>; 327 #size-cells = <0>;
330 328
331 cpu-map { 329 cpu-map {
332 cluster0 { 330 cluster0 {
333 core0 { 331 core0 {
334 cpu = 332 cpu = <&cpu0>;
335 }; 333 };
336 334
337 core1 { 335 core1 {
338 cpu = 336 cpu = <&cpu1>;
339 }; 337 };
340 338
341 core2 { 339 core2 {
342 cpu = 340 cpu = <&cpu2>;
343 }; 341 };
344 342
345 core3 { 343 core3 {
346 cpu = 344 cpu = <&cpu3>;
347 }; 345 };
348 346
349 core4 { 347 core4 {
350 cpu = 348 cpu = <&cpu4>;
351 }; 349 };
352 350
353 core5 { 351 core5 {
354 cpu = 352 cpu = <&cpu5>;
355 }; 353 };
356 354
357 core6 { 355 core6 {
358 cpu = 356 cpu = <&cpu6>;
359 }; 357 };
360 358
361 core7 { 359 core7 {
362 cpu = 360 cpu = <&cpu7>;
363 }; 361 };
364 }; 362 };
365 }; 363 };
366 364
367 cpu0: cpu@0 { 365 cpu0: cpu@0 {
368 device_type = "cpu"; 366 device_type = "cpu";
369 compatible = "arm,cort 367 compatible = "arm,cortex-a55";
370 reg = <0x000>; 368 reg = <0x000>;
371 enable-method = "psci" 369 enable-method = "psci";
372 clock-frequency = <200 370 clock-frequency = <2000000000>;
373 clocks = <&mcusys CLK_ 371 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
374 <&apmixedsys 372 <&apmixedsys CLK_APMIXED_MAINPLL>;
375 clock-names = "cpu", " 373 clock-names = "cpu", "intermediate";
376 operating-points-v2 = 374 operating-points-v2 = <&cluster0_opp>;
377 dynamic-power-coeffici 375 dynamic-power-coefficient = <84>;
378 capacity-dmips-mhz = < 376 capacity-dmips-mhz = <382>;
379 cpu-idle-states = <&cp 377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
380 i-cache-size = <32768> 378 i-cache-size = <32768>;
381 i-cache-line-size = <6 379 i-cache-line-size = <64>;
382 i-cache-sets = <128>; 380 i-cache-sets = <128>;
383 d-cache-size = <32768> 381 d-cache-size = <32768>;
384 d-cache-line-size = <6 382 d-cache-line-size = <64>;
385 d-cache-sets = <128>; 383 d-cache-sets = <128>;
386 next-level-cache = <&l 384 next-level-cache = <&l2_0>;
387 #cooling-cells = <2>; 385 #cooling-cells = <2>;
388 mediatek,cci = <&cci>; 386 mediatek,cci = <&cci>;
389 }; 387 };
390 388
391 cpu1: cpu@100 { 389 cpu1: cpu@100 {
392 device_type = "cpu"; 390 device_type = "cpu";
393 compatible = "arm,cort 391 compatible = "arm,cortex-a55";
394 reg = <0x100>; 392 reg = <0x100>;
395 enable-method = "psci" 393 enable-method = "psci";
396 clock-frequency = <200 394 clock-frequency = <2000000000>;
397 clocks = <&mcusys CLK_ 395 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
398 <&apmixedsys 396 <&apmixedsys CLK_APMIXED_MAINPLL>;
399 clock-names = "cpu", " 397 clock-names = "cpu", "intermediate";
400 operating-points-v2 = 398 operating-points-v2 = <&cluster0_opp>;
401 dynamic-power-coeffici 399 dynamic-power-coefficient = <84>;
402 capacity-dmips-mhz = < 400 capacity-dmips-mhz = <382>;
403 cpu-idle-states = <&cp 401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
404 i-cache-size = <32768> 402 i-cache-size = <32768>;
405 i-cache-line-size = <6 403 i-cache-line-size = <64>;
406 i-cache-sets = <128>; 404 i-cache-sets = <128>;
407 d-cache-size = <32768> 405 d-cache-size = <32768>;
408 d-cache-line-size = <6 406 d-cache-line-size = <64>;
409 d-cache-sets = <128>; 407 d-cache-sets = <128>;
410 next-level-cache = <&l 408 next-level-cache = <&l2_0>;
411 #cooling-cells = <2>; 409 #cooling-cells = <2>;
412 mediatek,cci = <&cci>; 410 mediatek,cci = <&cci>;
413 }; 411 };
414 412
415 cpu2: cpu@200 { 413 cpu2: cpu@200 {
416 device_type = "cpu"; 414 device_type = "cpu";
417 compatible = "arm,cort 415 compatible = "arm,cortex-a55";
418 reg = <0x200>; 416 reg = <0x200>;
419 enable-method = "psci" 417 enable-method = "psci";
420 clock-frequency = <200 418 clock-frequency = <2000000000>;
421 clocks = <&mcusys CLK_ 419 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
422 <&apmixedsys 420 <&apmixedsys CLK_APMIXED_MAINPLL>;
423 clock-names = "cpu", " 421 clock-names = "cpu", "intermediate";
424 operating-points-v2 = 422 operating-points-v2 = <&cluster0_opp>;
425 dynamic-power-coeffici 423 dynamic-power-coefficient = <84>;
426 capacity-dmips-mhz = < 424 capacity-dmips-mhz = <382>;
427 cpu-idle-states = <&cp 425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
428 i-cache-size = <32768> 426 i-cache-size = <32768>;
429 i-cache-line-size = <6 427 i-cache-line-size = <64>;
430 i-cache-sets = <128>; 428 i-cache-sets = <128>;
431 d-cache-size = <32768> 429 d-cache-size = <32768>;
432 d-cache-line-size = <6 430 d-cache-line-size = <64>;
433 d-cache-sets = <128>; 431 d-cache-sets = <128>;
434 next-level-cache = <&l 432 next-level-cache = <&l2_0>;
435 #cooling-cells = <2>; 433 #cooling-cells = <2>;
436 mediatek,cci = <&cci>; 434 mediatek,cci = <&cci>;
437 }; 435 };
438 436
439 cpu3: cpu@300 { 437 cpu3: cpu@300 {
440 device_type = "cpu"; 438 device_type = "cpu";
441 compatible = "arm,cort 439 compatible = "arm,cortex-a55";
442 reg = <0x300>; 440 reg = <0x300>;
443 enable-method = "psci" 441 enable-method = "psci";
444 clock-frequency = <200 442 clock-frequency = <2000000000>;
445 clocks = <&mcusys CLK_ 443 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
446 <&apmixedsys 444 <&apmixedsys CLK_APMIXED_MAINPLL>;
447 clock-names = "cpu", " 445 clock-names = "cpu", "intermediate";
448 operating-points-v2 = 446 operating-points-v2 = <&cluster0_opp>;
449 dynamic-power-coeffici 447 dynamic-power-coefficient = <84>;
450 capacity-dmips-mhz = < 448 capacity-dmips-mhz = <382>;
451 cpu-idle-states = <&cp 449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
452 i-cache-size = <32768> 450 i-cache-size = <32768>;
453 i-cache-line-size = <6 451 i-cache-line-size = <64>;
454 i-cache-sets = <128>; 452 i-cache-sets = <128>;
455 d-cache-size = <32768> 453 d-cache-size = <32768>;
456 d-cache-line-size = <6 454 d-cache-line-size = <64>;
457 d-cache-sets = <128>; 455 d-cache-sets = <128>;
458 next-level-cache = <&l 456 next-level-cache = <&l2_0>;
459 #cooling-cells = <2>; 457 #cooling-cells = <2>;
460 mediatek,cci = <&cci>; 458 mediatek,cci = <&cci>;
461 }; 459 };
462 460
463 cpu4: cpu@400 { 461 cpu4: cpu@400 {
464 device_type = "cpu"; 462 device_type = "cpu";
465 compatible = "arm,cort 463 compatible = "arm,cortex-a55";
466 reg = <0x400>; 464 reg = <0x400>;
467 enable-method = "psci" 465 enable-method = "psci";
468 clock-frequency = <200 466 clock-frequency = <2000000000>;
469 clocks = <&mcusys CLK_ 467 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
470 <&apmixedsys 468 <&apmixedsys CLK_APMIXED_MAINPLL>;
471 clock-names = "cpu", " 469 clock-names = "cpu", "intermediate";
472 operating-points-v2 = 470 operating-points-v2 = <&cluster0_opp>;
473 dynamic-power-coeffici 471 dynamic-power-coefficient = <84>;
474 capacity-dmips-mhz = < 472 capacity-dmips-mhz = <382>;
475 cpu-idle-states = <&cp 473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
476 i-cache-size = <32768> 474 i-cache-size = <32768>;
477 i-cache-line-size = <6 475 i-cache-line-size = <64>;
478 i-cache-sets = <128>; 476 i-cache-sets = <128>;
479 d-cache-size = <32768> 477 d-cache-size = <32768>;
480 d-cache-line-size = <6 478 d-cache-line-size = <64>;
481 d-cache-sets = <128>; 479 d-cache-sets = <128>;
482 next-level-cache = <&l 480 next-level-cache = <&l2_0>;
483 #cooling-cells = <2>; 481 #cooling-cells = <2>;
484 mediatek,cci = <&cci>; 482 mediatek,cci = <&cci>;
485 }; 483 };
486 484
487 cpu5: cpu@500 { 485 cpu5: cpu@500 {
488 device_type = "cpu"; 486 device_type = "cpu";
489 compatible = "arm,cort 487 compatible = "arm,cortex-a55";
490 reg = <0x500>; 488 reg = <0x500>;
491 enable-method = "psci" 489 enable-method = "psci";
492 clock-frequency = <200 490 clock-frequency = <2000000000>;
493 clocks = <&mcusys CLK_ 491 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
494 <&apmixedsys 492 <&apmixedsys CLK_APMIXED_MAINPLL>;
495 clock-names = "cpu", " 493 clock-names = "cpu", "intermediate";
496 operating-points-v2 = 494 operating-points-v2 = <&cluster0_opp>;
497 dynamic-power-coeffici 495 dynamic-power-coefficient = <84>;
498 capacity-dmips-mhz = < 496 capacity-dmips-mhz = <382>;
499 cpu-idle-states = <&cp 497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
500 i-cache-size = <32768> 498 i-cache-size = <32768>;
501 i-cache-line-size = <6 499 i-cache-line-size = <64>;
502 i-cache-sets = <128>; 500 i-cache-sets = <128>;
503 d-cache-size = <32768> 501 d-cache-size = <32768>;
504 d-cache-line-size = <6 502 d-cache-line-size = <64>;
505 d-cache-sets = <128>; 503 d-cache-sets = <128>;
506 next-level-cache = <&l 504 next-level-cache = <&l2_0>;
507 #cooling-cells = <2>; 505 #cooling-cells = <2>;
508 mediatek,cci = <&cci>; 506 mediatek,cci = <&cci>;
509 }; 507 };
510 508
511 cpu6: cpu@600 { 509 cpu6: cpu@600 {
512 device_type = "cpu"; 510 device_type = "cpu";
513 compatible = "arm,cort 511 compatible = "arm,cortex-a76";
514 reg = <0x600>; 512 reg = <0x600>;
515 enable-method = "psci" 513 enable-method = "psci";
516 clock-frequency = <205 514 clock-frequency = <2050000000>;
517 clocks = <&mcusys CLK_ 515 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
518 <&apmixedsys 516 <&apmixedsys CLK_APMIXED_MAINPLL>;
519 clock-names = "cpu", " 517 clock-names = "cpu", "intermediate";
520 operating-points-v2 = 518 operating-points-v2 = <&cluster1_opp>;
521 dynamic-power-coeffici 519 dynamic-power-coefficient = <335>;
522 capacity-dmips-mhz = < 520 capacity-dmips-mhz = <1024>;
523 cpu-idle-states = <&cp 521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
524 i-cache-size = <65536> 522 i-cache-size = <65536>;
525 i-cache-line-size = <6 523 i-cache-line-size = <64>;
526 i-cache-sets = <256>; 524 i-cache-sets = <256>;
527 d-cache-size = <65536> 525 d-cache-size = <65536>;
528 d-cache-line-size = <6 526 d-cache-line-size = <64>;
529 d-cache-sets = <256>; 527 d-cache-sets = <256>;
530 next-level-cache = <&l 528 next-level-cache = <&l2_1>;
531 #cooling-cells = <2>; 529 #cooling-cells = <2>;
532 mediatek,cci = <&cci>; 530 mediatek,cci = <&cci>;
533 }; 531 };
534 532
535 cpu7: cpu@700 { 533 cpu7: cpu@700 {
536 device_type = "cpu"; 534 device_type = "cpu";
537 compatible = "arm,cort 535 compatible = "arm,cortex-a76";
538 reg = <0x700>; 536 reg = <0x700>;
539 enable-method = "psci" 537 enable-method = "psci";
540 clock-frequency = <205 538 clock-frequency = <2050000000>;
541 clocks = <&mcusys CLK_ 539 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
542 <&apmixedsys 540 <&apmixedsys CLK_APMIXED_MAINPLL>;
543 clock-names = "cpu", " 541 clock-names = "cpu", "intermediate";
544 operating-points-v2 = 542 operating-points-v2 = <&cluster1_opp>;
545 dynamic-power-coeffici 543 dynamic-power-coefficient = <335>;
546 capacity-dmips-mhz = < 544 capacity-dmips-mhz = <1024>;
547 cpu-idle-states = <&cp 545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
548 i-cache-size = <65536> 546 i-cache-size = <65536>;
549 i-cache-line-size = <6 547 i-cache-line-size = <64>;
550 i-cache-sets = <256>; 548 i-cache-sets = <256>;
551 d-cache-size = <65536> 549 d-cache-size = <65536>;
552 d-cache-line-size = <6 550 d-cache-line-size = <64>;
553 d-cache-sets = <256>; 551 d-cache-sets = <256>;
554 next-level-cache = <&l 552 next-level-cache = <&l2_1>;
555 #cooling-cells = <2>; 553 #cooling-cells = <2>;
556 mediatek,cci = <&cci>; 554 mediatek,cci = <&cci>;
557 }; 555 };
558 556
559 idle-states { 557 idle-states {
560 entry-method = "psci"; 558 entry-method = "psci";
561 559
562 cpu_ret_l: cpu-retenti 560 cpu_ret_l: cpu-retention-l {
563 compatible = " 561 compatible = "arm,idle-state";
564 arm,psci-suspe 562 arm,psci-suspend-param = <0x00010001>;
565 local-timer-st 563 local-timer-stop;
566 entry-latency- 564 entry-latency-us = <50>;
567 exit-latency-u 565 exit-latency-us = <100>;
568 min-residency- 566 min-residency-us = <1600>;
569 }; 567 };
570 568
571 cpu_ret_b: cpu-retenti 569 cpu_ret_b: cpu-retention-b {
572 compatible = " 570 compatible = "arm,idle-state";
573 arm,psci-suspe 571 arm,psci-suspend-param = <0x00010001>;
574 local-timer-st 572 local-timer-stop;
575 entry-latency- 573 entry-latency-us = <50>;
576 exit-latency-u 574 exit-latency-us = <100>;
577 min-residency- 575 min-residency-us = <1400>;
578 }; 576 };
579 577
580 cpu_off_l: cpu-off-l { 578 cpu_off_l: cpu-off-l {
581 compatible = " 579 compatible = "arm,idle-state";
582 arm,psci-suspe 580 arm,psci-suspend-param = <0x01010001>;
583 local-timer-st 581 local-timer-stop;
584 entry-latency- 582 entry-latency-us = <100>;
585 exit-latency-u 583 exit-latency-us = <250>;
586 min-residency- 584 min-residency-us = <2100>;
587 }; 585 };
588 586
589 cpu_off_b: cpu-off-b { 587 cpu_off_b: cpu-off-b {
590 compatible = " 588 compatible = "arm,idle-state";
591 arm,psci-suspe 589 arm,psci-suspend-param = <0x01010001>;
592 local-timer-st 590 local-timer-stop;
593 entry-latency- 591 entry-latency-us = <100>;
594 exit-latency-u 592 exit-latency-us = <250>;
595 min-residency- 593 min-residency-us = <1900>;
596 }; 594 };
597 }; 595 };
598 596
599 l2_0: l2-cache0 { 597 l2_0: l2-cache0 {
600 compatible = "cache"; 598 compatible = "cache";
601 cache-level = <2>; 599 cache-level = <2>;
602 cache-size = <131072>; 600 cache-size = <131072>;
603 cache-line-size = <64> 601 cache-line-size = <64>;
604 cache-sets = <512>; 602 cache-sets = <512>;
605 next-level-cache = <&l 603 next-level-cache = <&l3_0>;
606 cache-unified; 604 cache-unified;
607 }; 605 };
608 606
609 l2_1: l2-cache1 { 607 l2_1: l2-cache1 {
610 compatible = "cache"; 608 compatible = "cache";
611 cache-level = <2>; 609 cache-level = <2>;
612 cache-size = <262144>; 610 cache-size = <262144>;
613 cache-line-size = <64> 611 cache-line-size = <64>;
614 cache-sets = <512>; 612 cache-sets = <512>;
615 next-level-cache = <&l 613 next-level-cache = <&l3_0>;
616 cache-unified; 614 cache-unified;
617 }; 615 };
618 616
619 l3_0: l3-cache { 617 l3_0: l3-cache {
620 compatible = "cache"; 618 compatible = "cache";
621 cache-level = <3>; 619 cache-level = <3>;
622 cache-size = <1048576> 620 cache-size = <1048576>;
623 cache-line-size = <64> 621 cache-line-size = <64>;
624 cache-sets = <1024>; 622 cache-sets = <1024>;
625 cache-unified; 623 cache-unified;
626 }; 624 };
627 }; 625 };
628 626
629 clk13m: fixed-factor-clock-13m { 627 clk13m: fixed-factor-clock-13m {
630 compatible = "fixed-factor-clo 628 compatible = "fixed-factor-clock";
631 #clock-cells = <0>; 629 #clock-cells = <0>;
632 clocks = <&clk26m>; 630 clocks = <&clk26m>;
633 clock-div = <2>; 631 clock-div = <2>;
634 clock-mult = <1>; 632 clock-mult = <1>;
635 clock-output-names = "clk13m"; 633 clock-output-names = "clk13m";
636 }; 634 };
637 635
638 clk26m: oscillator-26m { 636 clk26m: oscillator-26m {
639 compatible = "fixed-clock"; 637 compatible = "fixed-clock";
640 #clock-cells = <0>; 638 #clock-cells = <0>;
641 clock-frequency = <26000000>; 639 clock-frequency = <26000000>;
642 clock-output-names = "clk26m"; 640 clock-output-names = "clk26m";
643 }; 641 };
644 642
645 clk32k: oscillator-32k { 643 clk32k: oscillator-32k {
646 compatible = "fixed-clock"; 644 compatible = "fixed-clock";
647 #clock-cells = <0>; 645 #clock-cells = <0>;
648 clock-frequency = <32768>; 646 clock-frequency = <32768>;
649 clock-output-names = "clk32k"; 647 clock-output-names = "clk32k";
650 }; 648 };
651 649
652 gpu_opp_table: opp-table-gpu { 650 gpu_opp_table: opp-table-gpu {
653 compatible = "operating-points 651 compatible = "operating-points-v2";
654 652
655 opp-299000000 { 653 opp-299000000 {
656 opp-hz = /bits/ 64 <29 654 opp-hz = /bits/ 64 <299000000>;
657 opp-microvolt = <61250 655 opp-microvolt = <612500>;
658 opp-supported-hw = <0x 656 opp-supported-hw = <0xff>;
659 }; 657 };
660 658
661 opp-332000000 { 659 opp-332000000 {
662 opp-hz = /bits/ 64 <33 660 opp-hz = /bits/ 64 <332000000>;
663 opp-microvolt = <62500 661 opp-microvolt = <625000>;
664 opp-supported-hw = <0x 662 opp-supported-hw = <0xff>;
665 }; 663 };
666 664
667 opp-366000000 { 665 opp-366000000 {
668 opp-hz = /bits/ 64 <36 666 opp-hz = /bits/ 64 <366000000>;
669 opp-microvolt = <63750 667 opp-microvolt = <637500>;
670 opp-supported-hw = <0x 668 opp-supported-hw = <0xff>;
671 }; 669 };
672 670
673 opp-400000000 { 671 opp-400000000 {
674 opp-hz = /bits/ 64 <40 672 opp-hz = /bits/ 64 <400000000>;
675 opp-microvolt = <64375 673 opp-microvolt = <643750>;
676 opp-supported-hw = <0x 674 opp-supported-hw = <0xff>;
677 }; 675 };
678 676
679 opp-434000000 { 677 opp-434000000 {
680 opp-hz = /bits/ 64 <43 678 opp-hz = /bits/ 64 <434000000>;
681 opp-microvolt = <65625 679 opp-microvolt = <656250>;
682 opp-supported-hw = <0x 680 opp-supported-hw = <0xff>;
683 }; 681 };
684 682
685 opp-484000000 { 683 opp-484000000 {
686 opp-hz = /bits/ 64 <48 684 opp-hz = /bits/ 64 <484000000>;
687 opp-microvolt = <66875 685 opp-microvolt = <668750>;
688 opp-supported-hw = <0x 686 opp-supported-hw = <0xff>;
689 }; 687 };
690 688
691 opp-535000000 { 689 opp-535000000 {
692 opp-hz = /bits/ 64 <53 690 opp-hz = /bits/ 64 <535000000>;
693 opp-microvolt = <68750 691 opp-microvolt = <687500>;
694 opp-supported-hw = <0x 692 opp-supported-hw = <0xff>;
695 }; 693 };
696 694
697 opp-586000000 { 695 opp-586000000 {
698 opp-hz = /bits/ 64 <58 696 opp-hz = /bits/ 64 <586000000>;
699 opp-microvolt = <70000 697 opp-microvolt = <700000>;
700 opp-supported-hw = <0x 698 opp-supported-hw = <0xff>;
701 }; 699 };
702 700
703 opp-637000000 { 701 opp-637000000 {
704 opp-hz = /bits/ 64 <63 702 opp-hz = /bits/ 64 <637000000>;
705 opp-microvolt = <71250 703 opp-microvolt = <712500>;
706 opp-supported-hw = <0x 704 opp-supported-hw = <0xff>;
707 }; 705 };
708 706
709 opp-690000000 { 707 opp-690000000 {
710 opp-hz = /bits/ 64 <69 708 opp-hz = /bits/ 64 <690000000>;
711 opp-microvolt = <73750 709 opp-microvolt = <737500>;
712 opp-supported-hw = <0x 710 opp-supported-hw = <0xff>;
713 }; 711 };
714 712
715 opp-743000000 { 713 opp-743000000 {
716 opp-hz = /bits/ 64 <74 714 opp-hz = /bits/ 64 <743000000>;
717 opp-microvolt = <75625 715 opp-microvolt = <756250>;
718 opp-supported-hw = <0x 716 opp-supported-hw = <0xff>;
719 }; 717 };
720 718
721 opp-796000000 { 719 opp-796000000 {
722 opp-hz = /bits/ 64 <79 720 opp-hz = /bits/ 64 <796000000>;
723 opp-microvolt = <78125 721 opp-microvolt = <781250>;
724 opp-supported-hw = <0x 722 opp-supported-hw = <0xff>;
725 }; 723 };
726 724
727 opp-850000000 { 725 opp-850000000 {
728 opp-hz = /bits/ 64 <85 726 opp-hz = /bits/ 64 <850000000>;
729 opp-microvolt = <80000 727 opp-microvolt = <800000>;
730 opp-supported-hw = <0x 728 opp-supported-hw = <0xff>;
731 }; 729 };
732 730
733 opp-900000000-3 { 731 opp-900000000-3 {
734 opp-hz = /bits/ 64 <90 732 opp-hz = /bits/ 64 <900000000>;
735 opp-microvolt = <85000 733 opp-microvolt = <850000>;
736 opp-supported-hw = <0x 734 opp-supported-hw = <0xcf>;
737 }; 735 };
738 736
739 opp-900000000-4 { 737 opp-900000000-4 {
740 opp-hz = /bits/ 64 <90 738 opp-hz = /bits/ 64 <900000000>;
741 opp-microvolt = <83750 739 opp-microvolt = <837500>;
742 opp-supported-hw = <0x 740 opp-supported-hw = <0x10>;
743 }; 741 };
744 742
745 opp-900000000-5 { 743 opp-900000000-5 {
746 opp-hz = /bits/ 64 <90 744 opp-hz = /bits/ 64 <900000000>;
747 opp-microvolt = <82500 745 opp-microvolt = <825000>;
748 opp-supported-hw = <0x 746 opp-supported-hw = <0x20>;
749 }; 747 };
750 748
751 opp-950000000-3 { 749 opp-950000000-3 {
752 opp-hz = /bits/ 64 <95 750 opp-hz = /bits/ 64 <950000000>;
753 opp-microvolt = <90000 751 opp-microvolt = <900000>;
754 opp-supported-hw = <0x 752 opp-supported-hw = <0xcf>;
755 }; 753 };
756 754
757 opp-950000000-4 { 755 opp-950000000-4 {
758 opp-hz = /bits/ 64 <95 756 opp-hz = /bits/ 64 <950000000>;
759 opp-microvolt = <87500 757 opp-microvolt = <875000>;
760 opp-supported-hw = <0x 758 opp-supported-hw = <0x10>;
761 }; 759 };
762 760
763 opp-950000000-5 { 761 opp-950000000-5 {
764 opp-hz = /bits/ 64 <95 762 opp-hz = /bits/ 64 <950000000>;
765 opp-microvolt = <85000 763 opp-microvolt = <850000>;
766 opp-supported-hw = <0x 764 opp-supported-hw = <0x20>;
767 }; 765 };
768 766
769 opp-1000000000-3 { 767 opp-1000000000-3 {
770 opp-hz = /bits/ 64 <10 768 opp-hz = /bits/ 64 <1000000000>;
771 opp-microvolt = <95000 769 opp-microvolt = <950000>;
772 opp-supported-hw = <0x 770 opp-supported-hw = <0xcf>;
773 }; 771 };
774 772
775 opp-1000000000-4 { 773 opp-1000000000-4 {
776 opp-hz = /bits/ 64 <10 774 opp-hz = /bits/ 64 <1000000000>;
777 opp-microvolt = <91250 775 opp-microvolt = <912500>;
778 opp-supported-hw = <0x 776 opp-supported-hw = <0x10>;
779 }; 777 };
780 778
781 opp-1000000000-5 { 779 opp-1000000000-5 {
782 opp-hz = /bits/ 64 <10 780 opp-hz = /bits/ 64 <1000000000>;
783 opp-microvolt = <87500 781 opp-microvolt = <875000>;
784 opp-supported-hw = <0x 782 opp-supported-hw = <0x20>;
785 }; 783 };
786 }; 784 };
787 785
788 pmu-a55 { 786 pmu-a55 {
789 compatible = "arm,cortex-a55-p 787 compatible = "arm,cortex-a55-pmu";
790 interrupt-parent = <&gic>; 788 interrupt-parent = <&gic>;
791 interrupts = <GIC_PPI 7 IRQ_TY 789 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
792 }; 790 };
793 791
794 pmu-a76 { 792 pmu-a76 {
795 compatible = "arm,cortex-a76-p 793 compatible = "arm,cortex-a76-pmu";
796 interrupt-parent = <&gic>; 794 interrupt-parent = <&gic>;
797 interrupts = <GIC_PPI 7 IRQ_TY 795 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
798 }; 796 };
799 797
800 psci { 798 psci {
801 compatible = "arm,psci-1.0"; 799 compatible = "arm,psci-1.0";
802 method = "smc"; 800 method = "smc";
803 }; 801 };
804 802
805 timer { 803 timer {
806 compatible = "arm,armv8-timer" 804 compatible = "arm,armv8-timer";
807 interrupt-parent = <&gic>; 805 interrupt-parent = <&gic>;
808 interrupts = <GIC_PPI 13 IRQ_T 806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
809 <GIC_PPI 14 IRQ_T 807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
810 <GIC_PPI 11 IRQ_T 808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
811 <GIC_PPI 10 IRQ_T 809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
812 }; 810 };
813 811
814 soc { 812 soc {
815 #address-cells = <2>; 813 #address-cells = <2>;
816 #size-cells = <2>; 814 #size-cells = <2>;
817 compatible = "simple-bus"; 815 compatible = "simple-bus";
818 dma-ranges = <0x0 0x0 0x0 0x0 816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
819 ranges; 817 ranges;
820 818
821 gic: interrupt-controller@c000 819 gic: interrupt-controller@c000000 {
822 compatible = "arm,gic- 820 compatible = "arm,gic-v3";
823 #interrupt-cells = <4> 821 #interrupt-cells = <4>;
824 #redistributor-regions 822 #redistributor-regions = <1>;
825 interrupt-parent = <&g 823 interrupt-parent = <&gic>;
826 interrupt-controller; 824 interrupt-controller;
827 reg = <0 0x0c000000 0 825 reg = <0 0x0c000000 0 0x40000>,
828 <0 0x0c040000 0 826 <0 0x0c040000 0 0x200000>;
829 interrupts = <GIC_PPI 827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
830 828
831 ppi-partitions { 829 ppi-partitions {
832 ppi_cluster0: 830 ppi_cluster0: interrupt-partition-0 {
833 affini 831 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
834 }; 832 };
835 833
836 ppi_cluster1: 834 ppi_cluster1: interrupt-partition-1 {
837 affini 835 affinity = <&cpu6 &cpu7>;
838 }; 836 };
839 }; 837 };
840 }; 838 };
841 839
842 mcusys: syscon@c53a000 { 840 mcusys: syscon@c53a000 {
843 compatible = "mediatek 841 compatible = "mediatek,mt8186-mcusys", "syscon";
844 reg = <0 0xc53a000 0 0 842 reg = <0 0xc53a000 0 0x1000>;
845 #clock-cells = <1>; 843 #clock-cells = <1>;
846 }; 844 };
847 845
848 topckgen: syscon@10000000 { 846 topckgen: syscon@10000000 {
849 compatible = "mediatek 847 compatible = "mediatek,mt8186-topckgen", "syscon";
850 reg = <0 0x10000000 0 848 reg = <0 0x10000000 0 0x1000>;
851 #clock-cells = <1>; 849 #clock-cells = <1>;
852 }; 850 };
853 851
854 infracfg_ao: syscon@10001000 { 852 infracfg_ao: syscon@10001000 {
855 compatible = "mediatek 853 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
856 reg = <0 0x10001000 0 854 reg = <0 0x10001000 0 0x1000>;
857 #clock-cells = <1>; 855 #clock-cells = <1>;
858 #reset-cells = <1>; 856 #reset-cells = <1>;
859 }; 857 };
860 858
861 pericfg: syscon@10003000 { 859 pericfg: syscon@10003000 {
862 compatible = "mediatek 860 compatible = "mediatek,mt8186-pericfg", "syscon";
863 reg = <0 0x10003000 0 861 reg = <0 0x10003000 0 0x1000>;
864 }; 862 };
865 863
866 pio: pinctrl@10005000 { 864 pio: pinctrl@10005000 {
867 compatible = "mediatek 865 compatible = "mediatek,mt8186-pinctrl";
868 reg = <0 0x10005000 0 866 reg = <0 0x10005000 0 0x1000>,
869 <0 0x10002000 0 867 <0 0x10002000 0 0x0200>,
870 <0 0x10002200 0 868 <0 0x10002200 0 0x0200>,
871 <0 0x10002400 0 869 <0 0x10002400 0 0x0200>,
872 <0 0x10002600 0 870 <0 0x10002600 0 0x0200>,
873 <0 0x10002a00 0 871 <0 0x10002a00 0 0x0200>,
874 <0 0x10002c00 0 872 <0 0x10002c00 0 0x0200>,
875 <0 0x1000b000 0 873 <0 0x1000b000 0 0x1000>;
876 reg-names = "iocfg0", 874 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
877 "iocfg_bl" 875 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
878 gpio-controller; 876 gpio-controller;
879 #gpio-cells = <2>; 877 #gpio-cells = <2>;
880 gpio-ranges = <&pio 0 878 gpio-ranges = <&pio 0 0 185>;
881 interrupt-controller; 879 interrupt-controller;
882 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
883 #interrupt-cells = <2> 881 #interrupt-cells = <2>;
884 }; 882 };
885 883
886 scpsys: syscon@10006000 { 884 scpsys: syscon@10006000 {
887 compatible = "mediatek 885 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
888 reg = <0 0x10006000 0 886 reg = <0 0x10006000 0 0x1000>;
889 887
890 /* System Power Manage 888 /* System Power Manager */
891 spm: power-controller 889 spm: power-controller {
892 compatible = " 890 compatible = "mediatek,mt8186-power-controller";
893 #address-cells 891 #address-cells = <1>;
894 #size-cells = 892 #size-cells = <0>;
895 #power-domain- 893 #power-domain-cells = <1>;
896 894
897 /* power domai 895 /* power domain of the SoC */
898 mfg0: power-do 896 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
899 reg = 897 reg = <MT8186_POWER_DOMAIN_MFG0>;
900 clocks 898 clocks = <&topckgen CLK_TOP_MFG>;
901 clock- 899 clock-names = "mfg00";
902 #addre 900 #address-cells = <1>;
903 #size- 901 #size-cells = <0>;
904 #power 902 #power-domain-cells = <1>;
905 903
906 mfg1: 904 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
907 905 reg = <MT8186_POWER_DOMAIN_MFG1>;
908 906 mediatek,infracfg = <&infracfg_ao>;
909 907 #address-cells = <1>;
910 908 #size-cells = <0>;
911 909 #power-domain-cells = <1>;
912 910
913 911 power-domain@MT8186_POWER_DOMAIN_MFG2 {
914 912 reg = <MT8186_POWER_DOMAIN_MFG2>;
915 913 #power-domain-cells = <0>;
916 914 };
917 915
918 916 power-domain@MT8186_POWER_DOMAIN_MFG3 {
919 917 reg = <MT8186_POWER_DOMAIN_MFG3>;
920 918 #power-domain-cells = <0>;
921 919 };
922 }; 920 };
923 }; 921 };
924 922
925 power-domain@M 923 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
926 reg = 924 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
927 clocks 925 clocks = <&topckgen CLK_TOP_SENINF>,
928 926 <&topckgen CLK_TOP_SENINF1>;
929 clock- 927 clock-names = "subsys-csirx-top0",
930 928 "subsys-csirx-top1";
931 #power 929 #power-domain-cells = <0>;
932 }; 930 };
933 931
934 power-domain@M 932 power-domain@MT8186_POWER_DOMAIN_SSUSB {
935 reg = 933 reg = <MT8186_POWER_DOMAIN_SSUSB>;
936 clocks 934 clocks = <&topckgen CLK_TOP_USB_TOP>,
937 935 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>;
938 clock- 936 clock-names = "sys_ck", "ref_ck";
939 #power 937 #power-domain-cells = <0>;
940 }; 938 };
941 939
942 power-domain@M 940 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
943 reg = 941 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
944 clocks 942 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
945 943 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>;
946 clock- 944 clock-names = "sys_ck", "ref_ck";
947 #power 945 #power-domain-cells = <0>;
948 }; 946 };
949 947
950 power-domain@M 948 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
951 reg = 949 reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
952 clocks 950 clocks = <&topckgen CLK_TOP_AUDIODSP>,
953 951 <&topckgen CLK_TOP_ADSP_BUS>;
954 clock- 952 clock-names = "audioadsp",
955 953 "subsys-adsp-bus";
956 #addre 954 #address-cells = <1>;
957 #size- 955 #size-cells = <0>;
958 #power 956 #power-domain-cells = <1>;
959 957
960 power- 958 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
961 959 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
962 960 #address-cells = <1>;
963 961 #size-cells = <0>;
964 962 #power-domain-cells = <1>;
965 963
966 964 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
967 965 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
968 966 mediatek,infracfg = <&infracfg_ao>;
969 967 #power-domain-cells = <0>;
970 968 };
971 }; 969 };
972 }; 970 };
973 971
974 power-domain@M 972 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
975 reg = 973 reg = <MT8186_POWER_DOMAIN_CONN_ON>;
976 mediat 974 mediatek,infracfg = <&infracfg_ao>;
977 #power 975 #power-domain-cells = <0>;
978 }; 976 };
979 977
980 power-domain@M 978 power-domain@MT8186_POWER_DOMAIN_DIS {
981 reg = 979 reg = <MT8186_POWER_DOMAIN_DIS>;
982 clocks 980 clocks = <&topckgen CLK_TOP_DISP>,
983 981 <&topckgen CLK_TOP_MDP>,
984 982 <&mmsys CLK_MM_SMI_INFRA>,
985 983 <&mmsys CLK_MM_SMI_COMMON>,
986 984 <&mmsys CLK_MM_SMI_GALS>,
987 985 <&mmsys CLK_MM_SMI_IOMMU>;
988 clock- 986 clock-names = "disp", "mdp",
989 987 "subsys-smi-infra",
990 988 "subsys-smi-common",
991 989 "subsys-smi-gals",
992 990 "subsys-smi-iommu";
993 mediat 991 mediatek,infracfg = <&infracfg_ao>;
994 #addre 992 #address-cells = <1>;
995 #size- 993 #size-cells = <0>;
996 #power 994 #power-domain-cells = <1>;
997 995
998 power- 996 power-domain@MT8186_POWER_DOMAIN_VDEC {
999 997 reg = <MT8186_POWER_DOMAIN_VDEC>;
1000 998 clocks = <&topckgen CLK_TOP_VDEC>,
1001 999 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1002 1000 clock-names = "vdec0", "larb";
1003 1001 mediatek,infracfg = <&infracfg_ao>;
1004 1002 #power-domain-cells = <0>;
1005 }; 1003 };
1006 1004
1007 power 1005 power-domain@MT8186_POWER_DOMAIN_CAM {
1008 1006 reg = <MT8186_POWER_DOMAIN_CAM>;
1009 1007 clocks = <&topckgen CLK_TOP_SENINF>,
1010 1008 <&topckgen CLK_TOP_SENINF1>,
1011 1009 <&topckgen CLK_TOP_SENINF2>,
1012 1010 <&topckgen CLK_TOP_SENINF3>,
1013 1011 <&camsys CLK_CAM2MM_GALS>,
1014 1012 <&topckgen CLK_TOP_CAMTM>,
1015 1013 <&topckgen CLK_TOP_CAM>;
1016 1014 clock-names = "cam0", "cam1", "cam2",
1017 1015 "cam3", "gals",
1018 1016 "subsys-cam-tm",
1019 1017 "subsys-cam-top";
1020 1018 mediatek,infracfg = <&infracfg_ao>;
1021 1019 #address-cells = <1>;
1022 1020 #size-cells = <0>;
1023 1021 #power-domain-cells = <1>;
1024 1022
1025 1023 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1026 1024 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
1027 1025 #power-domain-cells = <0>;
1028 1026 };
1029 1027
1030 1028 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1031 1029 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
1032 1030 #power-domain-cells = <0>;
1033 1031 };
1034 }; 1032 };
1035 1033
1036 power 1034 power-domain@MT8186_POWER_DOMAIN_IMG {
1037 1035 reg = <MT8186_POWER_DOMAIN_IMG>;
1038 1036 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1039 1037 <&topckgen CLK_TOP_IMG1>;
1040 1038 clock-names = "gals", "subsys-img-top";
1041 1039 mediatek,infracfg = <&infracfg_ao>;
1042 1040 #address-cells = <1>;
1043 1041 #size-cells = <0>;
1044 1042 #power-domain-cells = <1>;
1045 1043
1046 1044 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1047 1045 reg = <MT8186_POWER_DOMAIN_IMG2>;
1048 1046 #power-domain-cells = <0>;
1049 1047 };
1050 }; 1048 };
1051 1049
1052 power 1050 power-domain@MT8186_POWER_DOMAIN_IPE {
1053 1051 reg = <MT8186_POWER_DOMAIN_IPE>;
1054 1052 clocks = <&topckgen CLK_TOP_IPE>,
1055 1053 <&ipesys CLK_IPE_LARB19>,
1056 1054 <&ipesys CLK_IPE_LARB20>,
1057 1055 <&ipesys CLK_IPE_SMI_SUBCOM>,
1058 1056 <&ipesys CLK_IPE_GALS_IPE>;
1059 1057 clock-names = "subsys-ipe-top",
1060 1058 "subsys-ipe-larb0",
1061 1059 "subsys-ipe-larb1",
1062 1060 "subsys-ipe-smi",
1063 1061 "subsys-ipe-gals";
1064 1062 mediatek,infracfg = <&infracfg_ao>;
1065 1063 #power-domain-cells = <0>;
1066 }; 1064 };
1067 1065
1068 power 1066 power-domain@MT8186_POWER_DOMAIN_VENC {
1069 1067 reg = <MT8186_POWER_DOMAIN_VENC>;
1070 1068 clocks = <&topckgen CLK_TOP_VENC>,
1071 1069 <&vencsys CLK_VENC_CKE1_VENC>;
1072 1070 clock-names = "venc0", "subsys-larb";
1073 1071 mediatek,infracfg = <&infracfg_ao>;
1074 1072 #power-domain-cells = <0>;
1075 }; 1073 };
1076 1074
1077 power 1075 power-domain@MT8186_POWER_DOMAIN_WPE {
1078 1076 reg = <MT8186_POWER_DOMAIN_WPE>;
1079 1077 clocks = <&topckgen CLK_TOP_WPE>,
1080 1078 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1081 1079 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
1082 1080 clock-names = "wpe0",
1083 1081 "subsys-larb-ck",
1084 1082 "subsys-larb-pclk";
1085 1083 mediatek,infracfg = <&infracfg_ao>;
1086 1084 #power-domain-cells = <0>;
1087 }; 1085 };
1088 }; 1086 };
1089 }; 1087 };
1090 }; 1088 };
1091 1089
1092 watchdog: watchdog@10007000 { 1090 watchdog: watchdog@10007000 {
1093 compatible = "mediate 1091 compatible = "mediatek,mt8186-wdt";
1094 mediatek,disable-extr 1092 mediatek,disable-extrst;
1095 reg = <0 0x10007000 0 1093 reg = <0 0x10007000 0 0x1000>;
1096 #reset-cells = <1>; 1094 #reset-cells = <1>;
1097 }; 1095 };
1098 1096
1099 apmixedsys: syscon@1000c000 { 1097 apmixedsys: syscon@1000c000 {
1100 compatible = "mediate 1098 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1101 reg = <0 0x1000c000 0 1099 reg = <0 0x1000c000 0 0x1000>;
1102 #clock-cells = <1>; 1100 #clock-cells = <1>;
1103 }; 1101 };
1104 1102
1105 pwrap: pwrap@1000d000 { 1103 pwrap: pwrap@1000d000 {
1106 compatible = "mediate 1104 compatible = "mediatek,mt8186-pwrap", "syscon";
1107 reg = <0 0x1000d000 0 1105 reg = <0 0x1000d000 0 0x1000>;
1108 reg-names = "pwrap"; 1106 reg-names = "pwrap";
1109 interrupts = <GIC_SPI 1107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1110 clocks = <&infracfg_a 1108 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1111 <&infracfg_a 1109 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1112 clock-names = "spi", 1110 clock-names = "spi", "wrap";
1113 }; 1111 };
1114 1112
1115 spmi: spmi@10015000 { 1113 spmi: spmi@10015000 {
1116 compatible = "mediate 1114 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1117 reg = <0 0x10015000 0 1115 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
1118 reg-names = "pmif", " 1116 reg-names = "pmif", "spmimst";
1119 clocks = <&infracfg_a 1117 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1120 <&infracfg_a 1118 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
1121 <&topckgen C 1119 <&topckgen CLK_TOP_SPMI_MST>;
1122 clock-names = "pmif_s 1120 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1123 assigned-clocks = <&t 1121 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1124 assigned-clock-parent 1122 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1125 interrupts = <GIC_SPI 1123 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
1126 <GIC_SPI 1124 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
1127 status = "disabled"; 1125 status = "disabled";
1128 }; 1126 };
1129 1127
1130 systimer: timer@10017000 { 1128 systimer: timer@10017000 {
1131 compatible = "mediate 1129 compatible = "mediatek,mt8186-timer",
1132 "mediate 1130 "mediatek,mt6765-timer";
1133 reg = <0 0x10017000 0 1131 reg = <0 0x10017000 0 0x1000>;
1134 interrupts = <GIC_SPI 1132 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1135 clocks = <&clk13m>; 1133 clocks = <&clk13m>;
1136 }; 1134 };
1137 1135
1138 gce: mailbox@1022c000 { 1136 gce: mailbox@1022c000 {
1139 compatible = "mediate 1137 compatible = "mediatek,mt8186-gce";
1140 reg = <0 0X1022c000 0 1138 reg = <0 0X1022c000 0 0x4000>;
1141 clocks = <&infracfg_a 1139 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
1142 clock-names = "gce"; 1140 clock-names = "gce";
1143 interrupts = <GIC_SPI 1141 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1144 #mbox-cells = <2>; 1142 #mbox-cells = <2>;
1145 }; 1143 };
1146 1144
1147 scp: scp@10500000 { 1145 scp: scp@10500000 {
1148 compatible = "mediate 1146 compatible = "mediatek,mt8186-scp";
1149 reg = <0 0x10500000 0 1147 reg = <0 0x10500000 0 0x40000>,
1150 <0 0x105c0000 0 1148 <0 0x105c0000 0 0x19080>;
1151 reg-names = "sram", " 1149 reg-names = "sram", "cfg";
1152 interrupts = <GIC_SPI 1150 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1153 }; 1151 };
1154 1152
1155 adsp: adsp@10680000 { 1153 adsp: adsp@10680000 {
1156 compatible = "mediate 1154 compatible = "mediatek,mt8186-dsp";
1157 reg = <0 0x10680000 0 1155 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
1158 <0 0x1068b000 0 1156 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
1159 reg-names = "cfg", "s 1157 reg-names = "cfg", "sram", "sec", "bus";
1160 clocks = <&topckgen C 1158 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
1161 clock-names = "audiod 1159 clock-names = "audiodsp", "adsp_bus";
1162 assigned-clocks = <&t 1160 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1163 <&t 1161 <&topckgen CLK_TOP_ADSP_BUS>;
1164 assigned-clock-parent 1162 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1165 mbox-names = "rx", "t 1163 mbox-names = "rx", "tx";
1166 mboxes = <&adsp_mailb 1164 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
1167 power-domains = <&spm 1165 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1168 status = "disabled"; 1166 status = "disabled";
1169 }; 1167 };
1170 1168
1171 adsp_mailbox0: mailbox@106861 1169 adsp_mailbox0: mailbox@10686100 {
1172 compatible = "mediate 1170 compatible = "mediatek,mt8186-adsp-mbox";
1173 #mbox-cells = <0>; 1171 #mbox-cells = <0>;
1174 reg = <0 0x10686100 0 1172 reg = <0 0x10686100 0 0x1000>;
1175 interrupts = <GIC_SPI 1173 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1176 }; 1174 };
1177 1175
1178 adsp_mailbox1: mailbox@106871 1176 adsp_mailbox1: mailbox@10687100 {
1179 compatible = "mediate 1177 compatible = "mediatek,mt8186-adsp-mbox";
1180 #mbox-cells = <0>; 1178 #mbox-cells = <0>;
1181 reg = <0 0x10687100 0 1179 reg = <0 0x10687100 0 0x1000>;
1182 interrupts = <GIC_SPI 1180 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1183 }; 1181 };
1184 1182
1185 nor_flash: spi@11000000 { 1183 nor_flash: spi@11000000 {
1186 compatible = "mediate 1184 compatible = "mediatek,mt8186-nor";
1187 reg = <0 0x11000000 0 1185 reg = <0 0x11000000 0 0x1000>;
1188 clocks = <&topckgen C 1186 clocks = <&topckgen CLK_TOP_SPINOR>,
1189 <&infracfg_a 1187 <&infracfg_ao CLK_INFRA_AO_SPINOR>,
1190 <&infracfg_a 1188 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
1191 <&infracfg_a 1189 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
1192 clock-names = "spi", 1190 clock-names = "spi", "sf", "axi", "axi_s";
1193 assigned-clocks = <&t 1191 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1194 assigned-clock-parent 1192 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1195 interrupts = <GIC_SPI 1193 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1196 status = "disabled"; 1194 status = "disabled";
1197 }; 1195 };
1198 1196
1199 auxadc: adc@11001000 { 1197 auxadc: adc@11001000 {
1200 compatible = "mediate 1198 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1201 reg = <0 0x11001000 0 1199 reg = <0 0x11001000 0 0x1000>;
1202 #io-channel-cells = < 1200 #io-channel-cells = <1>;
1203 clocks = <&infracfg_a 1201 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1204 clock-names = "main"; 1202 clock-names = "main";
1205 }; 1203 };
1206 1204
1207 uart0: serial@11002000 { 1205 uart0: serial@11002000 {
1208 compatible = "mediate 1206 compatible = "mediatek,mt8186-uart",
1209 "mediate 1207 "mediatek,mt6577-uart";
1210 reg = <0 0x11002000 0 1208 reg = <0 0x11002000 0 0x1000>;
1211 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1212 clocks = <&clk26m>, < 1210 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1213 clock-names = "baud", 1211 clock-names = "baud", "bus";
1214 status = "disabled"; 1212 status = "disabled";
1215 }; 1213 };
1216 1214
1217 uart1: serial@11003000 { 1215 uart1: serial@11003000 {
1218 compatible = "mediate 1216 compatible = "mediatek,mt8186-uart",
1219 "mediate 1217 "mediatek,mt6577-uart";
1220 reg = <0 0x11003000 0 1218 reg = <0 0x11003000 0 0x1000>;
1221 interrupts = <GIC_SPI 1219 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1222 clocks = <&clk26m>, < 1220 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1223 clock-names = "baud", 1221 clock-names = "baud", "bus";
1224 status = "disabled"; 1222 status = "disabled";
1225 }; 1223 };
1226 1224
1227 i2c0: i2c@11007000 { 1225 i2c0: i2c@11007000 {
1228 compatible = "mediate 1226 compatible = "mediatek,mt8186-i2c";
1229 reg = <0 0x11007000 0 1227 reg = <0 0x11007000 0 0x1000>,
1230 <0 0x10200100 0 1228 <0 0x10200100 0 0x100>;
1231 interrupts = <GIC_SPI 1229 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1232 clocks = <&imp_iic_wr 1230 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
1233 <&infracfg_a 1231 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1234 clock-names = "main", 1232 clock-names = "main", "dma";
1235 clock-div = <1>; 1233 clock-div = <1>;
1236 #address-cells = <1>; 1234 #address-cells = <1>;
1237 #size-cells = <0>; 1235 #size-cells = <0>;
1238 status = "disabled"; 1236 status = "disabled";
1239 }; 1237 };
1240 1238
1241 i2c1: i2c@11008000 { 1239 i2c1: i2c@11008000 {
1242 compatible = "mediate 1240 compatible = "mediatek,mt8186-i2c";
1243 reg = <0 0x11008000 0 1241 reg = <0 0x11008000 0 0x1000>,
1244 <0 0x10200200 0 1242 <0 0x10200200 0 0x100>;
1245 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1246 clocks = <&imp_iic_wr 1244 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
1247 <&infracfg_a 1245 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1248 clock-names = "main", 1246 clock-names = "main", "dma";
1249 clock-div = <1>; 1247 clock-div = <1>;
1250 #address-cells = <1>; 1248 #address-cells = <1>;
1251 #size-cells = <0>; 1249 #size-cells = <0>;
1252 status = "disabled"; 1250 status = "disabled";
1253 }; 1251 };
1254 1252
1255 i2c2: i2c@11009000 { 1253 i2c2: i2c@11009000 {
1256 compatible = "mediate 1254 compatible = "mediatek,mt8186-i2c";
1257 reg = <0 0x11009000 0 1255 reg = <0 0x11009000 0 0x1000>,
1258 <0 0x10200300 0 1256 <0 0x10200300 0 0x180>;
1259 interrupts = <GIC_SPI 1257 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1260 clocks = <&imp_iic_wr 1258 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
1261 <&infracfg_a 1259 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1262 clock-names = "main", 1260 clock-names = "main", "dma";
1263 clock-div = <1>; 1261 clock-div = <1>;
1264 #address-cells = <1>; 1262 #address-cells = <1>;
1265 #size-cells = <0>; 1263 #size-cells = <0>;
1266 status = "disabled"; 1264 status = "disabled";
1267 }; 1265 };
1268 1266
1269 i2c3: i2c@1100f000 { 1267 i2c3: i2c@1100f000 {
1270 compatible = "mediate 1268 compatible = "mediatek,mt8186-i2c";
1271 reg = <0 0x1100f000 0 1269 reg = <0 0x1100f000 0 0x1000>,
1272 <0 0x10200480 0 1270 <0 0x10200480 0 0x100>;
1273 interrupts = <GIC_SPI 1271 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1274 clocks = <&imp_iic_wr 1272 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
1275 <&infracfg_a 1273 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1276 clock-names = "main", 1274 clock-names = "main", "dma";
1277 clock-div = <1>; 1275 clock-div = <1>;
1278 #address-cells = <1>; 1276 #address-cells = <1>;
1279 #size-cells = <0>; 1277 #size-cells = <0>;
1280 status = "disabled"; 1278 status = "disabled";
1281 }; 1279 };
1282 1280
1283 i2c4: i2c@11011000 { 1281 i2c4: i2c@11011000 {
1284 compatible = "mediate 1282 compatible = "mediatek,mt8186-i2c";
1285 reg = <0 0x11011000 0 1283 reg = <0 0x11011000 0 0x1000>,
1286 <0 0x10200580 0 1284 <0 0x10200580 0 0x180>;
1287 interrupts = <GIC_SPI 1285 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1288 clocks = <&imp_iic_wr 1286 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
1289 <&infracfg_a 1287 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1290 clock-names = "main", 1288 clock-names = "main", "dma";
1291 clock-div = <1>; 1289 clock-div = <1>;
1292 #address-cells = <1>; 1290 #address-cells = <1>;
1293 #size-cells = <0>; 1291 #size-cells = <0>;
1294 status = "disabled"; 1292 status = "disabled";
1295 }; 1293 };
1296 1294
1297 i2c5: i2c@11016000 { 1295 i2c5: i2c@11016000 {
1298 compatible = "mediate 1296 compatible = "mediatek,mt8186-i2c";
1299 reg = <0 0x11016000 0 1297 reg = <0 0x11016000 0 0x1000>,
1300 <0 0x10200700 0 1298 <0 0x10200700 0 0x100>;
1301 interrupts = <GIC_SPI 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1302 clocks = <&imp_iic_wr 1300 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
1303 <&infracfg_a 1301 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1304 clock-names = "main", 1302 clock-names = "main", "dma";
1305 clock-div = <1>; 1303 clock-div = <1>;
1306 #address-cells = <1>; 1304 #address-cells = <1>;
1307 #size-cells = <0>; 1305 #size-cells = <0>;
1308 status = "disabled"; 1306 status = "disabled";
1309 }; 1307 };
1310 1308
1311 i2c6: i2c@1100d000 { 1309 i2c6: i2c@1100d000 {
1312 compatible = "mediate 1310 compatible = "mediatek,mt8186-i2c";
1313 reg = <0 0x1100d000 0 1311 reg = <0 0x1100d000 0 0x1000>,
1314 <0 0x10200800 0 1312 <0 0x10200800 0 0x100>;
1315 interrupts = <GIC_SPI 1313 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1316 clocks = <&imp_iic_wr 1314 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
1317 <&infracfg_a 1315 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1318 clock-names = "main", 1316 clock-names = "main", "dma";
1319 clock-div = <1>; 1317 clock-div = <1>;
1320 #address-cells = <1>; 1318 #address-cells = <1>;
1321 #size-cells = <0>; 1319 #size-cells = <0>;
1322 status = "disabled"; 1320 status = "disabled";
1323 }; 1321 };
1324 1322
1325 i2c7: i2c@11004000 { 1323 i2c7: i2c@11004000 {
1326 compatible = "mediate 1324 compatible = "mediatek,mt8186-i2c";
1327 reg = <0 0x11004000 0 1325 reg = <0 0x11004000 0 0x1000>,
1328 <0 0x10200900 0 1326 <0 0x10200900 0 0x180>;
1329 interrupts = <GIC_SPI 1327 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1330 clocks = <&imp_iic_wr 1328 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
1331 <&infracfg_a 1329 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1332 clock-names = "main", 1330 clock-names = "main", "dma";
1333 clock-div = <1>; 1331 clock-div = <1>;
1334 #address-cells = <1>; 1332 #address-cells = <1>;
1335 #size-cells = <0>; 1333 #size-cells = <0>;
1336 status = "disabled"; 1334 status = "disabled";
1337 }; 1335 };
1338 1336
1339 i2c8: i2c@11005000 { 1337 i2c8: i2c@11005000 {
1340 compatible = "mediate 1338 compatible = "mediatek,mt8186-i2c";
1341 reg = <0 0x11005000 0 1339 reg = <0 0x11005000 0 0x1000>,
1342 <0 0x10200A80 0 1340 <0 0x10200A80 0 0x180>;
1343 interrupts = <GIC_SPI 1341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1344 clocks = <&imp_iic_wr 1342 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
1345 <&infracfg_a 1343 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1346 clock-names = "main", 1344 clock-names = "main", "dma";
1347 clock-div = <1>; 1345 clock-div = <1>;
1348 #address-cells = <1>; 1346 #address-cells = <1>;
1349 #size-cells = <0>; 1347 #size-cells = <0>;
1350 status = "disabled"; 1348 status = "disabled";
1351 }; 1349 };
1352 1350
1353 spi0: spi@1100a000 { 1351 spi0: spi@1100a000 {
1354 compatible = "mediate 1352 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1355 #address-cells = <1>; 1353 #address-cells = <1>;
1356 #size-cells = <0>; 1354 #size-cells = <0>;
1357 reg = <0 0x1100a000 0 1355 reg = <0 0x1100a000 0 0x1000>;
1358 interrupts = <GIC_SPI 1356 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1359 clocks = <&topckgen C 1357 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1360 <&topckgen C 1358 <&topckgen CLK_TOP_SPI>,
1361 <&infracfg_a 1359 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1362 clock-names = "parent 1360 clock-names = "parent-clk", "sel-clk", "spi-clk";
1363 status = "disabled"; 1361 status = "disabled";
1364 }; 1362 };
1365 1363
1366 lvts: thermal-sensor@1100b000 <<
1367 compatible = "mediate <<
1368 reg = <0 0x1100b000 0 <<
1369 interrupts = <GIC_SPI <<
1370 clocks = <&infracfg_a <<
1371 resets = <&infracfg_a <<
1372 nvmem-cells = <&lvts_ <<
1373 nvmem-cell-names = "l <<
1374 #thermal-sensor-cells <<
1375 }; <<
1376 <<
1377 svs: svs@1100bc00 { <<
1378 compatible = "mediate <<
1379 reg = <0 0x1100bc00 0 <<
1380 interrupts = <GIC_SPI <<
1381 clocks = <&infracfg_a <<
1382 clock-names = "main"; <<
1383 nvmem-cells = <&svs_c <<
1384 nvmem-cell-names = "s <<
1385 resets = <&infracfg_a <<
1386 reset-names = "svs_rs <<
1387 }; <<
1388 <<
1389 pwm0: pwm@1100e000 { 1364 pwm0: pwm@1100e000 {
1390 compatible = "mediate 1365 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1391 reg = <0 0x1100e000 0 1366 reg = <0 0x1100e000 0 0x1000>;
1392 interrupts = <GIC_SPI 1367 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1393 #pwm-cells = <2>; 1368 #pwm-cells = <2>;
1394 clocks = <&topckgen C 1369 clocks = <&topckgen CLK_TOP_DISP_PWM>,
1395 <&infracfg_a 1370 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1396 clock-names = "main", 1371 clock-names = "main", "mm";
1397 status = "disabled"; 1372 status = "disabled";
1398 }; 1373 };
1399 1374
1400 spi1: spi@11010000 { 1375 spi1: spi@11010000 {
1401 compatible = "mediate 1376 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1402 #address-cells = <1>; 1377 #address-cells = <1>;
1403 #size-cells = <0>; 1378 #size-cells = <0>;
1404 reg = <0 0x11010000 0 1379 reg = <0 0x11010000 0 0x1000>;
1405 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1406 clocks = <&topckgen C 1381 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1407 <&topckgen C 1382 <&topckgen CLK_TOP_SPI>,
1408 <&infracfg_a 1383 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1409 clock-names = "parent 1384 clock-names = "parent-clk", "sel-clk", "spi-clk";
1410 status = "disabled"; 1385 status = "disabled";
1411 }; 1386 };
1412 1387
1413 spi2: spi@11012000 { 1388 spi2: spi@11012000 {
1414 compatible = "mediate 1389 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1415 #address-cells = <1>; 1390 #address-cells = <1>;
1416 #size-cells = <0>; 1391 #size-cells = <0>;
1417 reg = <0 0x11012000 0 1392 reg = <0 0x11012000 0 0x1000>;
1418 interrupts = <GIC_SPI 1393 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1419 clocks = <&topckgen C 1394 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1420 <&topckgen C 1395 <&topckgen CLK_TOP_SPI>,
1421 <&infracfg_a 1396 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1422 clock-names = "parent 1397 clock-names = "parent-clk", "sel-clk", "spi-clk";
1423 status = "disabled"; 1398 status = "disabled";
1424 }; 1399 };
1425 1400
1426 spi3: spi@11013000 { 1401 spi3: spi@11013000 {
1427 compatible = "mediate 1402 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1428 #address-cells = <1>; 1403 #address-cells = <1>;
1429 #size-cells = <0>; 1404 #size-cells = <0>;
1430 reg = <0 0x11013000 0 1405 reg = <0 0x11013000 0 0x1000>;
1431 interrupts = <GIC_SPI 1406 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1432 clocks = <&topckgen C 1407 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1433 <&topckgen C 1408 <&topckgen CLK_TOP_SPI>,
1434 <&infracfg_a 1409 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1435 clock-names = "parent 1410 clock-names = "parent-clk", "sel-clk", "spi-clk";
1436 status = "disabled"; 1411 status = "disabled";
1437 }; 1412 };
1438 1413
1439 spi4: spi@11014000 { 1414 spi4: spi@11014000 {
1440 compatible = "mediate 1415 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1441 #address-cells = <1>; 1416 #address-cells = <1>;
1442 #size-cells = <0>; 1417 #size-cells = <0>;
1443 reg = <0 0x11014000 0 1418 reg = <0 0x11014000 0 0x1000>;
1444 interrupts = <GIC_SPI 1419 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1445 clocks = <&topckgen C 1420 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1446 <&topckgen C 1421 <&topckgen CLK_TOP_SPI>,
1447 <&infracfg_a 1422 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1448 clock-names = "parent 1423 clock-names = "parent-clk", "sel-clk", "spi-clk";
1449 status = "disabled"; 1424 status = "disabled";
1450 }; 1425 };
1451 1426
1452 spi5: spi@11015000 { 1427 spi5: spi@11015000 {
1453 compatible = "mediate 1428 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1454 #address-cells = <1>; 1429 #address-cells = <1>;
1455 #size-cells = <0>; 1430 #size-cells = <0>;
1456 reg = <0 0x11015000 0 1431 reg = <0 0x11015000 0 0x1000>;
1457 interrupts = <GIC_SPI 1432 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1458 clocks = <&topckgen C 1433 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1459 <&topckgen C 1434 <&topckgen CLK_TOP_SPI>,
1460 <&infracfg_a 1435 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1461 clock-names = "parent 1436 clock-names = "parent-clk", "sel-clk", "spi-clk";
1462 status = "disabled"; 1437 status = "disabled";
1463 }; 1438 };
1464 1439
1465 imp_iic_wrap: clock-controlle 1440 imp_iic_wrap: clock-controller@11017000 {
1466 compatible = "mediate 1441 compatible = "mediatek,mt8186-imp_iic_wrap";
1467 reg = <0 0x11017000 0 1442 reg = <0 0x11017000 0 0x1000>;
1468 #clock-cells = <1>; 1443 #clock-cells = <1>;
1469 }; 1444 };
1470 1445
1471 uart2: serial@11018000 { 1446 uart2: serial@11018000 {
1472 compatible = "mediate 1447 compatible = "mediatek,mt8186-uart",
1473 "mediate 1448 "mediatek,mt6577-uart";
1474 reg = <0 0x11018000 0 1449 reg = <0 0x11018000 0 0x1000>;
1475 interrupts = <GIC_SPI 1450 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1476 clocks = <&clk26m>, < 1451 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1477 clock-names = "baud", 1452 clock-names = "baud", "bus";
1478 status = "disabled"; 1453 status = "disabled";
1479 }; 1454 };
1480 1455
1481 i2c9: i2c@11019000 { 1456 i2c9: i2c@11019000 {
1482 compatible = "mediate 1457 compatible = "mediatek,mt8186-i2c";
1483 reg = <0 0x11019000 0 1458 reg = <0 0x11019000 0 0x1000>,
1484 <0 0x10200c00 0 1459 <0 0x10200c00 0 0x180>;
1485 interrupts = <GIC_SPI 1460 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1486 clocks = <&imp_iic_wr 1461 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
1487 <&infracfg_a 1462 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1488 clock-names = "main", 1463 clock-names = "main", "dma";
1489 clock-div = <1>; 1464 clock-div = <1>;
1490 #address-cells = <1>; 1465 #address-cells = <1>;
1491 #size-cells = <0>; 1466 #size-cells = <0>;
1492 status = "disabled"; 1467 status = "disabled";
1493 }; 1468 };
1494 1469
1495 afe: audio-controller@1121000 1470 afe: audio-controller@11210000 {
1496 compatible = "mediate 1471 compatible = "mediatek,mt8186-sound";
1497 reg = <0 0x11210000 0 1472 reg = <0 0x11210000 0 0x2000>;
1498 clocks = <&infracfg_a 1473 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
1499 <&infracfg_a 1474 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
1500 <&topckgen C 1475 <&topckgen CLK_TOP_AUDIO>,
1501 <&topckgen C 1476 <&topckgen CLK_TOP_AUD_INTBUS>,
1502 <&topckgen C 1477 <&topckgen CLK_TOP_MAINPLL_D2_D4>,
1503 <&topckgen C 1478 <&topckgen CLK_TOP_AUD_1>,
1504 <&apmixedsys 1479 <&apmixedsys CLK_APMIXED_APLL1>,
1505 <&topckgen C 1480 <&topckgen CLK_TOP_AUD_2>,
1506 <&apmixedsys 1481 <&apmixedsys CLK_APMIXED_APLL2>,
1507 <&topckgen C 1482 <&topckgen CLK_TOP_AUD_ENGEN1>,
1508 <&topckgen C 1483 <&topckgen CLK_TOP_APLL1_D8>,
1509 <&topckgen C 1484 <&topckgen CLK_TOP_AUD_ENGEN2>,
1510 <&topckgen C 1485 <&topckgen CLK_TOP_APLL2_D8>,
1511 <&topckgen C 1486 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
1512 <&topckgen C 1487 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
1513 <&topckgen C 1488 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
1514 <&topckgen C 1489 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
1515 <&topckgen C 1490 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
1516 <&topckgen C 1491 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
1517 <&topckgen C 1492 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
1518 <&topckgen C 1493 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
1519 <&topckgen C 1494 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
1520 <&topckgen C 1495 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
1521 <&topckgen C 1496 <&topckgen CLK_TOP_AUDIO_H>,
1522 <&clk26m>; 1497 <&clk26m>;
1523 clock-names = "aud_in 1498 clock-names = "aud_infra_clk",
1524 "mtkaif 1499 "mtkaif_26m_clk",
1525 "top_mu 1500 "top_mux_audio",
1526 "top_mu 1501 "top_mux_audio_int",
1527 "top_ma 1502 "top_mainpll_d2_d4",
1528 "top_mu 1503 "top_mux_aud_1",
1529 "top_ap 1504 "top_apll1_ck",
1530 "top_mu 1505 "top_mux_aud_2",
1531 "top_ap 1506 "top_apll2_ck",
1532 "top_mu 1507 "top_mux_aud_eng1",
1533 "top_ap 1508 "top_apll1_d8",
1534 "top_mu 1509 "top_mux_aud_eng2",
1535 "top_ap 1510 "top_apll2_d8",
1536 "top_i2 1511 "top_i2s0_m_sel",
1537 "top_i2 1512 "top_i2s1_m_sel",
1538 "top_i2 1513 "top_i2s2_m_sel",
1539 "top_i2 1514 "top_i2s4_m_sel",
1540 "top_td 1515 "top_tdm_m_sel",
1541 "top_ap 1516 "top_apll12_div0",
1542 "top_ap 1517 "top_apll12_div1",
1543 "top_ap 1518 "top_apll12_div2",
1544 "top_ap 1519 "top_apll12_div4",
1545 "top_ap 1520 "top_apll12_div_tdm",
1546 "top_mu 1521 "top_mux_audio_h",
1547 "top_cl 1522 "top_clk26m_clk";
1548 interrupts = <GIC_SPI 1523 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1549 mediatek,apmixedsys = 1524 mediatek,apmixedsys = <&apmixedsys>;
1550 mediatek,infracfg = < 1525 mediatek,infracfg = <&infracfg_ao>;
1551 mediatek,topckgen = < 1526 mediatek,topckgen = <&topckgen>;
1552 resets = <&watchdog M 1527 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
1553 reset-names = "audios 1528 reset-names = "audiosys";
1554 status = "disabled"; 1529 status = "disabled";
1555 }; 1530 };
1556 1531
1557 ssusb0: usb@11201000 { 1532 ssusb0: usb@11201000 {
1558 compatible = "mediate 1533 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1559 reg = <0 0x11201000 0 1534 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1560 reg-names = "mac", "i 1535 reg-names = "mac", "ippc";
1561 clocks = <&topckgen C 1536 clocks = <&topckgen CLK_TOP_USB_TOP>,
1562 <&infracfg_a 1537 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1563 <&infracfg_a 1538 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1564 <&infracfg_a 1539 <&infracfg_ao CLK_INFRA_AO_ICUSB>,
1565 <&infracfg_a 1540 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
1566 clock-names = "sys_ck 1541 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1567 interrupts = <GIC_SPI 1542 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
1568 phys = <&u2port0 PHY_ 1543 phys = <&u2port0 PHY_TYPE_USB2>;
1569 power-domains = <&spm 1544 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1570 #address-cells = <2>; 1545 #address-cells = <2>;
1571 #size-cells = <2>; 1546 #size-cells = <2>;
1572 ranges; 1547 ranges;
1573 status = "disabled"; 1548 status = "disabled";
1574 1549
1575 usb_host0: usb@112000 1550 usb_host0: usb@11200000 {
1576 compatible = 1551 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1577 reg = <0 0x11 1552 reg = <0 0x11200000 0 0x1000>;
1578 reg-names = " 1553 reg-names = "mac";
1579 clocks = <&to 1554 clocks = <&topckgen CLK_TOP_USB_TOP>,
1580 <&in 1555 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1581 <&in 1556 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1582 <&in 1557 <&infracfg_ao CLK_INFRA_AO_ICUSB>,
1583 <&in 1558 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
1584 clock-names = 1559 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1585 interrupts = 1560 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
1586 mediatek,sysc 1561 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1587 wakeup-source 1562 wakeup-source;
1588 status = "dis 1563 status = "disabled";
1589 }; 1564 };
1590 }; 1565 };
1591 1566
1592 mmc0: mmc@11230000 { 1567 mmc0: mmc@11230000 {
1593 compatible = "mediate 1568 compatible = "mediatek,mt8186-mmc",
1594 "mediate 1569 "mediatek,mt8183-mmc";
1595 reg = <0 0x11230000 0 1570 reg = <0 0x11230000 0 0x10000>,
1596 <0 0x11cd0000 0 1571 <0 0x11cd0000 0 0x1000>;
1597 clocks = <&topckgen C 1572 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1598 <&infracfg_a 1573 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1599 <&infracfg_a 1574 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1600 <&infracfg_a 1575 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
1601 clock-names = "source 1576 clock-names = "source", "hclk", "source_cg", "crypto";
1602 interrupts = <GIC_SPI 1577 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1603 assigned-clocks = <&t 1578 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1604 assigned-clock-parent 1579 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1605 status = "disabled"; 1580 status = "disabled";
1606 }; 1581 };
1607 1582
1608 mmc1: mmc@11240000 { 1583 mmc1: mmc@11240000 {
1609 compatible = "mediate 1584 compatible = "mediatek,mt8186-mmc",
1610 "mediate 1585 "mediatek,mt8183-mmc";
1611 reg = <0 0x11240000 0 1586 reg = <0 0x11240000 0 0x1000>,
1612 <0 0x11c90000 0 1587 <0 0x11c90000 0 0x1000>;
1613 clocks = <&topckgen C 1588 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1614 <&infracfg_a 1589 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1615 <&infracfg_a 1590 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1616 clock-names = "source 1591 clock-names = "source", "hclk", "source_cg";
1617 interrupts = <GIC_SPI 1592 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1618 assigned-clocks = <&t 1593 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1619 assigned-clock-parent 1594 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1620 status = "disabled"; 1595 status = "disabled";
1621 }; 1596 };
1622 1597
1623 ssusb1: usb@11281000 { 1598 ssusb1: usb@11281000 {
1624 compatible = "mediate 1599 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1625 reg = <0 0x11281000 0 1600 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
1626 reg-names = "mac", "i 1601 reg-names = "mac", "ippc";
1627 clocks = <&infracfg_a 1602 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1628 <&infracfg_a 1603 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1629 <&infracfg_a 1604 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1630 <&clk26m>, 1605 <&clk26m>,
1631 <&infracfg_a 1606 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
1632 clock-names = "sys_ck 1607 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1633 interrupts = <GIC_SPI 1608 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
1634 phys = <&u2port1 PHY_ 1609 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1635 power-domains = <&spm 1610 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1636 #address-cells = <2>; 1611 #address-cells = <2>;
1637 #size-cells = <2>; 1612 #size-cells = <2>;
1638 ranges; 1613 ranges;
1639 status = "disabled"; 1614 status = "disabled";
1640 1615
1641 usb_host1: usb@112800 1616 usb_host1: usb@11280000 {
1642 compatible = 1617 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1643 reg = <0 0x11 1618 reg = <0 0x11280000 0 0x1000>;
1644 reg-names = " 1619 reg-names = "mac";
1645 clocks = <&in 1620 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1646 <&in 1621 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1647 <&in 1622 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1648 <&cl 1623 <&clk26m>,
1649 <&in 1624 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
1650 clock-names = 1625 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1651 interrupts = 1626 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1652 mediatek,sysc 1627 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1653 wakeup-source 1628 wakeup-source;
1654 status = "dis 1629 status = "disabled";
1655 }; 1630 };
1656 }; 1631 };
1657 1632
1658 u3phy0: t-phy@11c80000 { 1633 u3phy0: t-phy@11c80000 {
1659 compatible = "mediate 1634 compatible = "mediatek,mt8186-tphy",
1660 "mediate 1635 "mediatek,generic-tphy-v2";
1661 #address-cells = <1>; 1636 #address-cells = <1>;
1662 #size-cells = <1>; 1637 #size-cells = <1>;
1663 ranges = <0x0 0x0 0x1 1638 ranges = <0x0 0x0 0x11c80000 0x1000>;
1664 status = "disabled"; 1639 status = "disabled";
1665 1640
1666 u2port1: usb-phy@0 { 1641 u2port1: usb-phy@0 {
1667 reg = <0x0 0x 1642 reg = <0x0 0x700>;
1668 clocks = <&cl 1643 clocks = <&clk26m>;
1669 clock-names = 1644 clock-names = "ref";
1670 #phy-cells = 1645 #phy-cells = <1>;
1671 }; 1646 };
1672 1647
1673 u3port1: usb-phy@700 1648 u3port1: usb-phy@700 {
1674 reg = <0x700 1649 reg = <0x700 0x900>;
1675 clocks = <&cl 1650 clocks = <&clk26m>;
1676 clock-names = 1651 clock-names = "ref";
1677 #phy-cells = 1652 #phy-cells = <1>;
1678 }; 1653 };
1679 }; 1654 };
1680 1655
1681 u3phy1: t-phy@11ca0000 { 1656 u3phy1: t-phy@11ca0000 {
1682 compatible = "mediate 1657 compatible = "mediatek,mt8186-tphy",
1683 "mediate 1658 "mediatek,generic-tphy-v2";
1684 #address-cells = <1>; 1659 #address-cells = <1>;
1685 #size-cells = <1>; 1660 #size-cells = <1>;
1686 ranges = <0x0 0x0 0x1 1661 ranges = <0x0 0x0 0x11ca0000 0x1000>;
1687 status = "disabled"; 1662 status = "disabled";
1688 1663
1689 u2port0: usb-phy@0 { 1664 u2port0: usb-phy@0 {
1690 reg = <0x0 0x 1665 reg = <0x0 0x700>;
1691 clocks = <&cl 1666 clocks = <&clk26m>;
1692 clock-names = 1667 clock-names = "ref";
1693 #phy-cells = 1668 #phy-cells = <1>;
1694 mediatek,disc 1669 mediatek,discth = <0x8>;
1695 }; 1670 };
1696 }; 1671 };
1697 1672
1698 efuse: efuse@11cb0000 { 1673 efuse: efuse@11cb0000 {
1699 compatible = "mediate 1674 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1700 reg = <0 0x11cb0000 0 1675 reg = <0 0x11cb0000 0 0x1000>;
1701 #address-cells = <1>; 1676 #address-cells = <1>;
1702 #size-cells = <1>; 1677 #size-cells = <1>;
1703 1678
1704 lvts_efuse_data1: lvt <<
1705 reg = <0x1cc <<
1706 }; <<
1707 <<
1708 lvts_efuse_data2: lvt <<
1709 reg = <0x2f8 <<
1710 }; <<
1711 <<
1712 svs_calibration: cali <<
1713 reg = <0x550 <<
1714 }; <<
1715 <<
1716 gpu_speedbin: gpu-spe 1679 gpu_speedbin: gpu-speedbin@59c {
1717 reg = <0x59c 1680 reg = <0x59c 0x4>;
1718 bits = <0 3>; 1681 bits = <0 3>;
1719 }; 1682 };
1720 1683
1721 socinfo-data1@7a0 { 1684 socinfo-data1@7a0 {
1722 reg = <0x7a0 1685 reg = <0x7a0 0x4>;
1723 }; 1686 };
1724 }; 1687 };
1725 1688
1726 mipi_tx0: dsi-phy@11cc0000 { 1689 mipi_tx0: dsi-phy@11cc0000 {
1727 compatible = "mediate 1690 compatible = "mediatek,mt8183-mipi-tx";
1728 reg = <0 0x11cc0000 0 1691 reg = <0 0x11cc0000 0 0x1000>;
1729 clocks = <&clk26m>; 1692 clocks = <&clk26m>;
1730 #clock-cells = <0>; 1693 #clock-cells = <0>;
1731 #phy-cells = <0>; 1694 #phy-cells = <0>;
1732 clock-output-names = 1695 clock-output-names = "mipi_tx0_pll";
1733 status = "disabled"; 1696 status = "disabled";
1734 }; 1697 };
1735 1698
1736 mfgsys: clock-controller@1300 1699 mfgsys: clock-controller@13000000 {
1737 compatible = "mediate 1700 compatible = "mediatek,mt8186-mfgsys";
1738 reg = <0 0x13000000 0 1701 reg = <0 0x13000000 0 0x1000>;
1739 #clock-cells = <1>; 1702 #clock-cells = <1>;
1740 }; 1703 };
1741 1704
1742 gpu: gpu@13040000 { 1705 gpu: gpu@13040000 {
1743 compatible = "mediate 1706 compatible = "mediatek,mt8186-mali",
1744 "arm,mal 1707 "arm,mali-bifrost";
1745 reg = <0 0x13040000 0 1708 reg = <0 0x13040000 0 0x4000>;
1746 1709
1747 clocks = <&mfgsys CLK 1710 clocks = <&mfgsys CLK_MFG_BG3D>;
1748 interrupts = <GIC_SPI 1711 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1749 <GIC_SPI 1712 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1750 <GIC_SPI 1713 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1751 interrupt-names = "jo 1714 interrupt-names = "job", "mmu", "gpu";
1752 power-domains = <&spm 1715 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1753 <&spm 1716 <&spm MT8186_POWER_DOMAIN_MFG3>;
1754 power-domain-names = 1717 power-domain-names = "core0", "core1";
1755 #cooling-cells = <2>; 1718 #cooling-cells = <2>;
1756 nvmem-cells = <&gpu_s 1719 nvmem-cells = <&gpu_speedbin>;
1757 nvmem-cell-names = "s 1720 nvmem-cell-names = "speed-bin";
1758 operating-points-v2 = 1721 operating-points-v2 = <&gpu_opp_table>;
1759 dynamic-power-coeffic 1722 dynamic-power-coefficient = <4687>;
1760 status = "disabled"; 1723 status = "disabled";
1761 }; 1724 };
1762 1725
1763 mmsys: syscon@14000000 { 1726 mmsys: syscon@14000000 {
1764 compatible = "mediate 1727 compatible = "mediatek,mt8186-mmsys", "syscon";
1765 reg = <0 0x14000000 0 1728 reg = <0 0x14000000 0 0x1000>;
1766 #clock-cells = <1>; 1729 #clock-cells = <1>;
1767 #reset-cells = <1>; 1730 #reset-cells = <1>;
1768 mboxes = <&gce 0 CMDQ 1731 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1769 <&gce 1 CMDQ 1732 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1770 mediatek,gce-client-r 1733 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1771 }; 1734 };
1772 1735
1773 mutex: mutex@14001000 { 1736 mutex: mutex@14001000 {
1774 compatible = "mediate 1737 compatible = "mediatek,mt8186-disp-mutex";
1775 reg = <0 0x14001000 0 1738 reg = <0 0x14001000 0 0x1000>;
1776 clocks = <&mmsys CLK_ 1739 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1777 interrupts = <GIC_SPI 1740 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
1778 mediatek,gce-client-r 1741 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1779 mediatek,gce-events = 1742 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1780 1743 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1781 power-domains = <&spm 1744 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1782 }; 1745 };
1783 1746
1784 smi_common: smi@14002000 { 1747 smi_common: smi@14002000 {
1785 compatible = "mediate 1748 compatible = "mediatek,mt8186-smi-common";
1786 reg = <0 0x14002000 0 1749 reg = <0 0x14002000 0 0x1000>;
1787 clocks = <&mmsys CLK_ 1750 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1788 <&mmsys CLK_ 1751 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1789 clock-names = "apb", 1752 clock-names = "apb", "smi", "gals0", "gals1";
1790 power-domains = <&spm 1753 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1791 }; 1754 };
1792 1755
1793 larb0: smi@14003000 { 1756 larb0: smi@14003000 {
1794 compatible = "mediate 1757 compatible = "mediatek,mt8186-smi-larb";
1795 reg = <0 0x14003000 0 1758 reg = <0 0x14003000 0 0x1000>;
1796 clocks = <&mmsys CLK_ 1759 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1797 <&mmsys CLK_ 1760 <&mmsys CLK_MM_SMI_COMMON>;
1798 clock-names = "apb", 1761 clock-names = "apb", "smi";
1799 mediatek,larb-id = <0 1762 mediatek,larb-id = <0>;
1800 mediatek,smi = <&smi_ 1763 mediatek,smi = <&smi_common>;
1801 power-domains = <&spm 1764 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1802 }; 1765 };
1803 1766
1804 larb1: smi@14004000 { 1767 larb1: smi@14004000 {
1805 compatible = "mediate 1768 compatible = "mediatek,mt8186-smi-larb";
1806 reg = <0 0x14004000 0 1769 reg = <0 0x14004000 0 0x1000>;
1807 clocks = <&mmsys CLK_ 1770 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1808 <&mmsys CLK_ 1771 <&mmsys CLK_MM_SMI_COMMON>;
1809 clock-names = "apb", 1772 clock-names = "apb", "smi";
1810 mediatek,larb-id = <1 1773 mediatek,larb-id = <1>;
1811 mediatek,smi = <&smi_ 1774 mediatek,smi = <&smi_common>;
1812 power-domains = <&spm 1775 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1813 }; 1776 };
1814 1777
1815 ovl0: ovl@14005000 { 1778 ovl0: ovl@14005000 {
1816 compatible = "mediate 1779 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1817 reg = <0 0x14005000 0 1780 reg = <0 0x14005000 0 0x1000>;
1818 clocks = <&mmsys CLK_ 1781 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1819 interrupts = <GIC_SPI 1782 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
1820 iommus = <&iommu_mm I 1783 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
1821 mediatek,gce-client-r 1784 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1822 power-domains = <&spm 1785 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1823 }; 1786 };
1824 1787
1825 ovl_2l0: ovl@14006000 { 1788 ovl_2l0: ovl@14006000 {
1826 compatible = "mediate 1789 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1827 reg = <0 0x14006000 0 1790 reg = <0 0x14006000 0 0x1000>;
1828 clocks = <&mmsys CLK_ 1791 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1829 interrupts = <GIC_SPI 1792 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
1830 iommus = <&iommu_mm I 1793 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
1831 mediatek,gce-client-r 1794 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1832 power-domains = <&spm 1795 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1833 }; 1796 };
1834 1797
1835 rdma0: rdma@14007000 { 1798 rdma0: rdma@14007000 {
1836 compatible = "mediate 1799 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1837 reg = <0 0x14007000 0 1800 reg = <0 0x14007000 0 0x1000>;
1838 clocks = <&mmsys CLK_ 1801 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1839 interrupts = <GIC_SPI 1802 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
1840 iommus = <&iommu_mm I 1803 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
1841 mediatek,gce-client-r 1804 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1842 power-domains = <&spm 1805 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1843 }; 1806 };
1844 1807
1845 color: color@14009000 { 1808 color: color@14009000 {
1846 compatible = "mediate 1809 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1847 reg = <0 0x14009000 0 1810 reg = <0 0x14009000 0 0x1000>;
1848 clocks = <&mmsys CLK_ 1811 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1849 interrupts = <GIC_SPI 1812 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
1850 mediatek,gce-client-r 1813 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1851 power-domains = <&spm 1814 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1852 }; 1815 };
1853 1816
1854 dpi: dpi@1400a000 { 1817 dpi: dpi@1400a000 {
1855 compatible = "mediate 1818 compatible = "mediatek,mt8186-dpi";
1856 reg = <0 0x1400a000 0 1819 reg = <0 0x1400a000 0 0x1000>;
1857 clocks = <&topckgen C 1820 clocks = <&topckgen CLK_TOP_DPI>,
1858 <&mmsys CLK_ 1821 <&mmsys CLK_MM_DISP_DPI>,
1859 <&apmixedsys 1822 <&apmixedsys CLK_APMIXED_TVDPLL>;
1860 clock-names = "pixel" 1823 clock-names = "pixel", "engine", "pll";
1861 assigned-clocks = <&t 1824 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1862 assigned-clock-parent 1825 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1863 interrupts = <GIC_SPI 1826 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1864 power-domains = <&spm <<
1865 status = "disabled"; 1827 status = "disabled";
1866 1828
1867 port { 1829 port {
1868 dpi_out: endp 1830 dpi_out: endpoint { };
1869 }; 1831 };
1870 }; 1832 };
1871 1833
1872 ccorr: ccorr@1400b000 { 1834 ccorr: ccorr@1400b000 {
1873 compatible = "mediate 1835 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1874 reg = <0 0x1400b000 0 1836 reg = <0 0x1400b000 0 0x1000>;
1875 clocks = <&mmsys CLK_ 1837 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1876 interrupts = <GIC_SPI 1838 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
1877 mediatek,gce-client-r 1839 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1878 power-domains = <&spm 1840 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1879 }; 1841 };
1880 1842
1881 aal: aal@1400c000 { 1843 aal: aal@1400c000 {
1882 compatible = "mediate 1844 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1883 reg = <0 0x1400c000 0 1845 reg = <0 0x1400c000 0 0x1000>;
1884 clocks = <&mmsys CLK_ 1846 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1885 interrupts = <GIC_SPI 1847 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
1886 mediatek,gce-client-r 1848 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1887 power-domains = <&spm 1849 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1888 }; 1850 };
1889 1851
1890 gamma: gamma@1400d000 { 1852 gamma: gamma@1400d000 {
1891 compatible = "mediate 1853 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1892 reg = <0 0x1400d000 0 1854 reg = <0 0x1400d000 0 0x1000>;
1893 clocks = <&mmsys CLK_ 1855 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1894 interrupts = <GIC_SPI 1856 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
1895 mediatek,gce-client-r 1857 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1896 power-domains = <&spm 1858 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1897 }; 1859 };
1898 1860
1899 postmask: postmask@1400e000 { 1861 postmask: postmask@1400e000 {
1900 compatible = "mediate 1862 compatible = "mediatek,mt8186-disp-postmask",
1901 "mediate 1863 "mediatek,mt8192-disp-postmask";
1902 reg = <0 0x1400e000 0 1864 reg = <0 0x1400e000 0 0x1000>;
1903 clocks = <&mmsys CLK_ 1865 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1904 interrupts = <GIC_SPI 1866 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
1905 mediatek,gce-client-r 1867 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1906 power-domains = <&spm 1868 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1907 }; 1869 };
1908 1870
1909 dither: dither@1400f000 { 1871 dither: dither@1400f000 {
1910 compatible = "mediate 1872 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1911 reg = <0 0x1400f000 0 1873 reg = <0 0x1400f000 0 0x1000>;
1912 clocks = <&mmsys CLK_ 1874 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1913 interrupts = <GIC_SPI 1875 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
1914 mediatek,gce-client-r 1876 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1915 power-domains = <&spm 1877 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1916 }; 1878 };
1917 1879
1918 dsi0: dsi@14013000 { 1880 dsi0: dsi@14013000 {
1919 compatible = "mediate 1881 compatible = "mediatek,mt8186-dsi";
1920 reg = <0 0x14013000 0 1882 reg = <0 0x14013000 0 0x1000>;
1921 clocks = <&mmsys CLK_ 1883 clocks = <&mmsys CLK_MM_DSI0>,
1922 <&mmsys CLK_ 1884 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1923 <&mipi_tx0>; 1885 <&mipi_tx0>;
1924 clock-names = "engine 1886 clock-names = "engine", "digital", "hs";
1925 interrupts = <GIC_SPI 1887 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1926 power-domains = <&spm 1888 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1927 resets = <&mmsys MT81 1889 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1928 phys = <&mipi_tx0>; 1890 phys = <&mipi_tx0>;
1929 phy-names = "dphy"; 1891 phy-names = "dphy";
1930 status = "disabled"; 1892 status = "disabled";
1931 1893
1932 port { 1894 port {
1933 dsi_out: endp 1895 dsi_out: endpoint { };
1934 }; 1896 };
1935 }; 1897 };
1936 1898
1937 iommu_mm: iommu@14016000 { 1899 iommu_mm: iommu@14016000 {
1938 compatible = "mediate 1900 compatible = "mediatek,mt8186-iommu-mm";
1939 reg = <0 0x14016000 0 1901 reg = <0 0x14016000 0 0x1000>;
1940 clocks = <&mmsys CLK_ 1902 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1941 clock-names = "bclk"; 1903 clock-names = "bclk";
1942 interrupts = <GIC_SPI 1904 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1943 mediatek,larbs = <&la 1905 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1944 &la 1906 &larb7 &larb8 &larb9 &larb11
1945 &la 1907 &larb13 &larb14 &larb16 &larb17
1946 &la 1908 &larb19 &larb20>;
1947 power-domains = <&spm 1909 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1948 #iommu-cells = <1>; 1910 #iommu-cells = <1>;
1949 }; 1911 };
1950 1912
1951 rdma1: rdma@1401f000 { 1913 rdma1: rdma@1401f000 {
1952 compatible = "mediate 1914 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1953 reg = <0 0x1401f000 0 1915 reg = <0 0x1401f000 0 0x1000>;
1954 clocks = <&mmsys CLK_ 1916 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1955 interrupts = <GIC_SPI 1917 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
1956 iommus = <&iommu_mm I 1918 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
1957 mediatek,gce-client-r 1919 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1958 power-domains = <&spm 1920 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1959 }; 1921 };
1960 1922
1961 wpesys: clock-controller@1402 1923 wpesys: clock-controller@14020000 {
1962 compatible = "mediate 1924 compatible = "mediatek,mt8186-wpesys";
1963 reg = <0 0x14020000 0 1925 reg = <0 0x14020000 0 0x1000>;
1964 #clock-cells = <1>; 1926 #clock-cells = <1>;
1965 }; 1927 };
1966 1928
1967 larb8: smi@14023000 { 1929 larb8: smi@14023000 {
1968 compatible = "mediate 1930 compatible = "mediatek,mt8186-smi-larb";
1969 reg = <0 0x14023000 0 1931 reg = <0 0x14023000 0 0x1000>;
1970 clocks = <&wpesys CLK 1932 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1971 <&wpesys CLK 1933 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1972 clock-names = "apb", 1934 clock-names = "apb", "smi";
1973 mediatek,larb-id = <8 1935 mediatek,larb-id = <8>;
1974 mediatek,smi = <&smi_ 1936 mediatek,smi = <&smi_common>;
1975 power-domains = <&spm 1937 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1976 }; 1938 };
1977 1939
1978 imgsys1: clock-controller@150 1940 imgsys1: clock-controller@15020000 {
1979 compatible = "mediate 1941 compatible = "mediatek,mt8186-imgsys1";
1980 reg = <0 0x15020000 0 1942 reg = <0 0x15020000 0 0x1000>;
1981 #clock-cells = <1>; 1943 #clock-cells = <1>;
1982 }; 1944 };
1983 1945
1984 larb9: smi@1502e000 { 1946 larb9: smi@1502e000 {
1985 compatible = "mediate 1947 compatible = "mediatek,mt8186-smi-larb";
1986 reg = <0 0x1502e000 0 1948 reg = <0 0x1502e000 0 0x1000>;
1987 clocks = <&imgsys1 CL 1949 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1988 <&imgsys1 CL 1950 <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1989 clock-names = "apb", 1951 clock-names = "apb", "smi";
1990 mediatek,larb-id = <9 1952 mediatek,larb-id = <9>;
1991 mediatek,smi = <&smi_ 1953 mediatek,smi = <&smi_common>;
1992 power-domains = <&spm 1954 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1993 }; 1955 };
1994 1956
1995 imgsys2: clock-controller@158 1957 imgsys2: clock-controller@15820000 {
1996 compatible = "mediate 1958 compatible = "mediatek,mt8186-imgsys2";
1997 reg = <0 0x15820000 0 1959 reg = <0 0x15820000 0 0x1000>;
1998 #clock-cells = <1>; 1960 #clock-cells = <1>;
1999 }; 1961 };
2000 1962
2001 larb11: smi@1582e000 { 1963 larb11: smi@1582e000 {
2002 compatible = "mediate 1964 compatible = "mediatek,mt8186-smi-larb";
2003 reg = <0 0x1582e000 0 1965 reg = <0 0x1582e000 0 0x1000>;
2004 clocks = <&imgsys1 CL 1966 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
2005 <&imgsys2 CL 1967 <&imgsys2 CLK_IMG2_LARB9_IMG2>;
2006 clock-names = "apb", 1968 clock-names = "apb", "smi";
2007 mediatek,larb-id = <1 1969 mediatek,larb-id = <11>;
2008 mediatek,smi = <&smi_ 1970 mediatek,smi = <&smi_common>;
2009 power-domains = <&spm 1971 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
2010 }; 1972 };
2011 1973
2012 video_decoder: video-decoder@ 1974 video_decoder: video-decoder@16000000 {
2013 compatible = "mediate 1975 compatible = "mediatek,mt8186-vcodec-dec";
2014 reg = <0 0x16000000 0 1976 reg = <0 0x16000000 0 0x1000>;
2015 ranges; 1977 ranges;
2016 #address-cells = <2>; 1978 #address-cells = <2>;
2017 #size-cells = <2>; 1979 #size-cells = <2>;
2018 dma-ranges = <0x1 0x0 1980 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2019 iommus = <&iommu_mm I 1981 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>;
2020 mediatek,scp = <&scp> 1982 mediatek,scp = <&scp>;
2021 1983
2022 vcodec_core: video-co 1984 vcodec_core: video-codec@16025000 {
2023 compatible = 1985 compatible = "mediatek,mtk-vcodec-core";
2024 reg = <0 0x16 1986 reg = <0 0x16025000 0 0x1000>;
2025 interrupts = 1987 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
2026 iommus = <&io 1988 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>,
2027 <&io 1989 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>,
2028 <&io 1990 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>,
2029 <&io 1991 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>,
2030 <&io 1992 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>,
2031 <&io 1993 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>,
2032 <&io 1994 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>,
2033 <&io 1995 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>,
2034 <&io 1996 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>,
2035 <&io 1997 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>,
2036 <&io 1998 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
2037 <&io 1999 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>;
2038 clocks = <&to 2000 clocks = <&topckgen CLK_TOP_VDEC>,
2039 <&vd 2001 <&vdecsys CLK_VDEC_CKEN>,
2040 <&vd 2002 <&vdecsys CLK_VDEC_LARB1_CKEN>,
2041 <&to 2003 <&topckgen CLK_TOP_UNIVPLL_D3>;
2042 clock-names = 2004 clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
2043 assigned-cloc 2005 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2044 assigned-cloc 2006 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2045 power-domains 2007 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2046 }; 2008 };
2047 }; 2009 };
2048 2010
2049 larb4: smi@1602e000 { 2011 larb4: smi@1602e000 {
2050 compatible = "mediate 2012 compatible = "mediatek,mt8186-smi-larb";
2051 reg = <0 0x1602e000 0 2013 reg = <0 0x1602e000 0 0x1000>;
2052 clocks = <&vdecsys CL 2014 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
2053 <&vdecsys CL 2015 <&vdecsys CLK_VDEC_LARB1_CKEN>;
2054 clock-names = "apb", 2016 clock-names = "apb", "smi";
2055 mediatek,larb-id = <4 2017 mediatek,larb-id = <4>;
2056 mediatek,smi = <&smi_ 2018 mediatek,smi = <&smi_common>;
2057 power-domains = <&spm 2019 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2058 }; 2020 };
2059 2021
2060 vdecsys: clock-controller@160 2022 vdecsys: clock-controller@1602f000 {
2061 compatible = "mediate 2023 compatible = "mediatek,mt8186-vdecsys";
2062 reg = <0 0x1602f000 0 2024 reg = <0 0x1602f000 0 0x1000>;
2063 #clock-cells = <1>; 2025 #clock-cells = <1>;
2064 }; 2026 };
2065 2027
2066 vencsys: clock-controller@170 2028 vencsys: clock-controller@17000000 {
2067 compatible = "mediate 2029 compatible = "mediatek,mt8186-vencsys";
2068 reg = <0 0x17000000 0 2030 reg = <0 0x17000000 0 0x1000>;
2069 #clock-cells = <1>; 2031 #clock-cells = <1>;
2070 }; 2032 };
2071 2033
2072 larb7: smi@17010000 { 2034 larb7: smi@17010000 {
2073 compatible = "mediate 2035 compatible = "mediatek,mt8186-smi-larb";
2074 reg = <0 0x17010000 0 2036 reg = <0 0x17010000 0 0x1000>;
2075 clocks = <&vencsys CL 2037 clocks = <&vencsys CLK_VENC_CKE1_VENC>,
2076 <&vencsys CL 2038 <&vencsys CLK_VENC_CKE1_VENC>;
2077 clock-names = "apb", 2039 clock-names = "apb", "smi";
2078 mediatek,larb-id = <7 2040 mediatek,larb-id = <7>;
2079 mediatek,smi = <&smi_ 2041 mediatek,smi = <&smi_common>;
2080 power-domains = <&spm 2042 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2081 }; 2043 };
2082 2044
2083 venc: video-encoder@17020000 2045 venc: video-encoder@17020000 {
2084 compatible = "mediate 2046 compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
2085 reg = <0 0x17020000 0 2047 reg = <0 0x17020000 0 0x2000>;
2086 interrupts = <GIC_SPI 2048 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
2087 iommus = <&iommu_mm I 2049 iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
2088 <&iommu_mm I 2050 <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
2089 <&iommu_mm I 2051 <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
2090 <&iommu_mm I 2052 <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
2091 <&iommu_mm I 2053 <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
2092 <&iommu_mm I 2054 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
2093 <&iommu_mm I 2055 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
2094 <&iommu_mm I 2056 <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
2095 <&iommu_mm I 2057 <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
2096 clocks = <&vencsys CL 2058 clocks = <&vencsys CLK_VENC_CKE1_VENC>;
2097 clock-names = "venc_s 2059 clock-names = "venc_sel";
2098 assigned-clocks = <&t 2060 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2099 assigned-clock-parent 2061 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2100 power-domains = <&spm 2062 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2101 mediatek,scp = <&scp> 2063 mediatek,scp = <&scp>;
2102 }; 2064 };
2103 2065
2104 jpgenc: jpeg-encoder@17030000 2066 jpgenc: jpeg-encoder@17030000 {
2105 compatible = "mediate 2067 compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";
2106 reg = <0 0x17030000 0 2068 reg = <0 0x17030000 0 0x10000>;
2107 interrupts = <GIC_SPI 2069 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>;
2108 clocks = <&vencsys CL 2070 clocks = <&vencsys CLK_VENC_CKE2_JPGENC>;
2109 clock-names = "jpgenc 2071 clock-names = "jpgenc";
2110 iommus = <&iommu_mm I 2072 iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>,
2111 <&iommu_mm I 2073 <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>,
2112 <&iommu_mm I 2074 <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>,
2113 <&iommu_mm I 2075 <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>;
2114 power-domains = <&spm 2076 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2115 }; 2077 };
2116 2078
2117 camsys: clock-controller@1a00 2079 camsys: clock-controller@1a000000 {
2118 compatible = "mediate 2080 compatible = "mediatek,mt8186-camsys";
2119 reg = <0 0x1a000000 0 2081 reg = <0 0x1a000000 0 0x1000>;
2120 #clock-cells = <1>; 2082 #clock-cells = <1>;
2121 }; 2083 };
2122 2084
2123 larb13: smi@1a001000 { 2085 larb13: smi@1a001000 {
2124 compatible = "mediate 2086 compatible = "mediatek,mt8186-smi-larb";
2125 reg = <0 0x1a001000 0 2087 reg = <0 0x1a001000 0 0x1000>;
2126 clocks = <&camsys CLK 2088 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
2127 clock-names = "apb", 2089 clock-names = "apb", "smi";
2128 mediatek,larb-id = <1 2090 mediatek,larb-id = <13>;
2129 mediatek,smi = <&smi_ 2091 mediatek,smi = <&smi_common>;
2130 power-domains = <&spm 2092 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2131 }; 2093 };
2132 2094
2133 larb14: smi@1a002000 { 2095 larb14: smi@1a002000 {
2134 compatible = "mediate 2096 compatible = "mediatek,mt8186-smi-larb";
2135 reg = <0 0x1a002000 0 2097 reg = <0 0x1a002000 0 0x1000>;
2136 clocks = <&camsys CLK 2098 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
2137 clock-names = "apb", 2099 clock-names = "apb", "smi";
2138 mediatek,larb-id = <1 2100 mediatek,larb-id = <14>;
2139 mediatek,smi = <&smi_ 2101 mediatek,smi = <&smi_common>;
2140 power-domains = <&spm 2102 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2141 }; 2103 };
2142 2104
2143 larb16: smi@1a00f000 { 2105 larb16: smi@1a00f000 {
2144 compatible = "mediate 2106 compatible = "mediatek,mt8186-smi-larb";
2145 reg = <0 0x1a00f000 0 2107 reg = <0 0x1a00f000 0 0x1000>;
2146 clocks = <&camsys CLK 2108 clocks = <&camsys CLK_CAM_LARB14>,
2147 <&camsys_raw 2109 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
2148 clock-names = "apb", 2110 clock-names = "apb", "smi";
2149 mediatek,larb-id = <1 2111 mediatek,larb-id = <16>;
2150 mediatek,smi = <&smi_ 2112 mediatek,smi = <&smi_common>;
2151 power-domains = <&spm 2113 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2152 }; 2114 };
2153 2115
2154 larb17: smi@1a010000 { 2116 larb17: smi@1a010000 {
2155 compatible = "mediate 2117 compatible = "mediatek,mt8186-smi-larb";
2156 reg = <0 0x1a010000 0 2118 reg = <0 0x1a010000 0 0x1000>;
2157 clocks = <&camsys CLK 2119 clocks = <&camsys CLK_CAM_LARB13>,
2158 <&camsys_raw 2120 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
2159 clock-names = "apb", 2121 clock-names = "apb", "smi";
2160 mediatek,larb-id = <1 2122 mediatek,larb-id = <17>;
2161 mediatek,smi = <&smi_ 2123 mediatek,smi = <&smi_common>;
2162 power-domains = <&spm 2124 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2163 }; 2125 };
2164 2126
2165 camsys_rawa: clock-controller 2127 camsys_rawa: clock-controller@1a04f000 {
2166 compatible = "mediate 2128 compatible = "mediatek,mt8186-camsys_rawa";
2167 reg = <0 0x1a04f000 0 2129 reg = <0 0x1a04f000 0 0x1000>;
2168 #clock-cells = <1>; 2130 #clock-cells = <1>;
2169 }; 2131 };
2170 2132
2171 camsys_rawb: clock-controller 2133 camsys_rawb: clock-controller@1a06f000 {
2172 compatible = "mediate 2134 compatible = "mediatek,mt8186-camsys_rawb";
2173 reg = <0 0x1a06f000 0 2135 reg = <0 0x1a06f000 0 0x1000>;
2174 #clock-cells = <1>; 2136 #clock-cells = <1>;
2175 }; 2137 };
2176 2138
2177 mdpsys: clock-controller@1b00 2139 mdpsys: clock-controller@1b000000 {
2178 compatible = "mediate 2140 compatible = "mediatek,mt8186-mdpsys";
2179 reg = <0 0x1b000000 0 2141 reg = <0 0x1b000000 0 0x1000>;
2180 #clock-cells = <1>; 2142 #clock-cells = <1>;
2181 }; 2143 };
2182 2144
2183 larb2: smi@1b002000 { 2145 larb2: smi@1b002000 {
2184 compatible = "mediate 2146 compatible = "mediatek,mt8186-smi-larb";
2185 reg = <0 0x1b002000 0 2147 reg = <0 0x1b002000 0 0x1000>;
2186 clocks = <&mdpsys CLK 2148 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
2187 clock-names = "apb", 2149 clock-names = "apb", "smi";
2188 mediatek,larb-id = <2 2150 mediatek,larb-id = <2>;
2189 mediatek,smi = <&smi_ 2151 mediatek,smi = <&smi_common>;
2190 power-domains = <&spm 2152 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2191 }; 2153 };
2192 2154
2193 ipesys: clock-controller@1c00 2155 ipesys: clock-controller@1c000000 {
2194 compatible = "mediate 2156 compatible = "mediatek,mt8186-ipesys";
2195 reg = <0 0x1c000000 0 2157 reg = <0 0x1c000000 0 0x1000>;
2196 #clock-cells = <1>; 2158 #clock-cells = <1>;
2197 }; 2159 };
2198 2160
2199 larb20: smi@1c00f000 { 2161 larb20: smi@1c00f000 {
2200 compatible = "mediate 2162 compatible = "mediatek,mt8186-smi-larb";
2201 reg = <0 0x1c00f000 0 2163 reg = <0 0x1c00f000 0 0x1000>;
2202 clocks = <&ipesys CLK 2164 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
2203 clock-names = "apb", 2165 clock-names = "apb", "smi";
2204 mediatek,larb-id = <2 2166 mediatek,larb-id = <20>;
2205 mediatek,smi = <&smi_ 2167 mediatek,smi = <&smi_common>;
2206 power-domains = <&spm 2168 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2207 }; 2169 };
2208 2170
2209 larb19: smi@1c10f000 { 2171 larb19: smi@1c10f000 {
2210 compatible = "mediate 2172 compatible = "mediatek,mt8186-smi-larb";
2211 reg = <0 0x1c10f000 0 2173 reg = <0 0x1c10f000 0 0x1000>;
2212 clocks = <&ipesys CLK 2174 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
2213 clock-names = "apb", 2175 clock-names = "apb", "smi";
2214 mediatek,larb-id = <1 2176 mediatek,larb-id = <19>;
2215 mediatek,smi = <&smi_ 2177 mediatek,smi = <&smi_common>;
2216 power-domains = <&spm 2178 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2217 }; <<
2218 }; <<
2219 <<
2220 thermal_zones: thermal-zones { <<
2221 cpu-little0-thermal { <<
2222 polling-delay = <1000 <<
2223 polling-delay-passive <<
2224 thermal-sensors = <&l <<
2225 <<
2226 trips { <<
2227 cpu_little0_a <<
2228 tempe <<
2229 hyste <<
2230 type <<
2231 }; <<
2232 <<
2233 cpu_little0_a <<
2234 tempe <<
2235 hyste <<
2236 type <<
2237 }; <<
2238 <<
2239 cpu_little0_c <<
2240 tempe <<
2241 hyste <<
2242 type <<
2243 }; <<
2244 }; <<
2245 <<
2246 cooling-maps { <<
2247 map0 { <<
2248 trip <<
2249 cooli <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 }; <<
2257 }; <<
2258 <<
2259 cpu-little1-thermal { <<
2260 polling-delay = <1000 <<
2261 polling-delay-passive <<
2262 thermal-sensors = <&l <<
2263 <<
2264 trips { <<
2265 cpu_little1_a <<
2266 tempe <<
2267 hyste <<
2268 type <<
2269 }; <<
2270 <<
2271 cpu_little1_a <<
2272 tempe <<
2273 hyste <<
2274 type <<
2275 }; <<
2276 <<
2277 cpu_little1_c <<
2278 tempe <<
2279 hyste <<
2280 type <<
2281 }; <<
2282 }; <<
2283 <<
2284 cooling-maps { <<
2285 map0 { <<
2286 trip <<
2287 cooli <<
2288 <<
2289 <<
2290 <<
2291 <<
2292 <<
2293 }; <<
2294 }; <<
2295 }; <<
2296 <<
2297 cpu-little2-thermal { <<
2298 polling-delay = <1000 <<
2299 polling-delay-passive <<
2300 thermal-sensors = <&l <<
2301 <<
2302 trips { <<
2303 cpu_little2_a <<
2304 tempe <<
2305 hyste <<
2306 type <<
2307 }; <<
2308 <<
2309 cpu_little2_a <<
2310 tempe <<
2311 hyste <<
2312 type <<
2313 }; <<
2314 <<
2315 cpu_little2_c <<
2316 tempe <<
2317 hyste <<
2318 type <<
2319 }; <<
2320 }; <<
2321 <<
2322 cooling-maps { <<
2323 map0 { <<
2324 trip <<
2325 cooli <<
2326 <<
2327 <<
2328 <<
2329 <<
2330 <<
2331 }; <<
2332 }; <<
2333 }; <<
2334 <<
2335 cam-thermal { <<
2336 polling-delay = <1000 <<
2337 polling-delay-passive <<
2338 thermal-sensors = <&l <<
2339 <<
2340 trips { <<
2341 cam_alert0: t <<
2342 tempe <<
2343 hyste <<
2344 type <<
2345 }; <<
2346 <<
2347 cam_alert1: t <<
2348 tempe <<
2349 hyste <<
2350 type <<
2351 }; <<
2352 <<
2353 cam_crit: tri <<
2354 tempe <<
2355 hyste <<
2356 type <<
2357 }; <<
2358 }; <<
2359 }; <<
2360 <<
2361 nna-thermal { <<
2362 polling-delay = <1000 <<
2363 polling-delay-passive <<
2364 thermal-sensors = <&l <<
2365 <<
2366 trips { <<
2367 nna_alert0: t <<
2368 tempe <<
2369 hyste <<
2370 type <<
2371 }; <<
2372 <<
2373 nna_alert1: t <<
2374 tempe <<
2375 hyste <<
2376 type <<
2377 }; <<
2378 <<
2379 nna_crit: tri <<
2380 tempe <<
2381 hyste <<
2382 type <<
2383 }; <<
2384 }; <<
2385 }; <<
2386 <<
2387 adsp-thermal { <<
2388 polling-delay = <1000 <<
2389 polling-delay-passive <<
2390 thermal-sensors = <&l <<
2391 <<
2392 trips { <<
2393 adsp_alert0: <<
2394 tempe <<
2395 hyste <<
2396 type <<
2397 }; <<
2398 <<
2399 adsp_alert1: <<
2400 tempe <<
2401 hyste <<
2402 type <<
2403 }; <<
2404 <<
2405 adsp_crit: tr <<
2406 tempe <<
2407 hyste <<
2408 type <<
2409 }; <<
2410 }; <<
2411 }; <<
2412 <<
2413 gpu-thermal { <<
2414 polling-delay = <1000 <<
2415 polling-delay-passive <<
2416 thermal-sensors = <&l <<
2417 <<
2418 trips { <<
2419 gpu_alert0: t <<
2420 tempe <<
2421 hyste <<
2422 type <<
2423 }; <<
2424 <<
2425 gpu_alert1: t <<
2426 tempe <<
2427 hyste <<
2428 type <<
2429 }; <<
2430 <<
2431 gpu_crit: tri <<
2432 tempe <<
2433 hyste <<
2434 type <<
2435 }; <<
2436 }; <<
2437 <<
2438 cooling-maps { <<
2439 map0 { <<
2440 trip <<
2441 cooli <<
2442 }; <<
2443 }; <<
2444 }; <<
2445 <<
2446 cpu-big0-thermal { <<
2447 polling-delay = <1000 <<
2448 polling-delay-passive <<
2449 thermal-sensors = <&l <<
2450 <<
2451 trips { <<
2452 cpu_big0_aler <<
2453 tempe <<
2454 hyste <<
2455 type <<
2456 }; <<
2457 <<
2458 cpu_big0_aler <<
2459 tempe <<
2460 hyste <<
2461 type <<
2462 }; <<
2463 <<
2464 cpu_big0_crit <<
2465 tempe <<
2466 hyste <<
2467 type <<
2468 }; <<
2469 }; <<
2470 <<
2471 cooling-maps { <<
2472 map0 { <<
2473 trip <<
2474 cooli <<
2475 <<
2476 }; <<
2477 }; <<
2478 }; <<
2479 <<
2480 cpu-big1-thermal { <<
2481 polling-delay = <1000 <<
2482 polling-delay-passive <<
2483 thermal-sensors = <&l <<
2484 <<
2485 trips { <<
2486 cpu_big1_aler <<
2487 tempe <<
2488 hyste <<
2489 type <<
2490 }; <<
2491 <<
2492 cpu_big1_aler <<
2493 tempe <<
2494 hyste <<
2495 type <<
2496 }; <<
2497 <<
2498 cpu_big1_crit <<
2499 tempe <<
2500 hyste <<
2501 type <<
2502 }; <<
2503 }; <<
2504 <<
2505 cooling-maps { <<
2506 map0 { <<
2507 trip <<
2508 cooli <<
2509 <<
2510 }; <<
2511 }; <<
2512 }; 2179 };
2513 }; 2180 };
2514 }; 2181 };
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