1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Copyright (C) 2022 MediaTek Inc. 3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@media 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
5 */ 5 */
6 /dts-v1/; 6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h> 7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-por 10 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h 11 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h> 12 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h> 14 #include <dt-bindings/reset/mt8186-resets.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/thermal/mediatek,lvts-th <<
18 15
19 / { 16 / {
20 compatible = "mediatek,mt8186"; 17 compatible = "mediatek,mt8186";
21 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
22 #address-cells = <2>; 19 #address-cells = <2>;
23 #size-cells = <2>; 20 #size-cells = <2>;
24 21
25 aliases { <<
26 ovl0 = &ovl0; <<
27 ovl-2l0 = &ovl_2l0; <<
28 rdma0 = &rdma0; <<
29 rdma1 = &rdma1; <<
30 }; <<
31 <<
32 cci: cci { <<
33 compatible = "mediatek,mt8186- <<
34 clocks = <&mcusys CLK_MCU_ARMP <<
35 <&apmixedsys CLK_APMI <<
36 clock-names = "cci", "intermed <<
37 operating-points-v2 = <&cci_op <<
38 }; <<
39 <<
40 cci_opp: opp-table-cci { <<
41 compatible = "operating-points <<
42 opp-shared; <<
43 <<
44 cci_opp_0: opp-500000000 { <<
45 opp-hz = /bits/ 64 <50 <<
46 opp-microvolt = <60000 <<
47 }; <<
48 <<
49 cci_opp_1: opp-560000000 { <<
50 opp-hz = /bits/ 64 <56 <<
51 opp-microvolt = <67500 <<
52 }; <<
53 <<
54 cci_opp_2: opp-612000000 { <<
55 opp-hz = /bits/ 64 <61 <<
56 opp-microvolt = <69375 <<
57 }; <<
58 <<
59 cci_opp_3: opp-682000000 { <<
60 opp-hz = /bits/ 64 <68 <<
61 opp-microvolt = <71875 <<
62 }; <<
63 <<
64 cci_opp_4: opp-752000000 { <<
65 opp-hz = /bits/ 64 <75 <<
66 opp-microvolt = <74375 <<
67 }; <<
68 <<
69 cci_opp_5: opp-822000000 { <<
70 opp-hz = /bits/ 64 <82 <<
71 opp-microvolt = <76875 <<
72 }; <<
73 <<
74 cci_opp_6: opp-875000000 { <<
75 opp-hz = /bits/ 64 <87 <<
76 opp-microvolt = <78125 <<
77 }; <<
78 <<
79 cci_opp_7: opp-927000000 { <<
80 opp-hz = /bits/ 64 <92 <<
81 opp-microvolt = <80000 <<
82 }; <<
83 <<
84 cci_opp_8: opp-980000000 { <<
85 opp-hz = /bits/ 64 <98 <<
86 opp-microvolt = <81875 <<
87 }; <<
88 <<
89 cci_opp_9: opp-1050000000 { <<
90 opp-hz = /bits/ 64 <10 <<
91 opp-microvolt = <84375 <<
92 }; <<
93 <<
94 cci_opp_10: opp-1120000000 { <<
95 opp-hz = /bits/ 64 <11 <<
96 opp-microvolt = <86250 <<
97 }; <<
98 <<
99 cci_opp_11: opp-1155000000 { <<
100 opp-hz = /bits/ 64 <11 <<
101 opp-microvolt = <88750 <<
102 }; <<
103 <<
104 cci_opp_12: opp-1190000000 { <<
105 opp-hz = /bits/ 64 <11 <<
106 opp-microvolt = <90625 <<
107 }; <<
108 <<
109 cci_opp_13: opp-1260000000 { <<
110 opp-hz = /bits/ 64 <12 <<
111 opp-microvolt = <95000 <<
112 }; <<
113 <<
114 cci_opp_14: opp-1330000000 { <<
115 opp-hz = /bits/ 64 <13 <<
116 opp-microvolt = <99375 <<
117 }; <<
118 <<
119 cci_opp_15: opp-1400000000 { <<
120 opp-hz = /bits/ 64 <14 <<
121 opp-microvolt = <10312 <<
122 }; <<
123 }; <<
124 <<
125 cluster0_opp: opp-table-cluster0 { <<
126 compatible = "operating-points <<
127 opp-shared; <<
128 <<
129 opp-500000000 { <<
130 opp-hz = /bits/ 64 <50 <<
131 opp-microvolt = <60000 <<
132 required-opps = <&cci_ <<
133 }; <<
134 <<
135 opp-774000000 { <<
136 opp-hz = /bits/ 64 <77 <<
137 opp-microvolt = <67500 <<
138 required-opps = <&cci_ <<
139 }; <<
140 <<
141 opp-875000000 { <<
142 opp-hz = /bits/ 64 <87 <<
143 opp-microvolt = <70000 <<
144 required-opps = <&cci_ <<
145 }; <<
146 <<
147 opp-975000000 { <<
148 opp-hz = /bits/ 64 <97 <<
149 opp-microvolt = <72500 <<
150 required-opps = <&cci_ <<
151 }; <<
152 <<
153 opp-1075000000 { <<
154 opp-hz = /bits/ 64 <10 <<
155 opp-microvolt = <75000 <<
156 required-opps = <&cci_ <<
157 }; <<
158 <<
159 opp-1175000000 { <<
160 opp-hz = /bits/ 64 <11 <<
161 opp-microvolt = <77500 <<
162 required-opps = <&cci_ <<
163 }; <<
164 <<
165 opp-1275000000 { <<
166 opp-hz = /bits/ 64 <12 <<
167 opp-microvolt = <80000 <<
168 required-opps = <&cci_ <<
169 }; <<
170 <<
171 opp-1375000000 { <<
172 opp-hz = /bits/ 64 <13 <<
173 opp-microvolt = <82500 <<
174 required-opps = <&cci_ <<
175 }; <<
176 <<
177 opp-1500000000 { <<
178 opp-hz = /bits/ 64 <15 <<
179 opp-microvolt = <85625 <<
180 required-opps = <&cci_ <<
181 }; <<
182 <<
183 opp-1618000000 { <<
184 opp-hz = /bits/ 64 <16 <<
185 opp-microvolt = <87500 <<
186 required-opps = <&cci_ <<
187 }; <<
188 <<
189 opp-1666000000 { <<
190 opp-hz = /bits/ 64 <16 <<
191 opp-microvolt = <90000 <<
192 required-opps = <&cci_ <<
193 }; <<
194 <<
195 opp-1733000000 { <<
196 opp-hz = /bits/ 64 <17 <<
197 opp-microvolt = <92500 <<
198 required-opps = <&cci_ <<
199 }; <<
200 <<
201 opp-1800000000 { <<
202 opp-hz = /bits/ 64 <18 <<
203 opp-microvolt = <95000 <<
204 required-opps = <&cci_ <<
205 }; <<
206 <<
207 opp-1866000000 { <<
208 opp-hz = /bits/ 64 <18 <<
209 opp-microvolt = <98125 <<
210 required-opps = <&cci_ <<
211 }; <<
212 <<
213 opp-1933000000 { <<
214 opp-hz = /bits/ 64 <19 <<
215 opp-microvolt = <10062 <<
216 required-opps = <&cci_ <<
217 }; <<
218 <<
219 opp-2000000000 { <<
220 opp-hz = /bits/ 64 <20 <<
221 opp-microvolt = <10312 <<
222 required-opps = <&cci_ <<
223 }; <<
224 }; <<
225 <<
226 cluster1_opp: opp-table-cluster1 { <<
227 compatible = "operating-points <<
228 opp-shared; <<
229 <<
230 opp-774000000 { <<
231 opp-hz = /bits/ 64 <77 <<
232 opp-microvolt = <67500 <<
233 required-opps = <&cci_ <<
234 }; <<
235 <<
236 opp-835000000 { <<
237 opp-hz = /bits/ 64 <83 <<
238 opp-microvolt = <69375 <<
239 required-opps = <&cci_ <<
240 }; <<
241 <<
242 opp-919000000 { <<
243 opp-hz = /bits/ 64 <91 <<
244 opp-microvolt = <71875 <<
245 required-opps = <&cci_ <<
246 }; <<
247 <<
248 opp-1002000000 { <<
249 opp-hz = /bits/ 64 <10 <<
250 opp-microvolt = <74375 <<
251 required-opps = <&cci_ <<
252 }; <<
253 <<
254 opp-1085000000 { <<
255 opp-hz = /bits/ 64 <10 <<
256 opp-microvolt = <77500 <<
257 required-opps = <&cci_ <<
258 }; <<
259 <<
260 opp-1169000000 { <<
261 opp-hz = /bits/ 64 <11 <<
262 opp-microvolt = <80000 <<
263 required-opps = <&cci_ <<
264 }; <<
265 <<
266 opp-1308000000 { <<
267 opp-hz = /bits/ 64 <13 <<
268 opp-microvolt = <84375 <<
269 required-opps = <&cci_ <<
270 }; <<
271 <<
272 opp-1419000000 { <<
273 opp-hz = /bits/ 64 <14 <<
274 opp-microvolt = <87500 <<
275 required-opps = <&cci_ <<
276 }; <<
277 <<
278 opp-1530000000 { <<
279 opp-hz = /bits/ 64 <15 <<
280 opp-microvolt = <91250 <<
281 required-opps = <&cci_ <<
282 }; <<
283 <<
284 opp-1670000000 { <<
285 opp-hz = /bits/ 64 <16 <<
286 opp-microvolt = <95625 <<
287 required-opps = <&cci_ <<
288 }; <<
289 <<
290 opp-1733000000 { <<
291 opp-hz = /bits/ 64 <17 <<
292 opp-microvolt = <98125 <<
293 required-opps = <&cci_ <<
294 }; <<
295 <<
296 opp-1796000000 { <<
297 opp-hz = /bits/ 64 <17 <<
298 opp-microvolt = <10125 <<
299 required-opps = <&cci_ <<
300 }; <<
301 <<
302 opp-1860000000 { <<
303 opp-hz = /bits/ 64 <18 <<
304 opp-microvolt = <10375 <<
305 required-opps = <&cci_ <<
306 }; <<
307 <<
308 opp-1923000000 { <<
309 opp-hz = /bits/ 64 <19 <<
310 opp-microvolt = <10625 <<
311 required-opps = <&cci_ <<
312 }; <<
313 <<
314 cluster1_opp_14: opp-198600000 <<
315 opp-hz = /bits/ 64 <19 <<
316 opp-microvolt = <10937 <<
317 required-opps = <&cci_ <<
318 }; <<
319 <<
320 cluster1_opp_15: opp-205000000 <<
321 opp-hz = /bits/ 64 <20 <<
322 opp-microvolt = <11187 <<
323 required-opps = <&cci_ <<
324 }; <<
325 }; <<
326 <<
327 cpus { 22 cpus {
328 #address-cells = <1>; 23 #address-cells = <1>;
329 #size-cells = <0>; 24 #size-cells = <0>;
330 25
331 cpu-map { 26 cpu-map {
332 cluster0 { 27 cluster0 {
333 core0 { 28 core0 {
334 cpu = 29 cpu = <&cpu0>;
335 }; 30 };
336 31
337 core1 { 32 core1 {
338 cpu = 33 cpu = <&cpu1>;
339 }; 34 };
340 35
341 core2 { 36 core2 {
342 cpu = 37 cpu = <&cpu2>;
343 }; 38 };
344 39
345 core3 { 40 core3 {
346 cpu = 41 cpu = <&cpu3>;
347 }; 42 };
348 43
349 core4 { 44 core4 {
350 cpu = 45 cpu = <&cpu4>;
351 }; 46 };
352 47
353 core5 { 48 core5 {
354 cpu = 49 cpu = <&cpu5>;
355 }; 50 };
356 51
357 core6 { 52 core6 {
358 cpu = 53 cpu = <&cpu6>;
359 }; 54 };
360 55
361 core7 { 56 core7 {
362 cpu = 57 cpu = <&cpu7>;
363 }; 58 };
364 }; 59 };
365 }; 60 };
366 61
367 cpu0: cpu@0 { 62 cpu0: cpu@0 {
368 device_type = "cpu"; 63 device_type = "cpu";
369 compatible = "arm,cort 64 compatible = "arm,cortex-a55";
370 reg = <0x000>; 65 reg = <0x000>;
371 enable-method = "psci" 66 enable-method = "psci";
372 clock-frequency = <200 67 clock-frequency = <2000000000>;
373 clocks = <&mcusys CLK_ <<
374 <&apmixedsys <<
375 clock-names = "cpu", " <<
376 operating-points-v2 = <<
377 dynamic-power-coeffici <<
378 capacity-dmips-mhz = < 68 capacity-dmips-mhz = <382>;
379 cpu-idle-states = <&cp 69 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
380 i-cache-size = <32768> 70 i-cache-size = <32768>;
381 i-cache-line-size = <6 71 i-cache-line-size = <64>;
382 i-cache-sets = <128>; 72 i-cache-sets = <128>;
383 d-cache-size = <32768> 73 d-cache-size = <32768>;
384 d-cache-line-size = <6 74 d-cache-line-size = <64>;
385 d-cache-sets = <128>; 75 d-cache-sets = <128>;
386 next-level-cache = <&l 76 next-level-cache = <&l2_0>;
387 #cooling-cells = <2>; 77 #cooling-cells = <2>;
388 mediatek,cci = <&cci>; <<
389 }; 78 };
390 79
391 cpu1: cpu@100 { 80 cpu1: cpu@100 {
392 device_type = "cpu"; 81 device_type = "cpu";
393 compatible = "arm,cort 82 compatible = "arm,cortex-a55";
394 reg = <0x100>; 83 reg = <0x100>;
395 enable-method = "psci" 84 enable-method = "psci";
396 clock-frequency = <200 85 clock-frequency = <2000000000>;
397 clocks = <&mcusys CLK_ <<
398 <&apmixedsys <<
399 clock-names = "cpu", " <<
400 operating-points-v2 = <<
401 dynamic-power-coeffici <<
402 capacity-dmips-mhz = < 86 capacity-dmips-mhz = <382>;
403 cpu-idle-states = <&cp 87 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
404 i-cache-size = <32768> 88 i-cache-size = <32768>;
405 i-cache-line-size = <6 89 i-cache-line-size = <64>;
406 i-cache-sets = <128>; 90 i-cache-sets = <128>;
407 d-cache-size = <32768> 91 d-cache-size = <32768>;
408 d-cache-line-size = <6 92 d-cache-line-size = <64>;
409 d-cache-sets = <128>; 93 d-cache-sets = <128>;
410 next-level-cache = <&l 94 next-level-cache = <&l2_0>;
411 #cooling-cells = <2>; 95 #cooling-cells = <2>;
412 mediatek,cci = <&cci>; <<
413 }; 96 };
414 97
415 cpu2: cpu@200 { 98 cpu2: cpu@200 {
416 device_type = "cpu"; 99 device_type = "cpu";
417 compatible = "arm,cort 100 compatible = "arm,cortex-a55";
418 reg = <0x200>; 101 reg = <0x200>;
419 enable-method = "psci" 102 enable-method = "psci";
420 clock-frequency = <200 103 clock-frequency = <2000000000>;
421 clocks = <&mcusys CLK_ <<
422 <&apmixedsys <<
423 clock-names = "cpu", " <<
424 operating-points-v2 = <<
425 dynamic-power-coeffici <<
426 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <382>;
427 cpu-idle-states = <&cp 105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
428 i-cache-size = <32768> 106 i-cache-size = <32768>;
429 i-cache-line-size = <6 107 i-cache-line-size = <64>;
430 i-cache-sets = <128>; 108 i-cache-sets = <128>;
431 d-cache-size = <32768> 109 d-cache-size = <32768>;
432 d-cache-line-size = <6 110 d-cache-line-size = <64>;
433 d-cache-sets = <128>; 111 d-cache-sets = <128>;
434 next-level-cache = <&l 112 next-level-cache = <&l2_0>;
435 #cooling-cells = <2>; 113 #cooling-cells = <2>;
436 mediatek,cci = <&cci>; <<
437 }; 114 };
438 115
439 cpu3: cpu@300 { 116 cpu3: cpu@300 {
440 device_type = "cpu"; 117 device_type = "cpu";
441 compatible = "arm,cort 118 compatible = "arm,cortex-a55";
442 reg = <0x300>; 119 reg = <0x300>;
443 enable-method = "psci" 120 enable-method = "psci";
444 clock-frequency = <200 121 clock-frequency = <2000000000>;
445 clocks = <&mcusys CLK_ <<
446 <&apmixedsys <<
447 clock-names = "cpu", " <<
448 operating-points-v2 = <<
449 dynamic-power-coeffici <<
450 capacity-dmips-mhz = < 122 capacity-dmips-mhz = <382>;
451 cpu-idle-states = <&cp 123 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
452 i-cache-size = <32768> 124 i-cache-size = <32768>;
453 i-cache-line-size = <6 125 i-cache-line-size = <64>;
454 i-cache-sets = <128>; 126 i-cache-sets = <128>;
455 d-cache-size = <32768> 127 d-cache-size = <32768>;
456 d-cache-line-size = <6 128 d-cache-line-size = <64>;
457 d-cache-sets = <128>; 129 d-cache-sets = <128>;
458 next-level-cache = <&l 130 next-level-cache = <&l2_0>;
459 #cooling-cells = <2>; 131 #cooling-cells = <2>;
460 mediatek,cci = <&cci>; <<
461 }; 132 };
462 133
463 cpu4: cpu@400 { 134 cpu4: cpu@400 {
464 device_type = "cpu"; 135 device_type = "cpu";
465 compatible = "arm,cort 136 compatible = "arm,cortex-a55";
466 reg = <0x400>; 137 reg = <0x400>;
467 enable-method = "psci" 138 enable-method = "psci";
468 clock-frequency = <200 139 clock-frequency = <2000000000>;
469 clocks = <&mcusys CLK_ <<
470 <&apmixedsys <<
471 clock-names = "cpu", " <<
472 operating-points-v2 = <<
473 dynamic-power-coeffici <<
474 capacity-dmips-mhz = < 140 capacity-dmips-mhz = <382>;
475 cpu-idle-states = <&cp 141 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
476 i-cache-size = <32768> 142 i-cache-size = <32768>;
477 i-cache-line-size = <6 143 i-cache-line-size = <64>;
478 i-cache-sets = <128>; 144 i-cache-sets = <128>;
479 d-cache-size = <32768> 145 d-cache-size = <32768>;
480 d-cache-line-size = <6 146 d-cache-line-size = <64>;
481 d-cache-sets = <128>; 147 d-cache-sets = <128>;
482 next-level-cache = <&l 148 next-level-cache = <&l2_0>;
483 #cooling-cells = <2>; 149 #cooling-cells = <2>;
484 mediatek,cci = <&cci>; <<
485 }; 150 };
486 151
487 cpu5: cpu@500 { 152 cpu5: cpu@500 {
488 device_type = "cpu"; 153 device_type = "cpu";
489 compatible = "arm,cort 154 compatible = "arm,cortex-a55";
490 reg = <0x500>; 155 reg = <0x500>;
491 enable-method = "psci" 156 enable-method = "psci";
492 clock-frequency = <200 157 clock-frequency = <2000000000>;
493 clocks = <&mcusys CLK_ <<
494 <&apmixedsys <<
495 clock-names = "cpu", " <<
496 operating-points-v2 = <<
497 dynamic-power-coeffici <<
498 capacity-dmips-mhz = < 158 capacity-dmips-mhz = <382>;
499 cpu-idle-states = <&cp 159 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
500 i-cache-size = <32768> 160 i-cache-size = <32768>;
501 i-cache-line-size = <6 161 i-cache-line-size = <64>;
502 i-cache-sets = <128>; 162 i-cache-sets = <128>;
503 d-cache-size = <32768> 163 d-cache-size = <32768>;
504 d-cache-line-size = <6 164 d-cache-line-size = <64>;
505 d-cache-sets = <128>; 165 d-cache-sets = <128>;
506 next-level-cache = <&l 166 next-level-cache = <&l2_0>;
507 #cooling-cells = <2>; 167 #cooling-cells = <2>;
508 mediatek,cci = <&cci>; <<
509 }; 168 };
510 169
511 cpu6: cpu@600 { 170 cpu6: cpu@600 {
512 device_type = "cpu"; 171 device_type = "cpu";
513 compatible = "arm,cort 172 compatible = "arm,cortex-a76";
514 reg = <0x600>; 173 reg = <0x600>;
515 enable-method = "psci" 174 enable-method = "psci";
516 clock-frequency = <205 175 clock-frequency = <2050000000>;
517 clocks = <&mcusys CLK_ <<
518 <&apmixedsys <<
519 clock-names = "cpu", " <<
520 operating-points-v2 = <<
521 dynamic-power-coeffici <<
522 capacity-dmips-mhz = < 176 capacity-dmips-mhz = <1024>;
523 cpu-idle-states = <&cp 177 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
524 i-cache-size = <65536> 178 i-cache-size = <65536>;
525 i-cache-line-size = <6 179 i-cache-line-size = <64>;
526 i-cache-sets = <256>; 180 i-cache-sets = <256>;
527 d-cache-size = <65536> 181 d-cache-size = <65536>;
528 d-cache-line-size = <6 182 d-cache-line-size = <64>;
529 d-cache-sets = <256>; 183 d-cache-sets = <256>;
530 next-level-cache = <&l 184 next-level-cache = <&l2_1>;
531 #cooling-cells = <2>; 185 #cooling-cells = <2>;
532 mediatek,cci = <&cci>; <<
533 }; 186 };
534 187
535 cpu7: cpu@700 { 188 cpu7: cpu@700 {
536 device_type = "cpu"; 189 device_type = "cpu";
537 compatible = "arm,cort 190 compatible = "arm,cortex-a76";
538 reg = <0x700>; 191 reg = <0x700>;
539 enable-method = "psci" 192 enable-method = "psci";
540 clock-frequency = <205 193 clock-frequency = <2050000000>;
541 clocks = <&mcusys CLK_ <<
542 <&apmixedsys <<
543 clock-names = "cpu", " <<
544 operating-points-v2 = <<
545 dynamic-power-coeffici <<
546 capacity-dmips-mhz = < 194 capacity-dmips-mhz = <1024>;
547 cpu-idle-states = <&cp 195 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
548 i-cache-size = <65536> 196 i-cache-size = <65536>;
549 i-cache-line-size = <6 197 i-cache-line-size = <64>;
550 i-cache-sets = <256>; 198 i-cache-sets = <256>;
551 d-cache-size = <65536> 199 d-cache-size = <65536>;
552 d-cache-line-size = <6 200 d-cache-line-size = <64>;
553 d-cache-sets = <256>; 201 d-cache-sets = <256>;
554 next-level-cache = <&l 202 next-level-cache = <&l2_1>;
555 #cooling-cells = <2>; 203 #cooling-cells = <2>;
556 mediatek,cci = <&cci>; <<
557 }; 204 };
558 205
559 idle-states { 206 idle-states {
560 entry-method = "psci"; 207 entry-method = "psci";
561 208
562 cpu_ret_l: cpu-retenti 209 cpu_ret_l: cpu-retention-l {
563 compatible = " 210 compatible = "arm,idle-state";
564 arm,psci-suspe 211 arm,psci-suspend-param = <0x00010001>;
565 local-timer-st 212 local-timer-stop;
566 entry-latency- 213 entry-latency-us = <50>;
567 exit-latency-u 214 exit-latency-us = <100>;
568 min-residency- 215 min-residency-us = <1600>;
569 }; 216 };
570 217
571 cpu_ret_b: cpu-retenti 218 cpu_ret_b: cpu-retention-b {
572 compatible = " 219 compatible = "arm,idle-state";
573 arm,psci-suspe 220 arm,psci-suspend-param = <0x00010001>;
574 local-timer-st 221 local-timer-stop;
575 entry-latency- 222 entry-latency-us = <50>;
576 exit-latency-u 223 exit-latency-us = <100>;
577 min-residency- 224 min-residency-us = <1400>;
578 }; 225 };
579 226
580 cpu_off_l: cpu-off-l { 227 cpu_off_l: cpu-off-l {
581 compatible = " 228 compatible = "arm,idle-state";
582 arm,psci-suspe 229 arm,psci-suspend-param = <0x01010001>;
583 local-timer-st 230 local-timer-stop;
584 entry-latency- 231 entry-latency-us = <100>;
585 exit-latency-u 232 exit-latency-us = <250>;
586 min-residency- 233 min-residency-us = <2100>;
587 }; 234 };
588 235
589 cpu_off_b: cpu-off-b { 236 cpu_off_b: cpu-off-b {
590 compatible = " 237 compatible = "arm,idle-state";
591 arm,psci-suspe 238 arm,psci-suspend-param = <0x01010001>;
592 local-timer-st 239 local-timer-stop;
593 entry-latency- 240 entry-latency-us = <100>;
594 exit-latency-u 241 exit-latency-us = <250>;
595 min-residency- 242 min-residency-us = <1900>;
596 }; 243 };
597 }; 244 };
598 245
599 l2_0: l2-cache0 { 246 l2_0: l2-cache0 {
600 compatible = "cache"; 247 compatible = "cache";
601 cache-level = <2>; 248 cache-level = <2>;
602 cache-size = <131072>; 249 cache-size = <131072>;
603 cache-line-size = <64> 250 cache-line-size = <64>;
604 cache-sets = <512>; 251 cache-sets = <512>;
605 next-level-cache = <&l 252 next-level-cache = <&l3_0>;
606 cache-unified; <<
607 }; 253 };
608 254
609 l2_1: l2-cache1 { 255 l2_1: l2-cache1 {
610 compatible = "cache"; 256 compatible = "cache";
611 cache-level = <2>; 257 cache-level = <2>;
612 cache-size = <262144>; 258 cache-size = <262144>;
613 cache-line-size = <64> 259 cache-line-size = <64>;
614 cache-sets = <512>; 260 cache-sets = <512>;
615 next-level-cache = <&l 261 next-level-cache = <&l3_0>;
616 cache-unified; <<
617 }; 262 };
618 263
619 l3_0: l3-cache { 264 l3_0: l3-cache {
620 compatible = "cache"; 265 compatible = "cache";
621 cache-level = <3>; 266 cache-level = <3>;
622 cache-size = <1048576> 267 cache-size = <1048576>;
623 cache-line-size = <64> 268 cache-line-size = <64>;
624 cache-sets = <1024>; 269 cache-sets = <1024>;
625 cache-unified; 270 cache-unified;
626 }; 271 };
627 }; 272 };
628 273
629 clk13m: fixed-factor-clock-13m { 274 clk13m: fixed-factor-clock-13m {
630 compatible = "fixed-factor-clo 275 compatible = "fixed-factor-clock";
631 #clock-cells = <0>; 276 #clock-cells = <0>;
632 clocks = <&clk26m>; 277 clocks = <&clk26m>;
633 clock-div = <2>; 278 clock-div = <2>;
634 clock-mult = <1>; 279 clock-mult = <1>;
635 clock-output-names = "clk13m"; 280 clock-output-names = "clk13m";
636 }; 281 };
637 282
638 clk26m: oscillator-26m { 283 clk26m: oscillator-26m {
639 compatible = "fixed-clock"; 284 compatible = "fixed-clock";
640 #clock-cells = <0>; 285 #clock-cells = <0>;
641 clock-frequency = <26000000>; 286 clock-frequency = <26000000>;
642 clock-output-names = "clk26m"; 287 clock-output-names = "clk26m";
643 }; 288 };
644 289
645 clk32k: oscillator-32k { 290 clk32k: oscillator-32k {
646 compatible = "fixed-clock"; 291 compatible = "fixed-clock";
647 #clock-cells = <0>; 292 #clock-cells = <0>;
648 clock-frequency = <32768>; 293 clock-frequency = <32768>;
649 clock-output-names = "clk32k"; 294 clock-output-names = "clk32k";
650 }; 295 };
651 296
652 gpu_opp_table: opp-table-gpu { <<
653 compatible = "operating-points <<
654 <<
655 opp-299000000 { <<
656 opp-hz = /bits/ 64 <29 <<
657 opp-microvolt = <61250 <<
658 opp-supported-hw = <0x <<
659 }; <<
660 <<
661 opp-332000000 { <<
662 opp-hz = /bits/ 64 <33 <<
663 opp-microvolt = <62500 <<
664 opp-supported-hw = <0x <<
665 }; <<
666 <<
667 opp-366000000 { <<
668 opp-hz = /bits/ 64 <36 <<
669 opp-microvolt = <63750 <<
670 opp-supported-hw = <0x <<
671 }; <<
672 <<
673 opp-400000000 { <<
674 opp-hz = /bits/ 64 <40 <<
675 opp-microvolt = <64375 <<
676 opp-supported-hw = <0x <<
677 }; <<
678 <<
679 opp-434000000 { <<
680 opp-hz = /bits/ 64 <43 <<
681 opp-microvolt = <65625 <<
682 opp-supported-hw = <0x <<
683 }; <<
684 <<
685 opp-484000000 { <<
686 opp-hz = /bits/ 64 <48 <<
687 opp-microvolt = <66875 <<
688 opp-supported-hw = <0x <<
689 }; <<
690 <<
691 opp-535000000 { <<
692 opp-hz = /bits/ 64 <53 <<
693 opp-microvolt = <68750 <<
694 opp-supported-hw = <0x <<
695 }; <<
696 <<
697 opp-586000000 { <<
698 opp-hz = /bits/ 64 <58 <<
699 opp-microvolt = <70000 <<
700 opp-supported-hw = <0x <<
701 }; <<
702 <<
703 opp-637000000 { <<
704 opp-hz = /bits/ 64 <63 <<
705 opp-microvolt = <71250 <<
706 opp-supported-hw = <0x <<
707 }; <<
708 <<
709 opp-690000000 { <<
710 opp-hz = /bits/ 64 <69 <<
711 opp-microvolt = <73750 <<
712 opp-supported-hw = <0x <<
713 }; <<
714 <<
715 opp-743000000 { <<
716 opp-hz = /bits/ 64 <74 <<
717 opp-microvolt = <75625 <<
718 opp-supported-hw = <0x <<
719 }; <<
720 <<
721 opp-796000000 { <<
722 opp-hz = /bits/ 64 <79 <<
723 opp-microvolt = <78125 <<
724 opp-supported-hw = <0x <<
725 }; <<
726 <<
727 opp-850000000 { <<
728 opp-hz = /bits/ 64 <85 <<
729 opp-microvolt = <80000 <<
730 opp-supported-hw = <0x <<
731 }; <<
732 <<
733 opp-900000000-3 { <<
734 opp-hz = /bits/ 64 <90 <<
735 opp-microvolt = <85000 <<
736 opp-supported-hw = <0x <<
737 }; <<
738 <<
739 opp-900000000-4 { <<
740 opp-hz = /bits/ 64 <90 <<
741 opp-microvolt = <83750 <<
742 opp-supported-hw = <0x <<
743 }; <<
744 <<
745 opp-900000000-5 { <<
746 opp-hz = /bits/ 64 <90 <<
747 opp-microvolt = <82500 <<
748 opp-supported-hw = <0x <<
749 }; <<
750 <<
751 opp-950000000-3 { <<
752 opp-hz = /bits/ 64 <95 <<
753 opp-microvolt = <90000 <<
754 opp-supported-hw = <0x <<
755 }; <<
756 <<
757 opp-950000000-4 { <<
758 opp-hz = /bits/ 64 <95 <<
759 opp-microvolt = <87500 <<
760 opp-supported-hw = <0x <<
761 }; <<
762 <<
763 opp-950000000-5 { <<
764 opp-hz = /bits/ 64 <95 <<
765 opp-microvolt = <85000 <<
766 opp-supported-hw = <0x <<
767 }; <<
768 <<
769 opp-1000000000-3 { <<
770 opp-hz = /bits/ 64 <10 <<
771 opp-microvolt = <95000 <<
772 opp-supported-hw = <0x <<
773 }; <<
774 <<
775 opp-1000000000-4 { <<
776 opp-hz = /bits/ 64 <10 <<
777 opp-microvolt = <91250 <<
778 opp-supported-hw = <0x <<
779 }; <<
780 <<
781 opp-1000000000-5 { <<
782 opp-hz = /bits/ 64 <10 <<
783 opp-microvolt = <87500 <<
784 opp-supported-hw = <0x <<
785 }; <<
786 }; <<
787 <<
788 pmu-a55 { 297 pmu-a55 {
789 compatible = "arm,cortex-a55-p 298 compatible = "arm,cortex-a55-pmu";
790 interrupt-parent = <&gic>; 299 interrupt-parent = <&gic>;
791 interrupts = <GIC_PPI 7 IRQ_TY 300 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
792 }; 301 };
793 302
794 pmu-a76 { 303 pmu-a76 {
795 compatible = "arm,cortex-a76-p 304 compatible = "arm,cortex-a76-pmu";
796 interrupt-parent = <&gic>; 305 interrupt-parent = <&gic>;
797 interrupts = <GIC_PPI 7 IRQ_TY 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
798 }; 307 };
799 308
800 psci { 309 psci {
801 compatible = "arm,psci-1.0"; 310 compatible = "arm,psci-1.0";
802 method = "smc"; 311 method = "smc";
803 }; 312 };
804 313
805 timer { 314 timer {
806 compatible = "arm,armv8-timer" 315 compatible = "arm,armv8-timer";
807 interrupt-parent = <&gic>; 316 interrupt-parent = <&gic>;
808 interrupts = <GIC_PPI 13 IRQ_T 317 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
809 <GIC_PPI 14 IRQ_T 318 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
810 <GIC_PPI 11 IRQ_T 319 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
811 <GIC_PPI 10 IRQ_T 320 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
812 }; 321 };
813 322
814 soc { 323 soc {
815 #address-cells = <2>; 324 #address-cells = <2>;
816 #size-cells = <2>; 325 #size-cells = <2>;
817 compatible = "simple-bus"; 326 compatible = "simple-bus";
818 dma-ranges = <0x0 0x0 0x0 0x0 327 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
819 ranges; 328 ranges;
820 329
821 gic: interrupt-controller@c000 330 gic: interrupt-controller@c000000 {
822 compatible = "arm,gic- 331 compatible = "arm,gic-v3";
823 #interrupt-cells = <4> 332 #interrupt-cells = <4>;
824 #redistributor-regions 333 #redistributor-regions = <1>;
825 interrupt-parent = <&g 334 interrupt-parent = <&gic>;
826 interrupt-controller; 335 interrupt-controller;
827 reg = <0 0x0c000000 0 336 reg = <0 0x0c000000 0 0x40000>,
828 <0 0x0c040000 0 337 <0 0x0c040000 0 0x200000>;
829 interrupts = <GIC_PPI 338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
830 339
831 ppi-partitions { 340 ppi-partitions {
832 ppi_cluster0: 341 ppi_cluster0: interrupt-partition-0 {
833 affini 342 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
834 }; 343 };
835 344
836 ppi_cluster1: 345 ppi_cluster1: interrupt-partition-1 {
837 affini 346 affinity = <&cpu6 &cpu7>;
838 }; 347 };
839 }; 348 };
840 }; 349 };
841 350
842 mcusys: syscon@c53a000 { 351 mcusys: syscon@c53a000 {
843 compatible = "mediatek 352 compatible = "mediatek,mt8186-mcusys", "syscon";
844 reg = <0 0xc53a000 0 0 353 reg = <0 0xc53a000 0 0x1000>;
845 #clock-cells = <1>; 354 #clock-cells = <1>;
846 }; 355 };
847 356
848 topckgen: syscon@10000000 { 357 topckgen: syscon@10000000 {
849 compatible = "mediatek 358 compatible = "mediatek,mt8186-topckgen", "syscon";
850 reg = <0 0x10000000 0 359 reg = <0 0x10000000 0 0x1000>;
851 #clock-cells = <1>; 360 #clock-cells = <1>;
852 }; 361 };
853 362
854 infracfg_ao: syscon@10001000 { 363 infracfg_ao: syscon@10001000 {
855 compatible = "mediatek 364 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
856 reg = <0 0x10001000 0 365 reg = <0 0x10001000 0 0x1000>;
857 #clock-cells = <1>; 366 #clock-cells = <1>;
858 #reset-cells = <1>; 367 #reset-cells = <1>;
859 }; 368 };
860 369
861 pericfg: syscon@10003000 { 370 pericfg: syscon@10003000 {
862 compatible = "mediatek 371 compatible = "mediatek,mt8186-pericfg", "syscon";
863 reg = <0 0x10003000 0 372 reg = <0 0x10003000 0 0x1000>;
864 }; 373 };
865 374
866 pio: pinctrl@10005000 { 375 pio: pinctrl@10005000 {
867 compatible = "mediatek 376 compatible = "mediatek,mt8186-pinctrl";
868 reg = <0 0x10005000 0 377 reg = <0 0x10005000 0 0x1000>,
869 <0 0x10002000 0 378 <0 0x10002000 0 0x0200>,
870 <0 0x10002200 0 379 <0 0x10002200 0 0x0200>,
871 <0 0x10002400 0 380 <0 0x10002400 0 0x0200>,
872 <0 0x10002600 0 381 <0 0x10002600 0 0x0200>,
873 <0 0x10002a00 0 382 <0 0x10002a00 0 0x0200>,
874 <0 0x10002c00 0 383 <0 0x10002c00 0 0x0200>,
875 <0 0x1000b000 0 384 <0 0x1000b000 0 0x1000>;
876 reg-names = "iocfg0", 385 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
877 "iocfg_bl" 386 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
878 gpio-controller; 387 gpio-controller;
879 #gpio-cells = <2>; 388 #gpio-cells = <2>;
880 gpio-ranges = <&pio 0 389 gpio-ranges = <&pio 0 0 185>;
881 interrupt-controller; 390 interrupt-controller;
882 interrupts = <GIC_SPI 391 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
883 #interrupt-cells = <2> 392 #interrupt-cells = <2>;
884 }; 393 };
885 394
886 scpsys: syscon@10006000 { 395 scpsys: syscon@10006000 {
887 compatible = "mediatek 396 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
888 reg = <0 0x10006000 0 397 reg = <0 0x10006000 0 0x1000>;
889 398
890 /* System Power Manage 399 /* System Power Manager */
891 spm: power-controller 400 spm: power-controller {
892 compatible = " 401 compatible = "mediatek,mt8186-power-controller";
893 #address-cells 402 #address-cells = <1>;
894 #size-cells = 403 #size-cells = <0>;
895 #power-domain- 404 #power-domain-cells = <1>;
896 405
897 /* power domai 406 /* power domain of the SoC */
898 mfg0: power-do 407 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
899 reg = 408 reg = <MT8186_POWER_DOMAIN_MFG0>;
900 clocks 409 clocks = <&topckgen CLK_TOP_MFG>;
901 clock- 410 clock-names = "mfg00";
902 #addre 411 #address-cells = <1>;
903 #size- 412 #size-cells = <0>;
904 #power 413 #power-domain-cells = <1>;
905 414
906 mfg1: !! 415 power-domain@MT8186_POWER_DOMAIN_MFG1 {
907 416 reg = <MT8186_POWER_DOMAIN_MFG1>;
908 417 mediatek,infracfg = <&infracfg_ao>;
909 418 #address-cells = <1>;
910 419 #size-cells = <0>;
911 420 #power-domain-cells = <1>;
912 421
913 422 power-domain@MT8186_POWER_DOMAIN_MFG2 {
914 423 reg = <MT8186_POWER_DOMAIN_MFG2>;
915 424 #power-domain-cells = <0>;
916 425 };
917 426
918 427 power-domain@MT8186_POWER_DOMAIN_MFG3 {
919 428 reg = <MT8186_POWER_DOMAIN_MFG3>;
920 429 #power-domain-cells = <0>;
921 430 };
922 }; 431 };
923 }; 432 };
924 433
925 power-domain@M 434 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
926 reg = 435 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
927 clocks 436 clocks = <&topckgen CLK_TOP_SENINF>,
928 437 <&topckgen CLK_TOP_SENINF1>;
929 clock- !! 438 clock-names = "csirx_top0", "csirx_top1";
930 <<
931 #power 439 #power-domain-cells = <0>;
932 }; 440 };
933 441
934 power-domain@M 442 power-domain@MT8186_POWER_DOMAIN_SSUSB {
935 reg = 443 reg = <MT8186_POWER_DOMAIN_SSUSB>;
936 clocks <<
937 <<
938 clock- <<
939 #power 444 #power-domain-cells = <0>;
940 }; 445 };
941 446
942 power-domain@M 447 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
943 reg = 448 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
944 clocks <<
945 <<
946 clock- <<
947 #power 449 #power-domain-cells = <0>;
948 }; 450 };
949 451
950 power-domain@M 452 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
951 reg = 453 reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
952 clocks 454 clocks = <&topckgen CLK_TOP_AUDIODSP>,
953 455 <&topckgen CLK_TOP_ADSP_BUS>;
954 clock- !! 456 clock-names = "audioadsp", "adsp_bus";
955 <<
956 #addre 457 #address-cells = <1>;
957 #size- 458 #size-cells = <0>;
958 #power 459 #power-domain-cells = <1>;
959 460
960 power- 461 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
961 462 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
962 463 #address-cells = <1>;
963 464 #size-cells = <0>;
964 465 #power-domain-cells = <1>;
965 466
966 467 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
967 468 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
968 469 mediatek,infracfg = <&infracfg_ao>;
969 470 #power-domain-cells = <0>;
970 471 };
971 }; 472 };
972 }; 473 };
973 474
974 power-domain@M 475 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
975 reg = 476 reg = <MT8186_POWER_DOMAIN_CONN_ON>;
976 mediat 477 mediatek,infracfg = <&infracfg_ao>;
977 #power 478 #power-domain-cells = <0>;
978 }; 479 };
979 480
980 power-domain@M 481 power-domain@MT8186_POWER_DOMAIN_DIS {
981 reg = 482 reg = <MT8186_POWER_DOMAIN_DIS>;
982 clocks 483 clocks = <&topckgen CLK_TOP_DISP>,
983 484 <&topckgen CLK_TOP_MDP>,
984 485 <&mmsys CLK_MM_SMI_INFRA>,
985 486 <&mmsys CLK_MM_SMI_COMMON>,
986 487 <&mmsys CLK_MM_SMI_GALS>,
987 488 <&mmsys CLK_MM_SMI_IOMMU>;
988 clock- !! 489 clock-names = "disp", "mdp", "smi_infra", "smi_common",
989 !! 490 "smi_gals", "smi_iommu";
990 <<
991 <<
992 <<
993 mediat 491 mediatek,infracfg = <&infracfg_ao>;
994 #addre 492 #address-cells = <1>;
995 #size- 493 #size-cells = <0>;
996 #power 494 #power-domain-cells = <1>;
997 495
998 power- 496 power-domain@MT8186_POWER_DOMAIN_VDEC {
999 497 reg = <MT8186_POWER_DOMAIN_VDEC>;
1000 498 clocks = <&topckgen CLK_TOP_VDEC>,
1001 499 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1002 500 clock-names = "vdec0", "larb";
1003 501 mediatek,infracfg = <&infracfg_ao>;
1004 502 #power-domain-cells = <0>;
1005 }; 503 };
1006 504
1007 power 505 power-domain@MT8186_POWER_DOMAIN_CAM {
1008 506 reg = <MT8186_POWER_DOMAIN_CAM>;
1009 !! 507 clocks = <&topckgen CLK_TOP_CAM>,
>> 508 <&topckgen CLK_TOP_SENINF>,
1010 509 <&topckgen CLK_TOP_SENINF1>,
1011 510 <&topckgen CLK_TOP_SENINF2>,
1012 511 <&topckgen CLK_TOP_SENINF3>,
1013 <<
1014 512 <&topckgen CLK_TOP_CAMTM>,
1015 !! 513 <&camsys CLK_CAM2MM_GALS>;
1016 !! 514 clock-names = "cam-top", "cam0", "cam1", "cam2",
1017 !! 515 "cam3", "cam-tm", "gals";
1018 <<
1019 <<
1020 516 mediatek,infracfg = <&infracfg_ao>;
1021 517 #address-cells = <1>;
1022 518 #size-cells = <0>;
1023 519 #power-domain-cells = <1>;
1024 520
1025 521 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1026 522 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
1027 523 #power-domain-cells = <0>;
1028 524 };
1029 525
1030 526 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1031 527 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
1032 528 #power-domain-cells = <0>;
1033 529 };
1034 }; 530 };
1035 531
1036 power 532 power-domain@MT8186_POWER_DOMAIN_IMG {
1037 533 reg = <MT8186_POWER_DOMAIN_IMG>;
1038 !! 534 clocks = <&topckgen CLK_TOP_IMG1>,
1039 !! 535 <&imgsys1 CLK_IMG1_GALS_IMG1>;
1040 !! 536 clock-names = "img-top", "gals";
1041 537 mediatek,infracfg = <&infracfg_ao>;
1042 538 #address-cells = <1>;
1043 539 #size-cells = <0>;
1044 540 #power-domain-cells = <1>;
1045 541
1046 542 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1047 543 reg = <MT8186_POWER_DOMAIN_IMG2>;
1048 544 #power-domain-cells = <0>;
1049 545 };
1050 }; 546 };
1051 547
1052 power 548 power-domain@MT8186_POWER_DOMAIN_IPE {
1053 549 reg = <MT8186_POWER_DOMAIN_IPE>;
1054 550 clocks = <&topckgen CLK_TOP_IPE>,
1055 551 <&ipesys CLK_IPE_LARB19>,
1056 552 <&ipesys CLK_IPE_LARB20>,
1057 553 <&ipesys CLK_IPE_SMI_SUBCOM>,
1058 554 <&ipesys CLK_IPE_GALS_IPE>;
1059 !! 555 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
1060 !! 556 "ipe-smi", "ipe-gals";
1061 <<
1062 <<
1063 <<
1064 557 mediatek,infracfg = <&infracfg_ao>;
1065 558 #power-domain-cells = <0>;
1066 }; 559 };
1067 560
1068 power 561 power-domain@MT8186_POWER_DOMAIN_VENC {
1069 562 reg = <MT8186_POWER_DOMAIN_VENC>;
1070 563 clocks = <&topckgen CLK_TOP_VENC>,
1071 564 <&vencsys CLK_VENC_CKE1_VENC>;
1072 !! 565 clock-names = "venc0", "larb";
1073 566 mediatek,infracfg = <&infracfg_ao>;
1074 567 #power-domain-cells = <0>;
1075 }; 568 };
1076 569
1077 power 570 power-domain@MT8186_POWER_DOMAIN_WPE {
1078 571 reg = <MT8186_POWER_DOMAIN_WPE>;
1079 572 clocks = <&topckgen CLK_TOP_WPE>,
1080 573 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1081 574 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
1082 !! 575 clock-names = "wpe0", "larb-ck", "larb-pclk";
1083 <<
1084 <<
1085 576 mediatek,infracfg = <&infracfg_ao>;
1086 577 #power-domain-cells = <0>;
1087 }; 578 };
1088 }; 579 };
1089 }; 580 };
1090 }; 581 };
1091 582
1092 watchdog: watchdog@10007000 { 583 watchdog: watchdog@10007000 {
1093 compatible = "mediate 584 compatible = "mediatek,mt8186-wdt";
1094 mediatek,disable-extr 585 mediatek,disable-extrst;
1095 reg = <0 0x10007000 0 586 reg = <0 0x10007000 0 0x1000>;
1096 #reset-cells = <1>; 587 #reset-cells = <1>;
1097 }; 588 };
1098 589
1099 apmixedsys: syscon@1000c000 { 590 apmixedsys: syscon@1000c000 {
1100 compatible = "mediate 591 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1101 reg = <0 0x1000c000 0 592 reg = <0 0x1000c000 0 0x1000>;
1102 #clock-cells = <1>; 593 #clock-cells = <1>;
1103 }; 594 };
1104 595
1105 pwrap: pwrap@1000d000 { 596 pwrap: pwrap@1000d000 {
1106 compatible = "mediate 597 compatible = "mediatek,mt8186-pwrap", "syscon";
1107 reg = <0 0x1000d000 0 598 reg = <0 0x1000d000 0 0x1000>;
1108 reg-names = "pwrap"; 599 reg-names = "pwrap";
1109 interrupts = <GIC_SPI 600 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1110 clocks = <&infracfg_a 601 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1111 <&infracfg_a 602 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1112 clock-names = "spi", 603 clock-names = "spi", "wrap";
1113 }; 604 };
1114 605
1115 spmi: spmi@10015000 { <<
1116 compatible = "mediate <<
1117 reg = <0 0x10015000 0 <<
1118 reg-names = "pmif", " <<
1119 clocks = <&infracfg_a <<
1120 <&infracfg_a <<
1121 <&topckgen C <<
1122 clock-names = "pmif_s <<
1123 assigned-clocks = <&t <<
1124 assigned-clock-parent <<
1125 interrupts = <GIC_SPI <<
1126 <GIC_SPI <<
1127 status = "disabled"; <<
1128 }; <<
1129 <<
1130 systimer: timer@10017000 { 606 systimer: timer@10017000 {
1131 compatible = "mediate 607 compatible = "mediatek,mt8186-timer",
1132 "mediate 608 "mediatek,mt6765-timer";
1133 reg = <0 0x10017000 0 609 reg = <0 0x10017000 0 0x1000>;
1134 interrupts = <GIC_SPI 610 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1135 clocks = <&clk13m>; 611 clocks = <&clk13m>;
1136 }; 612 };
1137 613
1138 gce: mailbox@1022c000 { <<
1139 compatible = "mediate <<
1140 reg = <0 0X1022c000 0 <<
1141 clocks = <&infracfg_a <<
1142 clock-names = "gce"; <<
1143 interrupts = <GIC_SPI <<
1144 #mbox-cells = <2>; <<
1145 }; <<
1146 <<
1147 scp: scp@10500000 { 614 scp: scp@10500000 {
1148 compatible = "mediate 615 compatible = "mediatek,mt8186-scp";
1149 reg = <0 0x10500000 0 616 reg = <0 0x10500000 0 0x40000>,
1150 <0 0x105c0000 0 617 <0 0x105c0000 0 0x19080>;
1151 reg-names = "sram", " 618 reg-names = "sram", "cfg";
1152 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1153 }; 620 };
1154 621
1155 adsp: adsp@10680000 { !! 622 adsp_mailbox0: mailbox@10686000 {
1156 compatible = "mediate <<
1157 reg = <0 0x10680000 0 <<
1158 <0 0x1068b000 0 <<
1159 reg-names = "cfg", "s <<
1160 clocks = <&topckgen C <<
1161 clock-names = "audiod <<
1162 assigned-clocks = <&t <<
1163 <&t <<
1164 assigned-clock-parent <<
1165 mbox-names = "rx", "t <<
1166 mboxes = <&adsp_mailb <<
1167 power-domains = <&spm <<
1168 status = "disabled"; <<
1169 }; <<
1170 <<
1171 adsp_mailbox0: mailbox@106861 <<
1172 compatible = "mediate 623 compatible = "mediatek,mt8186-adsp-mbox";
1173 #mbox-cells = <0>; 624 #mbox-cells = <0>;
1174 reg = <0 0x10686100 0 625 reg = <0 0x10686100 0 0x1000>;
1175 interrupts = <GIC_SPI 626 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1176 }; 627 };
1177 628
1178 adsp_mailbox1: mailbox@106871 !! 629 adsp_mailbox1: mailbox@10687000 {
1179 compatible = "mediate 630 compatible = "mediatek,mt8186-adsp-mbox";
1180 #mbox-cells = <0>; 631 #mbox-cells = <0>;
1181 reg = <0 0x10687100 0 632 reg = <0 0x10687100 0 0x1000>;
1182 interrupts = <GIC_SPI 633 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1183 }; 634 };
1184 635
1185 nor_flash: spi@11000000 { 636 nor_flash: spi@11000000 {
1186 compatible = "mediate 637 compatible = "mediatek,mt8186-nor";
1187 reg = <0 0x11000000 0 638 reg = <0 0x11000000 0 0x1000>;
1188 clocks = <&topckgen C 639 clocks = <&topckgen CLK_TOP_SPINOR>,
1189 <&infracfg_a 640 <&infracfg_ao CLK_INFRA_AO_SPINOR>,
1190 <&infracfg_a 641 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
1191 <&infracfg_a 642 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
1192 clock-names = "spi", 643 clock-names = "spi", "sf", "axi", "axi_s";
1193 assigned-clocks = <&t 644 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1194 assigned-clock-parent 645 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1195 interrupts = <GIC_SPI 646 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1196 status = "disabled"; 647 status = "disabled";
1197 }; 648 };
1198 649
1199 auxadc: adc@11001000 { 650 auxadc: adc@11001000 {
1200 compatible = "mediate 651 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1201 reg = <0 0x11001000 0 652 reg = <0 0x11001000 0 0x1000>;
1202 #io-channel-cells = < 653 #io-channel-cells = <1>;
1203 clocks = <&infracfg_a 654 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1204 clock-names = "main"; 655 clock-names = "main";
1205 }; 656 };
1206 657
1207 uart0: serial@11002000 { 658 uart0: serial@11002000 {
1208 compatible = "mediate 659 compatible = "mediatek,mt8186-uart",
1209 "mediate 660 "mediatek,mt6577-uart";
1210 reg = <0 0x11002000 0 661 reg = <0 0x11002000 0 0x1000>;
1211 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1212 clocks = <&clk26m>, < 663 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1213 clock-names = "baud", 664 clock-names = "baud", "bus";
1214 status = "disabled"; 665 status = "disabled";
1215 }; 666 };
1216 667
1217 uart1: serial@11003000 { 668 uart1: serial@11003000 {
1218 compatible = "mediate 669 compatible = "mediatek,mt8186-uart",
1219 "mediate 670 "mediatek,mt6577-uart";
1220 reg = <0 0x11003000 0 671 reg = <0 0x11003000 0 0x1000>;
1221 interrupts = <GIC_SPI 672 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1222 clocks = <&clk26m>, < 673 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1223 clock-names = "baud", 674 clock-names = "baud", "bus";
1224 status = "disabled"; 675 status = "disabled";
1225 }; 676 };
1226 677
1227 i2c0: i2c@11007000 { 678 i2c0: i2c@11007000 {
1228 compatible = "mediate 679 compatible = "mediatek,mt8186-i2c";
1229 reg = <0 0x11007000 0 680 reg = <0 0x11007000 0 0x1000>,
1230 <0 0x10200100 0 681 <0 0x10200100 0 0x100>;
1231 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1232 clocks = <&imp_iic_wr 683 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
1233 <&infracfg_a 684 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1234 clock-names = "main", 685 clock-names = "main", "dma";
1235 clock-div = <1>; 686 clock-div = <1>;
1236 #address-cells = <1>; 687 #address-cells = <1>;
1237 #size-cells = <0>; 688 #size-cells = <0>;
1238 status = "disabled"; 689 status = "disabled";
1239 }; 690 };
1240 691
1241 i2c1: i2c@11008000 { 692 i2c1: i2c@11008000 {
1242 compatible = "mediate 693 compatible = "mediatek,mt8186-i2c";
1243 reg = <0 0x11008000 0 694 reg = <0 0x11008000 0 0x1000>,
1244 <0 0x10200200 0 695 <0 0x10200200 0 0x100>;
1245 interrupts = <GIC_SPI 696 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1246 clocks = <&imp_iic_wr 697 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
1247 <&infracfg_a 698 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1248 clock-names = "main", 699 clock-names = "main", "dma";
1249 clock-div = <1>; 700 clock-div = <1>;
1250 #address-cells = <1>; 701 #address-cells = <1>;
1251 #size-cells = <0>; 702 #size-cells = <0>;
1252 status = "disabled"; 703 status = "disabled";
1253 }; 704 };
1254 705
1255 i2c2: i2c@11009000 { 706 i2c2: i2c@11009000 {
1256 compatible = "mediate 707 compatible = "mediatek,mt8186-i2c";
1257 reg = <0 0x11009000 0 708 reg = <0 0x11009000 0 0x1000>,
1258 <0 0x10200300 0 709 <0 0x10200300 0 0x180>;
1259 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1260 clocks = <&imp_iic_wr 711 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
1261 <&infracfg_a 712 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1262 clock-names = "main", 713 clock-names = "main", "dma";
1263 clock-div = <1>; 714 clock-div = <1>;
1264 #address-cells = <1>; 715 #address-cells = <1>;
1265 #size-cells = <0>; 716 #size-cells = <0>;
1266 status = "disabled"; 717 status = "disabled";
1267 }; 718 };
1268 719
1269 i2c3: i2c@1100f000 { 720 i2c3: i2c@1100f000 {
1270 compatible = "mediate 721 compatible = "mediatek,mt8186-i2c";
1271 reg = <0 0x1100f000 0 722 reg = <0 0x1100f000 0 0x1000>,
1272 <0 0x10200480 0 723 <0 0x10200480 0 0x100>;
1273 interrupts = <GIC_SPI 724 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1274 clocks = <&imp_iic_wr 725 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
1275 <&infracfg_a 726 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1276 clock-names = "main", 727 clock-names = "main", "dma";
1277 clock-div = <1>; 728 clock-div = <1>;
1278 #address-cells = <1>; 729 #address-cells = <1>;
1279 #size-cells = <0>; 730 #size-cells = <0>;
1280 status = "disabled"; 731 status = "disabled";
1281 }; 732 };
1282 733
1283 i2c4: i2c@11011000 { 734 i2c4: i2c@11011000 {
1284 compatible = "mediate 735 compatible = "mediatek,mt8186-i2c";
1285 reg = <0 0x11011000 0 736 reg = <0 0x11011000 0 0x1000>,
1286 <0 0x10200580 0 737 <0 0x10200580 0 0x180>;
1287 interrupts = <GIC_SPI 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1288 clocks = <&imp_iic_wr 739 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
1289 <&infracfg_a 740 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1290 clock-names = "main", 741 clock-names = "main", "dma";
1291 clock-div = <1>; 742 clock-div = <1>;
1292 #address-cells = <1>; 743 #address-cells = <1>;
1293 #size-cells = <0>; 744 #size-cells = <0>;
1294 status = "disabled"; 745 status = "disabled";
1295 }; 746 };
1296 747
1297 i2c5: i2c@11016000 { 748 i2c5: i2c@11016000 {
1298 compatible = "mediate 749 compatible = "mediatek,mt8186-i2c";
1299 reg = <0 0x11016000 0 750 reg = <0 0x11016000 0 0x1000>,
1300 <0 0x10200700 0 751 <0 0x10200700 0 0x100>;
1301 interrupts = <GIC_SPI 752 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1302 clocks = <&imp_iic_wr 753 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
1303 <&infracfg_a 754 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1304 clock-names = "main", 755 clock-names = "main", "dma";
1305 clock-div = <1>; 756 clock-div = <1>;
1306 #address-cells = <1>; 757 #address-cells = <1>;
1307 #size-cells = <0>; 758 #size-cells = <0>;
1308 status = "disabled"; 759 status = "disabled";
1309 }; 760 };
1310 761
1311 i2c6: i2c@1100d000 { 762 i2c6: i2c@1100d000 {
1312 compatible = "mediate 763 compatible = "mediatek,mt8186-i2c";
1313 reg = <0 0x1100d000 0 764 reg = <0 0x1100d000 0 0x1000>,
1314 <0 0x10200800 0 765 <0 0x10200800 0 0x100>;
1315 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1316 clocks = <&imp_iic_wr 767 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
1317 <&infracfg_a 768 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1318 clock-names = "main", 769 clock-names = "main", "dma";
1319 clock-div = <1>; 770 clock-div = <1>;
1320 #address-cells = <1>; 771 #address-cells = <1>;
1321 #size-cells = <0>; 772 #size-cells = <0>;
1322 status = "disabled"; 773 status = "disabled";
1323 }; 774 };
1324 775
1325 i2c7: i2c@11004000 { 776 i2c7: i2c@11004000 {
1326 compatible = "mediate 777 compatible = "mediatek,mt8186-i2c";
1327 reg = <0 0x11004000 0 778 reg = <0 0x11004000 0 0x1000>,
1328 <0 0x10200900 0 779 <0 0x10200900 0 0x180>;
1329 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1330 clocks = <&imp_iic_wr 781 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
1331 <&infracfg_a 782 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1332 clock-names = "main", 783 clock-names = "main", "dma";
1333 clock-div = <1>; 784 clock-div = <1>;
1334 #address-cells = <1>; 785 #address-cells = <1>;
1335 #size-cells = <0>; 786 #size-cells = <0>;
1336 status = "disabled"; 787 status = "disabled";
1337 }; 788 };
1338 789
1339 i2c8: i2c@11005000 { 790 i2c8: i2c@11005000 {
1340 compatible = "mediate 791 compatible = "mediatek,mt8186-i2c";
1341 reg = <0 0x11005000 0 792 reg = <0 0x11005000 0 0x1000>,
1342 <0 0x10200A80 0 793 <0 0x10200A80 0 0x180>;
1343 interrupts = <GIC_SPI 794 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1344 clocks = <&imp_iic_wr 795 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
1345 <&infracfg_a 796 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1346 clock-names = "main", 797 clock-names = "main", "dma";
1347 clock-div = <1>; 798 clock-div = <1>;
1348 #address-cells = <1>; 799 #address-cells = <1>;
1349 #size-cells = <0>; 800 #size-cells = <0>;
1350 status = "disabled"; 801 status = "disabled";
1351 }; 802 };
1352 803
1353 spi0: spi@1100a000 { 804 spi0: spi@1100a000 {
1354 compatible = "mediate 805 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1355 #address-cells = <1>; 806 #address-cells = <1>;
1356 #size-cells = <0>; 807 #size-cells = <0>;
1357 reg = <0 0x1100a000 0 808 reg = <0 0x1100a000 0 0x1000>;
1358 interrupts = <GIC_SPI 809 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1359 clocks = <&topckgen C 810 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1360 <&topckgen C 811 <&topckgen CLK_TOP_SPI>,
1361 <&infracfg_a 812 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1362 clock-names = "parent 813 clock-names = "parent-clk", "sel-clk", "spi-clk";
1363 status = "disabled"; 814 status = "disabled";
1364 }; 815 };
1365 816
1366 lvts: thermal-sensor@1100b000 <<
1367 compatible = "mediate <<
1368 reg = <0 0x1100b000 0 <<
1369 interrupts = <GIC_SPI <<
1370 clocks = <&infracfg_a <<
1371 resets = <&infracfg_a <<
1372 nvmem-cells = <&lvts_ <<
1373 nvmem-cell-names = "l <<
1374 #thermal-sensor-cells <<
1375 }; <<
1376 <<
1377 svs: svs@1100bc00 { <<
1378 compatible = "mediate <<
1379 reg = <0 0x1100bc00 0 <<
1380 interrupts = <GIC_SPI <<
1381 clocks = <&infracfg_a <<
1382 clock-names = "main"; <<
1383 nvmem-cells = <&svs_c <<
1384 nvmem-cell-names = "s <<
1385 resets = <&infracfg_a <<
1386 reset-names = "svs_rs <<
1387 }; <<
1388 <<
1389 pwm0: pwm@1100e000 { 817 pwm0: pwm@1100e000 {
1390 compatible = "mediate 818 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1391 reg = <0 0x1100e000 0 819 reg = <0 0x1100e000 0 0x1000>;
1392 interrupts = <GIC_SPI 820 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1393 #pwm-cells = <2>; 821 #pwm-cells = <2>;
1394 clocks = <&topckgen C 822 clocks = <&topckgen CLK_TOP_DISP_PWM>,
1395 <&infracfg_a 823 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1396 clock-names = "main", 824 clock-names = "main", "mm";
1397 status = "disabled"; 825 status = "disabled";
1398 }; 826 };
1399 827
1400 spi1: spi@11010000 { 828 spi1: spi@11010000 {
1401 compatible = "mediate 829 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1402 #address-cells = <1>; 830 #address-cells = <1>;
1403 #size-cells = <0>; 831 #size-cells = <0>;
1404 reg = <0 0x11010000 0 832 reg = <0 0x11010000 0 0x1000>;
1405 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1406 clocks = <&topckgen C 834 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1407 <&topckgen C 835 <&topckgen CLK_TOP_SPI>,
1408 <&infracfg_a 836 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1409 clock-names = "parent 837 clock-names = "parent-clk", "sel-clk", "spi-clk";
1410 status = "disabled"; 838 status = "disabled";
1411 }; 839 };
1412 840
1413 spi2: spi@11012000 { 841 spi2: spi@11012000 {
1414 compatible = "mediate 842 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1415 #address-cells = <1>; 843 #address-cells = <1>;
1416 #size-cells = <0>; 844 #size-cells = <0>;
1417 reg = <0 0x11012000 0 845 reg = <0 0x11012000 0 0x1000>;
1418 interrupts = <GIC_SPI 846 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1419 clocks = <&topckgen C 847 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1420 <&topckgen C 848 <&topckgen CLK_TOP_SPI>,
1421 <&infracfg_a 849 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1422 clock-names = "parent 850 clock-names = "parent-clk", "sel-clk", "spi-clk";
1423 status = "disabled"; 851 status = "disabled";
1424 }; 852 };
1425 853
1426 spi3: spi@11013000 { 854 spi3: spi@11013000 {
1427 compatible = "mediate 855 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1428 #address-cells = <1>; 856 #address-cells = <1>;
1429 #size-cells = <0>; 857 #size-cells = <0>;
1430 reg = <0 0x11013000 0 858 reg = <0 0x11013000 0 0x1000>;
1431 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1432 clocks = <&topckgen C 860 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1433 <&topckgen C 861 <&topckgen CLK_TOP_SPI>,
1434 <&infracfg_a 862 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1435 clock-names = "parent 863 clock-names = "parent-clk", "sel-clk", "spi-clk";
1436 status = "disabled"; 864 status = "disabled";
1437 }; 865 };
1438 866
1439 spi4: spi@11014000 { 867 spi4: spi@11014000 {
1440 compatible = "mediate 868 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1441 #address-cells = <1>; 869 #address-cells = <1>;
1442 #size-cells = <0>; 870 #size-cells = <0>;
1443 reg = <0 0x11014000 0 871 reg = <0 0x11014000 0 0x1000>;
1444 interrupts = <GIC_SPI 872 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1445 clocks = <&topckgen C 873 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1446 <&topckgen C 874 <&topckgen CLK_TOP_SPI>,
1447 <&infracfg_a 875 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1448 clock-names = "parent 876 clock-names = "parent-clk", "sel-clk", "spi-clk";
1449 status = "disabled"; 877 status = "disabled";
1450 }; 878 };
1451 879
1452 spi5: spi@11015000 { 880 spi5: spi@11015000 {
1453 compatible = "mediate 881 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1454 #address-cells = <1>; 882 #address-cells = <1>;
1455 #size-cells = <0>; 883 #size-cells = <0>;
1456 reg = <0 0x11015000 0 884 reg = <0 0x11015000 0 0x1000>;
1457 interrupts = <GIC_SPI 885 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1458 clocks = <&topckgen C 886 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1459 <&topckgen C 887 <&topckgen CLK_TOP_SPI>,
1460 <&infracfg_a 888 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1461 clock-names = "parent 889 clock-names = "parent-clk", "sel-clk", "spi-clk";
1462 status = "disabled"; 890 status = "disabled";
1463 }; 891 };
1464 892
1465 imp_iic_wrap: clock-controlle 893 imp_iic_wrap: clock-controller@11017000 {
1466 compatible = "mediate 894 compatible = "mediatek,mt8186-imp_iic_wrap";
1467 reg = <0 0x11017000 0 895 reg = <0 0x11017000 0 0x1000>;
1468 #clock-cells = <1>; 896 #clock-cells = <1>;
1469 }; 897 };
1470 898
1471 uart2: serial@11018000 { 899 uart2: serial@11018000 {
1472 compatible = "mediate 900 compatible = "mediatek,mt8186-uart",
1473 "mediate 901 "mediatek,mt6577-uart";
1474 reg = <0 0x11018000 0 902 reg = <0 0x11018000 0 0x1000>;
1475 interrupts = <GIC_SPI 903 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1476 clocks = <&clk26m>, < 904 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1477 clock-names = "baud", 905 clock-names = "baud", "bus";
1478 status = "disabled"; 906 status = "disabled";
1479 }; 907 };
1480 908
1481 i2c9: i2c@11019000 { 909 i2c9: i2c@11019000 {
1482 compatible = "mediate 910 compatible = "mediatek,mt8186-i2c";
1483 reg = <0 0x11019000 0 911 reg = <0 0x11019000 0 0x1000>,
1484 <0 0x10200c00 0 912 <0 0x10200c00 0 0x180>;
1485 interrupts = <GIC_SPI 913 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1486 clocks = <&imp_iic_wr 914 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
1487 <&infracfg_a 915 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1488 clock-names = "main", 916 clock-names = "main", "dma";
1489 clock-div = <1>; 917 clock-div = <1>;
1490 #address-cells = <1>; 918 #address-cells = <1>;
1491 #size-cells = <0>; 919 #size-cells = <0>;
1492 status = "disabled"; 920 status = "disabled";
1493 }; 921 };
1494 922
1495 afe: audio-controller@1121000 923 afe: audio-controller@11210000 {
1496 compatible = "mediate 924 compatible = "mediatek,mt8186-sound";
1497 reg = <0 0x11210000 0 925 reg = <0 0x11210000 0 0x2000>;
1498 clocks = <&infracfg_a 926 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
1499 <&infracfg_a 927 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
1500 <&topckgen C 928 <&topckgen CLK_TOP_AUDIO>,
1501 <&topckgen C 929 <&topckgen CLK_TOP_AUD_INTBUS>,
1502 <&topckgen C 930 <&topckgen CLK_TOP_MAINPLL_D2_D4>,
1503 <&topckgen C 931 <&topckgen CLK_TOP_AUD_1>,
1504 <&apmixedsys 932 <&apmixedsys CLK_APMIXED_APLL1>,
1505 <&topckgen C 933 <&topckgen CLK_TOP_AUD_2>,
1506 <&apmixedsys 934 <&apmixedsys CLK_APMIXED_APLL2>,
1507 <&topckgen C 935 <&topckgen CLK_TOP_AUD_ENGEN1>,
1508 <&topckgen C 936 <&topckgen CLK_TOP_APLL1_D8>,
1509 <&topckgen C 937 <&topckgen CLK_TOP_AUD_ENGEN2>,
1510 <&topckgen C 938 <&topckgen CLK_TOP_APLL2_D8>,
1511 <&topckgen C 939 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
1512 <&topckgen C 940 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
1513 <&topckgen C 941 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
1514 <&topckgen C 942 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
1515 <&topckgen C 943 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
1516 <&topckgen C 944 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
1517 <&topckgen C 945 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
1518 <&topckgen C 946 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
1519 <&topckgen C 947 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
1520 <&topckgen C 948 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
1521 <&topckgen C 949 <&topckgen CLK_TOP_AUDIO_H>,
1522 <&clk26m>; 950 <&clk26m>;
1523 clock-names = "aud_in 951 clock-names = "aud_infra_clk",
1524 "mtkaif 952 "mtkaif_26m_clk",
1525 "top_mu 953 "top_mux_audio",
1526 "top_mu 954 "top_mux_audio_int",
1527 "top_ma 955 "top_mainpll_d2_d4",
1528 "top_mu 956 "top_mux_aud_1",
1529 "top_ap 957 "top_apll1_ck",
1530 "top_mu 958 "top_mux_aud_2",
1531 "top_ap 959 "top_apll2_ck",
1532 "top_mu 960 "top_mux_aud_eng1",
1533 "top_ap 961 "top_apll1_d8",
1534 "top_mu 962 "top_mux_aud_eng2",
1535 "top_ap 963 "top_apll2_d8",
1536 "top_i2 964 "top_i2s0_m_sel",
1537 "top_i2 965 "top_i2s1_m_sel",
1538 "top_i2 966 "top_i2s2_m_sel",
1539 "top_i2 967 "top_i2s4_m_sel",
1540 "top_td 968 "top_tdm_m_sel",
1541 "top_ap 969 "top_apll12_div0",
1542 "top_ap 970 "top_apll12_div1",
1543 "top_ap 971 "top_apll12_div2",
1544 "top_ap 972 "top_apll12_div4",
1545 "top_ap 973 "top_apll12_div_tdm",
1546 "top_mu 974 "top_mux_audio_h",
1547 "top_cl 975 "top_clk26m_clk";
1548 interrupts = <GIC_SPI 976 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1549 mediatek,apmixedsys = 977 mediatek,apmixedsys = <&apmixedsys>;
1550 mediatek,infracfg = < 978 mediatek,infracfg = <&infracfg_ao>;
1551 mediatek,topckgen = < 979 mediatek,topckgen = <&topckgen>;
1552 resets = <&watchdog M 980 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
1553 reset-names = "audios 981 reset-names = "audiosys";
1554 status = "disabled"; 982 status = "disabled";
1555 }; 983 };
1556 984
1557 ssusb0: usb@11201000 { <<
1558 compatible = "mediate <<
1559 reg = <0 0x11201000 0 <<
1560 reg-names = "mac", "i <<
1561 clocks = <&topckgen C <<
1562 <&infracfg_a <<
1563 <&infracfg_a <<
1564 <&infracfg_a <<
1565 <&infracfg_a <<
1566 clock-names = "sys_ck <<
1567 interrupts = <GIC_SPI <<
1568 phys = <&u2port0 PHY_ <<
1569 power-domains = <&spm <<
1570 #address-cells = <2>; <<
1571 #size-cells = <2>; <<
1572 ranges; <<
1573 status = "disabled"; <<
1574 <<
1575 usb_host0: usb@112000 <<
1576 compatible = <<
1577 reg = <0 0x11 <<
1578 reg-names = " <<
1579 clocks = <&to <<
1580 <&in <<
1581 <&in <<
1582 <&in <<
1583 <&in <<
1584 clock-names = <<
1585 interrupts = <<
1586 mediatek,sysc <<
1587 wakeup-source <<
1588 status = "dis <<
1589 }; <<
1590 }; <<
1591 <<
1592 mmc0: mmc@11230000 { 985 mmc0: mmc@11230000 {
1593 compatible = "mediate 986 compatible = "mediatek,mt8186-mmc",
1594 "mediate 987 "mediatek,mt8183-mmc";
1595 reg = <0 0x11230000 0 988 reg = <0 0x11230000 0 0x10000>,
1596 <0 0x11cd0000 0 989 <0 0x11cd0000 0 0x1000>;
1597 clocks = <&topckgen C 990 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1598 <&infracfg_a 991 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1599 <&infracfg_a 992 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1600 <&infracfg_a 993 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
1601 clock-names = "source 994 clock-names = "source", "hclk", "source_cg", "crypto";
1602 interrupts = <GIC_SPI 995 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1603 assigned-clocks = <&t 996 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1604 assigned-clock-parent 997 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1605 status = "disabled"; 998 status = "disabled";
1606 }; 999 };
1607 1000
1608 mmc1: mmc@11240000 { 1001 mmc1: mmc@11240000 {
1609 compatible = "mediate 1002 compatible = "mediatek,mt8186-mmc",
1610 "mediate 1003 "mediatek,mt8183-mmc";
1611 reg = <0 0x11240000 0 1004 reg = <0 0x11240000 0 0x1000>,
1612 <0 0x11c90000 0 1005 <0 0x11c90000 0 0x1000>;
1613 clocks = <&topckgen C 1006 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1614 <&infracfg_a 1007 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1615 <&infracfg_a 1008 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1616 clock-names = "source 1009 clock-names = "source", "hclk", "source_cg";
1617 interrupts = <GIC_SPI 1010 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1618 assigned-clocks = <&t 1011 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1619 assigned-clock-parent 1012 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1620 status = "disabled"; 1013 status = "disabled";
1621 }; 1014 };
1622 1015
1623 ssusb1: usb@11281000 { <<
1624 compatible = "mediate <<
1625 reg = <0 0x11281000 0 <<
1626 reg-names = "mac", "i <<
1627 clocks = <&infracfg_a <<
1628 <&infracfg_a <<
1629 <&infracfg_a <<
1630 <&clk26m>, <<
1631 <&infracfg_a <<
1632 clock-names = "sys_ck <<
1633 interrupts = <GIC_SPI <<
1634 phys = <&u2port1 PHY_ <<
1635 power-domains = <&spm <<
1636 #address-cells = <2>; <<
1637 #size-cells = <2>; <<
1638 ranges; <<
1639 status = "disabled"; <<
1640 <<
1641 usb_host1: usb@112800 <<
1642 compatible = <<
1643 reg = <0 0x11 <<
1644 reg-names = " <<
1645 clocks = <&in <<
1646 <&in <<
1647 <&in <<
1648 <&cl <<
1649 <&in <<
1650 clock-names = <<
1651 interrupts = <<
1652 mediatek,sysc <<
1653 wakeup-source <<
1654 status = "dis <<
1655 }; <<
1656 }; <<
1657 <<
1658 u3phy0: t-phy@11c80000 { 1016 u3phy0: t-phy@11c80000 {
1659 compatible = "mediate 1017 compatible = "mediatek,mt8186-tphy",
1660 "mediate 1018 "mediatek,generic-tphy-v2";
1661 #address-cells = <1>; 1019 #address-cells = <1>;
1662 #size-cells = <1>; 1020 #size-cells = <1>;
1663 ranges = <0x0 0x0 0x1 1021 ranges = <0x0 0x0 0x11c80000 0x1000>;
1664 status = "disabled"; 1022 status = "disabled";
1665 1023
1666 u2port1: usb-phy@0 { 1024 u2port1: usb-phy@0 {
1667 reg = <0x0 0x 1025 reg = <0x0 0x700>;
1668 clocks = <&cl 1026 clocks = <&clk26m>;
1669 clock-names = 1027 clock-names = "ref";
1670 #phy-cells = 1028 #phy-cells = <1>;
1671 }; 1029 };
1672 1030
1673 u3port1: usb-phy@700 1031 u3port1: usb-phy@700 {
1674 reg = <0x700 1032 reg = <0x700 0x900>;
1675 clocks = <&cl 1033 clocks = <&clk26m>;
1676 clock-names = 1034 clock-names = "ref";
1677 #phy-cells = 1035 #phy-cells = <1>;
1678 }; 1036 };
1679 }; 1037 };
1680 1038
1681 u3phy1: t-phy@11ca0000 { 1039 u3phy1: t-phy@11ca0000 {
1682 compatible = "mediate 1040 compatible = "mediatek,mt8186-tphy",
1683 "mediate 1041 "mediatek,generic-tphy-v2";
1684 #address-cells = <1>; 1042 #address-cells = <1>;
1685 #size-cells = <1>; 1043 #size-cells = <1>;
1686 ranges = <0x0 0x0 0x1 1044 ranges = <0x0 0x0 0x11ca0000 0x1000>;
1687 status = "disabled"; 1045 status = "disabled";
1688 1046
1689 u2port0: usb-phy@0 { 1047 u2port0: usb-phy@0 {
1690 reg = <0x0 0x 1048 reg = <0x0 0x700>;
1691 clocks = <&cl 1049 clocks = <&clk26m>;
1692 clock-names = 1050 clock-names = "ref";
1693 #phy-cells = 1051 #phy-cells = <1>;
1694 mediatek,disc 1052 mediatek,discth = <0x8>;
1695 }; 1053 };
1696 }; 1054 };
1697 1055
1698 efuse: efuse@11cb0000 { 1056 efuse: efuse@11cb0000 {
1699 compatible = "mediate 1057 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1700 reg = <0 0x11cb0000 0 1058 reg = <0 0x11cb0000 0 0x1000>;
1701 #address-cells = <1>; 1059 #address-cells = <1>;
1702 #size-cells = <1>; 1060 #size-cells = <1>;
1703 <<
1704 lvts_efuse_data1: lvt <<
1705 reg = <0x1cc <<
1706 }; <<
1707 <<
1708 lvts_efuse_data2: lvt <<
1709 reg = <0x2f8 <<
1710 }; <<
1711 <<
1712 svs_calibration: cali <<
1713 reg = <0x550 <<
1714 }; <<
1715 <<
1716 gpu_speedbin: gpu-spe <<
1717 reg = <0x59c <<
1718 bits = <0 3>; <<
1719 }; <<
1720 <<
1721 socinfo-data1@7a0 { <<
1722 reg = <0x7a0 <<
1723 }; <<
1724 }; 1061 };
1725 1062
1726 mipi_tx0: dsi-phy@11cc0000 { 1063 mipi_tx0: dsi-phy@11cc0000 {
1727 compatible = "mediate 1064 compatible = "mediatek,mt8183-mipi-tx";
1728 reg = <0 0x11cc0000 0 1065 reg = <0 0x11cc0000 0 0x1000>;
1729 clocks = <&clk26m>; 1066 clocks = <&clk26m>;
1730 #clock-cells = <0>; 1067 #clock-cells = <0>;
1731 #phy-cells = <0>; 1068 #phy-cells = <0>;
1732 clock-output-names = 1069 clock-output-names = "mipi_tx0_pll";
1733 status = "disabled"; 1070 status = "disabled";
1734 }; 1071 };
1735 1072
1736 mfgsys: clock-controller@1300 1073 mfgsys: clock-controller@13000000 {
1737 compatible = "mediate 1074 compatible = "mediatek,mt8186-mfgsys";
1738 reg = <0 0x13000000 0 1075 reg = <0 0x13000000 0 0x1000>;
1739 #clock-cells = <1>; 1076 #clock-cells = <1>;
1740 }; 1077 };
1741 1078
1742 gpu: gpu@13040000 { 1079 gpu: gpu@13040000 {
1743 compatible = "mediate 1080 compatible = "mediatek,mt8186-mali",
1744 "arm,mal 1081 "arm,mali-bifrost";
1745 reg = <0 0x13040000 0 1082 reg = <0 0x13040000 0 0x4000>;
1746 1083
1747 clocks = <&mfgsys CLK 1084 clocks = <&mfgsys CLK_MFG_BG3D>;
1748 interrupts = <GIC_SPI 1085 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1749 <GIC_SPI 1086 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1750 <GIC_SPI 1087 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1751 interrupt-names = "jo 1088 interrupt-names = "job", "mmu", "gpu";
1752 power-domains = <&spm 1089 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1753 <&spm 1090 <&spm MT8186_POWER_DOMAIN_MFG3>;
1754 power-domain-names = 1091 power-domain-names = "core0", "core1";
1755 #cooling-cells = <2>; 1092 #cooling-cells = <2>;
1756 nvmem-cells = <&gpu_s <<
1757 nvmem-cell-names = "s <<
1758 operating-points-v2 = <<
1759 dynamic-power-coeffic <<
1760 status = "disabled"; 1093 status = "disabled";
1761 }; 1094 };
1762 1095
1763 mmsys: syscon@14000000 { 1096 mmsys: syscon@14000000 {
1764 compatible = "mediate 1097 compatible = "mediatek,mt8186-mmsys", "syscon";
1765 reg = <0 0x14000000 0 1098 reg = <0 0x14000000 0 0x1000>;
1766 #clock-cells = <1>; 1099 #clock-cells = <1>;
1767 #reset-cells = <1>; 1100 #reset-cells = <1>;
1768 mboxes = <&gce 0 CMDQ <<
1769 <&gce 1 CMDQ <<
1770 mediatek,gce-client-r <<
1771 }; <<
1772 <<
1773 mutex: mutex@14001000 { <<
1774 compatible = "mediate <<
1775 reg = <0 0x14001000 0 <<
1776 clocks = <&mmsys CLK_ <<
1777 interrupts = <GIC_SPI <<
1778 mediatek,gce-client-r <<
1779 mediatek,gce-events = <<
1780 <<
1781 power-domains = <&spm <<
1782 }; 1101 };
1783 1102
1784 smi_common: smi@14002000 { 1103 smi_common: smi@14002000 {
1785 compatible = "mediate 1104 compatible = "mediatek,mt8186-smi-common";
1786 reg = <0 0x14002000 0 1105 reg = <0 0x14002000 0 0x1000>;
1787 clocks = <&mmsys CLK_ 1106 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1788 <&mmsys CLK_ 1107 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1789 clock-names = "apb", 1108 clock-names = "apb", "smi", "gals0", "gals1";
1790 power-domains = <&spm 1109 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1791 }; 1110 };
1792 1111
1793 larb0: smi@14003000 { 1112 larb0: smi@14003000 {
1794 compatible = "mediate 1113 compatible = "mediatek,mt8186-smi-larb";
1795 reg = <0 0x14003000 0 1114 reg = <0 0x14003000 0 0x1000>;
1796 clocks = <&mmsys CLK_ 1115 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1797 <&mmsys CLK_ 1116 <&mmsys CLK_MM_SMI_COMMON>;
1798 clock-names = "apb", 1117 clock-names = "apb", "smi";
1799 mediatek,larb-id = <0 1118 mediatek,larb-id = <0>;
1800 mediatek,smi = <&smi_ 1119 mediatek,smi = <&smi_common>;
1801 power-domains = <&spm 1120 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1802 }; 1121 };
1803 1122
1804 larb1: smi@14004000 { 1123 larb1: smi@14004000 {
1805 compatible = "mediate 1124 compatible = "mediatek,mt8186-smi-larb";
1806 reg = <0 0x14004000 0 1125 reg = <0 0x14004000 0 0x1000>;
1807 clocks = <&mmsys CLK_ 1126 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1808 <&mmsys CLK_ 1127 <&mmsys CLK_MM_SMI_COMMON>;
1809 clock-names = "apb", 1128 clock-names = "apb", "smi";
1810 mediatek,larb-id = <1 1129 mediatek,larb-id = <1>;
1811 mediatek,smi = <&smi_ 1130 mediatek,smi = <&smi_common>;
1812 power-domains = <&spm 1131 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1813 }; 1132 };
1814 1133
1815 ovl0: ovl@14005000 { <<
1816 compatible = "mediate <<
1817 reg = <0 0x14005000 0 <<
1818 clocks = <&mmsys CLK_ <<
1819 interrupts = <GIC_SPI <<
1820 iommus = <&iommu_mm I <<
1821 mediatek,gce-client-r <<
1822 power-domains = <&spm <<
1823 }; <<
1824 <<
1825 ovl_2l0: ovl@14006000 { <<
1826 compatible = "mediate <<
1827 reg = <0 0x14006000 0 <<
1828 clocks = <&mmsys CLK_ <<
1829 interrupts = <GIC_SPI <<
1830 iommus = <&iommu_mm I <<
1831 mediatek,gce-client-r <<
1832 power-domains = <&spm <<
1833 }; <<
1834 <<
1835 rdma0: rdma@14007000 { <<
1836 compatible = "mediate <<
1837 reg = <0 0x14007000 0 <<
1838 clocks = <&mmsys CLK_ <<
1839 interrupts = <GIC_SPI <<
1840 iommus = <&iommu_mm I <<
1841 mediatek,gce-client-r <<
1842 power-domains = <&spm <<
1843 }; <<
1844 <<
1845 color: color@14009000 { <<
1846 compatible = "mediate <<
1847 reg = <0 0x14009000 0 <<
1848 clocks = <&mmsys CLK_ <<
1849 interrupts = <GIC_SPI <<
1850 mediatek,gce-client-r <<
1851 power-domains = <&spm <<
1852 }; <<
1853 <<
1854 dpi: dpi@1400a000 { 1134 dpi: dpi@1400a000 {
1855 compatible = "mediate 1135 compatible = "mediatek,mt8186-dpi";
1856 reg = <0 0x1400a000 0 1136 reg = <0 0x1400a000 0 0x1000>;
1857 clocks = <&topckgen C 1137 clocks = <&topckgen CLK_TOP_DPI>,
1858 <&mmsys CLK_ 1138 <&mmsys CLK_MM_DISP_DPI>,
1859 <&apmixedsys 1139 <&apmixedsys CLK_APMIXED_TVDPLL>;
1860 clock-names = "pixel" 1140 clock-names = "pixel", "engine", "pll";
1861 assigned-clocks = <&t 1141 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1862 assigned-clock-parent 1142 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1863 interrupts = <GIC_SPI 1143 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1864 power-domains = <&spm <<
1865 status = "disabled"; 1144 status = "disabled";
1866 1145
1867 port { 1146 port {
1868 dpi_out: endp 1147 dpi_out: endpoint { };
1869 }; 1148 };
1870 }; 1149 };
1871 1150
1872 ccorr: ccorr@1400b000 { <<
1873 compatible = "mediate <<
1874 reg = <0 0x1400b000 0 <<
1875 clocks = <&mmsys CLK_ <<
1876 interrupts = <GIC_SPI <<
1877 mediatek,gce-client-r <<
1878 power-domains = <&spm <<
1879 }; <<
1880 <<
1881 aal: aal@1400c000 { <<
1882 compatible = "mediate <<
1883 reg = <0 0x1400c000 0 <<
1884 clocks = <&mmsys CLK_ <<
1885 interrupts = <GIC_SPI <<
1886 mediatek,gce-client-r <<
1887 power-domains = <&spm <<
1888 }; <<
1889 <<
1890 gamma: gamma@1400d000 { <<
1891 compatible = "mediate <<
1892 reg = <0 0x1400d000 0 <<
1893 clocks = <&mmsys CLK_ <<
1894 interrupts = <GIC_SPI <<
1895 mediatek,gce-client-r <<
1896 power-domains = <&spm <<
1897 }; <<
1898 <<
1899 postmask: postmask@1400e000 { <<
1900 compatible = "mediate <<
1901 "mediate <<
1902 reg = <0 0x1400e000 0 <<
1903 clocks = <&mmsys CLK_ <<
1904 interrupts = <GIC_SPI <<
1905 mediatek,gce-client-r <<
1906 power-domains = <&spm <<
1907 }; <<
1908 <<
1909 dither: dither@1400f000 { <<
1910 compatible = "mediate <<
1911 reg = <0 0x1400f000 0 <<
1912 clocks = <&mmsys CLK_ <<
1913 interrupts = <GIC_SPI <<
1914 mediatek,gce-client-r <<
1915 power-domains = <&spm <<
1916 }; <<
1917 <<
1918 dsi0: dsi@14013000 { 1151 dsi0: dsi@14013000 {
1919 compatible = "mediate 1152 compatible = "mediatek,mt8186-dsi";
1920 reg = <0 0x14013000 0 1153 reg = <0 0x14013000 0 0x1000>;
1921 clocks = <&mmsys CLK_ 1154 clocks = <&mmsys CLK_MM_DSI0>,
1922 <&mmsys CLK_ 1155 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1923 <&mipi_tx0>; 1156 <&mipi_tx0>;
1924 clock-names = "engine 1157 clock-names = "engine", "digital", "hs";
1925 interrupts = <GIC_SPI 1158 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1926 power-domains = <&spm 1159 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1927 resets = <&mmsys MT81 1160 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1928 phys = <&mipi_tx0>; 1161 phys = <&mipi_tx0>;
1929 phy-names = "dphy"; 1162 phy-names = "dphy";
1930 status = "disabled"; 1163 status = "disabled";
1931 1164
1932 port { 1165 port {
1933 dsi_out: endp 1166 dsi_out: endpoint { };
1934 }; 1167 };
1935 }; 1168 };
1936 1169
1937 iommu_mm: iommu@14016000 { 1170 iommu_mm: iommu@14016000 {
1938 compatible = "mediate 1171 compatible = "mediatek,mt8186-iommu-mm";
1939 reg = <0 0x14016000 0 1172 reg = <0 0x14016000 0 0x1000>;
1940 clocks = <&mmsys CLK_ 1173 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1941 clock-names = "bclk"; 1174 clock-names = "bclk";
1942 interrupts = <GIC_SPI 1175 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1943 mediatek,larbs = <&la 1176 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1944 &la 1177 &larb7 &larb8 &larb9 &larb11
1945 &la 1178 &larb13 &larb14 &larb16 &larb17
1946 &la 1179 &larb19 &larb20>;
1947 power-domains = <&spm 1180 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1948 #iommu-cells = <1>; 1181 #iommu-cells = <1>;
1949 }; 1182 };
1950 1183
1951 rdma1: rdma@1401f000 { <<
1952 compatible = "mediate <<
1953 reg = <0 0x1401f000 0 <<
1954 clocks = <&mmsys CLK_ <<
1955 interrupts = <GIC_SPI <<
1956 iommus = <&iommu_mm I <<
1957 mediatek,gce-client-r <<
1958 power-domains = <&spm <<
1959 }; <<
1960 <<
1961 wpesys: clock-controller@1402 1184 wpesys: clock-controller@14020000 {
1962 compatible = "mediate 1185 compatible = "mediatek,mt8186-wpesys";
1963 reg = <0 0x14020000 0 1186 reg = <0 0x14020000 0 0x1000>;
1964 #clock-cells = <1>; 1187 #clock-cells = <1>;
1965 }; 1188 };
1966 1189
1967 larb8: smi@14023000 { 1190 larb8: smi@14023000 {
1968 compatible = "mediate 1191 compatible = "mediatek,mt8186-smi-larb";
1969 reg = <0 0x14023000 0 1192 reg = <0 0x14023000 0 0x1000>;
1970 clocks = <&wpesys CLK 1193 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1971 <&wpesys CLK 1194 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1972 clock-names = "apb", 1195 clock-names = "apb", "smi";
1973 mediatek,larb-id = <8 1196 mediatek,larb-id = <8>;
1974 mediatek,smi = <&smi_ 1197 mediatek,smi = <&smi_common>;
1975 power-domains = <&spm 1198 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1976 }; 1199 };
1977 1200
1978 imgsys1: clock-controller@150 1201 imgsys1: clock-controller@15020000 {
1979 compatible = "mediate 1202 compatible = "mediatek,mt8186-imgsys1";
1980 reg = <0 0x15020000 0 1203 reg = <0 0x15020000 0 0x1000>;
1981 #clock-cells = <1>; 1204 #clock-cells = <1>;
1982 }; 1205 };
1983 1206
1984 larb9: smi@1502e000 { 1207 larb9: smi@1502e000 {
1985 compatible = "mediate 1208 compatible = "mediatek,mt8186-smi-larb";
1986 reg = <0 0x1502e000 0 1209 reg = <0 0x1502e000 0 0x1000>;
1987 clocks = <&imgsys1 CL 1210 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1988 <&imgsys1 CL 1211 <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1989 clock-names = "apb", 1212 clock-names = "apb", "smi";
1990 mediatek,larb-id = <9 1213 mediatek,larb-id = <9>;
1991 mediatek,smi = <&smi_ 1214 mediatek,smi = <&smi_common>;
1992 power-domains = <&spm 1215 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1993 }; 1216 };
1994 1217
1995 imgsys2: clock-controller@158 1218 imgsys2: clock-controller@15820000 {
1996 compatible = "mediate 1219 compatible = "mediatek,mt8186-imgsys2";
1997 reg = <0 0x15820000 0 1220 reg = <0 0x15820000 0 0x1000>;
1998 #clock-cells = <1>; 1221 #clock-cells = <1>;
1999 }; 1222 };
2000 1223
2001 larb11: smi@1582e000 { 1224 larb11: smi@1582e000 {
2002 compatible = "mediate 1225 compatible = "mediatek,mt8186-smi-larb";
2003 reg = <0 0x1582e000 0 1226 reg = <0 0x1582e000 0 0x1000>;
2004 clocks = <&imgsys1 CL 1227 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
2005 <&imgsys2 CL 1228 <&imgsys2 CLK_IMG2_LARB9_IMG2>;
2006 clock-names = "apb", 1229 clock-names = "apb", "smi";
2007 mediatek,larb-id = <1 1230 mediatek,larb-id = <11>;
2008 mediatek,smi = <&smi_ 1231 mediatek,smi = <&smi_common>;
2009 power-domains = <&spm 1232 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
2010 }; 1233 };
2011 1234
2012 video_decoder: video-decoder@ <<
2013 compatible = "mediate <<
2014 reg = <0 0x16000000 0 <<
2015 ranges; <<
2016 #address-cells = <2>; <<
2017 #size-cells = <2>; <<
2018 dma-ranges = <0x1 0x0 <<
2019 iommus = <&iommu_mm I <<
2020 mediatek,scp = <&scp> <<
2021 <<
2022 vcodec_core: video-co <<
2023 compatible = <<
2024 reg = <0 0x16 <<
2025 interrupts = <<
2026 iommus = <&io <<
2027 <&io <<
2028 <&io <<
2029 <&io <<
2030 <&io <<
2031 <&io <<
2032 <&io <<
2033 <&io <<
2034 <&io <<
2035 <&io <<
2036 <&io <<
2037 <&io <<
2038 clocks = <&to <<
2039 <&vd <<
2040 <&vd <<
2041 <&to <<
2042 clock-names = <<
2043 assigned-cloc <<
2044 assigned-cloc <<
2045 power-domains <<
2046 }; <<
2047 }; <<
2048 <<
2049 larb4: smi@1602e000 { 1235 larb4: smi@1602e000 {
2050 compatible = "mediate 1236 compatible = "mediatek,mt8186-smi-larb";
2051 reg = <0 0x1602e000 0 1237 reg = <0 0x1602e000 0 0x1000>;
2052 clocks = <&vdecsys CL 1238 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
2053 <&vdecsys CL 1239 <&vdecsys CLK_VDEC_LARB1_CKEN>;
2054 clock-names = "apb", 1240 clock-names = "apb", "smi";
2055 mediatek,larb-id = <4 1241 mediatek,larb-id = <4>;
2056 mediatek,smi = <&smi_ 1242 mediatek,smi = <&smi_common>;
2057 power-domains = <&spm 1243 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2058 }; 1244 };
2059 1245
2060 vdecsys: clock-controller@160 1246 vdecsys: clock-controller@1602f000 {
2061 compatible = "mediate 1247 compatible = "mediatek,mt8186-vdecsys";
2062 reg = <0 0x1602f000 0 1248 reg = <0 0x1602f000 0 0x1000>;
2063 #clock-cells = <1>; 1249 #clock-cells = <1>;
2064 }; 1250 };
2065 1251
2066 vencsys: clock-controller@170 1252 vencsys: clock-controller@17000000 {
2067 compatible = "mediate 1253 compatible = "mediatek,mt8186-vencsys";
2068 reg = <0 0x17000000 0 1254 reg = <0 0x17000000 0 0x1000>;
2069 #clock-cells = <1>; 1255 #clock-cells = <1>;
2070 }; 1256 };
2071 1257
2072 larb7: smi@17010000 { 1258 larb7: smi@17010000 {
2073 compatible = "mediate 1259 compatible = "mediatek,mt8186-smi-larb";
2074 reg = <0 0x17010000 0 1260 reg = <0 0x17010000 0 0x1000>;
2075 clocks = <&vencsys CL 1261 clocks = <&vencsys CLK_VENC_CKE1_VENC>,
2076 <&vencsys CL 1262 <&vencsys CLK_VENC_CKE1_VENC>;
2077 clock-names = "apb", 1263 clock-names = "apb", "smi";
2078 mediatek,larb-id = <7 1264 mediatek,larb-id = <7>;
2079 mediatek,smi = <&smi_ 1265 mediatek,smi = <&smi_common>;
2080 power-domains = <&spm 1266 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2081 }; 1267 };
2082 1268
2083 venc: video-encoder@17020000 <<
2084 compatible = "mediate <<
2085 reg = <0 0x17020000 0 <<
2086 interrupts = <GIC_SPI <<
2087 iommus = <&iommu_mm I <<
2088 <&iommu_mm I <<
2089 <&iommu_mm I <<
2090 <&iommu_mm I <<
2091 <&iommu_mm I <<
2092 <&iommu_mm I <<
2093 <&iommu_mm I <<
2094 <&iommu_mm I <<
2095 <&iommu_mm I <<
2096 clocks = <&vencsys CL <<
2097 clock-names = "venc_s <<
2098 assigned-clocks = <&t <<
2099 assigned-clock-parent <<
2100 power-domains = <&spm <<
2101 mediatek,scp = <&scp> <<
2102 }; <<
2103 <<
2104 jpgenc: jpeg-encoder@17030000 <<
2105 compatible = "mediate <<
2106 reg = <0 0x17030000 0 <<
2107 interrupts = <GIC_SPI <<
2108 clocks = <&vencsys CL <<
2109 clock-names = "jpgenc <<
2110 iommus = <&iommu_mm I <<
2111 <&iommu_mm I <<
2112 <&iommu_mm I <<
2113 <&iommu_mm I <<
2114 power-domains = <&spm <<
2115 }; <<
2116 <<
2117 camsys: clock-controller@1a00 1269 camsys: clock-controller@1a000000 {
2118 compatible = "mediate 1270 compatible = "mediatek,mt8186-camsys";
2119 reg = <0 0x1a000000 0 1271 reg = <0 0x1a000000 0 0x1000>;
2120 #clock-cells = <1>; 1272 #clock-cells = <1>;
2121 }; 1273 };
2122 1274
2123 larb13: smi@1a001000 { 1275 larb13: smi@1a001000 {
2124 compatible = "mediate 1276 compatible = "mediatek,mt8186-smi-larb";
2125 reg = <0 0x1a001000 0 1277 reg = <0 0x1a001000 0 0x1000>;
2126 clocks = <&camsys CLK 1278 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
2127 clock-names = "apb", 1279 clock-names = "apb", "smi";
2128 mediatek,larb-id = <1 1280 mediatek,larb-id = <13>;
2129 mediatek,smi = <&smi_ 1281 mediatek,smi = <&smi_common>;
2130 power-domains = <&spm 1282 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2131 }; 1283 };
2132 1284
2133 larb14: smi@1a002000 { 1285 larb14: smi@1a002000 {
2134 compatible = "mediate 1286 compatible = "mediatek,mt8186-smi-larb";
2135 reg = <0 0x1a002000 0 1287 reg = <0 0x1a002000 0 0x1000>;
2136 clocks = <&camsys CLK 1288 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
2137 clock-names = "apb", 1289 clock-names = "apb", "smi";
2138 mediatek,larb-id = <1 1290 mediatek,larb-id = <14>;
2139 mediatek,smi = <&smi_ 1291 mediatek,smi = <&smi_common>;
2140 power-domains = <&spm 1292 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2141 }; 1293 };
2142 1294
2143 larb16: smi@1a00f000 { 1295 larb16: smi@1a00f000 {
2144 compatible = "mediate 1296 compatible = "mediatek,mt8186-smi-larb";
2145 reg = <0 0x1a00f000 0 1297 reg = <0 0x1a00f000 0 0x1000>;
2146 clocks = <&camsys CLK 1298 clocks = <&camsys CLK_CAM_LARB14>,
2147 <&camsys_raw 1299 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
2148 clock-names = "apb", 1300 clock-names = "apb", "smi";
2149 mediatek,larb-id = <1 1301 mediatek,larb-id = <16>;
2150 mediatek,smi = <&smi_ 1302 mediatek,smi = <&smi_common>;
2151 power-domains = <&spm 1303 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2152 }; 1304 };
2153 1305
2154 larb17: smi@1a010000 { 1306 larb17: smi@1a010000 {
2155 compatible = "mediate 1307 compatible = "mediatek,mt8186-smi-larb";
2156 reg = <0 0x1a010000 0 1308 reg = <0 0x1a010000 0 0x1000>;
2157 clocks = <&camsys CLK 1309 clocks = <&camsys CLK_CAM_LARB13>,
2158 <&camsys_raw 1310 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
2159 clock-names = "apb", 1311 clock-names = "apb", "smi";
2160 mediatek,larb-id = <1 1312 mediatek,larb-id = <17>;
2161 mediatek,smi = <&smi_ 1313 mediatek,smi = <&smi_common>;
2162 power-domains = <&spm 1314 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2163 }; 1315 };
2164 1316
2165 camsys_rawa: clock-controller 1317 camsys_rawa: clock-controller@1a04f000 {
2166 compatible = "mediate 1318 compatible = "mediatek,mt8186-camsys_rawa";
2167 reg = <0 0x1a04f000 0 1319 reg = <0 0x1a04f000 0 0x1000>;
2168 #clock-cells = <1>; 1320 #clock-cells = <1>;
2169 }; 1321 };
2170 1322
2171 camsys_rawb: clock-controller 1323 camsys_rawb: clock-controller@1a06f000 {
2172 compatible = "mediate 1324 compatible = "mediatek,mt8186-camsys_rawb";
2173 reg = <0 0x1a06f000 0 1325 reg = <0 0x1a06f000 0 0x1000>;
2174 #clock-cells = <1>; 1326 #clock-cells = <1>;
2175 }; 1327 };
2176 1328
2177 mdpsys: clock-controller@1b00 1329 mdpsys: clock-controller@1b000000 {
2178 compatible = "mediate 1330 compatible = "mediatek,mt8186-mdpsys";
2179 reg = <0 0x1b000000 0 1331 reg = <0 0x1b000000 0 0x1000>;
2180 #clock-cells = <1>; 1332 #clock-cells = <1>;
2181 }; 1333 };
2182 1334
2183 larb2: smi@1b002000 { 1335 larb2: smi@1b002000 {
2184 compatible = "mediate 1336 compatible = "mediatek,mt8186-smi-larb";
2185 reg = <0 0x1b002000 0 1337 reg = <0 0x1b002000 0 0x1000>;
2186 clocks = <&mdpsys CLK 1338 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
2187 clock-names = "apb", 1339 clock-names = "apb", "smi";
2188 mediatek,larb-id = <2 1340 mediatek,larb-id = <2>;
2189 mediatek,smi = <&smi_ 1341 mediatek,smi = <&smi_common>;
2190 power-domains = <&spm 1342 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2191 }; 1343 };
2192 1344
2193 ipesys: clock-controller@1c00 1345 ipesys: clock-controller@1c000000 {
2194 compatible = "mediate 1346 compatible = "mediatek,mt8186-ipesys";
2195 reg = <0 0x1c000000 0 1347 reg = <0 0x1c000000 0 0x1000>;
2196 #clock-cells = <1>; 1348 #clock-cells = <1>;
2197 }; 1349 };
2198 1350
2199 larb20: smi@1c00f000 { 1351 larb20: smi@1c00f000 {
2200 compatible = "mediate 1352 compatible = "mediatek,mt8186-smi-larb";
2201 reg = <0 0x1c00f000 0 1353 reg = <0 0x1c00f000 0 0x1000>;
2202 clocks = <&ipesys CLK 1354 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
2203 clock-names = "apb", 1355 clock-names = "apb", "smi";
2204 mediatek,larb-id = <2 1356 mediatek,larb-id = <20>;
2205 mediatek,smi = <&smi_ 1357 mediatek,smi = <&smi_common>;
2206 power-domains = <&spm 1358 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2207 }; 1359 };
2208 1360
2209 larb19: smi@1c10f000 { 1361 larb19: smi@1c10f000 {
2210 compatible = "mediate 1362 compatible = "mediatek,mt8186-smi-larb";
2211 reg = <0 0x1c10f000 0 1363 reg = <0 0x1c10f000 0 0x1000>;
2212 clocks = <&ipesys CLK 1364 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
2213 clock-names = "apb", 1365 clock-names = "apb", "smi";
2214 mediatek,larb-id = <1 1366 mediatek,larb-id = <19>;
2215 mediatek,smi = <&smi_ 1367 mediatek,smi = <&smi_common>;
2216 power-domains = <&spm 1368 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2217 }; <<
2218 }; <<
2219 <<
2220 thermal_zones: thermal-zones { <<
2221 cpu-little0-thermal { <<
2222 polling-delay = <1000 <<
2223 polling-delay-passive <<
2224 thermal-sensors = <&l <<
2225 <<
2226 trips { <<
2227 cpu_little0_a <<
2228 tempe <<
2229 hyste <<
2230 type <<
2231 }; <<
2232 <<
2233 cpu_little0_a <<
2234 tempe <<
2235 hyste <<
2236 type <<
2237 }; <<
2238 <<
2239 cpu_little0_c <<
2240 tempe <<
2241 hyste <<
2242 type <<
2243 }; <<
2244 }; <<
2245 <<
2246 cooling-maps { <<
2247 map0 { <<
2248 trip <<
2249 cooli <<
2250 <<
2251 <<
2252 <<
2253 <<
2254 <<
2255 }; <<
2256 }; <<
2257 }; <<
2258 <<
2259 cpu-little1-thermal { <<
2260 polling-delay = <1000 <<
2261 polling-delay-passive <<
2262 thermal-sensors = <&l <<
2263 <<
2264 trips { <<
2265 cpu_little1_a <<
2266 tempe <<
2267 hyste <<
2268 type <<
2269 }; <<
2270 <<
2271 cpu_little1_a <<
2272 tempe <<
2273 hyste <<
2274 type <<
2275 }; <<
2276 <<
2277 cpu_little1_c <<
2278 tempe <<
2279 hyste <<
2280 type <<
2281 }; <<
2282 }; <<
2283 <<
2284 cooling-maps { <<
2285 map0 { <<
2286 trip <<
2287 cooli <<
2288 <<
2289 <<
2290 <<
2291 <<
2292 <<
2293 }; <<
2294 }; <<
2295 }; <<
2296 <<
2297 cpu-little2-thermal { <<
2298 polling-delay = <1000 <<
2299 polling-delay-passive <<
2300 thermal-sensors = <&l <<
2301 <<
2302 trips { <<
2303 cpu_little2_a <<
2304 tempe <<
2305 hyste <<
2306 type <<
2307 }; <<
2308 <<
2309 cpu_little2_a <<
2310 tempe <<
2311 hyste <<
2312 type <<
2313 }; <<
2314 <<
2315 cpu_little2_c <<
2316 tempe <<
2317 hyste <<
2318 type <<
2319 }; <<
2320 }; <<
2321 <<
2322 cooling-maps { <<
2323 map0 { <<
2324 trip <<
2325 cooli <<
2326 <<
2327 <<
2328 <<
2329 <<
2330 <<
2331 }; <<
2332 }; <<
2333 }; <<
2334 <<
2335 cam-thermal { <<
2336 polling-delay = <1000 <<
2337 polling-delay-passive <<
2338 thermal-sensors = <&l <<
2339 <<
2340 trips { <<
2341 cam_alert0: t <<
2342 tempe <<
2343 hyste <<
2344 type <<
2345 }; <<
2346 <<
2347 cam_alert1: t <<
2348 tempe <<
2349 hyste <<
2350 type <<
2351 }; <<
2352 <<
2353 cam_crit: tri <<
2354 tempe <<
2355 hyste <<
2356 type <<
2357 }; <<
2358 }; <<
2359 }; <<
2360 <<
2361 nna-thermal { <<
2362 polling-delay = <1000 <<
2363 polling-delay-passive <<
2364 thermal-sensors = <&l <<
2365 <<
2366 trips { <<
2367 nna_alert0: t <<
2368 tempe <<
2369 hyste <<
2370 type <<
2371 }; <<
2372 <<
2373 nna_alert1: t <<
2374 tempe <<
2375 hyste <<
2376 type <<
2377 }; <<
2378 <<
2379 nna_crit: tri <<
2380 tempe <<
2381 hyste <<
2382 type <<
2383 }; <<
2384 }; <<
2385 }; <<
2386 <<
2387 adsp-thermal { <<
2388 polling-delay = <1000 <<
2389 polling-delay-passive <<
2390 thermal-sensors = <&l <<
2391 <<
2392 trips { <<
2393 adsp_alert0: <<
2394 tempe <<
2395 hyste <<
2396 type <<
2397 }; <<
2398 <<
2399 adsp_alert1: <<
2400 tempe <<
2401 hyste <<
2402 type <<
2403 }; <<
2404 <<
2405 adsp_crit: tr <<
2406 tempe <<
2407 hyste <<
2408 type <<
2409 }; <<
2410 }; <<
2411 }; <<
2412 <<
2413 gpu-thermal { <<
2414 polling-delay = <1000 <<
2415 polling-delay-passive <<
2416 thermal-sensors = <&l <<
2417 <<
2418 trips { <<
2419 gpu_alert0: t <<
2420 tempe <<
2421 hyste <<
2422 type <<
2423 }; <<
2424 <<
2425 gpu_alert1: t <<
2426 tempe <<
2427 hyste <<
2428 type <<
2429 }; <<
2430 <<
2431 gpu_crit: tri <<
2432 tempe <<
2433 hyste <<
2434 type <<
2435 }; <<
2436 }; <<
2437 <<
2438 cooling-maps { <<
2439 map0 { <<
2440 trip <<
2441 cooli <<
2442 }; <<
2443 }; <<
2444 }; <<
2445 <<
2446 cpu-big0-thermal { <<
2447 polling-delay = <1000 <<
2448 polling-delay-passive <<
2449 thermal-sensors = <&l <<
2450 <<
2451 trips { <<
2452 cpu_big0_aler <<
2453 tempe <<
2454 hyste <<
2455 type <<
2456 }; <<
2457 <<
2458 cpu_big0_aler <<
2459 tempe <<
2460 hyste <<
2461 type <<
2462 }; <<
2463 <<
2464 cpu_big0_crit <<
2465 tempe <<
2466 hyste <<
2467 type <<
2468 }; <<
2469 }; <<
2470 <<
2471 cooling-maps { <<
2472 map0 { <<
2473 trip <<
2474 cooli <<
2475 <<
2476 }; <<
2477 }; <<
2478 }; <<
2479 <<
2480 cpu-big1-thermal { <<
2481 polling-delay = <1000 <<
2482 polling-delay-passive <<
2483 thermal-sensors = <&l <<
2484 <<
2485 trips { <<
2486 cpu_big1_aler <<
2487 tempe <<
2488 hyste <<
2489 type <<
2490 }; <<
2491 <<
2492 cpu_big1_aler <<
2493 tempe <<
2494 hyste <<
2495 type <<
2496 }; <<
2497 <<
2498 cpu_big1_crit <<
2499 tempe <<
2500 hyste <<
2501 type <<
2502 }; <<
2503 }; <<
2504 <<
2505 cooling-maps { <<
2506 map0 { <<
2507 trip <<
2508 cooli <<
2509 <<
2510 }; <<
2511 }; <<
2512 }; 1369 };
2513 }; 1370 };
2514 }; 1371 };
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