1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2021 MediaTek Inc. 3 * Copyright (C) 2021 MediaTek Inc.
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h> <<
8 #include "mt8195.dtsi" 7 #include "mt8195.dtsi"
9 #include "mt6359.dtsi" 8 #include "mt6359.dtsi"
10 9
11 / { 10 / {
12 aliases { 11 aliases {
13 i2c0 = &i2c0; 12 i2c0 = &i2c0;
14 i2c1 = &i2c1; 13 i2c1 = &i2c1;
15 i2c2 = &i2c2; 14 i2c2 = &i2c2;
16 i2c3 = &i2c3; 15 i2c3 = &i2c3;
17 i2c4 = &i2c4; 16 i2c4 = &i2c4;
18 i2c5 = &i2c5; 17 i2c5 = &i2c5;
19 i2c7 = &i2c7; 18 i2c7 = &i2c7;
20 mmc0 = &mmc0; 19 mmc0 = &mmc0;
21 mmc1 = &mmc1; <<
22 serial0 = &uart0; 20 serial0 = &uart0;
23 }; 21 };
24 22
25 backlight_lcd0: backlight-lcd0 { <<
26 compatible = "pwm-backlight"; <<
27 brightness-levels = <0 1023>; <<
28 default-brightness-level = <57 <<
29 enable-gpios = <&pio 82 GPIO_A <<
30 num-interpolated-steps = <1023 <<
31 pwms = <&disp_pwm0 0 500000>; <<
32 power-supply = <&ppvar_sys>; <<
33 }; <<
34 <<
35 chosen { 23 chosen {
36 stdout-path = "serial0:115200n 24 stdout-path = "serial0:115200n8";
37 }; 25 };
38 26
39 dmic-codec { <<
40 compatible = "dmic-codec"; <<
41 num-channels = <2>; <<
42 wakeup-delay-ms = <50>; <<
43 }; <<
44 <<
45 memory@40000000 { 27 memory@40000000 {
46 device_type = "memory"; 28 device_type = "memory";
47 reg = <0 0x40000000 0 0x800000 29 reg = <0 0x40000000 0 0x80000000>;
48 }; 30 };
49 31
50 pp3300_disp_x: regulator-pp3300-disp-x <<
51 compatible = "regulator-fixed" <<
52 regulator-name = "pp3300_disp_ <<
53 regulator-min-microvolt = <330 <<
54 regulator-max-microvolt = <330 <<
55 regulator-enable-ramp-delay = <<
56 enable-active-high; <<
57 gpio = <&pio 55 GPIO_ACTIVE_HI <<
58 pinctrl-names = "default"; <<
59 pinctrl-0 = <&panel_fixed_pins <<
60 vin-supply = <&pp3300_z2>; <<
61 }; <<
62 <<
63 /* system wide LDO 3.3V power rail */ 32 /* system wide LDO 3.3V power rail */
64 pp3300_z5: regulator-pp3300-ldo-z5 { 33 pp3300_z5: regulator-pp3300-ldo-z5 {
65 compatible = "regulator-fixed" 34 compatible = "regulator-fixed";
66 regulator-name = "pp3300_ldo_z 35 regulator-name = "pp3300_ldo_z5";
67 regulator-always-on; 36 regulator-always-on;
68 regulator-boot-on; 37 regulator-boot-on;
69 regulator-min-microvolt = <330 38 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <330 39 regulator-max-microvolt = <3300000>;
71 vin-supply = <&ppvar_sys>; 40 vin-supply = <&ppvar_sys>;
72 }; 41 };
73 42
74 /* separately switched 3.3V power rail 43 /* separately switched 3.3V power rail */
75 pp3300_s3: regulator-pp3300-s3 { 44 pp3300_s3: regulator-pp3300-s3 {
76 compatible = "regulator-fixed" 45 compatible = "regulator-fixed";
77 regulator-name = "pp3300_s3"; 46 regulator-name = "pp3300_s3";
78 /* automatically sequenced by 47 /* automatically sequenced by PMIC EXT_PMIC_EN2 */
79 regulator-always-on; 48 regulator-always-on;
80 regulator-boot-on; 49 regulator-boot-on;
81 regulator-min-microvolt = <330 50 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <330 51 regulator-max-microvolt = <3300000>;
83 vin-supply = <&pp3300_z2>; 52 vin-supply = <&pp3300_z2>;
84 }; 53 };
85 54
86 /* system wide 3.3V power rail */ 55 /* system wide 3.3V power rail */
87 pp3300_z2: regulator-pp3300-z2 { 56 pp3300_z2: regulator-pp3300-z2 {
88 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
89 regulator-name = "pp3300_z2"; 58 regulator-name = "pp3300_z2";
90 /* EN pin tied to pp4200_z2, w 59 /* EN pin tied to pp4200_z2, which is controlled by EC */
91 regulator-always-on; 60 regulator-always-on;
92 regulator-boot-on; 61 regulator-boot-on;
93 regulator-min-microvolt = <330 62 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <330 63 regulator-max-microvolt = <3300000>;
95 vin-supply = <&ppvar_sys>; 64 vin-supply = <&ppvar_sys>;
96 }; 65 };
97 66
98 /* system wide 4.2V power rail */ 67 /* system wide 4.2V power rail */
99 pp4200_z2: regulator-pp4200-z2 { 68 pp4200_z2: regulator-pp4200-z2 {
100 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
101 regulator-name = "pp4200_z2"; 70 regulator-name = "pp4200_z2";
102 /* controlled by EC */ 71 /* controlled by EC */
103 regulator-always-on; 72 regulator-always-on;
104 regulator-boot-on; 73 regulator-boot-on;
105 regulator-min-microvolt = <420 74 regulator-min-microvolt = <4200000>;
106 regulator-max-microvolt = <420 75 regulator-max-microvolt = <4200000>;
107 vin-supply = <&ppvar_sys>; 76 vin-supply = <&ppvar_sys>;
108 }; 77 };
109 78
110 /* system wide switching 5.0V power ra 79 /* system wide switching 5.0V power rail */
111 pp5000_s5: regulator-pp5000-s5 { 80 pp5000_s5: regulator-pp5000-s5 {
112 compatible = "regulator-fixed" 81 compatible = "regulator-fixed";
113 regulator-name = "pp5000_s5"; 82 regulator-name = "pp5000_s5";
114 /* controlled by EC */ 83 /* controlled by EC */
115 regulator-always-on; 84 regulator-always-on;
116 regulator-boot-on; 85 regulator-boot-on;
117 regulator-min-microvolt = <500 86 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <500 87 regulator-max-microvolt = <5000000>;
119 vin-supply = <&ppvar_sys>; 88 vin-supply = <&ppvar_sys>;
120 }; 89 };
121 90
122 /* system wide semi-regulated power ra 91 /* system wide semi-regulated power rail from battery or USB */
123 ppvar_sys: regulator-ppvar-sys { 92 ppvar_sys: regulator-ppvar-sys {
124 compatible = "regulator-fixed" 93 compatible = "regulator-fixed";
125 regulator-name = "ppvar_sys"; 94 regulator-name = "ppvar_sys";
126 regulator-always-on; 95 regulator-always-on;
127 regulator-boot-on; 96 regulator-boot-on;
128 }; 97 };
129 98
130 /* Murata NCP03WF104F05RL */ <<
131 tboard_thermistor1: thermal-sensor-t1 <<
132 compatible = "generic-adc-ther <<
133 #thermal-sensor-cells = <0>; <<
134 io-channels = <&auxadc 0>; <<
135 io-channel-names = "sensor-cha <<
136 temperature-lookup-table = < <<
137 <<
138 <<
139 <<
140 <<
141 <<
142 <<
143 <<
144 <<
145 <<
146 <<
147 <<
148 <<
149 <<
150 <<
151 <<
152 <<
153 <<
154 <<
155 <<
156 <<
157 <<
158 <<
159 <<
160 <<
161 <<
162 <<
163 <<
164 }; <<
165 <<
166 tboard_thermistor2: thermal-sensor-t2 <<
167 compatible = "generic-adc-ther <<
168 #thermal-sensor-cells = <0>; <<
169 io-channels = <&auxadc 1>; <<
170 io-channel-names = "sensor-cha <<
171 temperature-lookup-table = < <<
172 <<
173 <<
174 <<
175 <<
176 <<
177 <<
178 <<
179 <<
180 <<
181 <<
182 <<
183 <<
184 <<
185 <<
186 <<
187 <<
188 <<
189 <<
190 <<
191 <<
192 <<
193 <<
194 <<
195 <<
196 <<
197 <<
198 <<
199 }; <<
200 <<
201 usb_vbus: regulator-5v0-usb-vbus { 99 usb_vbus: regulator-5v0-usb-vbus {
202 compatible = "regulator-fixed" 100 compatible = "regulator-fixed";
203 regulator-name = "usb-vbus"; 101 regulator-name = "usb-vbus";
204 regulator-min-microvolt = <500 102 regulator-min-microvolt = <5000000>;
205 regulator-max-microvolt = <500 103 regulator-max-microvolt = <5000000>;
206 enable-active-high; 104 enable-active-high;
207 regulator-always-on; 105 regulator-always-on;
208 }; 106 };
209 <<
210 reserved_memory: reserved-memory { <<
211 #address-cells = <2>; <<
212 #size-cells = <2>; <<
213 ranges; <<
214 <<
215 scp_mem: memory@50000000 { <<
216 compatible = "shared-d <<
217 reg = <0 0x50000000 0 <<
218 no-map; <<
219 }; <<
220 <<
221 adsp_mem: memory@60000000 { <<
222 compatible = "shared-d <<
223 reg = <0 0x60000000 0 <<
224 no-map; <<
225 }; <<
226 <<
227 afe_mem: memory@60d80000 { <<
228 compatible = "shared-d <<
229 reg = <0 0x60d80000 0 <<
230 no-map; <<
231 }; <<
232 <<
233 adsp_device_mem: memory@60e800 <<
234 compatible = "shared-d <<
235 reg = <0 0x60e80000 0 <<
236 no-map; <<
237 }; <<
238 }; <<
239 <<
240 spk_amplifier: rt1019p { <<
241 compatible = "realtek,rt1019p" <<
242 label = "rt1019p"; <<
243 #sound-dai-cells = <0>; <<
244 pinctrl-names = "default"; <<
245 pinctrl-0 = <&rt1019p_pins_def <<
246 sdb-gpios = <&pio 100 GPIO_ACT <<
247 }; <<
248 }; <<
249 <<
250 &adsp { <<
251 status = "okay"; <<
252 <<
253 memory-region = <&adsp_device_mem>, <& <<
254 }; <<
255 <<
256 &afe { <<
257 status = "okay"; <<
258 <<
259 mediatek,etdm-in2-cowork-source = <2>; <<
260 mediatek,etdm-out2-cowork-source = <0> <<
261 memory-region = <&afe_mem>; <<
262 }; <<
263 <<
264 &auxadc { <<
265 status = "okay"; <<
266 }; <<
267 <<
268 &cpu0 { <<
269 cpu-supply = <&mt6359_vcore_buck_reg>; <<
270 }; <<
271 <<
272 &cpu1 { <<
273 cpu-supply = <&mt6359_vcore_buck_reg>; <<
274 }; <<
275 <<
276 &cpu2 { <<
277 cpu-supply = <&mt6359_vcore_buck_reg>; <<
278 }; <<
279 <<
280 &cpu3 { <<
281 cpu-supply = <&mt6359_vcore_buck_reg>; <<
282 }; <<
283 <<
284 &cpu4 { <<
285 cpu-supply = <&mt6315_6_vbuck1>; <<
286 }; <<
287 <<
288 &cpu5 { <<
289 cpu-supply = <&mt6315_6_vbuck1>; <<
290 }; <<
291 <<
292 &cpu6 { <<
293 cpu-supply = <&mt6315_6_vbuck1>; <<
294 }; <<
295 <<
296 &cpu7 { <<
297 cpu-supply = <&mt6315_6_vbuck1>; <<
298 }; <<
299 <<
300 &dp_intf0 { <<
301 status = "okay"; <<
302 <<
303 port { <<
304 dp_intf0_out: endpoint { <<
305 remote-endpoint = <&ed <<
306 }; <<
307 }; <<
308 }; <<
309 <<
310 &dp_intf1 { <<
311 status = "okay"; <<
312 <<
313 port { <<
314 dp_intf1_out: endpoint { <<
315 remote-endpoint = <&dp <<
316 }; <<
317 }; <<
318 }; <<
319 <<
320 &edp_tx { <<
321 status = "okay"; <<
322 <<
323 pinctrl-names = "default"; <<
324 pinctrl-0 = <&edptx_pins_default>; <<
325 <<
326 ports { <<
327 #address-cells = <1>; <<
328 #size-cells = <0>; <<
329 <<
330 port@0 { <<
331 reg = <0>; <<
332 edp_in: endpoint { <<
333 remote-endpoin <<
334 }; <<
335 }; <<
336 <<
337 port@1 { <<
338 reg = <1>; <<
339 edp_out: endpoint { <<
340 data-lanes = < <<
341 remote-endpoin <<
342 }; <<
343 }; <<
344 }; <<
345 <<
346 aux-bus { <<
347 panel { <<
348 compatible = "edp-pane <<
349 power-supply = <&pp330 <<
350 backlight = <&backligh <<
351 port { <<
352 panel_in: endp <<
353 remote <<
354 }; <<
355 }; <<
356 }; <<
357 }; <<
358 }; <<
359 <<
360 &disp_pwm0 { <<
361 status = "okay"; <<
362 <<
363 pinctrl-names = "default"; <<
364 pinctrl-0 = <&disp_pwm0_pin_default>; <<
365 }; <<
366 <<
367 &dp_tx { <<
368 status = "okay"; <<
369 <<
370 #sound-dai-cells = <0>; <<
371 pinctrl-names = "default"; <<
372 pinctrl-0 = <&dptx_pin>; <<
373 <<
374 ports { <<
375 #address-cells = <1>; <<
376 #size-cells = <0>; <<
377 <<
378 port@0 { <<
379 reg = <0>; <<
380 dptx_in: endpoint { <<
381 remote-endpoin <<
382 }; <<
383 }; <<
384 <<
385 port@1 { <<
386 reg = <1>; <<
387 dptx_out: endpoint { <<
388 data-lanes = < <<
389 }; <<
390 }; <<
391 }; <<
392 }; <<
393 <<
394 &gic { <<
395 mediatek,broken-save-restore-fw; <<
396 }; <<
397 <<
398 &gpu { <<
399 status = "okay"; <<
400 mali-supply = <&mt6315_7_vbuck1>; <<
401 }; 107 };
402 108
403 &i2c0 { 109 &i2c0 {
404 status = "okay"; 110 status = "okay";
405 111
406 clock-frequency = <400000>; 112 clock-frequency = <400000>;
407 pinctrl-names = "default"; 113 pinctrl-names = "default";
408 pinctrl-0 = <&i2c0_pins>; 114 pinctrl-0 = <&i2c0_pins>;
409 }; 115 };
410 116
411 &i2c1 { 117 &i2c1 {
412 status = "okay"; 118 status = "okay";
413 119
414 clock-frequency = <400000>; 120 clock-frequency = <400000>;
415 i2c-scl-internal-delay-ns = <12500>; 121 i2c-scl-internal-delay-ns = <12500>;
416 pinctrl-names = "default"; 122 pinctrl-names = "default";
417 pinctrl-0 = <&i2c1_pins>; 123 pinctrl-0 = <&i2c1_pins>;
418 <<
419 trackpad@15 { <<
420 compatible = "elan,ekth3000"; <<
421 reg = <0x15>; <<
422 interrupts-extended = <&pio 6 <<
423 pinctrl-names = "default"; <<
424 pinctrl-0 = <&trackpad_pins>; <<
425 vcc-supply = <&pp3300_s3>; <<
426 wakeup-source; <<
427 }; <<
428 }; 124 };
429 125
430 &i2c2 { 126 &i2c2 {
431 status = "okay"; 127 status = "okay";
432 128
433 clock-frequency = <400000>; 129 clock-frequency = <400000>;
434 pinctrl-names = "default"; 130 pinctrl-names = "default";
435 pinctrl-0 = <&i2c2_pins>; 131 pinctrl-0 = <&i2c2_pins>;
436 <<
437 audio_codec: codec@1a { <<
438 /* Realtek RT5682i or RT5682s, <<
439 reg = <0x1a>; <<
440 interrupts-extended = <&pio 89 <<
441 #sound-dai-cells = <0>; <<
442 realtek,jd-src = <1>; <<
443 <<
444 AVDD-supply = <&mt6359_vio18_l <<
445 MICVDD-supply = <&pp3300_z2>; <<
446 VBAT-supply = <&pp3300_z5>; <<
447 }; <<
448 }; 132 };
449 133
450 &i2c3 { 134 &i2c3 {
451 status = "okay"; 135 status = "okay";
452 136
453 clock-frequency = <400000>; 137 clock-frequency = <400000>;
454 pinctrl-names = "default"; 138 pinctrl-names = "default";
455 pinctrl-0 = <&i2c3_pins>; 139 pinctrl-0 = <&i2c3_pins>;
456 <<
457 tpm@50 { <<
458 compatible = "google,cr50"; <<
459 reg = <0x50>; <<
460 interrupts-extended = <&pio 88 <<
461 pinctrl-names = "default"; <<
462 pinctrl-0 = <&cr50_int>; <<
463 }; <<
464 }; 140 };
465 141
466 &i2c4 { 142 &i2c4 {
467 status = "okay"; 143 status = "okay";
468 144
469 clock-frequency = <400000>; 145 clock-frequency = <400000>;
470 pinctrl-names = "default"; 146 pinctrl-names = "default";
471 pinctrl-0 = <&i2c4_pins>; 147 pinctrl-0 = <&i2c4_pins>;
472 148
473 ts_10: touchscreen@10 { 149 ts_10: touchscreen@10 {
474 compatible = "hid-over-i2c"; 150 compatible = "hid-over-i2c";
475 reg = <0x10>; 151 reg = <0x10>;
476 hid-descr-addr = <0x0001>; 152 hid-descr-addr = <0x0001>;
477 interrupts-extended = <&pio 92 153 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
478 pinctrl-names = "default"; 154 pinctrl-names = "default";
479 pinctrl-0 = <&touchscreen_pins 155 pinctrl-0 = <&touchscreen_pins>;
480 post-power-on-delay-ms = <10>; 156 post-power-on-delay-ms = <10>;
481 vdd-supply = <&pp3300_s3>; 157 vdd-supply = <&pp3300_s3>;
482 status = "disabled"; 158 status = "disabled";
483 }; 159 };
484 }; 160 };
485 161
486 &i2c5 { 162 &i2c5 {
487 status = "okay"; 163 status = "okay";
488 164
489 clock-frequency = <400000>; 165 clock-frequency = <400000>;
490 pinctrl-names = "default"; 166 pinctrl-names = "default";
491 pinctrl-0 = <&i2c5_pins>; 167 pinctrl-0 = <&i2c5_pins>;
492 }; 168 };
493 169
494 &i2c7 { 170 &i2c7 {
495 status = "okay"; 171 status = "okay";
496 172
497 clock-frequency = <400000>; 173 clock-frequency = <400000>;
498 pinctrl-names = "default"; 174 pinctrl-names = "default";
499 pinctrl-0 = <&i2c7_pins>; 175 pinctrl-0 = <&i2c7_pins>;
500 176
501 pmic@34 { 177 pmic@34 {
502 #interrupt-cells = <2>; !! 178 #interrupt-cells = <1>;
503 compatible = "mediatek,mt6360" 179 compatible = "mediatek,mt6360";
504 reg = <0x34>; 180 reg = <0x34>;
505 interrupt-controller; 181 interrupt-controller;
506 interrupts-extended = <&pio 13 182 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
507 interrupt-names = "IRQB"; 183 interrupt-names = "IRQB";
508 pinctrl-names = "default"; 184 pinctrl-names = "default";
509 pinctrl-0 = <&subpmic_default> 185 pinctrl-0 = <&subpmic_default>;
510 wakeup-source; 186 wakeup-source;
511 }; 187 };
512 }; 188 };
513 189
514 &mfg0 { <<
515 domain-supply = <&mt6315_7_vbuck1>; <<
516 }; <<
517 <<
518 &mfg1 { <<
519 domain-supply = <&mt6359_vsram_others_ <<
520 }; <<
521 <<
522 &mmc0 { 190 &mmc0 {
523 status = "okay"; 191 status = "okay";
524 192
525 bus-width = <8>; 193 bus-width = <8>;
526 cap-mmc-highspeed; 194 cap-mmc-highspeed;
527 cap-mmc-hw-reset; 195 cap-mmc-hw-reset;
528 hs400-ds-delay = <0x14c11>; 196 hs400-ds-delay = <0x14c11>;
529 max-frequency = <200000000>; 197 max-frequency = <200000000>;
530 mmc-hs200-1_8v; 198 mmc-hs200-1_8v;
531 mmc-hs400-1_8v; 199 mmc-hs400-1_8v;
532 no-sdio; 200 no-sdio;
533 no-sd; 201 no-sd;
534 non-removable; 202 non-removable;
535 pinctrl-names = "default", "state_uhs" 203 pinctrl-names = "default", "state_uhs";
536 pinctrl-0 = <&mmc0_pins_default>; 204 pinctrl-0 = <&mmc0_pins_default>;
537 pinctrl-1 = <&mmc0_pins_uhs>; 205 pinctrl-1 = <&mmc0_pins_uhs>;
538 vmmc-supply = <&mt6359_vemc_1_ldo_reg> 206 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
539 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 207 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
540 }; 208 };
541 209
542 &mmc1 { <<
543 status = "okay"; <<
544 <<
545 bus-width = <4>; <<
546 cap-sd-highspeed; <<
547 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; <<
548 max-frequency = <200000000>; <<
549 no-mmc; <<
550 no-sdio; <<
551 pinctrl-names = "default", "state_uhs" <<
552 pinctrl-0 = <&mmc1_pins_default>, <&mm <<
553 pinctrl-1 = <&mmc1_pins_default>; <<
554 sd-uhs-sdr50; <<
555 sd-uhs-sdr104; <<
556 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; <<
557 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; <<
558 }; <<
559 <<
560 &mt6359codec { <<
561 mediatek,dmic-mode = <1>; /* one-wire <<
562 mediatek,mic-type-0 = <2>; /* DMIC */ <<
563 }; <<
564 <<
565 /* for CPU-L */ 210 /* for CPU-L */
566 &mt6359_vcore_buck_reg { 211 &mt6359_vcore_buck_reg {
567 regulator-always-on; 212 regulator-always-on;
568 }; 213 };
569 214
570 /* for CORE */ 215 /* for CORE */
571 &mt6359_vgpu11_buck_reg { 216 &mt6359_vgpu11_buck_reg {
572 regulator-always-on; 217 regulator-always-on;
573 }; 218 };
574 219
575 &mt6359_vgpu11_sshub_buck_reg { 220 &mt6359_vgpu11_sshub_buck_reg {
576 regulator-always-on; 221 regulator-always-on;
577 regulator-min-microvolt = <550000>; 222 regulator-min-microvolt = <550000>;
578 regulator-max-microvolt = <550000>; 223 regulator-max-microvolt = <550000>;
579 }; 224 };
580 225
581 /* for CORE SRAM */ 226 /* for CORE SRAM */
582 &mt6359_vpu_buck_reg { 227 &mt6359_vpu_buck_reg {
583 regulator-always-on; 228 regulator-always-on;
584 }; 229 };
585 230
586 &mt6359_vrf12_ldo_reg { 231 &mt6359_vrf12_ldo_reg {
587 regulator-always-on; 232 regulator-always-on;
588 }; 233 };
589 234
590 /* for GPU SRAM */ 235 /* for GPU SRAM */
591 &mt6359_vsram_others_ldo_reg { 236 &mt6359_vsram_others_ldo_reg {
>> 237 regulator-always-on;
592 regulator-min-microvolt = <750000>; 238 regulator-min-microvolt = <750000>;
593 regulator-max-microvolt = <750000>; 239 regulator-max-microvolt = <750000>;
594 }; 240 };
595 241
596 &mt6359_vufs_ldo_reg { 242 &mt6359_vufs_ldo_reg {
597 regulator-always-on; 243 regulator-always-on;
598 }; 244 };
599 245
600 &nor_flash { 246 &nor_flash {
601 status = "okay"; 247 status = "okay";
602 248
603 pinctrl-names = "default"; 249 pinctrl-names = "default";
604 pinctrl-0 = <&nor_pins_default>; 250 pinctrl-0 = <&nor_pins_default>;
605 251
606 flash@0 { 252 flash@0 {
607 compatible = "jedec,spi-nor"; 253 compatible = "jedec,spi-nor";
608 reg = <0>; 254 reg = <0>;
609 spi-max-frequency = <52000000> 255 spi-max-frequency = <52000000>;
610 spi-rx-bus-width = <2>; 256 spi-rx-bus-width = <2>;
611 spi-tx-bus-width = <2>; 257 spi-tx-bus-width = <2>;
612 }; 258 };
613 }; 259 };
614 260
615 &pcie1 { <<
616 status = "okay"; <<
617 <<
618 pinctrl-names = "default"; <<
619 pinctrl-0 = <&pcie1_pins_default>; <<
620 }; <<
621 <<
622 &pio { 261 &pio {
623 mediatek,rsel-resistance-in-si-unit; 262 mediatek,rsel-resistance-in-si-unit;
624 pinctrl-names = "default"; 263 pinctrl-names = "default";
625 pinctrl-0 = <&pio_default>; 264 pinctrl-0 = <&pio_default>;
626 265
627 /* 144 lines */ 266 /* 144 lines */
628 gpio-line-names = 267 gpio-line-names =
629 "I2S_SPKR_MCLK", 268 "I2S_SPKR_MCLK",
630 "I2S_SPKR_DATAIN", 269 "I2S_SPKR_DATAIN",
631 "I2S_SPKR_LRCK", 270 "I2S_SPKR_LRCK",
632 "I2S_SPKR_BCLK", 271 "I2S_SPKR_BCLK",
633 "EC_AP_INT_ODL", 272 "EC_AP_INT_ODL",
634 /* 273 /*
635 * AP_FLASH_WP_L is crossystem 274 * AP_FLASH_WP_L is crossystem ABI. Schematics
636 * call it AP_FLASH_WP_ODL. 275 * call it AP_FLASH_WP_ODL.
637 */ 276 */
638 "AP_FLASH_WP_L", 277 "AP_FLASH_WP_L",
639 "TCHPAD_INT_ODL", 278 "TCHPAD_INT_ODL",
640 "EDP_HPD_1V8", 279 "EDP_HPD_1V8",
641 "AP_I2C_CAM_SDA", 280 "AP_I2C_CAM_SDA",
642 "AP_I2C_CAM_SCL", 281 "AP_I2C_CAM_SCL",
643 "AP_I2C_TCHPAD_SDA_1V8", 282 "AP_I2C_TCHPAD_SDA_1V8",
644 "AP_I2C_TCHPAD_SCL_1V8", 283 "AP_I2C_TCHPAD_SCL_1V8",
645 "AP_I2C_AUD_SDA", 284 "AP_I2C_AUD_SDA",
646 "AP_I2C_AUD_SCL", 285 "AP_I2C_AUD_SCL",
647 "AP_I2C_TPM_SDA_1V8", 286 "AP_I2C_TPM_SDA_1V8",
648 "AP_I2C_TPM_SCL_1V8", 287 "AP_I2C_TPM_SCL_1V8",
649 "AP_I2C_TCHSCR_SDA_1V8", 288 "AP_I2C_TCHSCR_SDA_1V8",
650 "AP_I2C_TCHSCR_SCL_1V8", 289 "AP_I2C_TCHSCR_SCL_1V8",
651 "EC_AP_HPD_OD", 290 "EC_AP_HPD_OD",
652 "", 291 "",
653 "PCIE_NVME_RST_L", 292 "PCIE_NVME_RST_L",
654 "PCIE_NVME_CLKREQ_ODL", 293 "PCIE_NVME_CLKREQ_ODL",
655 "PCIE_RST_1V8_L", 294 "PCIE_RST_1V8_L",
656 "PCIE_CLKREQ_1V8_ODL", 295 "PCIE_CLKREQ_1V8_ODL",
657 "PCIE_WAKE_1V8_ODL", 296 "PCIE_WAKE_1V8_ODL",
658 "CLK_24M_CAM0", 297 "CLK_24M_CAM0",
659 "CAM1_SEN_EN", 298 "CAM1_SEN_EN",
660 "AP_I2C_PWR_SCL_1V8", 299 "AP_I2C_PWR_SCL_1V8",
661 "AP_I2C_PWR_SDA_1V8", 300 "AP_I2C_PWR_SDA_1V8",
662 "AP_I2C_MISC_SCL", 301 "AP_I2C_MISC_SCL",
663 "AP_I2C_MISC_SDA", 302 "AP_I2C_MISC_SDA",
664 "EN_PP5000_HDMI_X", 303 "EN_PP5000_HDMI_X",
665 "AP_HDMITX_HTPLG", 304 "AP_HDMITX_HTPLG",
666 "", 305 "",
667 "AP_HDMITX_SCL_1V8", 306 "AP_HDMITX_SCL_1V8",
668 "AP_HDMITX_SDA_1V8", 307 "AP_HDMITX_SDA_1V8",
669 "AP_RTC_CLK32K", 308 "AP_RTC_CLK32K",
670 "AP_EC_WATCHDOG_L", 309 "AP_EC_WATCHDOG_L",
671 "SRCLKENA0", 310 "SRCLKENA0",
672 "SRCLKENA1", 311 "SRCLKENA1",
673 "PWRAP_SPI0_CS_L", 312 "PWRAP_SPI0_CS_L",
674 "PWRAP_SPI0_CK", 313 "PWRAP_SPI0_CK",
675 "PWRAP_SPI0_MOSI", 314 "PWRAP_SPI0_MOSI",
676 "PWRAP_SPI0_MISO", 315 "PWRAP_SPI0_MISO",
677 "SPMI_SCL", 316 "SPMI_SCL",
678 "SPMI_SDA", 317 "SPMI_SDA",
679 "", 318 "",
680 "", 319 "",
681 "", 320 "",
682 "I2S_HP_DATAIN", 321 "I2S_HP_DATAIN",
683 "I2S_HP_MCLK", 322 "I2S_HP_MCLK",
684 "I2S_HP_BCK", 323 "I2S_HP_BCK",
685 "I2S_HP_LRCK", 324 "I2S_HP_LRCK",
686 "I2S_HP_DATAOUT", 325 "I2S_HP_DATAOUT",
687 "SD_CD_ODL", 326 "SD_CD_ODL",
688 "EN_PP3300_DISP_X", 327 "EN_PP3300_DISP_X",
689 "TCHSCR_RST_1V8_L", 328 "TCHSCR_RST_1V8_L",
690 "TCHSCR_REPORT_DISABLE", 329 "TCHSCR_REPORT_DISABLE",
691 "EN_PP3300_WLAN_X", 330 "EN_PP3300_WLAN_X",
692 "BT_KILL_1V8_L", 331 "BT_KILL_1V8_L",
693 "I2S_SPKR_DATAOUT", 332 "I2S_SPKR_DATAOUT",
694 "WIFI_KILL_1V8_L", 333 "WIFI_KILL_1V8_L",
695 "BEEP_ON", 334 "BEEP_ON",
696 "SCP_I2C_SENSOR_SCL_1V8", 335 "SCP_I2C_SENSOR_SCL_1V8",
697 "SCP_I2C_SENSOR_SDA_1V8", 336 "SCP_I2C_SENSOR_SDA_1V8",
698 "", 337 "",
699 "", 338 "",
700 "", 339 "",
701 "", 340 "",
702 "AUD_CLK_MOSI", 341 "AUD_CLK_MOSI",
703 "AUD_SYNC_MOSI", 342 "AUD_SYNC_MOSI",
704 "AUD_DAT_MOSI0", 343 "AUD_DAT_MOSI0",
705 "AUD_DAT_MOSI1", 344 "AUD_DAT_MOSI1",
706 "AUD_DAT_MISO0", 345 "AUD_DAT_MISO0",
707 "AUD_DAT_MISO1", 346 "AUD_DAT_MISO1",
708 "AUD_DAT_MISO2", 347 "AUD_DAT_MISO2",
709 "SCP_VREQ_VAO", 348 "SCP_VREQ_VAO",
710 "AP_SPI_GSC_TPM_CLK", 349 "AP_SPI_GSC_TPM_CLK",
711 "AP_SPI_GSC_TPM_MOSI", 350 "AP_SPI_GSC_TPM_MOSI",
712 "AP_SPI_GSC_TPM_CS_L", 351 "AP_SPI_GSC_TPM_CS_L",
713 "AP_SPI_GSC_TPM_MISO", 352 "AP_SPI_GSC_TPM_MISO",
714 "EN_PP1000_CAM_X", 353 "EN_PP1000_CAM_X",
715 "AP_EDP_BKLTEN", 354 "AP_EDP_BKLTEN",
716 "", 355 "",
717 "USB3_HUB_RST_L", 356 "USB3_HUB_RST_L",
718 "", 357 "",
719 "WLAN_ALERT_ODL", 358 "WLAN_ALERT_ODL",
720 "EC_IN_RW_ODL", 359 "EC_IN_RW_ODL",
721 "GSC_AP_INT_ODL", 360 "GSC_AP_INT_ODL",
722 "HP_INT_ODL", 361 "HP_INT_ODL",
723 "CAM0_RST_L", 362 "CAM0_RST_L",
724 "CAM1_RST_L", 363 "CAM1_RST_L",
725 "TCHSCR_INT_1V8_L", 364 "TCHSCR_INT_1V8_L",
726 "CAM1_DET_L", 365 "CAM1_DET_L",
727 "RST_ALC1011_L", 366 "RST_ALC1011_L",
728 "", 367 "",
729 "", 368 "",
730 "BL_PWM_1V8", 369 "BL_PWM_1V8",
731 "UART_AP_TX_DBG_RX", 370 "UART_AP_TX_DBG_RX",
732 "UART_DBG_TX_AP_RX", 371 "UART_DBG_TX_AP_RX",
733 "EN_SPKR", 372 "EN_SPKR",
734 "AP_EC_WARM_RST_REQ", 373 "AP_EC_WARM_RST_REQ",
735 "UART_SCP_TX_DBGCON_RX", 374 "UART_SCP_TX_DBGCON_RX",
736 "UART_DBGCON_TX_SCP_RX", 375 "UART_DBGCON_TX_SCP_RX",
737 "", 376 "",
738 "", 377 "",
739 "KPCOL0", 378 "KPCOL0",
740 "", 379 "",
741 "MT6315_GPU_INT", 380 "MT6315_GPU_INT",
742 "MT6315_PROC_BC_INT", 381 "MT6315_PROC_BC_INT",
743 "SD_CMD", 382 "SD_CMD",
744 "SD_CLK", 383 "SD_CLK",
745 "SD_DAT0", 384 "SD_DAT0",
746 "SD_DAT1", 385 "SD_DAT1",
747 "SD_DAT2", 386 "SD_DAT2",
748 "SD_DAT3", 387 "SD_DAT3",
749 "EMMC_DAT7", 388 "EMMC_DAT7",
750 "EMMC_DAT6", 389 "EMMC_DAT6",
751 "EMMC_DAT5", 390 "EMMC_DAT5",
752 "EMMC_DAT4", 391 "EMMC_DAT4",
753 "EMMC_RSTB", 392 "EMMC_RSTB",
754 "EMMC_CMD", 393 "EMMC_CMD",
755 "EMMC_CLK", 394 "EMMC_CLK",
756 "EMMC_DAT3", 395 "EMMC_DAT3",
757 "EMMC_DAT2", 396 "EMMC_DAT2",
758 "EMMC_DAT1", 397 "EMMC_DAT1",
759 "EMMC_DAT0", 398 "EMMC_DAT0",
760 "EMMC_DSL", 399 "EMMC_DSL",
761 "", 400 "",
762 "", 401 "",
763 "MT6360_INT_ODL", 402 "MT6360_INT_ODL",
764 "SCP_JTAG0_TRSTN", 403 "SCP_JTAG0_TRSTN",
765 "AP_SPI_EC_CS_L", 404 "AP_SPI_EC_CS_L",
766 "AP_SPI_EC_CLK", 405 "AP_SPI_EC_CLK",
767 "AP_SPI_EC_MOSI", 406 "AP_SPI_EC_MOSI",
768 "AP_SPI_EC_MISO", 407 "AP_SPI_EC_MISO",
769 "SCP_JTAG0_TMS", 408 "SCP_JTAG0_TMS",
770 "SCP_JTAG0_TCK", 409 "SCP_JTAG0_TCK",
771 "SCP_JTAG0_TDO", 410 "SCP_JTAG0_TDO",
772 "SCP_JTAG0_TDI", 411 "SCP_JTAG0_TDI",
773 "AP_SPI_FLASH_CS_L", 412 "AP_SPI_FLASH_CS_L",
774 "AP_SPI_FLASH_CLK", 413 "AP_SPI_FLASH_CLK",
775 "AP_SPI_FLASH_MOSI", 414 "AP_SPI_FLASH_MOSI",
776 "AP_SPI_FLASH_MISO"; 415 "AP_SPI_FLASH_MISO";
777 416
778 aud_pins_default: audio-default-pins { <<
779 pins-cmd-dat { <<
780 pinmux = <PINMUX_GPIO69__F <<
781 <PINMUX_GPIO70__F <<
782 <PINMUX_GPIO71__F <<
783 <PINMUX_GPIO72__F <<
784 <PINMUX_GPIO73__F <<
785 <PINMUX_GPIO74__F <<
786 <PINMUX_GPIO75__F <<
787 <PINMUX_GPIO0__FU <<
788 <PINMUX_GPIO1__FU <<
789 <PINMUX_GPIO2__FU <<
790 <PINMUX_GPIO3__FU <<
791 <PINMUX_GPIO60__F <<
792 <PINMUX_GPIO49__F <<
793 <PINMUX_GPIO50__F <<
794 <PINMUX_GPIO51__F <<
795 <PINMUX_GPIO52__F <<
796 <PINMUX_GPIO53__F <<
797 }; <<
798 <<
799 pins-hp-jack-int-odl { <<
800 pinmux = <PINMUX_GPIO8 <<
801 input-enable; <<
802 bias-pull-up = <MTK_PU <<
803 }; <<
804 }; <<
805 <<
806 cr50_int: cr50-irq-default-pins { <<
807 pins-gsc-ap-int-odl { <<
808 pinmux = <PINMUX_GPIO8 <<
809 input-enable; <<
810 }; <<
811 }; <<
812 <<
813 cros_ec_int: cros-ec-irq-default-pins <<
814 pins-ec-ap-int-odl { <<
815 pinmux = <PINMUX_GPIO4 <<
816 bias-pull-up = <MTK_PU <<
817 input-enable; <<
818 }; <<
819 }; <<
820 <<
821 edptx_pins_default: edptx-default-pins <<
822 pins-cmd-dat { <<
823 pinmux = <PINMUX_GPIO7 <<
824 bias-pull-up; <<
825 }; <<
826 }; <<
827 <<
828 disp_pwm0_pin_default: disp-pwm0-defau <<
829 pins-disp-pwm { <<
830 pinmux = <PINMUX_GPIO8 <<
831 <PINMUX_GPIO9 <<
832 }; <<
833 }; <<
834 <<
835 dptx_pin: dptx-default-pins { <<
836 pins-cmd-dat { <<
837 pinmux = <PINMUX_GPIO1 <<
838 bias-pull-up; <<
839 }; <<
840 }; <<
841 <<
842 i2c0_pins: i2c0-default-pins { 417 i2c0_pins: i2c0-default-pins {
843 pins-bus { 418 pins-bus {
844 pinmux = <PINMUX_GPIO8 419 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
845 <PINMUX_GPIO9 420 <PINMUX_GPIO9__FUNC_SCL0>;
846 bias-disable; 421 bias-disable;
847 drive-strength-microam 422 drive-strength-microamp = <1000>;
848 }; 423 };
849 }; 424 };
850 425
851 i2c1_pins: i2c1-default-pins { 426 i2c1_pins: i2c1-default-pins {
852 pins-bus { 427 pins-bus {
853 pinmux = <PINMUX_GPIO1 428 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
854 <PINMUX_GPIO1 429 <PINMUX_GPIO11__FUNC_SCL1>;
855 bias-pull-up = <1000>; 430 bias-pull-up = <1000>;
856 drive-strength-microam 431 drive-strength-microamp = <1000>;
857 }; 432 };
858 }; 433 };
859 434
860 i2c2_pins: i2c2-default-pins { 435 i2c2_pins: i2c2-default-pins {
861 pins-bus { 436 pins-bus {
862 pinmux = <PINMUX_GPIO1 437 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
863 <PINMUX_GPIO1 438 <PINMUX_GPIO13__FUNC_SCL2>;
864 bias-disable; 439 bias-disable;
865 drive-strength-microam 440 drive-strength-microamp = <1000>;
866 }; 441 };
867 }; 442 };
868 443
869 i2c3_pins: i2c3-default-pins { 444 i2c3_pins: i2c3-default-pins {
870 pins-bus { 445 pins-bus {
871 pinmux = <PINMUX_GPIO1 446 pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
872 <PINMUX_GPIO1 447 <PINMUX_GPIO15__FUNC_SCL3>;
873 bias-pull-up = <1000>; 448 bias-pull-up = <1000>;
874 drive-strength-microam 449 drive-strength-microamp = <1000>;
875 }; 450 };
876 }; 451 };
877 452
878 i2c4_pins: i2c4-default-pins { 453 i2c4_pins: i2c4-default-pins {
879 pins-bus { 454 pins-bus {
880 pinmux = <PINMUX_GPIO1 455 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
881 <PINMUX_GPIO1 456 <PINMUX_GPIO17__FUNC_SCL4>;
882 bias-pull-up = <1000>; 457 bias-pull-up = <1000>;
883 drive-strength = <4>; 458 drive-strength = <4>;
884 }; 459 };
885 }; 460 };
886 461
887 i2c5_pins: i2c5-default-pins { 462 i2c5_pins: i2c5-default-pins {
888 pins-bus { 463 pins-bus {
889 pinmux = <PINMUX_GPIO2 464 pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
890 <PINMUX_GPIO3 465 <PINMUX_GPIO30__FUNC_SDA5>;
891 bias-disable; 466 bias-disable;
892 drive-strength-microam 467 drive-strength-microamp = <1000>;
893 }; 468 };
894 }; 469 };
895 470
896 i2c7_pins: i2c7-default-pins { 471 i2c7_pins: i2c7-default-pins {
897 pins-bus { 472 pins-bus {
898 pinmux = <PINMUX_GPIO2 473 pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
899 <PINMUX_GPIO2 474 <PINMUX_GPIO28__FUNC_SDA7>;
900 bias-disable; 475 bias-disable;
901 }; 476 };
902 }; 477 };
903 478
904 mmc0_pins_default: mmc0-default-pins { 479 mmc0_pins_default: mmc0-default-pins {
905 pins-cmd-dat { 480 pins-cmd-dat {
906 pinmux = <PINMUX_GPIO1 481 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
907 <PINMUX_GPIO1 482 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
908 <PINMUX_GPIO1 483 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
909 <PINMUX_GPIO1 484 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
910 <PINMUX_GPIO1 485 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
911 <PINMUX_GPIO1 486 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
912 <PINMUX_GPIO1 487 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
913 <PINMUX_GPIO1 488 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
914 <PINMUX_GPIO1 489 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
915 input-enable; 490 input-enable;
916 drive-strength = <6>; 491 drive-strength = <6>;
917 bias-pull-up = <MTK_PU 492 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
918 }; 493 };
919 494
920 pins-clk { 495 pins-clk {
921 pinmux = <PINMUX_GPIO1 496 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
922 drive-strength = <6>; 497 drive-strength = <6>;
923 bias-pull-down = <MTK_ 498 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
924 }; 499 };
925 500
926 pins-rst { 501 pins-rst {
927 pinmux = <PINMUX_GPIO1 502 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
928 drive-strength = <6>; 503 drive-strength = <6>;
929 bias-pull-up = <MTK_PU 504 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
930 }; 505 };
931 }; 506 };
932 507
933 mmc0_pins_uhs: mmc0-uhs-pins { 508 mmc0_pins_uhs: mmc0-uhs-pins {
934 pins-cmd-dat { 509 pins-cmd-dat {
935 pinmux = <PINMUX_GPIO1 510 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
936 <PINMUX_GPIO1 511 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
937 <PINMUX_GPIO1 512 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
938 <PINMUX_GPIO1 513 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
939 <PINMUX_GPIO1 514 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
940 <PINMUX_GPIO1 515 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
941 <PINMUX_GPIO1 516 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
942 <PINMUX_GPIO1 517 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
943 <PINMUX_GPIO1 518 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
944 input-enable; 519 input-enable;
945 drive-strength = <8>; 520 drive-strength = <8>;
946 bias-pull-up = <MTK_PU 521 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
947 }; 522 };
948 523
949 pins-clk { 524 pins-clk {
950 pinmux = <PINMUX_GPIO1 525 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
951 drive-strength = <8>; 526 drive-strength = <8>;
952 bias-pull-down = <MTK_ 527 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
953 }; 528 };
954 529
955 pins-ds { 530 pins-ds {
956 pinmux = <PINMUX_GPIO1 531 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
957 drive-strength = <8>; 532 drive-strength = <8>;
958 bias-pull-down = <MTK_ 533 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
959 }; 534 };
960 535
961 pins-rst { 536 pins-rst {
962 pinmux = <PINMUX_GPIO1 537 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
963 drive-strength = <8>; 538 drive-strength = <8>;
964 bias-pull-up = <MTK_PU 539 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
965 }; 540 };
966 }; 541 };
967 542
968 mmc1_pins_detect: mmc1-detect-pins { <<
969 pins-insert { <<
970 pinmux = <PINMUX_GPIO5 <<
971 bias-pull-up; <<
972 }; <<
973 }; <<
974 <<
975 mmc1_pins_default: mmc1-default-pins { <<
976 pins-cmd-dat { <<
977 pinmux = <PINMUX_GPIO1 <<
978 <PINMUX_GPIO1 <<
979 <PINMUX_GPIO1 <<
980 <PINMUX_GPIO1 <<
981 <PINMUX_GPIO1 <<
982 input-enable; <<
983 drive-strength = <8>; <<
984 bias-pull-up = <MTK_PU <<
985 }; <<
986 <<
987 pins-clk { <<
988 pinmux = <PINMUX_GPIO1 <<
989 drive-strength = <8>; <<
990 bias-pull-down = <MTK_ <<
991 }; <<
992 }; <<
993 <<
994 nor_pins_default: nor-default-pins { 543 nor_pins_default: nor-default-pins {
995 pins-ck-io { 544 pins-ck-io {
996 pinmux = <PINMUX_GPIO1 545 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
997 <PINMUX_GPIO1 546 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
998 <PINMUX_GPIO1 547 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
999 drive-strength = <6>; 548 drive-strength = <6>;
1000 bias-pull-down; 549 bias-pull-down;
1001 }; 550 };
1002 551
1003 pins-cs { 552 pins-cs {
1004 pinmux = <PINMUX_GPIO 553 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
1005 drive-strength = <6>; 554 drive-strength = <6>;
1006 bias-pull-up; 555 bias-pull-up;
1007 }; 556 };
1008 }; 557 };
1009 558
1010 pcie0_pins_default: pcie0-default-pin <<
1011 pins-bus { <<
1012 pinmux = <PINMUX_GPIO <<
1013 <PINMUX_GPIO <<
1014 <PINMUX_GPIO <<
1015 bias-pull-up <<
1016 }; <<
1017 }; <<
1018 <<
1019 pcie1_pins_default: pcie1-default-pin <<
1020 pins-bus { <<
1021 pinmux = <PINMUX_GPIO <<
1022 <PINMUX_GPIO <<
1023 <PINMUX_GPIO <<
1024 bias-pull-up <<
1025 }; <<
1026 }; <<
1027 <<
1028 panel_fixed_pins: panel-pwr-default-p <<
1029 pins-vreg-en { <<
1030 pinmux = <PINMUX_GPIO <<
1031 }; <<
1032 }; <<
1033 <<
1034 pio_default: pio-default-pins { 559 pio_default: pio-default-pins {
1035 pins-wifi-enable { 560 pins-wifi-enable {
1036 pinmux = <PINMUX_GPIO 561 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
1037 output-high; 562 output-high;
1038 drive-strength = <14> 563 drive-strength = <14>;
1039 }; 564 };
1040 565
1041 pins-low-power-pd { 566 pins-low-power-pd {
1042 pinmux = <PINMUX_GPIO 567 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
1043 <PINMUX_GPIO 568 <PINMUX_GPIO26__FUNC_GPIO26>,
1044 <PINMUX_GPIO 569 <PINMUX_GPIO46__FUNC_GPIO46>,
1045 <PINMUX_GPIO 570 <PINMUX_GPIO47__FUNC_GPIO47>,
1046 <PINMUX_GPIO 571 <PINMUX_GPIO48__FUNC_GPIO48>,
1047 <PINMUX_GPIO 572 <PINMUX_GPIO65__FUNC_GPIO65>,
1048 <PINMUX_GPIO 573 <PINMUX_GPIO66__FUNC_GPIO66>,
1049 <PINMUX_GPIO 574 <PINMUX_GPIO67__FUNC_GPIO67>,
1050 <PINMUX_GPIO 575 <PINMUX_GPIO68__FUNC_GPIO68>,
1051 <PINMUX_GPIO 576 <PINMUX_GPIO128__FUNC_GPIO128>,
1052 <PINMUX_GPIO 577 <PINMUX_GPIO129__FUNC_GPIO129>;
1053 input-enable; 578 input-enable;
1054 bias-pull-down; 579 bias-pull-down;
1055 }; 580 };
1056 581
1057 pins-low-power-pupd { 582 pins-low-power-pupd {
1058 pinmux = <PINMUX_GPIO 583 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
1059 <PINMUX_GPIO 584 <PINMUX_GPIO78__FUNC_GPIO78>,
1060 <PINMUX_GPIO 585 <PINMUX_GPIO79__FUNC_GPIO79>,
1061 <PINMUX_GPIO 586 <PINMUX_GPIO80__FUNC_GPIO80>,
1062 <PINMUX_GPIO 587 <PINMUX_GPIO83__FUNC_GPIO83>,
1063 <PINMUX_GPIO 588 <PINMUX_GPIO85__FUNC_GPIO85>,
1064 <PINMUX_GPIO 589 <PINMUX_GPIO90__FUNC_GPIO90>,
1065 <PINMUX_GPIO 590 <PINMUX_GPIO91__FUNC_GPIO91>,
1066 <PINMUX_GPIO 591 <PINMUX_GPIO93__FUNC_GPIO93>,
1067 <PINMUX_GPIO 592 <PINMUX_GPIO94__FUNC_GPIO94>,
1068 <PINMUX_GPIO 593 <PINMUX_GPIO95__FUNC_GPIO95>,
1069 <PINMUX_GPIO 594 <PINMUX_GPIO96__FUNC_GPIO96>,
1070 <PINMUX_GPIO 595 <PINMUX_GPIO104__FUNC_GPIO104>,
1071 <PINMUX_GPIO 596 <PINMUX_GPIO105__FUNC_GPIO105>,
1072 <PINMUX_GPIO 597 <PINMUX_GPIO107__FUNC_GPIO107>;
1073 input-enable; 598 input-enable;
1074 bias-pull-down = <MTK 599 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1075 }; 600 };
1076 }; 601 };
1077 602
1078 rt1019p_pins_default: rt1019p-default <<
1079 pins-amp-sdb { <<
1080 pinmux = <PINMUX_GPIO <<
1081 output-low; <<
1082 }; <<
1083 }; <<
1084 <<
1085 scp_pins: scp-default-pins { <<
1086 pins-vreq { <<
1087 pinmux = <PINMUX_GPIO <<
1088 bias-disable; <<
1089 input-enable; <<
1090 }; <<
1091 }; <<
1092 <<
1093 spi0_pins: spi0-default-pins { 603 spi0_pins: spi0-default-pins {
1094 pins-cs-mosi-clk { 604 pins-cs-mosi-clk {
1095 pinmux = <PINMUX_GPIO 605 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
1096 <PINMUX_GPIO 606 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
1097 <PINMUX_GPIO 607 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
1098 bias-disable; 608 bias-disable;
1099 }; 609 };
1100 610
1101 pins-miso { 611 pins-miso {
1102 pinmux = <PINMUX_GPIO 612 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
1103 bias-pull-down; 613 bias-pull-down;
1104 }; 614 };
1105 }; 615 };
1106 616
1107 subpmic_default: subpmic-default-pins 617 subpmic_default: subpmic-default-pins {
1108 subpmic_pin_irq: pins-subpmic 618 subpmic_pin_irq: pins-subpmic-int-n {
1109 pinmux = <PINMUX_GPIO 619 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
1110 input-enable; 620 input-enable;
1111 bias-pull-up; 621 bias-pull-up;
1112 }; 622 };
1113 }; 623 };
1114 624
1115 trackpad_pins: trackpad-default-pins <<
1116 pins-int-n { <<
1117 pinmux = <PINMUX_GPIO <<
1118 input-enable; <<
1119 bias-pull-up; <<
1120 }; <<
1121 }; <<
1122 <<
1123 touchscreen_pins: touchscreen-default 625 touchscreen_pins: touchscreen-default-pins {
1124 pins-int-n { 626 pins-int-n {
1125 pinmux = <PINMUX_GPIO 627 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
1126 input-enable; 628 input-enable;
1127 bias-pull-up = <MTK_P 629 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1128 }; 630 };
1129 pins-rst { 631 pins-rst {
1130 pinmux = <PINMUX_GPIO 632 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
1131 output-high; 633 output-high;
1132 }; 634 };
1133 pins-report-sw { 635 pins-report-sw {
1134 pinmux = <PINMUX_GPIO 636 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
1135 output-low; 637 output-low;
1136 }; 638 };
1137 }; 639 };
1138 }; 640 };
1139 641
1140 &pmic { 642 &pmic {
1141 interrupts-extended = <&pio 222 IRQ_T 643 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1142 }; 644 };
1143 645
1144 &scp { <<
1145 status = "okay"; <<
1146 <<
1147 firmware-name = "mediatek/mt8195/scp. <<
1148 memory-region = <&scp_mem>; <<
1149 pinctrl-names = "default"; <<
1150 pinctrl-0 = <&scp_pins>; <<
1151 <<
1152 cros-ec-rpmsg { <<
1153 compatible = "google,cros-ec- <<
1154 mediatek,rpmsg-name = "cros-e <<
1155 }; <<
1156 }; <<
1157 <<
1158 &sound { <<
1159 status = "okay"; <<
1160 <<
1161 mediatek,adsp = <&adsp>; <<
1162 mediatek,dai-link = <<
1163 "DL10_FE", "DPTX_BE", "ETDM1_ <<
1164 "ETDM1_OUT_BE", "ETDM2_OUT_BE <<
1165 "AFE_SOF_DL2", "AFE_SOF_DL3", <<
1166 pinctrl-names = "default"; <<
1167 pinctrl-0 = <&aud_pins_default>; <<
1168 <<
1169 audio-routing = <<
1170 "Headphone", "HPOL", <<
1171 "Headphone", "HPOR", <<
1172 "IN1P", "Headset Mic", <<
1173 "Ext Spk", "Speaker"; <<
1174 <<
1175 mm-dai-link { <<
1176 link-name = "ETDM1_IN_BE"; <<
1177 mediatek,clk-provider = "cpu" <<
1178 }; <<
1179 <<
1180 hs-playback-dai-link { <<
1181 link-name = "ETDM1_OUT_BE"; <<
1182 mediatek,clk-provider = "cpu" <<
1183 codec { <<
1184 sound-dai = <&audio_c <<
1185 }; <<
1186 }; <<
1187 <<
1188 hs-capture-dai-link { <<
1189 link-name = "ETDM2_IN_BE"; <<
1190 mediatek,clk-provider = "cpu" <<
1191 codec { <<
1192 sound-dai = <&audio_c <<
1193 }; <<
1194 }; <<
1195 <<
1196 spk-playback-dai-link { <<
1197 link-name = "ETDM2_OUT_BE"; <<
1198 mediatek,clk-provider = "cpu" <<
1199 codec { <<
1200 sound-dai = <&spk_amp <<
1201 }; <<
1202 }; <<
1203 <<
1204 displayport-dai-link { <<
1205 link-name = "DPTX_BE"; <<
1206 codec { <<
1207 sound-dai = <&dp_tx>; <<
1208 }; <<
1209 }; <<
1210 }; <<
1211 <<
1212 &spi0 { 646 &spi0 {
1213 status = "okay"; 647 status = "okay";
1214 648
1215 pinctrl-names = "default"; 649 pinctrl-names = "default";
1216 pinctrl-0 = <&spi0_pins>; 650 pinctrl-0 = <&spi0_pins>;
1217 mediatek,pad-select = <0>; 651 mediatek,pad-select = <0>;
1218 <<
1219 cros_ec: ec@0 { <<
1220 #address-cells = <1>; <<
1221 #size-cells = <0>; <<
1222 <<
1223 compatible = "google,cros-ec- <<
1224 reg = <0>; <<
1225 interrupts-extended = <&pio 4 <<
1226 pinctrl-names = "default"; <<
1227 pinctrl-0 = <&cros_ec_int>; <<
1228 spi-max-frequency = <3000000> <<
1229 wakeup-source; <<
1230 <<
1231 i2c_tunnel: i2c-tunnel { <<
1232 compatible = "google, <<
1233 google,remote-bus = < <<
1234 #address-cells = <1>; <<
1235 #size-cells = <0>; <<
1236 }; <<
1237 <<
1238 mt_pmic_vmc_ldo_reg: regulato <<
1239 compatible = "google, <<
1240 reg = <0>; <<
1241 regulator-name = "mt_ <<
1242 regulator-min-microvo <<
1243 regulator-max-microvo <<
1244 }; <<
1245 <<
1246 mt_pmic_vmch_ldo_reg: regulat <<
1247 compatible = "google, <<
1248 reg = <1>; <<
1249 regulator-name = "mt_ <<
1250 regulator-min-microvo <<
1251 regulator-max-microvo <<
1252 }; <<
1253 <<
1254 typec { <<
1255 compatible = "google, <<
1256 #address-cells = <1>; <<
1257 #size-cells = <0>; <<
1258 <<
1259 usb_c0: connector@0 { <<
1260 compatible = <<
1261 reg = <0>; <<
1262 power-role = <<
1263 data-role = " <<
1264 try-power-rol <<
1265 }; <<
1266 <<
1267 usb_c1: connector@1 { <<
1268 compatible = <<
1269 reg = <1>; <<
1270 power-role = <<
1271 data-role = " <<
1272 try-power-rol <<
1273 }; <<
1274 }; <<
1275 }; <<
1276 }; <<
1277 <<
1278 &spmi { <<
1279 #address-cells = <2>; <<
1280 #size-cells = <0>; <<
1281 <<
1282 mt6315@6 { <<
1283 compatible = "mediatek,mt6315 <<
1284 reg = <0x6 SPMI_USID>; <<
1285 <<
1286 regulators { <<
1287 mt6315_6_vbuck1: vbuc <<
1288 regulator-com <<
1289 regulator-nam <<
1290 regulator-min <<
1291 regulator-max <<
1292 regulator-ena <<
1293 regulator-ram <<
1294 regulator-all <<
1295 regulator-alw <<
1296 }; <<
1297 }; <<
1298 }; <<
1299 <<
1300 mt6315@7 { <<
1301 compatible = "mediatek,mt6315 <<
1302 reg = <0x7 SPMI_USID>; <<
1303 <<
1304 regulators { <<
1305 mt6315_7_vbuck1: vbuc <<
1306 regulator-com <<
1307 regulator-nam <<
1308 regulator-min <<
1309 regulator-max <<
1310 regulator-ena <<
1311 regulator-ram <<
1312 regulator-all <<
1313 }; <<
1314 }; <<
1315 }; <<
1316 }; <<
1317 <<
1318 &thermal_zones { <<
1319 soc-area-thermal { <<
1320 polling-delay = <1000>; <<
1321 polling-delay-passive = <250> <<
1322 thermal-sensors = <&tboard_th <<
1323 <<
1324 trips { <<
1325 trip-crit { <<
1326 temperature = <<
1327 hysteresis = <<
1328 type = "criti <<
1329 }; <<
1330 }; <<
1331 }; <<
1332 <<
1333 pmic-area-thermal { <<
1334 polling-delay = <1000>; <<
1335 polling-delay-passive = <0>; <<
1336 thermal-sensors = <&tboard_th <<
1337 <<
1338 trips { <<
1339 trip-crit { <<
1340 temperature = <<
1341 hysteresis = <<
1342 type = "criti <<
1343 }; <<
1344 }; <<
1345 }; <<
1346 }; 652 };
1347 653
1348 &u3phy0 { 654 &u3phy0 {
1349 status = "okay"; 655 status = "okay";
1350 }; 656 };
1351 657
1352 &u3phy1 { 658 &u3phy1 {
1353 status = "okay"; 659 status = "okay";
1354 }; 660 };
1355 661
1356 &u3phy2 { 662 &u3phy2 {
1357 status = "okay"; 663 status = "okay";
1358 }; 664 };
1359 665
1360 &u3phy3 { 666 &u3phy3 {
1361 status = "okay"; 667 status = "okay";
1362 }; 668 };
1363 669
1364 &uart0 { 670 &uart0 {
1365 status = "okay"; 671 status = "okay";
1366 }; 672 };
1367 673
1368 /* <<
1369 * For the USB Type-C ports the role and alte <<
1370 * done by the EC so we set dr_mode to host t <<
1371 */ <<
1372 &ssusb0 { <<
1373 dr_mode = "host"; <<
1374 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1375 status = "okay"; <<
1376 }; <<
1377 <<
1378 &ssusb2 { <<
1379 dr_mode = "host"; <<
1380 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1381 status = "okay"; <<
1382 }; <<
1383 <<
1384 &ssusb3 { <<
1385 dr_mode = "host"; <<
1386 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1387 status = "okay"; <<
1388 }; <<
1389 <<
1390 &xhci0 { 674 &xhci0 {
1391 status = "okay"; 675 status = "okay";
1392 676
1393 rx-fifo-depth = <3072>; !! 677 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1394 vbus-supply = <&usb_vbus>; 678 vbus-supply = <&usb_vbus>;
1395 }; 679 };
1396 680
1397 &xhci1 { 681 &xhci1 {
1398 status = "okay"; 682 status = "okay";
1399 683
1400 phys = <&u2port1 PHY_TYPE_USB2>; <<
1401 rx-fifo-depth = <3072>; <<
1402 vusb33-supply = <&mt6359_vusb_ldo_reg 684 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1403 vbus-supply = <&usb_vbus>; 685 vbus-supply = <&usb_vbus>;
1404 mediatek,u3p-dis-msk = <1>; <<
1405 }; 686 };
1406 687
1407 &xhci2 { 688 &xhci2 {
1408 status = "okay"; 689 status = "okay";
>> 690
>> 691 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1409 vbus-supply = <&usb_vbus>; 692 vbus-supply = <&usb_vbus>;
1410 }; 693 };
1411 694
1412 &xhci3 { 695 &xhci3 {
1413 status = "okay"; 696 status = "okay";
1414 697
1415 /* MT7921's USB Bluetooth has issues 698 /* MT7921's USB Bluetooth has issues with USB2 LPM */
1416 usb2-lpm-disable; 699 usb2-lpm-disable;
>> 700 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1417 vbus-supply = <&usb_vbus>; 701 vbus-supply = <&usb_vbus>;
1418 }; <<
1419 <<
1420 #include <arm/cros-ec-keyboard.dtsi> <<
1421 #include <arm/cros-ec-sbs.dtsi> <<
1422 <<
1423 &keyboard_controller { <<
1424 function-row-physmap = < <<
1425 MATRIX_KEY(0x00, 0x02, 0) <<
1426 MATRIX_KEY(0x03, 0x02, 0) <<
1427 MATRIX_KEY(0x02, 0x02, 0) <<
1428 MATRIX_KEY(0x01, 0x02, 0) <<
1429 MATRIX_KEY(0x03, 0x04, 0) <<
1430 MATRIX_KEY(0x02, 0x04, 0) <<
1431 MATRIX_KEY(0x01, 0x04, 0) <<
1432 MATRIX_KEY(0x02, 0x09, 0) <<
1433 MATRIX_KEY(0x01, 0x09, 0) <<
1434 MATRIX_KEY(0x00, 0x04, 0) <<
1435 <<
1436 /* T11 to T13 are present onl <<
1437 MATRIX_KEY(0x00, 0x01, 0) <<
1438 MATRIX_KEY(0x01, 0x05, 0) <<
1439 MATRIX_KEY(0x03, 0x05, 0) <<
1440 >; <<
1441 <<
1442 linux,keymap = < <<
1443 MATRIX_KEY(0x00, 0x02, KEY_BA <<
1444 MATRIX_KEY(0x03, 0x02, KEY_RE <<
1445 MATRIX_KEY(0x02, 0x02, KEY_ZO <<
1446 MATRIX_KEY(0x01, 0x02, KEY_SC <<
1447 MATRIX_KEY(0x03, 0x04, KEY_SY <<
1448 MATRIX_KEY(0x02, 0x04, KEY_BR <<
1449 MATRIX_KEY(0x01, 0x04, KEY_BR <<
1450 MATRIX_KEY(0x02, 0x09, KEY_MU <<
1451 MATRIX_KEY(0x01, 0x09, KEY_VO <<
1452 MATRIX_KEY(0x00, 0x04, KEY_VO <<
1453 <<
1454 CROS_STD_MAIN_KEYMAP <<
1455 >; <<
1456 }; 702 };
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