1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2021 MediaTek Inc. 3 * Copyright (C) 2021 MediaTek Inc.
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h> 7 #include <dt-bindings/spmi/spmi.h>
8 #include "mt8195.dtsi" 8 #include "mt8195.dtsi"
9 #include "mt6359.dtsi" 9 #include "mt6359.dtsi"
10 10
11 / { 11 / {
12 aliases { 12 aliases {
13 i2c0 = &i2c0; 13 i2c0 = &i2c0;
14 i2c1 = &i2c1; 14 i2c1 = &i2c1;
15 i2c2 = &i2c2; 15 i2c2 = &i2c2;
16 i2c3 = &i2c3; 16 i2c3 = &i2c3;
17 i2c4 = &i2c4; 17 i2c4 = &i2c4;
18 i2c5 = &i2c5; 18 i2c5 = &i2c5;
19 i2c7 = &i2c7; 19 i2c7 = &i2c7;
20 mmc0 = &mmc0; 20 mmc0 = &mmc0;
21 mmc1 = &mmc1; 21 mmc1 = &mmc1;
22 serial0 = &uart0; 22 serial0 = &uart0;
23 }; 23 };
24 24
25 backlight_lcd0: backlight-lcd0 { <<
26 compatible = "pwm-backlight"; <<
27 brightness-levels = <0 1023>; <<
28 default-brightness-level = <57 <<
29 enable-gpios = <&pio 82 GPIO_A <<
30 num-interpolated-steps = <1023 <<
31 pwms = <&disp_pwm0 0 500000>; <<
32 power-supply = <&ppvar_sys>; <<
33 }; <<
34 <<
35 chosen { 25 chosen {
36 stdout-path = "serial0:115200n 26 stdout-path = "serial0:115200n8";
37 }; 27 };
38 28
39 dmic-codec { <<
40 compatible = "dmic-codec"; <<
41 num-channels = <2>; <<
42 wakeup-delay-ms = <50>; <<
43 }; <<
44 <<
45 memory@40000000 { 29 memory@40000000 {
46 device_type = "memory"; 30 device_type = "memory";
47 reg = <0 0x40000000 0 0x800000 31 reg = <0 0x40000000 0 0x80000000>;
48 }; 32 };
49 33
50 pp3300_disp_x: regulator-pp3300-disp-x <<
51 compatible = "regulator-fixed" <<
52 regulator-name = "pp3300_disp_ <<
53 regulator-min-microvolt = <330 <<
54 regulator-max-microvolt = <330 <<
55 regulator-enable-ramp-delay = <<
56 enable-active-high; <<
57 gpio = <&pio 55 GPIO_ACTIVE_HI <<
58 pinctrl-names = "default"; <<
59 pinctrl-0 = <&panel_fixed_pins <<
60 vin-supply = <&pp3300_z2>; <<
61 }; <<
62 <<
63 /* system wide LDO 3.3V power rail */ 34 /* system wide LDO 3.3V power rail */
64 pp3300_z5: regulator-pp3300-ldo-z5 { 35 pp3300_z5: regulator-pp3300-ldo-z5 {
65 compatible = "regulator-fixed" 36 compatible = "regulator-fixed";
66 regulator-name = "pp3300_ldo_z 37 regulator-name = "pp3300_ldo_z5";
67 regulator-always-on; 38 regulator-always-on;
68 regulator-boot-on; 39 regulator-boot-on;
69 regulator-min-microvolt = <330 40 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <330 41 regulator-max-microvolt = <3300000>;
71 vin-supply = <&ppvar_sys>; 42 vin-supply = <&ppvar_sys>;
72 }; 43 };
73 44
74 /* separately switched 3.3V power rail 45 /* separately switched 3.3V power rail */
75 pp3300_s3: regulator-pp3300-s3 { 46 pp3300_s3: regulator-pp3300-s3 {
76 compatible = "regulator-fixed" 47 compatible = "regulator-fixed";
77 regulator-name = "pp3300_s3"; 48 regulator-name = "pp3300_s3";
78 /* automatically sequenced by 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */
79 regulator-always-on; 50 regulator-always-on;
80 regulator-boot-on; 51 regulator-boot-on;
81 regulator-min-microvolt = <330 52 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <330 53 regulator-max-microvolt = <3300000>;
83 vin-supply = <&pp3300_z2>; 54 vin-supply = <&pp3300_z2>;
84 }; 55 };
85 56
86 /* system wide 3.3V power rail */ 57 /* system wide 3.3V power rail */
87 pp3300_z2: regulator-pp3300-z2 { 58 pp3300_z2: regulator-pp3300-z2 {
88 compatible = "regulator-fixed" 59 compatible = "regulator-fixed";
89 regulator-name = "pp3300_z2"; 60 regulator-name = "pp3300_z2";
90 /* EN pin tied to pp4200_z2, w 61 /* EN pin tied to pp4200_z2, which is controlled by EC */
91 regulator-always-on; 62 regulator-always-on;
92 regulator-boot-on; 63 regulator-boot-on;
93 regulator-min-microvolt = <330 64 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <330 65 regulator-max-microvolt = <3300000>;
95 vin-supply = <&ppvar_sys>; 66 vin-supply = <&ppvar_sys>;
96 }; 67 };
97 68
98 /* system wide 4.2V power rail */ 69 /* system wide 4.2V power rail */
99 pp4200_z2: regulator-pp4200-z2 { 70 pp4200_z2: regulator-pp4200-z2 {
100 compatible = "regulator-fixed" 71 compatible = "regulator-fixed";
101 regulator-name = "pp4200_z2"; 72 regulator-name = "pp4200_z2";
102 /* controlled by EC */ 73 /* controlled by EC */
103 regulator-always-on; 74 regulator-always-on;
104 regulator-boot-on; 75 regulator-boot-on;
105 regulator-min-microvolt = <420 76 regulator-min-microvolt = <4200000>;
106 regulator-max-microvolt = <420 77 regulator-max-microvolt = <4200000>;
107 vin-supply = <&ppvar_sys>; 78 vin-supply = <&ppvar_sys>;
108 }; 79 };
109 80
110 /* system wide switching 5.0V power ra 81 /* system wide switching 5.0V power rail */
111 pp5000_s5: regulator-pp5000-s5 { 82 pp5000_s5: regulator-pp5000-s5 {
112 compatible = "regulator-fixed" 83 compatible = "regulator-fixed";
113 regulator-name = "pp5000_s5"; 84 regulator-name = "pp5000_s5";
114 /* controlled by EC */ 85 /* controlled by EC */
115 regulator-always-on; 86 regulator-always-on;
116 regulator-boot-on; 87 regulator-boot-on;
117 regulator-min-microvolt = <500 88 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <500 89 regulator-max-microvolt = <5000000>;
119 vin-supply = <&ppvar_sys>; 90 vin-supply = <&ppvar_sys>;
120 }; 91 };
121 92
122 /* system wide semi-regulated power ra 93 /* system wide semi-regulated power rail from battery or USB */
123 ppvar_sys: regulator-ppvar-sys { 94 ppvar_sys: regulator-ppvar-sys {
124 compatible = "regulator-fixed" 95 compatible = "regulator-fixed";
125 regulator-name = "ppvar_sys"; 96 regulator-name = "ppvar_sys";
126 regulator-always-on; 97 regulator-always-on;
127 regulator-boot-on; 98 regulator-boot-on;
128 }; 99 };
129 100
130 /* Murata NCP03WF104F05RL */ <<
131 tboard_thermistor1: thermal-sensor-t1 <<
132 compatible = "generic-adc-ther <<
133 #thermal-sensor-cells = <0>; <<
134 io-channels = <&auxadc 0>; <<
135 io-channel-names = "sensor-cha <<
136 temperature-lookup-table = < <<
137 <<
138 <<
139 <<
140 <<
141 <<
142 <<
143 <<
144 <<
145 <<
146 <<
147 <<
148 <<
149 <<
150 <<
151 <<
152 <<
153 <<
154 <<
155 <<
156 <<
157 <<
158 <<
159 <<
160 <<
161 <<
162 <<
163 <<
164 }; <<
165 <<
166 tboard_thermistor2: thermal-sensor-t2 <<
167 compatible = "generic-adc-ther <<
168 #thermal-sensor-cells = <0>; <<
169 io-channels = <&auxadc 1>; <<
170 io-channel-names = "sensor-cha <<
171 temperature-lookup-table = < <<
172 <<
173 <<
174 <<
175 <<
176 <<
177 <<
178 <<
179 <<
180 <<
181 <<
182 <<
183 <<
184 <<
185 <<
186 <<
187 <<
188 <<
189 <<
190 <<
191 <<
192 <<
193 <<
194 <<
195 <<
196 <<
197 <<
198 <<
199 }; <<
200 <<
201 usb_vbus: regulator-5v0-usb-vbus { 101 usb_vbus: regulator-5v0-usb-vbus {
202 compatible = "regulator-fixed" 102 compatible = "regulator-fixed";
203 regulator-name = "usb-vbus"; 103 regulator-name = "usb-vbus";
204 regulator-min-microvolt = <500 104 regulator-min-microvolt = <5000000>;
205 regulator-max-microvolt = <500 105 regulator-max-microvolt = <5000000>;
206 enable-active-high; 106 enable-active-high;
207 regulator-always-on; 107 regulator-always-on;
208 }; 108 };
209 109
210 reserved_memory: reserved-memory { 110 reserved_memory: reserved-memory {
211 #address-cells = <2>; 111 #address-cells = <2>;
212 #size-cells = <2>; 112 #size-cells = <2>;
213 ranges; 113 ranges;
214 114
215 scp_mem: memory@50000000 { 115 scp_mem: memory@50000000 {
216 compatible = "shared-d 116 compatible = "shared-dma-pool";
217 reg = <0 0x50000000 0 117 reg = <0 0x50000000 0 0x2900000>;
218 no-map; 118 no-map;
219 }; 119 };
220 <<
221 adsp_mem: memory@60000000 { <<
222 compatible = "shared-d <<
223 reg = <0 0x60000000 0 <<
224 no-map; <<
225 }; <<
226 <<
227 afe_mem: memory@60d80000 { <<
228 compatible = "shared-d <<
229 reg = <0 0x60d80000 0 <<
230 no-map; <<
231 }; <<
232 <<
233 adsp_device_mem: memory@60e800 <<
234 compatible = "shared-d <<
235 reg = <0 0x60e80000 0 <<
236 no-map; <<
237 }; <<
238 }; <<
239 <<
240 spk_amplifier: rt1019p { <<
241 compatible = "realtek,rt1019p" <<
242 label = "rt1019p"; <<
243 #sound-dai-cells = <0>; <<
244 pinctrl-names = "default"; <<
245 pinctrl-0 = <&rt1019p_pins_def <<
246 sdb-gpios = <&pio 100 GPIO_ACT <<
247 }; <<
248 }; <<
249 <<
250 &adsp { <<
251 status = "okay"; <<
252 <<
253 memory-region = <&adsp_device_mem>, <& <<
254 }; <<
255 <<
256 &afe { <<
257 status = "okay"; <<
258 <<
259 mediatek,etdm-in2-cowork-source = <2>; <<
260 mediatek,etdm-out2-cowork-source = <0> <<
261 memory-region = <&afe_mem>; <<
262 }; <<
263 <<
264 &auxadc { <<
265 status = "okay"; <<
266 }; <<
267 <<
268 &cpu0 { <<
269 cpu-supply = <&mt6359_vcore_buck_reg>; <<
270 }; <<
271 <<
272 &cpu1 { <<
273 cpu-supply = <&mt6359_vcore_buck_reg>; <<
274 }; <<
275 <<
276 &cpu2 { <<
277 cpu-supply = <&mt6359_vcore_buck_reg>; <<
278 }; <<
279 <<
280 &cpu3 { <<
281 cpu-supply = <&mt6359_vcore_buck_reg>; <<
282 }; <<
283 <<
284 &cpu4 { <<
285 cpu-supply = <&mt6315_6_vbuck1>; <<
286 }; <<
287 <<
288 &cpu5 { <<
289 cpu-supply = <&mt6315_6_vbuck1>; <<
290 }; <<
291 <<
292 &cpu6 { <<
293 cpu-supply = <&mt6315_6_vbuck1>; <<
294 }; <<
295 <<
296 &cpu7 { <<
297 cpu-supply = <&mt6315_6_vbuck1>; <<
298 }; <<
299 <<
300 &dp_intf0 { <<
301 status = "okay"; <<
302 <<
303 port { <<
304 dp_intf0_out: endpoint { <<
305 remote-endpoint = <&ed <<
306 }; <<
307 }; <<
308 }; <<
309 <<
310 &dp_intf1 { <<
311 status = "okay"; <<
312 <<
313 port { <<
314 dp_intf1_out: endpoint { <<
315 remote-endpoint = <&dp <<
316 }; <<
317 }; <<
318 }; <<
319 <<
320 &edp_tx { <<
321 status = "okay"; <<
322 <<
323 pinctrl-names = "default"; <<
324 pinctrl-0 = <&edptx_pins_default>; <<
325 <<
326 ports { <<
327 #address-cells = <1>; <<
328 #size-cells = <0>; <<
329 <<
330 port@0 { <<
331 reg = <0>; <<
332 edp_in: endpoint { <<
333 remote-endpoin <<
334 }; <<
335 }; <<
336 <<
337 port@1 { <<
338 reg = <1>; <<
339 edp_out: endpoint { <<
340 data-lanes = < <<
341 remote-endpoin <<
342 }; <<
343 }; <<
344 }; <<
345 <<
346 aux-bus { <<
347 panel { <<
348 compatible = "edp-pane <<
349 power-supply = <&pp330 <<
350 backlight = <&backligh <<
351 port { <<
352 panel_in: endp <<
353 remote <<
354 }; <<
355 }; <<
356 }; <<
357 }; <<
358 }; <<
359 <<
360 &disp_pwm0 { <<
361 status = "okay"; <<
362 <<
363 pinctrl-names = "default"; <<
364 pinctrl-0 = <&disp_pwm0_pin_default>; <<
365 }; <<
366 <<
367 &dp_tx { <<
368 status = "okay"; <<
369 <<
370 #sound-dai-cells = <0>; <<
371 pinctrl-names = "default"; <<
372 pinctrl-0 = <&dptx_pin>; <<
373 <<
374 ports { <<
375 #address-cells = <1>; <<
376 #size-cells = <0>; <<
377 <<
378 port@0 { <<
379 reg = <0>; <<
380 dptx_in: endpoint { <<
381 remote-endpoin <<
382 }; <<
383 }; <<
384 <<
385 port@1 { <<
386 reg = <1>; <<
387 dptx_out: endpoint { <<
388 data-lanes = < <<
389 }; <<
390 }; <<
391 }; 120 };
392 }; 121 };
393 122
394 &gic { <<
395 mediatek,broken-save-restore-fw; <<
396 }; <<
397 <<
398 &gpu { <<
399 status = "okay"; <<
400 mali-supply = <&mt6315_7_vbuck1>; <<
401 }; <<
402 <<
403 &i2c0 { 123 &i2c0 {
404 status = "okay"; 124 status = "okay";
405 125
406 clock-frequency = <400000>; 126 clock-frequency = <400000>;
407 pinctrl-names = "default"; 127 pinctrl-names = "default";
408 pinctrl-0 = <&i2c0_pins>; 128 pinctrl-0 = <&i2c0_pins>;
409 }; 129 };
410 130
411 &i2c1 { 131 &i2c1 {
412 status = "okay"; 132 status = "okay";
413 133
414 clock-frequency = <400000>; 134 clock-frequency = <400000>;
415 i2c-scl-internal-delay-ns = <12500>; 135 i2c-scl-internal-delay-ns = <12500>;
416 pinctrl-names = "default"; 136 pinctrl-names = "default";
417 pinctrl-0 = <&i2c1_pins>; 137 pinctrl-0 = <&i2c1_pins>;
418 138
419 trackpad@15 { 139 trackpad@15 {
420 compatible = "elan,ekth3000"; 140 compatible = "elan,ekth3000";
421 reg = <0x15>; 141 reg = <0x15>;
422 interrupts-extended = <&pio 6 142 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
423 pinctrl-names = "default"; 143 pinctrl-names = "default";
424 pinctrl-0 = <&trackpad_pins>; 144 pinctrl-0 = <&trackpad_pins>;
425 vcc-supply = <&pp3300_s3>; 145 vcc-supply = <&pp3300_s3>;
426 wakeup-source; 146 wakeup-source;
427 }; 147 };
428 }; 148 };
429 149
430 &i2c2 { 150 &i2c2 {
431 status = "okay"; 151 status = "okay";
432 152
433 clock-frequency = <400000>; 153 clock-frequency = <400000>;
434 pinctrl-names = "default"; 154 pinctrl-names = "default";
435 pinctrl-0 = <&i2c2_pins>; 155 pinctrl-0 = <&i2c2_pins>;
436 <<
437 audio_codec: codec@1a { <<
438 /* Realtek RT5682i or RT5682s, <<
439 reg = <0x1a>; <<
440 interrupts-extended = <&pio 89 <<
441 #sound-dai-cells = <0>; <<
442 realtek,jd-src = <1>; <<
443 <<
444 AVDD-supply = <&mt6359_vio18_l <<
445 MICVDD-supply = <&pp3300_z2>; <<
446 VBAT-supply = <&pp3300_z5>; <<
447 }; <<
448 }; 156 };
449 157
450 &i2c3 { 158 &i2c3 {
451 status = "okay"; 159 status = "okay";
452 160
453 clock-frequency = <400000>; 161 clock-frequency = <400000>;
454 pinctrl-names = "default"; 162 pinctrl-names = "default";
455 pinctrl-0 = <&i2c3_pins>; 163 pinctrl-0 = <&i2c3_pins>;
456 164
457 tpm@50 { 165 tpm@50 {
458 compatible = "google,cr50"; 166 compatible = "google,cr50";
459 reg = <0x50>; 167 reg = <0x50>;
460 interrupts-extended = <&pio 88 168 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
461 pinctrl-names = "default"; 169 pinctrl-names = "default";
462 pinctrl-0 = <&cr50_int>; 170 pinctrl-0 = <&cr50_int>;
463 }; 171 };
464 }; 172 };
465 173
466 &i2c4 { 174 &i2c4 {
467 status = "okay"; 175 status = "okay";
468 176
469 clock-frequency = <400000>; 177 clock-frequency = <400000>;
470 pinctrl-names = "default"; 178 pinctrl-names = "default";
471 pinctrl-0 = <&i2c4_pins>; 179 pinctrl-0 = <&i2c4_pins>;
472 180
473 ts_10: touchscreen@10 { 181 ts_10: touchscreen@10 {
474 compatible = "hid-over-i2c"; 182 compatible = "hid-over-i2c";
475 reg = <0x10>; 183 reg = <0x10>;
476 hid-descr-addr = <0x0001>; 184 hid-descr-addr = <0x0001>;
477 interrupts-extended = <&pio 92 185 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
478 pinctrl-names = "default"; 186 pinctrl-names = "default";
479 pinctrl-0 = <&touchscreen_pins 187 pinctrl-0 = <&touchscreen_pins>;
480 post-power-on-delay-ms = <10>; 188 post-power-on-delay-ms = <10>;
481 vdd-supply = <&pp3300_s3>; 189 vdd-supply = <&pp3300_s3>;
482 status = "disabled"; 190 status = "disabled";
483 }; 191 };
484 }; 192 };
485 193
486 &i2c5 { 194 &i2c5 {
487 status = "okay"; 195 status = "okay";
488 196
489 clock-frequency = <400000>; 197 clock-frequency = <400000>;
490 pinctrl-names = "default"; 198 pinctrl-names = "default";
491 pinctrl-0 = <&i2c5_pins>; 199 pinctrl-0 = <&i2c5_pins>;
492 }; 200 };
493 201
494 &i2c7 { 202 &i2c7 {
495 status = "okay"; 203 status = "okay";
496 204
497 clock-frequency = <400000>; 205 clock-frequency = <400000>;
498 pinctrl-names = "default"; 206 pinctrl-names = "default";
499 pinctrl-0 = <&i2c7_pins>; 207 pinctrl-0 = <&i2c7_pins>;
500 208
501 pmic@34 { 209 pmic@34 {
502 #interrupt-cells = <2>; 210 #interrupt-cells = <2>;
503 compatible = "mediatek,mt6360" 211 compatible = "mediatek,mt6360";
504 reg = <0x34>; 212 reg = <0x34>;
505 interrupt-controller; 213 interrupt-controller;
506 interrupts-extended = <&pio 13 214 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
507 interrupt-names = "IRQB"; 215 interrupt-names = "IRQB";
508 pinctrl-names = "default"; 216 pinctrl-names = "default";
509 pinctrl-0 = <&subpmic_default> 217 pinctrl-0 = <&subpmic_default>;
510 wakeup-source; 218 wakeup-source;
511 }; 219 };
512 }; 220 };
513 221
514 &mfg0 { <<
515 domain-supply = <&mt6315_7_vbuck1>; <<
516 }; <<
517 <<
518 &mfg1 { <<
519 domain-supply = <&mt6359_vsram_others_ <<
520 }; <<
521 <<
522 &mmc0 { 222 &mmc0 {
523 status = "okay"; 223 status = "okay";
524 224
525 bus-width = <8>; 225 bus-width = <8>;
526 cap-mmc-highspeed; 226 cap-mmc-highspeed;
527 cap-mmc-hw-reset; 227 cap-mmc-hw-reset;
528 hs400-ds-delay = <0x14c11>; 228 hs400-ds-delay = <0x14c11>;
529 max-frequency = <200000000>; 229 max-frequency = <200000000>;
530 mmc-hs200-1_8v; 230 mmc-hs200-1_8v;
531 mmc-hs400-1_8v; 231 mmc-hs400-1_8v;
532 no-sdio; 232 no-sdio;
533 no-sd; 233 no-sd;
534 non-removable; 234 non-removable;
535 pinctrl-names = "default", "state_uhs" 235 pinctrl-names = "default", "state_uhs";
536 pinctrl-0 = <&mmc0_pins_default>; 236 pinctrl-0 = <&mmc0_pins_default>;
537 pinctrl-1 = <&mmc0_pins_uhs>; 237 pinctrl-1 = <&mmc0_pins_uhs>;
538 vmmc-supply = <&mt6359_vemc_1_ldo_reg> 238 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
539 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 239 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
540 }; 240 };
541 241
542 &mmc1 { 242 &mmc1 {
543 status = "okay"; 243 status = "okay";
544 244
545 bus-width = <4>; 245 bus-width = <4>;
546 cap-sd-highspeed; 246 cap-sd-highspeed;
547 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 247 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
548 max-frequency = <200000000>; 248 max-frequency = <200000000>;
549 no-mmc; 249 no-mmc;
550 no-sdio; 250 no-sdio;
551 pinctrl-names = "default", "state_uhs" 251 pinctrl-names = "default", "state_uhs";
552 pinctrl-0 = <&mmc1_pins_default>, <&mm 252 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
553 pinctrl-1 = <&mmc1_pins_default>; 253 pinctrl-1 = <&mmc1_pins_default>;
554 sd-uhs-sdr50; 254 sd-uhs-sdr50;
555 sd-uhs-sdr104; 255 sd-uhs-sdr104;
556 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 256 vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
557 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 257 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
558 }; 258 };
559 259
560 &mt6359codec { <<
561 mediatek,dmic-mode = <1>; /* one-wire <<
562 mediatek,mic-type-0 = <2>; /* DMIC */ <<
563 }; <<
564 <<
565 /* for CPU-L */ 260 /* for CPU-L */
566 &mt6359_vcore_buck_reg { 261 &mt6359_vcore_buck_reg {
567 regulator-always-on; 262 regulator-always-on;
568 }; 263 };
569 264
570 /* for CORE */ 265 /* for CORE */
571 &mt6359_vgpu11_buck_reg { 266 &mt6359_vgpu11_buck_reg {
572 regulator-always-on; 267 regulator-always-on;
573 }; 268 };
574 269
575 &mt6359_vgpu11_sshub_buck_reg { 270 &mt6359_vgpu11_sshub_buck_reg {
576 regulator-always-on; 271 regulator-always-on;
577 regulator-min-microvolt = <550000>; 272 regulator-min-microvolt = <550000>;
578 regulator-max-microvolt = <550000>; 273 regulator-max-microvolt = <550000>;
579 }; 274 };
580 275
581 /* for CORE SRAM */ 276 /* for CORE SRAM */
582 &mt6359_vpu_buck_reg { 277 &mt6359_vpu_buck_reg {
583 regulator-always-on; 278 regulator-always-on;
584 }; 279 };
585 280
586 &mt6359_vrf12_ldo_reg { 281 &mt6359_vrf12_ldo_reg {
587 regulator-always-on; 282 regulator-always-on;
588 }; 283 };
589 284
590 /* for GPU SRAM */ 285 /* for GPU SRAM */
591 &mt6359_vsram_others_ldo_reg { 286 &mt6359_vsram_others_ldo_reg {
>> 287 regulator-always-on;
592 regulator-min-microvolt = <750000>; 288 regulator-min-microvolt = <750000>;
593 regulator-max-microvolt = <750000>; 289 regulator-max-microvolt = <750000>;
594 }; 290 };
595 291
596 &mt6359_vufs_ldo_reg { 292 &mt6359_vufs_ldo_reg {
597 regulator-always-on; 293 regulator-always-on;
598 }; 294 };
599 295
600 &nor_flash { 296 &nor_flash {
601 status = "okay"; 297 status = "okay";
602 298
603 pinctrl-names = "default"; 299 pinctrl-names = "default";
604 pinctrl-0 = <&nor_pins_default>; 300 pinctrl-0 = <&nor_pins_default>;
605 301
606 flash@0 { 302 flash@0 {
607 compatible = "jedec,spi-nor"; 303 compatible = "jedec,spi-nor";
608 reg = <0>; 304 reg = <0>;
609 spi-max-frequency = <52000000> 305 spi-max-frequency = <52000000>;
610 spi-rx-bus-width = <2>; 306 spi-rx-bus-width = <2>;
611 spi-tx-bus-width = <2>; 307 spi-tx-bus-width = <2>;
612 }; 308 };
613 }; 309 };
614 310
615 &pcie1 { <<
616 status = "okay"; <<
617 <<
618 pinctrl-names = "default"; <<
619 pinctrl-0 = <&pcie1_pins_default>; <<
620 }; <<
621 <<
622 &pio { 311 &pio {
623 mediatek,rsel-resistance-in-si-unit; 312 mediatek,rsel-resistance-in-si-unit;
624 pinctrl-names = "default"; 313 pinctrl-names = "default";
625 pinctrl-0 = <&pio_default>; 314 pinctrl-0 = <&pio_default>;
626 315
627 /* 144 lines */ 316 /* 144 lines */
628 gpio-line-names = 317 gpio-line-names =
629 "I2S_SPKR_MCLK", 318 "I2S_SPKR_MCLK",
630 "I2S_SPKR_DATAIN", 319 "I2S_SPKR_DATAIN",
631 "I2S_SPKR_LRCK", 320 "I2S_SPKR_LRCK",
632 "I2S_SPKR_BCLK", 321 "I2S_SPKR_BCLK",
633 "EC_AP_INT_ODL", 322 "EC_AP_INT_ODL",
634 /* 323 /*
635 * AP_FLASH_WP_L is crossystem 324 * AP_FLASH_WP_L is crossystem ABI. Schematics
636 * call it AP_FLASH_WP_ODL. 325 * call it AP_FLASH_WP_ODL.
637 */ 326 */
638 "AP_FLASH_WP_L", 327 "AP_FLASH_WP_L",
639 "TCHPAD_INT_ODL", 328 "TCHPAD_INT_ODL",
640 "EDP_HPD_1V8", 329 "EDP_HPD_1V8",
641 "AP_I2C_CAM_SDA", 330 "AP_I2C_CAM_SDA",
642 "AP_I2C_CAM_SCL", 331 "AP_I2C_CAM_SCL",
643 "AP_I2C_TCHPAD_SDA_1V8", 332 "AP_I2C_TCHPAD_SDA_1V8",
644 "AP_I2C_TCHPAD_SCL_1V8", 333 "AP_I2C_TCHPAD_SCL_1V8",
645 "AP_I2C_AUD_SDA", 334 "AP_I2C_AUD_SDA",
646 "AP_I2C_AUD_SCL", 335 "AP_I2C_AUD_SCL",
647 "AP_I2C_TPM_SDA_1V8", 336 "AP_I2C_TPM_SDA_1V8",
648 "AP_I2C_TPM_SCL_1V8", 337 "AP_I2C_TPM_SCL_1V8",
649 "AP_I2C_TCHSCR_SDA_1V8", 338 "AP_I2C_TCHSCR_SDA_1V8",
650 "AP_I2C_TCHSCR_SCL_1V8", 339 "AP_I2C_TCHSCR_SCL_1V8",
651 "EC_AP_HPD_OD", 340 "EC_AP_HPD_OD",
652 "", 341 "",
653 "PCIE_NVME_RST_L", 342 "PCIE_NVME_RST_L",
654 "PCIE_NVME_CLKREQ_ODL", 343 "PCIE_NVME_CLKREQ_ODL",
655 "PCIE_RST_1V8_L", 344 "PCIE_RST_1V8_L",
656 "PCIE_CLKREQ_1V8_ODL", 345 "PCIE_CLKREQ_1V8_ODL",
657 "PCIE_WAKE_1V8_ODL", 346 "PCIE_WAKE_1V8_ODL",
658 "CLK_24M_CAM0", 347 "CLK_24M_CAM0",
659 "CAM1_SEN_EN", 348 "CAM1_SEN_EN",
660 "AP_I2C_PWR_SCL_1V8", 349 "AP_I2C_PWR_SCL_1V8",
661 "AP_I2C_PWR_SDA_1V8", 350 "AP_I2C_PWR_SDA_1V8",
662 "AP_I2C_MISC_SCL", 351 "AP_I2C_MISC_SCL",
663 "AP_I2C_MISC_SDA", 352 "AP_I2C_MISC_SDA",
664 "EN_PP5000_HDMI_X", 353 "EN_PP5000_HDMI_X",
665 "AP_HDMITX_HTPLG", 354 "AP_HDMITX_HTPLG",
666 "", 355 "",
667 "AP_HDMITX_SCL_1V8", 356 "AP_HDMITX_SCL_1V8",
668 "AP_HDMITX_SDA_1V8", 357 "AP_HDMITX_SDA_1V8",
669 "AP_RTC_CLK32K", 358 "AP_RTC_CLK32K",
670 "AP_EC_WATCHDOG_L", 359 "AP_EC_WATCHDOG_L",
671 "SRCLKENA0", 360 "SRCLKENA0",
672 "SRCLKENA1", 361 "SRCLKENA1",
673 "PWRAP_SPI0_CS_L", 362 "PWRAP_SPI0_CS_L",
674 "PWRAP_SPI0_CK", 363 "PWRAP_SPI0_CK",
675 "PWRAP_SPI0_MOSI", 364 "PWRAP_SPI0_MOSI",
676 "PWRAP_SPI0_MISO", 365 "PWRAP_SPI0_MISO",
677 "SPMI_SCL", 366 "SPMI_SCL",
678 "SPMI_SDA", 367 "SPMI_SDA",
679 "", 368 "",
680 "", 369 "",
681 "", 370 "",
682 "I2S_HP_DATAIN", 371 "I2S_HP_DATAIN",
683 "I2S_HP_MCLK", 372 "I2S_HP_MCLK",
684 "I2S_HP_BCK", 373 "I2S_HP_BCK",
685 "I2S_HP_LRCK", 374 "I2S_HP_LRCK",
686 "I2S_HP_DATAOUT", 375 "I2S_HP_DATAOUT",
687 "SD_CD_ODL", 376 "SD_CD_ODL",
688 "EN_PP3300_DISP_X", 377 "EN_PP3300_DISP_X",
689 "TCHSCR_RST_1V8_L", 378 "TCHSCR_RST_1V8_L",
690 "TCHSCR_REPORT_DISABLE", 379 "TCHSCR_REPORT_DISABLE",
691 "EN_PP3300_WLAN_X", 380 "EN_PP3300_WLAN_X",
692 "BT_KILL_1V8_L", 381 "BT_KILL_1V8_L",
693 "I2S_SPKR_DATAOUT", 382 "I2S_SPKR_DATAOUT",
694 "WIFI_KILL_1V8_L", 383 "WIFI_KILL_1V8_L",
695 "BEEP_ON", 384 "BEEP_ON",
696 "SCP_I2C_SENSOR_SCL_1V8", 385 "SCP_I2C_SENSOR_SCL_1V8",
697 "SCP_I2C_SENSOR_SDA_1V8", 386 "SCP_I2C_SENSOR_SDA_1V8",
698 "", 387 "",
699 "", 388 "",
700 "", 389 "",
701 "", 390 "",
702 "AUD_CLK_MOSI", 391 "AUD_CLK_MOSI",
703 "AUD_SYNC_MOSI", 392 "AUD_SYNC_MOSI",
704 "AUD_DAT_MOSI0", 393 "AUD_DAT_MOSI0",
705 "AUD_DAT_MOSI1", 394 "AUD_DAT_MOSI1",
706 "AUD_DAT_MISO0", 395 "AUD_DAT_MISO0",
707 "AUD_DAT_MISO1", 396 "AUD_DAT_MISO1",
708 "AUD_DAT_MISO2", 397 "AUD_DAT_MISO2",
709 "SCP_VREQ_VAO", 398 "SCP_VREQ_VAO",
710 "AP_SPI_GSC_TPM_CLK", 399 "AP_SPI_GSC_TPM_CLK",
711 "AP_SPI_GSC_TPM_MOSI", 400 "AP_SPI_GSC_TPM_MOSI",
712 "AP_SPI_GSC_TPM_CS_L", 401 "AP_SPI_GSC_TPM_CS_L",
713 "AP_SPI_GSC_TPM_MISO", 402 "AP_SPI_GSC_TPM_MISO",
714 "EN_PP1000_CAM_X", 403 "EN_PP1000_CAM_X",
715 "AP_EDP_BKLTEN", 404 "AP_EDP_BKLTEN",
716 "", 405 "",
717 "USB3_HUB_RST_L", 406 "USB3_HUB_RST_L",
718 "", 407 "",
719 "WLAN_ALERT_ODL", 408 "WLAN_ALERT_ODL",
720 "EC_IN_RW_ODL", 409 "EC_IN_RW_ODL",
721 "GSC_AP_INT_ODL", 410 "GSC_AP_INT_ODL",
722 "HP_INT_ODL", 411 "HP_INT_ODL",
723 "CAM0_RST_L", 412 "CAM0_RST_L",
724 "CAM1_RST_L", 413 "CAM1_RST_L",
725 "TCHSCR_INT_1V8_L", 414 "TCHSCR_INT_1V8_L",
726 "CAM1_DET_L", 415 "CAM1_DET_L",
727 "RST_ALC1011_L", 416 "RST_ALC1011_L",
728 "", 417 "",
729 "", 418 "",
730 "BL_PWM_1V8", 419 "BL_PWM_1V8",
731 "UART_AP_TX_DBG_RX", 420 "UART_AP_TX_DBG_RX",
732 "UART_DBG_TX_AP_RX", 421 "UART_DBG_TX_AP_RX",
733 "EN_SPKR", 422 "EN_SPKR",
734 "AP_EC_WARM_RST_REQ", 423 "AP_EC_WARM_RST_REQ",
735 "UART_SCP_TX_DBGCON_RX", 424 "UART_SCP_TX_DBGCON_RX",
736 "UART_DBGCON_TX_SCP_RX", 425 "UART_DBGCON_TX_SCP_RX",
737 "", 426 "",
738 "", 427 "",
739 "KPCOL0", 428 "KPCOL0",
740 "", 429 "",
741 "MT6315_GPU_INT", 430 "MT6315_GPU_INT",
742 "MT6315_PROC_BC_INT", 431 "MT6315_PROC_BC_INT",
743 "SD_CMD", 432 "SD_CMD",
744 "SD_CLK", 433 "SD_CLK",
745 "SD_DAT0", 434 "SD_DAT0",
746 "SD_DAT1", 435 "SD_DAT1",
747 "SD_DAT2", 436 "SD_DAT2",
748 "SD_DAT3", 437 "SD_DAT3",
749 "EMMC_DAT7", 438 "EMMC_DAT7",
750 "EMMC_DAT6", 439 "EMMC_DAT6",
751 "EMMC_DAT5", 440 "EMMC_DAT5",
752 "EMMC_DAT4", 441 "EMMC_DAT4",
753 "EMMC_RSTB", 442 "EMMC_RSTB",
754 "EMMC_CMD", 443 "EMMC_CMD",
755 "EMMC_CLK", 444 "EMMC_CLK",
756 "EMMC_DAT3", 445 "EMMC_DAT3",
757 "EMMC_DAT2", 446 "EMMC_DAT2",
758 "EMMC_DAT1", 447 "EMMC_DAT1",
759 "EMMC_DAT0", 448 "EMMC_DAT0",
760 "EMMC_DSL", 449 "EMMC_DSL",
761 "", 450 "",
762 "", 451 "",
763 "MT6360_INT_ODL", 452 "MT6360_INT_ODL",
764 "SCP_JTAG0_TRSTN", 453 "SCP_JTAG0_TRSTN",
765 "AP_SPI_EC_CS_L", 454 "AP_SPI_EC_CS_L",
766 "AP_SPI_EC_CLK", 455 "AP_SPI_EC_CLK",
767 "AP_SPI_EC_MOSI", 456 "AP_SPI_EC_MOSI",
768 "AP_SPI_EC_MISO", 457 "AP_SPI_EC_MISO",
769 "SCP_JTAG0_TMS", 458 "SCP_JTAG0_TMS",
770 "SCP_JTAG0_TCK", 459 "SCP_JTAG0_TCK",
771 "SCP_JTAG0_TDO", 460 "SCP_JTAG0_TDO",
772 "SCP_JTAG0_TDI", 461 "SCP_JTAG0_TDI",
773 "AP_SPI_FLASH_CS_L", 462 "AP_SPI_FLASH_CS_L",
774 "AP_SPI_FLASH_CLK", 463 "AP_SPI_FLASH_CLK",
775 "AP_SPI_FLASH_MOSI", 464 "AP_SPI_FLASH_MOSI",
776 "AP_SPI_FLASH_MISO"; 465 "AP_SPI_FLASH_MISO";
777 466
778 aud_pins_default: audio-default-pins { <<
779 pins-cmd-dat { <<
780 pinmux = <PINMUX_GPIO69__F <<
781 <PINMUX_GPIO70__F <<
782 <PINMUX_GPIO71__F <<
783 <PINMUX_GPIO72__F <<
784 <PINMUX_GPIO73__F <<
785 <PINMUX_GPIO74__F <<
786 <PINMUX_GPIO75__F <<
787 <PINMUX_GPIO0__FU <<
788 <PINMUX_GPIO1__FU <<
789 <PINMUX_GPIO2__FU <<
790 <PINMUX_GPIO3__FU <<
791 <PINMUX_GPIO60__F <<
792 <PINMUX_GPIO49__F <<
793 <PINMUX_GPIO50__F <<
794 <PINMUX_GPIO51__F <<
795 <PINMUX_GPIO52__F <<
796 <PINMUX_GPIO53__F <<
797 }; <<
798 <<
799 pins-hp-jack-int-odl { <<
800 pinmux = <PINMUX_GPIO8 <<
801 input-enable; <<
802 bias-pull-up = <MTK_PU <<
803 }; <<
804 }; <<
805 <<
806 cr50_int: cr50-irq-default-pins { 467 cr50_int: cr50-irq-default-pins {
807 pins-gsc-ap-int-odl { 468 pins-gsc-ap-int-odl {
808 pinmux = <PINMUX_GPIO8 469 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
809 input-enable; 470 input-enable;
810 }; 471 };
811 }; 472 };
812 473
813 cros_ec_int: cros-ec-irq-default-pins 474 cros_ec_int: cros-ec-irq-default-pins {
814 pins-ec-ap-int-odl { 475 pins-ec-ap-int-odl {
815 pinmux = <PINMUX_GPIO4 476 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
816 bias-pull-up = <MTK_PU 477 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
817 input-enable; 478 input-enable;
818 }; 479 };
819 }; 480 };
820 481
821 edptx_pins_default: edptx-default-pins <<
822 pins-cmd-dat { <<
823 pinmux = <PINMUX_GPIO7 <<
824 bias-pull-up; <<
825 }; <<
826 }; <<
827 <<
828 disp_pwm0_pin_default: disp-pwm0-defau <<
829 pins-disp-pwm { <<
830 pinmux = <PINMUX_GPIO8 <<
831 <PINMUX_GPIO9 <<
832 }; <<
833 }; <<
834 <<
835 dptx_pin: dptx-default-pins { <<
836 pins-cmd-dat { <<
837 pinmux = <PINMUX_GPIO1 <<
838 bias-pull-up; <<
839 }; <<
840 }; <<
841 <<
842 i2c0_pins: i2c0-default-pins { 482 i2c0_pins: i2c0-default-pins {
843 pins-bus { 483 pins-bus {
844 pinmux = <PINMUX_GPIO8 484 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
845 <PINMUX_GPIO9 485 <PINMUX_GPIO9__FUNC_SCL0>;
846 bias-disable; 486 bias-disable;
847 drive-strength-microam 487 drive-strength-microamp = <1000>;
848 }; 488 };
849 }; 489 };
850 490
851 i2c1_pins: i2c1-default-pins { 491 i2c1_pins: i2c1-default-pins {
852 pins-bus { 492 pins-bus {
853 pinmux = <PINMUX_GPIO1 493 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
854 <PINMUX_GPIO1 494 <PINMUX_GPIO11__FUNC_SCL1>;
855 bias-pull-up = <1000>; 495 bias-pull-up = <1000>;
856 drive-strength-microam 496 drive-strength-microamp = <1000>;
857 }; 497 };
858 }; 498 };
859 499
860 i2c2_pins: i2c2-default-pins { 500 i2c2_pins: i2c2-default-pins {
861 pins-bus { 501 pins-bus {
862 pinmux = <PINMUX_GPIO1 502 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
863 <PINMUX_GPIO1 503 <PINMUX_GPIO13__FUNC_SCL2>;
864 bias-disable; 504 bias-disable;
865 drive-strength-microam 505 drive-strength-microamp = <1000>;
866 }; 506 };
867 }; 507 };
868 508
869 i2c3_pins: i2c3-default-pins { 509 i2c3_pins: i2c3-default-pins {
870 pins-bus { 510 pins-bus {
871 pinmux = <PINMUX_GPIO1 511 pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
872 <PINMUX_GPIO1 512 <PINMUX_GPIO15__FUNC_SCL3>;
873 bias-pull-up = <1000>; 513 bias-pull-up = <1000>;
874 drive-strength-microam 514 drive-strength-microamp = <1000>;
875 }; 515 };
876 }; 516 };
877 517
878 i2c4_pins: i2c4-default-pins { 518 i2c4_pins: i2c4-default-pins {
879 pins-bus { 519 pins-bus {
880 pinmux = <PINMUX_GPIO1 520 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
881 <PINMUX_GPIO1 521 <PINMUX_GPIO17__FUNC_SCL4>;
882 bias-pull-up = <1000>; 522 bias-pull-up = <1000>;
883 drive-strength = <4>; 523 drive-strength = <4>;
884 }; 524 };
885 }; 525 };
886 526
887 i2c5_pins: i2c5-default-pins { 527 i2c5_pins: i2c5-default-pins {
888 pins-bus { 528 pins-bus {
889 pinmux = <PINMUX_GPIO2 529 pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
890 <PINMUX_GPIO3 530 <PINMUX_GPIO30__FUNC_SDA5>;
891 bias-disable; 531 bias-disable;
892 drive-strength-microam 532 drive-strength-microamp = <1000>;
893 }; 533 };
894 }; 534 };
895 535
896 i2c7_pins: i2c7-default-pins { 536 i2c7_pins: i2c7-default-pins {
897 pins-bus { 537 pins-bus {
898 pinmux = <PINMUX_GPIO2 538 pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
899 <PINMUX_GPIO2 539 <PINMUX_GPIO28__FUNC_SDA7>;
900 bias-disable; 540 bias-disable;
901 }; 541 };
902 }; 542 };
903 543
904 mmc0_pins_default: mmc0-default-pins { 544 mmc0_pins_default: mmc0-default-pins {
905 pins-cmd-dat { 545 pins-cmd-dat {
906 pinmux = <PINMUX_GPIO1 546 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
907 <PINMUX_GPIO1 547 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
908 <PINMUX_GPIO1 548 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
909 <PINMUX_GPIO1 549 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
910 <PINMUX_GPIO1 550 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
911 <PINMUX_GPIO1 551 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
912 <PINMUX_GPIO1 552 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
913 <PINMUX_GPIO1 553 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
914 <PINMUX_GPIO1 554 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
915 input-enable; 555 input-enable;
916 drive-strength = <6>; 556 drive-strength = <6>;
917 bias-pull-up = <MTK_PU 557 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
918 }; 558 };
919 559
920 pins-clk { 560 pins-clk {
921 pinmux = <PINMUX_GPIO1 561 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
922 drive-strength = <6>; 562 drive-strength = <6>;
923 bias-pull-down = <MTK_ 563 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
924 }; 564 };
925 565
926 pins-rst { 566 pins-rst {
927 pinmux = <PINMUX_GPIO1 567 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
928 drive-strength = <6>; 568 drive-strength = <6>;
929 bias-pull-up = <MTK_PU 569 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
930 }; 570 };
931 }; 571 };
932 572
933 mmc0_pins_uhs: mmc0-uhs-pins { 573 mmc0_pins_uhs: mmc0-uhs-pins {
934 pins-cmd-dat { 574 pins-cmd-dat {
935 pinmux = <PINMUX_GPIO1 575 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
936 <PINMUX_GPIO1 576 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
937 <PINMUX_GPIO1 577 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
938 <PINMUX_GPIO1 578 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
939 <PINMUX_GPIO1 579 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
940 <PINMUX_GPIO1 580 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
941 <PINMUX_GPIO1 581 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
942 <PINMUX_GPIO1 582 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
943 <PINMUX_GPIO1 583 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
944 input-enable; 584 input-enable;
945 drive-strength = <8>; 585 drive-strength = <8>;
946 bias-pull-up = <MTK_PU 586 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
947 }; 587 };
948 588
949 pins-clk { 589 pins-clk {
950 pinmux = <PINMUX_GPIO1 590 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
951 drive-strength = <8>; 591 drive-strength = <8>;
952 bias-pull-down = <MTK_ 592 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
953 }; 593 };
954 594
955 pins-ds { 595 pins-ds {
956 pinmux = <PINMUX_GPIO1 596 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
957 drive-strength = <8>; 597 drive-strength = <8>;
958 bias-pull-down = <MTK_ 598 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
959 }; 599 };
960 600
961 pins-rst { 601 pins-rst {
962 pinmux = <PINMUX_GPIO1 602 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
963 drive-strength = <8>; 603 drive-strength = <8>;
964 bias-pull-up = <MTK_PU 604 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
965 }; 605 };
966 }; 606 };
967 607
968 mmc1_pins_detect: mmc1-detect-pins { 608 mmc1_pins_detect: mmc1-detect-pins {
969 pins-insert { 609 pins-insert {
970 pinmux = <PINMUX_GPIO5 610 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
971 bias-pull-up; 611 bias-pull-up;
972 }; 612 };
973 }; 613 };
974 614
975 mmc1_pins_default: mmc1-default-pins { 615 mmc1_pins_default: mmc1-default-pins {
976 pins-cmd-dat { 616 pins-cmd-dat {
977 pinmux = <PINMUX_GPIO1 617 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
978 <PINMUX_GPIO1 618 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
979 <PINMUX_GPIO1 619 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
980 <PINMUX_GPIO1 620 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
981 <PINMUX_GPIO1 621 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
982 input-enable; 622 input-enable;
983 drive-strength = <8>; 623 drive-strength = <8>;
984 bias-pull-up = <MTK_PU 624 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
985 }; 625 };
986 626
987 pins-clk { 627 pins-clk {
988 pinmux = <PINMUX_GPIO1 628 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
989 drive-strength = <8>; 629 drive-strength = <8>;
990 bias-pull-down = <MTK_ 630 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
991 }; 631 };
992 }; 632 };
993 633
994 nor_pins_default: nor-default-pins { 634 nor_pins_default: nor-default-pins {
995 pins-ck-io { 635 pins-ck-io {
996 pinmux = <PINMUX_GPIO1 636 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
997 <PINMUX_GPIO1 637 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
998 <PINMUX_GPIO1 638 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
999 drive-strength = <6>; 639 drive-strength = <6>;
1000 bias-pull-down; 640 bias-pull-down;
1001 }; 641 };
1002 642
1003 pins-cs { 643 pins-cs {
1004 pinmux = <PINMUX_GPIO 644 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
1005 drive-strength = <6>; 645 drive-strength = <6>;
1006 bias-pull-up; 646 bias-pull-up;
1007 }; 647 };
1008 }; 648 };
1009 649
1010 pcie0_pins_default: pcie0-default-pin <<
1011 pins-bus { <<
1012 pinmux = <PINMUX_GPIO <<
1013 <PINMUX_GPIO <<
1014 <PINMUX_GPIO <<
1015 bias-pull-up <<
1016 }; <<
1017 }; <<
1018 <<
1019 pcie1_pins_default: pcie1-default-pin <<
1020 pins-bus { <<
1021 pinmux = <PINMUX_GPIO <<
1022 <PINMUX_GPIO <<
1023 <PINMUX_GPIO <<
1024 bias-pull-up <<
1025 }; <<
1026 }; <<
1027 <<
1028 panel_fixed_pins: panel-pwr-default-p <<
1029 pins-vreg-en { <<
1030 pinmux = <PINMUX_GPIO <<
1031 }; <<
1032 }; <<
1033 <<
1034 pio_default: pio-default-pins { 650 pio_default: pio-default-pins {
1035 pins-wifi-enable { 651 pins-wifi-enable {
1036 pinmux = <PINMUX_GPIO 652 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
1037 output-high; 653 output-high;
1038 drive-strength = <14> 654 drive-strength = <14>;
1039 }; 655 };
1040 656
1041 pins-low-power-pd { 657 pins-low-power-pd {
1042 pinmux = <PINMUX_GPIO 658 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
1043 <PINMUX_GPIO 659 <PINMUX_GPIO26__FUNC_GPIO26>,
1044 <PINMUX_GPIO 660 <PINMUX_GPIO46__FUNC_GPIO46>,
1045 <PINMUX_GPIO 661 <PINMUX_GPIO47__FUNC_GPIO47>,
1046 <PINMUX_GPIO 662 <PINMUX_GPIO48__FUNC_GPIO48>,
1047 <PINMUX_GPIO 663 <PINMUX_GPIO65__FUNC_GPIO65>,
1048 <PINMUX_GPIO 664 <PINMUX_GPIO66__FUNC_GPIO66>,
1049 <PINMUX_GPIO 665 <PINMUX_GPIO67__FUNC_GPIO67>,
1050 <PINMUX_GPIO 666 <PINMUX_GPIO68__FUNC_GPIO68>,
1051 <PINMUX_GPIO 667 <PINMUX_GPIO128__FUNC_GPIO128>,
1052 <PINMUX_GPIO 668 <PINMUX_GPIO129__FUNC_GPIO129>;
1053 input-enable; 669 input-enable;
1054 bias-pull-down; 670 bias-pull-down;
1055 }; 671 };
1056 672
1057 pins-low-power-pupd { 673 pins-low-power-pupd {
1058 pinmux = <PINMUX_GPIO 674 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
1059 <PINMUX_GPIO 675 <PINMUX_GPIO78__FUNC_GPIO78>,
1060 <PINMUX_GPIO 676 <PINMUX_GPIO79__FUNC_GPIO79>,
1061 <PINMUX_GPIO 677 <PINMUX_GPIO80__FUNC_GPIO80>,
1062 <PINMUX_GPIO 678 <PINMUX_GPIO83__FUNC_GPIO83>,
1063 <PINMUX_GPIO 679 <PINMUX_GPIO85__FUNC_GPIO85>,
1064 <PINMUX_GPIO 680 <PINMUX_GPIO90__FUNC_GPIO90>,
1065 <PINMUX_GPIO 681 <PINMUX_GPIO91__FUNC_GPIO91>,
1066 <PINMUX_GPIO 682 <PINMUX_GPIO93__FUNC_GPIO93>,
1067 <PINMUX_GPIO 683 <PINMUX_GPIO94__FUNC_GPIO94>,
1068 <PINMUX_GPIO 684 <PINMUX_GPIO95__FUNC_GPIO95>,
1069 <PINMUX_GPIO 685 <PINMUX_GPIO96__FUNC_GPIO96>,
1070 <PINMUX_GPIO 686 <PINMUX_GPIO104__FUNC_GPIO104>,
1071 <PINMUX_GPIO 687 <PINMUX_GPIO105__FUNC_GPIO105>,
1072 <PINMUX_GPIO 688 <PINMUX_GPIO107__FUNC_GPIO107>;
1073 input-enable; 689 input-enable;
1074 bias-pull-down = <MTK 690 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1075 }; 691 };
1076 }; 692 };
1077 693
1078 rt1019p_pins_default: rt1019p-default <<
1079 pins-amp-sdb { <<
1080 pinmux = <PINMUX_GPIO <<
1081 output-low; <<
1082 }; <<
1083 }; <<
1084 <<
1085 scp_pins: scp-default-pins { 694 scp_pins: scp-default-pins {
1086 pins-vreq { 695 pins-vreq {
1087 pinmux = <PINMUX_GPIO 696 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
1088 bias-disable; 697 bias-disable;
1089 input-enable; 698 input-enable;
1090 }; 699 };
1091 }; 700 };
1092 701
1093 spi0_pins: spi0-default-pins { 702 spi0_pins: spi0-default-pins {
1094 pins-cs-mosi-clk { 703 pins-cs-mosi-clk {
1095 pinmux = <PINMUX_GPIO 704 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
1096 <PINMUX_GPIO 705 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
1097 <PINMUX_GPIO 706 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
1098 bias-disable; 707 bias-disable;
1099 }; 708 };
1100 709
1101 pins-miso { 710 pins-miso {
1102 pinmux = <PINMUX_GPIO 711 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
1103 bias-pull-down; 712 bias-pull-down;
1104 }; 713 };
1105 }; 714 };
1106 715
1107 subpmic_default: subpmic-default-pins 716 subpmic_default: subpmic-default-pins {
1108 subpmic_pin_irq: pins-subpmic 717 subpmic_pin_irq: pins-subpmic-int-n {
1109 pinmux = <PINMUX_GPIO 718 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
1110 input-enable; 719 input-enable;
1111 bias-pull-up; 720 bias-pull-up;
1112 }; 721 };
1113 }; 722 };
1114 723
1115 trackpad_pins: trackpad-default-pins 724 trackpad_pins: trackpad-default-pins {
1116 pins-int-n { 725 pins-int-n {
1117 pinmux = <PINMUX_GPIO 726 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
1118 input-enable; 727 input-enable;
1119 bias-pull-up; 728 bias-pull-up;
1120 }; 729 };
1121 }; 730 };
1122 731
1123 touchscreen_pins: touchscreen-default 732 touchscreen_pins: touchscreen-default-pins {
1124 pins-int-n { 733 pins-int-n {
1125 pinmux = <PINMUX_GPIO 734 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
1126 input-enable; 735 input-enable;
1127 bias-pull-up = <MTK_P 736 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1128 }; 737 };
1129 pins-rst { 738 pins-rst {
1130 pinmux = <PINMUX_GPIO 739 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
1131 output-high; 740 output-high;
1132 }; 741 };
1133 pins-report-sw { 742 pins-report-sw {
1134 pinmux = <PINMUX_GPIO 743 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
1135 output-low; 744 output-low;
1136 }; 745 };
1137 }; 746 };
1138 }; 747 };
1139 748
1140 &pmic { 749 &pmic {
1141 interrupts-extended = <&pio 222 IRQ_T 750 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1142 }; 751 };
1143 752
1144 &scp { 753 &scp {
1145 status = "okay"; 754 status = "okay";
1146 755
1147 firmware-name = "mediatek/mt8195/scp. 756 firmware-name = "mediatek/mt8195/scp.img";
1148 memory-region = <&scp_mem>; 757 memory-region = <&scp_mem>;
1149 pinctrl-names = "default"; 758 pinctrl-names = "default";
1150 pinctrl-0 = <&scp_pins>; 759 pinctrl-0 = <&scp_pins>;
1151 760
1152 cros-ec-rpmsg { 761 cros-ec-rpmsg {
1153 compatible = "google,cros-ec- 762 compatible = "google,cros-ec-rpmsg";
1154 mediatek,rpmsg-name = "cros-e 763 mediatek,rpmsg-name = "cros-ec-rpmsg";
1155 }; 764 };
1156 }; 765 };
1157 766
1158 &sound { <<
1159 status = "okay"; <<
1160 <<
1161 mediatek,adsp = <&adsp>; <<
1162 mediatek,dai-link = <<
1163 "DL10_FE", "DPTX_BE", "ETDM1_ <<
1164 "ETDM1_OUT_BE", "ETDM2_OUT_BE <<
1165 "AFE_SOF_DL2", "AFE_SOF_DL3", <<
1166 pinctrl-names = "default"; <<
1167 pinctrl-0 = <&aud_pins_default>; <<
1168 <<
1169 audio-routing = <<
1170 "Headphone", "HPOL", <<
1171 "Headphone", "HPOR", <<
1172 "IN1P", "Headset Mic", <<
1173 "Ext Spk", "Speaker"; <<
1174 <<
1175 mm-dai-link { <<
1176 link-name = "ETDM1_IN_BE"; <<
1177 mediatek,clk-provider = "cpu" <<
1178 }; <<
1179 <<
1180 hs-playback-dai-link { <<
1181 link-name = "ETDM1_OUT_BE"; <<
1182 mediatek,clk-provider = "cpu" <<
1183 codec { <<
1184 sound-dai = <&audio_c <<
1185 }; <<
1186 }; <<
1187 <<
1188 hs-capture-dai-link { <<
1189 link-name = "ETDM2_IN_BE"; <<
1190 mediatek,clk-provider = "cpu" <<
1191 codec { <<
1192 sound-dai = <&audio_c <<
1193 }; <<
1194 }; <<
1195 <<
1196 spk-playback-dai-link { <<
1197 link-name = "ETDM2_OUT_BE"; <<
1198 mediatek,clk-provider = "cpu" <<
1199 codec { <<
1200 sound-dai = <&spk_amp <<
1201 }; <<
1202 }; <<
1203 <<
1204 displayport-dai-link { <<
1205 link-name = "DPTX_BE"; <<
1206 codec { <<
1207 sound-dai = <&dp_tx>; <<
1208 }; <<
1209 }; <<
1210 }; <<
1211 <<
1212 &spi0 { 767 &spi0 {
1213 status = "okay"; 768 status = "okay";
1214 769
1215 pinctrl-names = "default"; 770 pinctrl-names = "default";
1216 pinctrl-0 = <&spi0_pins>; 771 pinctrl-0 = <&spi0_pins>;
1217 mediatek,pad-select = <0>; 772 mediatek,pad-select = <0>;
1218 773
1219 cros_ec: ec@0 { 774 cros_ec: ec@0 {
1220 #address-cells = <1>; 775 #address-cells = <1>;
1221 #size-cells = <0>; 776 #size-cells = <0>;
1222 777
1223 compatible = "google,cros-ec- 778 compatible = "google,cros-ec-spi";
1224 reg = <0>; 779 reg = <0>;
1225 interrupts-extended = <&pio 4 780 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
1226 pinctrl-names = "default"; 781 pinctrl-names = "default";
1227 pinctrl-0 = <&cros_ec_int>; 782 pinctrl-0 = <&cros_ec_int>;
1228 spi-max-frequency = <3000000> 783 spi-max-frequency = <3000000>;
1229 wakeup-source; !! 784
>> 785 keyboard-backlight {
>> 786 compatible = "google,cros-kbd-led-backlight";
>> 787 };
1230 788
1231 i2c_tunnel: i2c-tunnel { 789 i2c_tunnel: i2c-tunnel {
1232 compatible = "google, 790 compatible = "google,cros-ec-i2c-tunnel";
1233 google,remote-bus = < 791 google,remote-bus = <0>;
1234 #address-cells = <1>; 792 #address-cells = <1>;
1235 #size-cells = <0>; 793 #size-cells = <0>;
1236 }; 794 };
1237 795
1238 mt_pmic_vmc_ldo_reg: regulato 796 mt_pmic_vmc_ldo_reg: regulator@0 {
1239 compatible = "google, 797 compatible = "google,cros-ec-regulator";
1240 reg = <0>; 798 reg = <0>;
1241 regulator-name = "mt_ 799 regulator-name = "mt_pmic_vmc_ldo";
1242 regulator-min-microvo 800 regulator-min-microvolt = <1200000>;
1243 regulator-max-microvo 801 regulator-max-microvolt = <3600000>;
1244 }; 802 };
1245 803
1246 mt_pmic_vmch_ldo_reg: regulat 804 mt_pmic_vmch_ldo_reg: regulator@1 {
1247 compatible = "google, 805 compatible = "google,cros-ec-regulator";
1248 reg = <1>; 806 reg = <1>;
1249 regulator-name = "mt_ 807 regulator-name = "mt_pmic_vmch_ldo";
1250 regulator-min-microvo 808 regulator-min-microvolt = <2700000>;
1251 regulator-max-microvo 809 regulator-max-microvolt = <3600000>;
1252 }; 810 };
1253 811
1254 typec { 812 typec {
1255 compatible = "google, 813 compatible = "google,cros-ec-typec";
1256 #address-cells = <1>; 814 #address-cells = <1>;
1257 #size-cells = <0>; 815 #size-cells = <0>;
1258 816
1259 usb_c0: connector@0 { 817 usb_c0: connector@0 {
1260 compatible = 818 compatible = "usb-c-connector";
1261 reg = <0>; 819 reg = <0>;
1262 power-role = 820 power-role = "dual";
1263 data-role = " 821 data-role = "host";
1264 try-power-rol 822 try-power-role = "source";
1265 }; 823 };
1266 824
1267 usb_c1: connector@1 { 825 usb_c1: connector@1 {
1268 compatible = 826 compatible = "usb-c-connector";
1269 reg = <1>; 827 reg = <1>;
1270 power-role = 828 power-role = "dual";
1271 data-role = " 829 data-role = "host";
1272 try-power-rol 830 try-power-role = "source";
1273 }; 831 };
1274 }; 832 };
1275 }; 833 };
1276 }; 834 };
1277 835
1278 &spmi { 836 &spmi {
1279 #address-cells = <2>; 837 #address-cells = <2>;
1280 #size-cells = <0>; 838 #size-cells = <0>;
1281 839
1282 mt6315@6 { 840 mt6315@6 {
1283 compatible = "mediatek,mt6315 841 compatible = "mediatek,mt6315-regulator";
1284 reg = <0x6 SPMI_USID>; 842 reg = <0x6 SPMI_USID>;
1285 843
1286 regulators { 844 regulators {
1287 mt6315_6_vbuck1: vbuc 845 mt6315_6_vbuck1: vbuck1 {
1288 regulator-com 846 regulator-compatible = "vbuck1";
1289 regulator-nam 847 regulator-name = "Vbcpu";
1290 regulator-min 848 regulator-min-microvolt = <400000>;
1291 regulator-max 849 regulator-max-microvolt = <1193750>;
1292 regulator-ena 850 regulator-enable-ramp-delay = <256>;
1293 regulator-ram 851 regulator-ramp-delay = <6250>;
1294 regulator-all 852 regulator-allowed-modes = <0 1 2>;
1295 regulator-alw 853 regulator-always-on;
1296 }; 854 };
1297 }; 855 };
1298 }; 856 };
1299 857
1300 mt6315@7 { 858 mt6315@7 {
1301 compatible = "mediatek,mt6315 859 compatible = "mediatek,mt6315-regulator";
1302 reg = <0x7 SPMI_USID>; 860 reg = <0x7 SPMI_USID>;
1303 861
1304 regulators { 862 regulators {
1305 mt6315_7_vbuck1: vbuc 863 mt6315_7_vbuck1: vbuck1 {
1306 regulator-com 864 regulator-compatible = "vbuck1";
1307 regulator-nam 865 regulator-name = "Vgpu";
1308 regulator-min 866 regulator-min-microvolt = <400000>;
1309 regulator-max 867 regulator-max-microvolt = <1193750>;
1310 regulator-ena 868 regulator-enable-ramp-delay = <256>;
1311 regulator-ram 869 regulator-ramp-delay = <6250>;
1312 regulator-all 870 regulator-allowed-modes = <0 1 2>;
1313 }; !! 871 regulator-always-on;
1314 }; <<
1315 }; <<
1316 }; <<
1317 <<
1318 &thermal_zones { <<
1319 soc-area-thermal { <<
1320 polling-delay = <1000>; <<
1321 polling-delay-passive = <250> <<
1322 thermal-sensors = <&tboard_th <<
1323 <<
1324 trips { <<
1325 trip-crit { <<
1326 temperature = <<
1327 hysteresis = <<
1328 type = "criti <<
1329 }; <<
1330 }; <<
1331 }; <<
1332 <<
1333 pmic-area-thermal { <<
1334 polling-delay = <1000>; <<
1335 polling-delay-passive = <0>; <<
1336 thermal-sensors = <&tboard_th <<
1337 <<
1338 trips { <<
1339 trip-crit { <<
1340 temperature = <<
1341 hysteresis = <<
1342 type = "criti <<
1343 }; 872 };
1344 }; 873 };
1345 }; 874 };
1346 }; 875 };
1347 876
1348 &u3phy0 { 877 &u3phy0 {
1349 status = "okay"; 878 status = "okay";
1350 }; 879 };
1351 880
1352 &u3phy1 { 881 &u3phy1 {
1353 status = "okay"; 882 status = "okay";
1354 }; 883 };
1355 884
1356 &u3phy2 { 885 &u3phy2 {
1357 status = "okay"; 886 status = "okay";
1358 }; 887 };
1359 888
1360 &u3phy3 { 889 &u3phy3 {
1361 status = "okay"; 890 status = "okay";
1362 }; 891 };
1363 892
1364 &uart0 { 893 &uart0 {
1365 status = "okay"; 894 status = "okay";
1366 }; 895 };
1367 896
1368 /* <<
1369 * For the USB Type-C ports the role and alte <<
1370 * done by the EC so we set dr_mode to host t <<
1371 */ <<
1372 &ssusb0 { <<
1373 dr_mode = "host"; <<
1374 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1375 status = "okay"; <<
1376 }; <<
1377 <<
1378 &ssusb2 { <<
1379 dr_mode = "host"; <<
1380 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1381 status = "okay"; <<
1382 }; <<
1383 <<
1384 &ssusb3 { <<
1385 dr_mode = "host"; <<
1386 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1387 status = "okay"; <<
1388 }; <<
1389 <<
1390 &xhci0 { 897 &xhci0 {
1391 status = "okay"; 898 status = "okay";
1392 899
1393 rx-fifo-depth = <3072>; !! 900 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1394 vbus-supply = <&usb_vbus>; 901 vbus-supply = <&usb_vbus>;
1395 }; 902 };
1396 903
1397 &xhci1 { 904 &xhci1 {
1398 status = "okay"; 905 status = "okay";
1399 906
1400 phys = <&u2port1 PHY_TYPE_USB2>; <<
1401 rx-fifo-depth = <3072>; <<
1402 vusb33-supply = <&mt6359_vusb_ldo_reg 907 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1403 vbus-supply = <&usb_vbus>; 908 vbus-supply = <&usb_vbus>;
1404 mediatek,u3p-dis-msk = <1>; <<
1405 }; 909 };
1406 910
1407 &xhci2 { 911 &xhci2 {
1408 status = "okay"; 912 status = "okay";
>> 913
>> 914 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1409 vbus-supply = <&usb_vbus>; 915 vbus-supply = <&usb_vbus>;
1410 }; 916 };
1411 917
1412 &xhci3 { 918 &xhci3 {
1413 status = "okay"; 919 status = "okay";
1414 920
1415 /* MT7921's USB Bluetooth has issues 921 /* MT7921's USB Bluetooth has issues with USB2 LPM */
1416 usb2-lpm-disable; 922 usb2-lpm-disable;
>> 923 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1417 vbus-supply = <&usb_vbus>; 924 vbus-supply = <&usb_vbus>;
>> 925 mediatek,u3p-dis-msk = <1>;
1418 }; 926 };
1419 927
1420 #include <arm/cros-ec-keyboard.dtsi> 928 #include <arm/cros-ec-keyboard.dtsi>
1421 #include <arm/cros-ec-sbs.dtsi> 929 #include <arm/cros-ec-sbs.dtsi>
1422 930
1423 &keyboard_controller { 931 &keyboard_controller {
1424 function-row-physmap = < 932 function-row-physmap = <
1425 MATRIX_KEY(0x00, 0x02, 0) 933 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
1426 MATRIX_KEY(0x03, 0x02, 0) 934 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
1427 MATRIX_KEY(0x02, 0x02, 0) 935 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
1428 MATRIX_KEY(0x01, 0x02, 0) 936 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
1429 MATRIX_KEY(0x03, 0x04, 0) 937 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
1430 MATRIX_KEY(0x02, 0x04, 0) 938 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
1431 MATRIX_KEY(0x01, 0x04, 0) 939 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
1432 MATRIX_KEY(0x02, 0x09, 0) 940 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
1433 MATRIX_KEY(0x01, 0x09, 0) 941 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
1434 MATRIX_KEY(0x00, 0x04, 0) 942 MATRIX_KEY(0x00, 0x04, 0) /* T10 */
1435 <<
1436 /* T11 to T13 are present onl <<
1437 MATRIX_KEY(0x00, 0x01, 0) <<
1438 MATRIX_KEY(0x01, 0x05, 0) <<
1439 MATRIX_KEY(0x03, 0x05, 0) <<
1440 >; 943 >;
1441 944
1442 linux,keymap = < 945 linux,keymap = <
1443 MATRIX_KEY(0x00, 0x02, KEY_BA 946 MATRIX_KEY(0x00, 0x02, KEY_BACK)
1444 MATRIX_KEY(0x03, 0x02, KEY_RE 947 MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
1445 MATRIX_KEY(0x02, 0x02, KEY_ZO 948 MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
1446 MATRIX_KEY(0x01, 0x02, KEY_SC 949 MATRIX_KEY(0x01, 0x02, KEY_SCALE)
1447 MATRIX_KEY(0x03, 0x04, KEY_SY 950 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
1448 MATRIX_KEY(0x02, 0x04, KEY_BR 951 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
1449 MATRIX_KEY(0x01, 0x04, KEY_BR 952 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
1450 MATRIX_KEY(0x02, 0x09, KEY_MU 953 MATRIX_KEY(0x02, 0x09, KEY_MUTE)
1451 MATRIX_KEY(0x01, 0x09, KEY_VO 954 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
1452 MATRIX_KEY(0x00, 0x04, KEY_VO 955 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
1453 956
1454 CROS_STD_MAIN_KEYMAP 957 CROS_STD_MAIN_KEYMAP
1455 >; 958 >;
1456 }; 959 };
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