1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2021 MediaTek Inc. 3 * Copyright (C) 2021 MediaTek Inc.
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h> 7 #include <dt-bindings/spmi/spmi.h>
8 #include "mt8195.dtsi" 8 #include "mt8195.dtsi"
9 #include "mt6359.dtsi" 9 #include "mt6359.dtsi"
10 10
11 / { 11 / {
12 aliases { 12 aliases {
13 i2c0 = &i2c0; 13 i2c0 = &i2c0;
14 i2c1 = &i2c1; 14 i2c1 = &i2c1;
15 i2c2 = &i2c2; 15 i2c2 = &i2c2;
16 i2c3 = &i2c3; 16 i2c3 = &i2c3;
17 i2c4 = &i2c4; 17 i2c4 = &i2c4;
18 i2c5 = &i2c5; 18 i2c5 = &i2c5;
19 i2c7 = &i2c7; 19 i2c7 = &i2c7;
20 mmc0 = &mmc0; 20 mmc0 = &mmc0;
21 mmc1 = &mmc1; 21 mmc1 = &mmc1;
22 serial0 = &uart0; 22 serial0 = &uart0;
23 }; 23 };
24 24
25 backlight_lcd0: backlight-lcd0 { 25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight"; 26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>; 27 brightness-levels = <0 1023>;
28 default-brightness-level = <57 28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_A 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023 30 num-interpolated-steps = <1023>;
31 pwms = <&disp_pwm0 0 500000>; 31 pwms = <&disp_pwm0 0 500000>;
32 power-supply = <&ppvar_sys>; 32 power-supply = <&ppvar_sys>;
33 }; 33 };
34 34
35 chosen { 35 chosen {
36 stdout-path = "serial0:115200n 36 stdout-path = "serial0:115200n8";
37 }; 37 };
38 38
39 dmic-codec { 39 dmic-codec {
40 compatible = "dmic-codec"; 40 compatible = "dmic-codec";
41 num-channels = <2>; 41 num-channels = <2>;
42 wakeup-delay-ms = <50>; 42 wakeup-delay-ms = <50>;
43 }; 43 };
44 44
45 memory@40000000 { 45 memory@40000000 {
46 device_type = "memory"; 46 device_type = "memory";
47 reg = <0 0x40000000 0 0x800000 47 reg = <0 0x40000000 0 0x80000000>;
48 }; 48 };
49 49
50 pp3300_disp_x: regulator-pp3300-disp-x <<
51 compatible = "regulator-fixed" <<
52 regulator-name = "pp3300_disp_ <<
53 regulator-min-microvolt = <330 <<
54 regulator-max-microvolt = <330 <<
55 regulator-enable-ramp-delay = <<
56 enable-active-high; <<
57 gpio = <&pio 55 GPIO_ACTIVE_HI <<
58 pinctrl-names = "default"; <<
59 pinctrl-0 = <&panel_fixed_pins <<
60 vin-supply = <&pp3300_z2>; <<
61 }; <<
62 <<
63 /* system wide LDO 3.3V power rail */ 50 /* system wide LDO 3.3V power rail */
64 pp3300_z5: regulator-pp3300-ldo-z5 { 51 pp3300_z5: regulator-pp3300-ldo-z5 {
65 compatible = "regulator-fixed" 52 compatible = "regulator-fixed";
66 regulator-name = "pp3300_ldo_z 53 regulator-name = "pp3300_ldo_z5";
67 regulator-always-on; 54 regulator-always-on;
68 regulator-boot-on; 55 regulator-boot-on;
69 regulator-min-microvolt = <330 56 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <330 57 regulator-max-microvolt = <3300000>;
71 vin-supply = <&ppvar_sys>; 58 vin-supply = <&ppvar_sys>;
72 }; 59 };
73 60
74 /* separately switched 3.3V power rail 61 /* separately switched 3.3V power rail */
75 pp3300_s3: regulator-pp3300-s3 { 62 pp3300_s3: regulator-pp3300-s3 {
76 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
77 regulator-name = "pp3300_s3"; 64 regulator-name = "pp3300_s3";
78 /* automatically sequenced by 65 /* automatically sequenced by PMIC EXT_PMIC_EN2 */
79 regulator-always-on; 66 regulator-always-on;
80 regulator-boot-on; 67 regulator-boot-on;
81 regulator-min-microvolt = <330 68 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
83 vin-supply = <&pp3300_z2>; 70 vin-supply = <&pp3300_z2>;
84 }; 71 };
85 72
86 /* system wide 3.3V power rail */ 73 /* system wide 3.3V power rail */
87 pp3300_z2: regulator-pp3300-z2 { 74 pp3300_z2: regulator-pp3300-z2 {
88 compatible = "regulator-fixed" 75 compatible = "regulator-fixed";
89 regulator-name = "pp3300_z2"; 76 regulator-name = "pp3300_z2";
90 /* EN pin tied to pp4200_z2, w 77 /* EN pin tied to pp4200_z2, which is controlled by EC */
91 regulator-always-on; 78 regulator-always-on;
92 regulator-boot-on; 79 regulator-boot-on;
93 regulator-min-microvolt = <330 80 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <330 81 regulator-max-microvolt = <3300000>;
95 vin-supply = <&ppvar_sys>; 82 vin-supply = <&ppvar_sys>;
96 }; 83 };
97 84
98 /* system wide 4.2V power rail */ 85 /* system wide 4.2V power rail */
99 pp4200_z2: regulator-pp4200-z2 { 86 pp4200_z2: regulator-pp4200-z2 {
100 compatible = "regulator-fixed" 87 compatible = "regulator-fixed";
101 regulator-name = "pp4200_z2"; 88 regulator-name = "pp4200_z2";
102 /* controlled by EC */ 89 /* controlled by EC */
103 regulator-always-on; 90 regulator-always-on;
104 regulator-boot-on; 91 regulator-boot-on;
105 regulator-min-microvolt = <420 92 regulator-min-microvolt = <4200000>;
106 regulator-max-microvolt = <420 93 regulator-max-microvolt = <4200000>;
107 vin-supply = <&ppvar_sys>; 94 vin-supply = <&ppvar_sys>;
108 }; 95 };
109 96
110 /* system wide switching 5.0V power ra 97 /* system wide switching 5.0V power rail */
111 pp5000_s5: regulator-pp5000-s5 { 98 pp5000_s5: regulator-pp5000-s5 {
112 compatible = "regulator-fixed" 99 compatible = "regulator-fixed";
113 regulator-name = "pp5000_s5"; 100 regulator-name = "pp5000_s5";
114 /* controlled by EC */ 101 /* controlled by EC */
115 regulator-always-on; 102 regulator-always-on;
116 regulator-boot-on; 103 regulator-boot-on;
117 regulator-min-microvolt = <500 104 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <500 105 regulator-max-microvolt = <5000000>;
119 vin-supply = <&ppvar_sys>; 106 vin-supply = <&ppvar_sys>;
120 }; 107 };
121 108
122 /* system wide semi-regulated power ra 109 /* system wide semi-regulated power rail from battery or USB */
123 ppvar_sys: regulator-ppvar-sys { 110 ppvar_sys: regulator-ppvar-sys {
124 compatible = "regulator-fixed" 111 compatible = "regulator-fixed";
125 regulator-name = "ppvar_sys"; 112 regulator-name = "ppvar_sys";
126 regulator-always-on; 113 regulator-always-on;
127 regulator-boot-on; 114 regulator-boot-on;
128 }; 115 };
129 116
130 /* Murata NCP03WF104F05RL */ <<
131 tboard_thermistor1: thermal-sensor-t1 <<
132 compatible = "generic-adc-ther <<
133 #thermal-sensor-cells = <0>; <<
134 io-channels = <&auxadc 0>; <<
135 io-channel-names = "sensor-cha <<
136 temperature-lookup-table = < <<
137 <<
138 <<
139 <<
140 <<
141 <<
142 <<
143 <<
144 <<
145 <<
146 <<
147 <<
148 <<
149 <<
150 <<
151 <<
152 <<
153 <<
154 <<
155 <<
156 <<
157 <<
158 <<
159 <<
160 <<
161 <<
162 <<
163 <<
164 }; <<
165 <<
166 tboard_thermistor2: thermal-sensor-t2 <<
167 compatible = "generic-adc-ther <<
168 #thermal-sensor-cells = <0>; <<
169 io-channels = <&auxadc 1>; <<
170 io-channel-names = "sensor-cha <<
171 temperature-lookup-table = < <<
172 <<
173 <<
174 <<
175 <<
176 <<
177 <<
178 <<
179 <<
180 <<
181 <<
182 <<
183 <<
184 <<
185 <<
186 <<
187 <<
188 <<
189 <<
190 <<
191 <<
192 <<
193 <<
194 <<
195 <<
196 <<
197 <<
198 <<
199 }; <<
200 <<
201 usb_vbus: regulator-5v0-usb-vbus { 117 usb_vbus: regulator-5v0-usb-vbus {
202 compatible = "regulator-fixed" 118 compatible = "regulator-fixed";
203 regulator-name = "usb-vbus"; 119 regulator-name = "usb-vbus";
204 regulator-min-microvolt = <500 120 regulator-min-microvolt = <5000000>;
205 regulator-max-microvolt = <500 121 regulator-max-microvolt = <5000000>;
206 enable-active-high; 122 enable-active-high;
207 regulator-always-on; 123 regulator-always-on;
208 }; 124 };
209 125
210 reserved_memory: reserved-memory { 126 reserved_memory: reserved-memory {
211 #address-cells = <2>; 127 #address-cells = <2>;
212 #size-cells = <2>; 128 #size-cells = <2>;
213 ranges; 129 ranges;
214 130
215 scp_mem: memory@50000000 { 131 scp_mem: memory@50000000 {
216 compatible = "shared-d 132 compatible = "shared-dma-pool";
217 reg = <0 0x50000000 0 133 reg = <0 0x50000000 0 0x2900000>;
218 no-map; 134 no-map;
219 }; 135 };
220 136
221 adsp_mem: memory@60000000 { 137 adsp_mem: memory@60000000 {
222 compatible = "shared-d 138 compatible = "shared-dma-pool";
223 reg = <0 0x60000000 0 139 reg = <0 0x60000000 0 0xd80000>;
224 no-map; 140 no-map;
225 }; 141 };
226 142
227 afe_mem: memory@60d80000 { 143 afe_mem: memory@60d80000 {
228 compatible = "shared-d 144 compatible = "shared-dma-pool";
229 reg = <0 0x60d80000 0 145 reg = <0 0x60d80000 0 0x100000>;
230 no-map; 146 no-map;
231 }; 147 };
232 148
233 adsp_device_mem: memory@60e800 149 adsp_device_mem: memory@60e80000 {
234 compatible = "shared-d 150 compatible = "shared-dma-pool";
235 reg = <0 0x60e80000 0 151 reg = <0 0x60e80000 0 0x280000>;
236 no-map; 152 no-map;
237 }; 153 };
238 }; 154 };
239 155
240 spk_amplifier: rt1019p { 156 spk_amplifier: rt1019p {
241 compatible = "realtek,rt1019p" 157 compatible = "realtek,rt1019p";
242 label = "rt1019p"; 158 label = "rt1019p";
243 #sound-dai-cells = <0>; <<
244 pinctrl-names = "default"; 159 pinctrl-names = "default";
245 pinctrl-0 = <&rt1019p_pins_def 160 pinctrl-0 = <&rt1019p_pins_default>;
246 sdb-gpios = <&pio 100 GPIO_ACT 161 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
247 }; 162 };
248 }; 163 };
249 164
250 &adsp { 165 &adsp {
251 status = "okay"; 166 status = "okay";
252 167
253 memory-region = <&adsp_device_mem>, <& 168 memory-region = <&adsp_device_mem>, <&adsp_mem>;
254 }; 169 };
255 170
256 &afe { 171 &afe {
257 status = "okay"; 172 status = "okay";
258 173
259 mediatek,etdm-in2-cowork-source = <2>; 174 mediatek,etdm-in2-cowork-source = <2>;
260 mediatek,etdm-out2-cowork-source = <0> 175 mediatek,etdm-out2-cowork-source = <0>;
261 memory-region = <&afe_mem>; 176 memory-region = <&afe_mem>;
262 }; 177 };
263 178
264 &auxadc { <<
265 status = "okay"; <<
266 }; <<
267 <<
268 &cpu0 { <<
269 cpu-supply = <&mt6359_vcore_buck_reg>; <<
270 }; <<
271 <<
272 &cpu1 { <<
273 cpu-supply = <&mt6359_vcore_buck_reg>; <<
274 }; <<
275 <<
276 &cpu2 { <<
277 cpu-supply = <&mt6359_vcore_buck_reg>; <<
278 }; <<
279 <<
280 &cpu3 { <<
281 cpu-supply = <&mt6359_vcore_buck_reg>; <<
282 }; <<
283 <<
284 &cpu4 { <<
285 cpu-supply = <&mt6315_6_vbuck1>; <<
286 }; <<
287 <<
288 &cpu5 { <<
289 cpu-supply = <&mt6315_6_vbuck1>; <<
290 }; <<
291 <<
292 &cpu6 { <<
293 cpu-supply = <&mt6315_6_vbuck1>; <<
294 }; <<
295 <<
296 &cpu7 { <<
297 cpu-supply = <&mt6315_6_vbuck1>; <<
298 }; <<
299 <<
300 &dp_intf0 { 179 &dp_intf0 {
301 status = "okay"; 180 status = "okay";
302 181
303 port { 182 port {
304 dp_intf0_out: endpoint { 183 dp_intf0_out: endpoint {
305 remote-endpoint = <&ed 184 remote-endpoint = <&edp_in>;
306 }; 185 };
307 }; 186 };
308 }; 187 };
309 188
310 &dp_intf1 { 189 &dp_intf1 {
311 status = "okay"; 190 status = "okay";
312 191
313 port { 192 port {
314 dp_intf1_out: endpoint { 193 dp_intf1_out: endpoint {
315 remote-endpoint = <&dp 194 remote-endpoint = <&dptx_in>;
316 }; 195 };
317 }; 196 };
318 }; 197 };
319 198
320 &edp_tx { 199 &edp_tx {
321 status = "okay"; 200 status = "okay";
322 201
323 pinctrl-names = "default"; 202 pinctrl-names = "default";
324 pinctrl-0 = <&edptx_pins_default>; 203 pinctrl-0 = <&edptx_pins_default>;
325 204
326 ports { 205 ports {
327 #address-cells = <1>; 206 #address-cells = <1>;
328 #size-cells = <0>; 207 #size-cells = <0>;
329 208
330 port@0 { 209 port@0 {
331 reg = <0>; 210 reg = <0>;
332 edp_in: endpoint { 211 edp_in: endpoint {
333 remote-endpoin 212 remote-endpoint = <&dp_intf0_out>;
334 }; 213 };
335 }; 214 };
336 215
337 port@1 { 216 port@1 {
338 reg = <1>; 217 reg = <1>;
339 edp_out: endpoint { 218 edp_out: endpoint {
340 data-lanes = < 219 data-lanes = <0 1 2 3>;
341 remote-endpoin <<
342 }; <<
343 }; <<
344 }; <<
345 <<
346 aux-bus { <<
347 panel { <<
348 compatible = "edp-pane <<
349 power-supply = <&pp330 <<
350 backlight = <&backligh <<
351 port { <<
352 panel_in: endp <<
353 remote <<
354 }; <<
355 }; 220 };
356 }; 221 };
357 }; 222 };
358 }; 223 };
359 224
360 &disp_pwm0 { 225 &disp_pwm0 {
361 status = "okay"; 226 status = "okay";
362 227
363 pinctrl-names = "default"; 228 pinctrl-names = "default";
364 pinctrl-0 = <&disp_pwm0_pin_default>; 229 pinctrl-0 = <&disp_pwm0_pin_default>;
365 }; 230 };
366 231
367 &dp_tx { 232 &dp_tx {
368 status = "okay"; 233 status = "okay";
369 234
370 #sound-dai-cells = <0>; <<
371 pinctrl-names = "default"; 235 pinctrl-names = "default";
372 pinctrl-0 = <&dptx_pin>; 236 pinctrl-0 = <&dptx_pin>;
373 237
374 ports { 238 ports {
375 #address-cells = <1>; 239 #address-cells = <1>;
376 #size-cells = <0>; 240 #size-cells = <0>;
377 241
378 port@0 { 242 port@0 {
379 reg = <0>; 243 reg = <0>;
380 dptx_in: endpoint { 244 dptx_in: endpoint {
381 remote-endpoin 245 remote-endpoint = <&dp_intf1_out>;
382 }; 246 };
383 }; 247 };
384 248
385 port@1 { 249 port@1 {
386 reg = <1>; 250 reg = <1>;
387 dptx_out: endpoint { 251 dptx_out: endpoint {
388 data-lanes = < 252 data-lanes = <0 1 2 3>;
389 }; 253 };
390 }; 254 };
391 }; 255 };
392 }; 256 };
393 257
394 &gic { 258 &gic {
395 mediatek,broken-save-restore-fw; 259 mediatek,broken-save-restore-fw;
396 }; 260 };
397 261
398 &gpu { 262 &gpu {
399 status = "okay"; 263 status = "okay";
400 mali-supply = <&mt6315_7_vbuck1>; 264 mali-supply = <&mt6315_7_vbuck1>;
401 }; 265 };
402 266
403 &i2c0 { 267 &i2c0 {
404 status = "okay"; 268 status = "okay";
405 269
406 clock-frequency = <400000>; 270 clock-frequency = <400000>;
407 pinctrl-names = "default"; 271 pinctrl-names = "default";
408 pinctrl-0 = <&i2c0_pins>; 272 pinctrl-0 = <&i2c0_pins>;
409 }; 273 };
410 274
411 &i2c1 { 275 &i2c1 {
412 status = "okay"; 276 status = "okay";
413 277
414 clock-frequency = <400000>; 278 clock-frequency = <400000>;
415 i2c-scl-internal-delay-ns = <12500>; 279 i2c-scl-internal-delay-ns = <12500>;
416 pinctrl-names = "default"; 280 pinctrl-names = "default";
417 pinctrl-0 = <&i2c1_pins>; 281 pinctrl-0 = <&i2c1_pins>;
418 282
419 trackpad@15 { 283 trackpad@15 {
420 compatible = "elan,ekth3000"; 284 compatible = "elan,ekth3000";
421 reg = <0x15>; 285 reg = <0x15>;
422 interrupts-extended = <&pio 6 286 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
423 pinctrl-names = "default"; 287 pinctrl-names = "default";
424 pinctrl-0 = <&trackpad_pins>; 288 pinctrl-0 = <&trackpad_pins>;
425 vcc-supply = <&pp3300_s3>; 289 vcc-supply = <&pp3300_s3>;
426 wakeup-source; 290 wakeup-source;
427 }; 291 };
428 }; 292 };
429 293
430 &i2c2 { 294 &i2c2 {
431 status = "okay"; 295 status = "okay";
432 296
433 clock-frequency = <400000>; 297 clock-frequency = <400000>;
434 pinctrl-names = "default"; 298 pinctrl-names = "default";
435 pinctrl-0 = <&i2c2_pins>; 299 pinctrl-0 = <&i2c2_pins>;
436 300
437 audio_codec: codec@1a { 301 audio_codec: codec@1a {
438 /* Realtek RT5682i or RT5682s, 302 /* Realtek RT5682i or RT5682s, sharing the same configuration */
439 reg = <0x1a>; 303 reg = <0x1a>;
440 interrupts-extended = <&pio 89 304 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
441 #sound-dai-cells = <0>; <<
442 realtek,jd-src = <1>; 305 realtek,jd-src = <1>;
443 306
444 AVDD-supply = <&mt6359_vio18_l 307 AVDD-supply = <&mt6359_vio18_ldo_reg>;
445 MICVDD-supply = <&pp3300_z2>; 308 MICVDD-supply = <&pp3300_z2>;
446 VBAT-supply = <&pp3300_z5>; 309 VBAT-supply = <&pp3300_z5>;
447 }; 310 };
448 }; 311 };
449 312
450 &i2c3 { 313 &i2c3 {
451 status = "okay"; 314 status = "okay";
452 315
453 clock-frequency = <400000>; 316 clock-frequency = <400000>;
454 pinctrl-names = "default"; 317 pinctrl-names = "default";
455 pinctrl-0 = <&i2c3_pins>; 318 pinctrl-0 = <&i2c3_pins>;
456 319
457 tpm@50 { 320 tpm@50 {
458 compatible = "google,cr50"; 321 compatible = "google,cr50";
459 reg = <0x50>; 322 reg = <0x50>;
460 interrupts-extended = <&pio 88 323 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
461 pinctrl-names = "default"; 324 pinctrl-names = "default";
462 pinctrl-0 = <&cr50_int>; 325 pinctrl-0 = <&cr50_int>;
463 }; 326 };
464 }; 327 };
465 328
466 &i2c4 { 329 &i2c4 {
467 status = "okay"; 330 status = "okay";
468 331
469 clock-frequency = <400000>; 332 clock-frequency = <400000>;
470 pinctrl-names = "default"; 333 pinctrl-names = "default";
471 pinctrl-0 = <&i2c4_pins>; 334 pinctrl-0 = <&i2c4_pins>;
472 335
473 ts_10: touchscreen@10 { 336 ts_10: touchscreen@10 {
474 compatible = "hid-over-i2c"; 337 compatible = "hid-over-i2c";
475 reg = <0x10>; 338 reg = <0x10>;
476 hid-descr-addr = <0x0001>; 339 hid-descr-addr = <0x0001>;
477 interrupts-extended = <&pio 92 340 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
478 pinctrl-names = "default"; 341 pinctrl-names = "default";
479 pinctrl-0 = <&touchscreen_pins 342 pinctrl-0 = <&touchscreen_pins>;
480 post-power-on-delay-ms = <10>; 343 post-power-on-delay-ms = <10>;
481 vdd-supply = <&pp3300_s3>; 344 vdd-supply = <&pp3300_s3>;
482 status = "disabled"; 345 status = "disabled";
483 }; 346 };
484 }; 347 };
485 348
486 &i2c5 { 349 &i2c5 {
487 status = "okay"; 350 status = "okay";
488 351
489 clock-frequency = <400000>; 352 clock-frequency = <400000>;
490 pinctrl-names = "default"; 353 pinctrl-names = "default";
491 pinctrl-0 = <&i2c5_pins>; 354 pinctrl-0 = <&i2c5_pins>;
492 }; 355 };
493 356
494 &i2c7 { 357 &i2c7 {
495 status = "okay"; 358 status = "okay";
496 359
497 clock-frequency = <400000>; 360 clock-frequency = <400000>;
498 pinctrl-names = "default"; 361 pinctrl-names = "default";
499 pinctrl-0 = <&i2c7_pins>; 362 pinctrl-0 = <&i2c7_pins>;
500 363
501 pmic@34 { 364 pmic@34 {
502 #interrupt-cells = <2>; !! 365 #interrupt-cells = <1>;
503 compatible = "mediatek,mt6360" 366 compatible = "mediatek,mt6360";
504 reg = <0x34>; 367 reg = <0x34>;
505 interrupt-controller; 368 interrupt-controller;
506 interrupts-extended = <&pio 13 369 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
507 interrupt-names = "IRQB"; 370 interrupt-names = "IRQB";
508 pinctrl-names = "default"; 371 pinctrl-names = "default";
509 pinctrl-0 = <&subpmic_default> 372 pinctrl-0 = <&subpmic_default>;
510 wakeup-source; 373 wakeup-source;
511 }; 374 };
512 }; 375 };
513 376
514 &mfg0 { <<
515 domain-supply = <&mt6315_7_vbuck1>; <<
516 }; <<
517 <<
518 &mfg1 { <<
519 domain-supply = <&mt6359_vsram_others_ <<
520 }; <<
521 <<
522 &mmc0 { 377 &mmc0 {
523 status = "okay"; 378 status = "okay";
524 379
525 bus-width = <8>; 380 bus-width = <8>;
526 cap-mmc-highspeed; 381 cap-mmc-highspeed;
527 cap-mmc-hw-reset; 382 cap-mmc-hw-reset;
528 hs400-ds-delay = <0x14c11>; 383 hs400-ds-delay = <0x14c11>;
529 max-frequency = <200000000>; 384 max-frequency = <200000000>;
530 mmc-hs200-1_8v; 385 mmc-hs200-1_8v;
531 mmc-hs400-1_8v; 386 mmc-hs400-1_8v;
532 no-sdio; 387 no-sdio;
533 no-sd; 388 no-sd;
534 non-removable; 389 non-removable;
535 pinctrl-names = "default", "state_uhs" 390 pinctrl-names = "default", "state_uhs";
536 pinctrl-0 = <&mmc0_pins_default>; 391 pinctrl-0 = <&mmc0_pins_default>;
537 pinctrl-1 = <&mmc0_pins_uhs>; 392 pinctrl-1 = <&mmc0_pins_uhs>;
538 vmmc-supply = <&mt6359_vemc_1_ldo_reg> 393 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
539 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 394 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
540 }; 395 };
541 396
542 &mmc1 { 397 &mmc1 {
543 status = "okay"; 398 status = "okay";
544 399
545 bus-width = <4>; 400 bus-width = <4>;
546 cap-sd-highspeed; 401 cap-sd-highspeed;
547 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 402 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
548 max-frequency = <200000000>; 403 max-frequency = <200000000>;
549 no-mmc; 404 no-mmc;
550 no-sdio; 405 no-sdio;
551 pinctrl-names = "default", "state_uhs" 406 pinctrl-names = "default", "state_uhs";
552 pinctrl-0 = <&mmc1_pins_default>, <&mm 407 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
553 pinctrl-1 = <&mmc1_pins_default>; 408 pinctrl-1 = <&mmc1_pins_default>;
554 sd-uhs-sdr50; 409 sd-uhs-sdr50;
555 sd-uhs-sdr104; 410 sd-uhs-sdr104;
556 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 411 vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
557 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 412 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
558 }; 413 };
559 414
560 &mt6359codec { 415 &mt6359codec {
561 mediatek,dmic-mode = <1>; /* one-wire 416 mediatek,dmic-mode = <1>; /* one-wire */
562 mediatek,mic-type-0 = <2>; /* DMIC */ 417 mediatek,mic-type-0 = <2>; /* DMIC */
563 }; 418 };
564 419
565 /* for CPU-L */ 420 /* for CPU-L */
566 &mt6359_vcore_buck_reg { 421 &mt6359_vcore_buck_reg {
567 regulator-always-on; 422 regulator-always-on;
568 }; 423 };
569 424
570 /* for CORE */ 425 /* for CORE */
571 &mt6359_vgpu11_buck_reg { 426 &mt6359_vgpu11_buck_reg {
572 regulator-always-on; 427 regulator-always-on;
573 }; 428 };
574 429
575 &mt6359_vgpu11_sshub_buck_reg { 430 &mt6359_vgpu11_sshub_buck_reg {
576 regulator-always-on; 431 regulator-always-on;
577 regulator-min-microvolt = <550000>; 432 regulator-min-microvolt = <550000>;
578 regulator-max-microvolt = <550000>; 433 regulator-max-microvolt = <550000>;
579 }; 434 };
580 435
581 /* for CORE SRAM */ 436 /* for CORE SRAM */
582 &mt6359_vpu_buck_reg { 437 &mt6359_vpu_buck_reg {
583 regulator-always-on; 438 regulator-always-on;
584 }; 439 };
585 440
586 &mt6359_vrf12_ldo_reg { 441 &mt6359_vrf12_ldo_reg {
587 regulator-always-on; 442 regulator-always-on;
588 }; 443 };
589 444
590 /* for GPU SRAM */ 445 /* for GPU SRAM */
591 &mt6359_vsram_others_ldo_reg { 446 &mt6359_vsram_others_ldo_reg {
>> 447 regulator-always-on;
592 regulator-min-microvolt = <750000>; 448 regulator-min-microvolt = <750000>;
593 regulator-max-microvolt = <750000>; 449 regulator-max-microvolt = <750000>;
594 }; 450 };
595 451
596 &mt6359_vufs_ldo_reg { 452 &mt6359_vufs_ldo_reg {
597 regulator-always-on; 453 regulator-always-on;
598 }; 454 };
599 455
600 &nor_flash { 456 &nor_flash {
601 status = "okay"; 457 status = "okay";
602 458
603 pinctrl-names = "default"; 459 pinctrl-names = "default";
604 pinctrl-0 = <&nor_pins_default>; 460 pinctrl-0 = <&nor_pins_default>;
605 461
606 flash@0 { 462 flash@0 {
607 compatible = "jedec,spi-nor"; 463 compatible = "jedec,spi-nor";
608 reg = <0>; 464 reg = <0>;
609 spi-max-frequency = <52000000> 465 spi-max-frequency = <52000000>;
610 spi-rx-bus-width = <2>; 466 spi-rx-bus-width = <2>;
611 spi-tx-bus-width = <2>; 467 spi-tx-bus-width = <2>;
612 }; 468 };
613 }; 469 };
614 470
615 &pcie1 { <<
616 status = "okay"; <<
617 <<
618 pinctrl-names = "default"; <<
619 pinctrl-0 = <&pcie1_pins_default>; <<
620 }; <<
621 <<
622 &pio { 471 &pio {
623 mediatek,rsel-resistance-in-si-unit; 472 mediatek,rsel-resistance-in-si-unit;
624 pinctrl-names = "default"; 473 pinctrl-names = "default";
625 pinctrl-0 = <&pio_default>; 474 pinctrl-0 = <&pio_default>;
626 475
627 /* 144 lines */ 476 /* 144 lines */
628 gpio-line-names = 477 gpio-line-names =
629 "I2S_SPKR_MCLK", 478 "I2S_SPKR_MCLK",
630 "I2S_SPKR_DATAIN", 479 "I2S_SPKR_DATAIN",
631 "I2S_SPKR_LRCK", 480 "I2S_SPKR_LRCK",
632 "I2S_SPKR_BCLK", 481 "I2S_SPKR_BCLK",
633 "EC_AP_INT_ODL", 482 "EC_AP_INT_ODL",
634 /* 483 /*
635 * AP_FLASH_WP_L is crossystem 484 * AP_FLASH_WP_L is crossystem ABI. Schematics
636 * call it AP_FLASH_WP_ODL. 485 * call it AP_FLASH_WP_ODL.
637 */ 486 */
638 "AP_FLASH_WP_L", 487 "AP_FLASH_WP_L",
639 "TCHPAD_INT_ODL", 488 "TCHPAD_INT_ODL",
640 "EDP_HPD_1V8", 489 "EDP_HPD_1V8",
641 "AP_I2C_CAM_SDA", 490 "AP_I2C_CAM_SDA",
642 "AP_I2C_CAM_SCL", 491 "AP_I2C_CAM_SCL",
643 "AP_I2C_TCHPAD_SDA_1V8", 492 "AP_I2C_TCHPAD_SDA_1V8",
644 "AP_I2C_TCHPAD_SCL_1V8", 493 "AP_I2C_TCHPAD_SCL_1V8",
645 "AP_I2C_AUD_SDA", 494 "AP_I2C_AUD_SDA",
646 "AP_I2C_AUD_SCL", 495 "AP_I2C_AUD_SCL",
647 "AP_I2C_TPM_SDA_1V8", 496 "AP_I2C_TPM_SDA_1V8",
648 "AP_I2C_TPM_SCL_1V8", 497 "AP_I2C_TPM_SCL_1V8",
649 "AP_I2C_TCHSCR_SDA_1V8", 498 "AP_I2C_TCHSCR_SDA_1V8",
650 "AP_I2C_TCHSCR_SCL_1V8", 499 "AP_I2C_TCHSCR_SCL_1V8",
651 "EC_AP_HPD_OD", 500 "EC_AP_HPD_OD",
652 "", 501 "",
653 "PCIE_NVME_RST_L", 502 "PCIE_NVME_RST_L",
654 "PCIE_NVME_CLKREQ_ODL", 503 "PCIE_NVME_CLKREQ_ODL",
655 "PCIE_RST_1V8_L", 504 "PCIE_RST_1V8_L",
656 "PCIE_CLKREQ_1V8_ODL", 505 "PCIE_CLKREQ_1V8_ODL",
657 "PCIE_WAKE_1V8_ODL", 506 "PCIE_WAKE_1V8_ODL",
658 "CLK_24M_CAM0", 507 "CLK_24M_CAM0",
659 "CAM1_SEN_EN", 508 "CAM1_SEN_EN",
660 "AP_I2C_PWR_SCL_1V8", 509 "AP_I2C_PWR_SCL_1V8",
661 "AP_I2C_PWR_SDA_1V8", 510 "AP_I2C_PWR_SDA_1V8",
662 "AP_I2C_MISC_SCL", 511 "AP_I2C_MISC_SCL",
663 "AP_I2C_MISC_SDA", 512 "AP_I2C_MISC_SDA",
664 "EN_PP5000_HDMI_X", 513 "EN_PP5000_HDMI_X",
665 "AP_HDMITX_HTPLG", 514 "AP_HDMITX_HTPLG",
666 "", 515 "",
667 "AP_HDMITX_SCL_1V8", 516 "AP_HDMITX_SCL_1V8",
668 "AP_HDMITX_SDA_1V8", 517 "AP_HDMITX_SDA_1V8",
669 "AP_RTC_CLK32K", 518 "AP_RTC_CLK32K",
670 "AP_EC_WATCHDOG_L", 519 "AP_EC_WATCHDOG_L",
671 "SRCLKENA0", 520 "SRCLKENA0",
672 "SRCLKENA1", 521 "SRCLKENA1",
673 "PWRAP_SPI0_CS_L", 522 "PWRAP_SPI0_CS_L",
674 "PWRAP_SPI0_CK", 523 "PWRAP_SPI0_CK",
675 "PWRAP_SPI0_MOSI", 524 "PWRAP_SPI0_MOSI",
676 "PWRAP_SPI0_MISO", 525 "PWRAP_SPI0_MISO",
677 "SPMI_SCL", 526 "SPMI_SCL",
678 "SPMI_SDA", 527 "SPMI_SDA",
679 "", 528 "",
680 "", 529 "",
681 "", 530 "",
682 "I2S_HP_DATAIN", 531 "I2S_HP_DATAIN",
683 "I2S_HP_MCLK", 532 "I2S_HP_MCLK",
684 "I2S_HP_BCK", 533 "I2S_HP_BCK",
685 "I2S_HP_LRCK", 534 "I2S_HP_LRCK",
686 "I2S_HP_DATAOUT", 535 "I2S_HP_DATAOUT",
687 "SD_CD_ODL", 536 "SD_CD_ODL",
688 "EN_PP3300_DISP_X", 537 "EN_PP3300_DISP_X",
689 "TCHSCR_RST_1V8_L", 538 "TCHSCR_RST_1V8_L",
690 "TCHSCR_REPORT_DISABLE", 539 "TCHSCR_REPORT_DISABLE",
691 "EN_PP3300_WLAN_X", 540 "EN_PP3300_WLAN_X",
692 "BT_KILL_1V8_L", 541 "BT_KILL_1V8_L",
693 "I2S_SPKR_DATAOUT", 542 "I2S_SPKR_DATAOUT",
694 "WIFI_KILL_1V8_L", 543 "WIFI_KILL_1V8_L",
695 "BEEP_ON", 544 "BEEP_ON",
696 "SCP_I2C_SENSOR_SCL_1V8", 545 "SCP_I2C_SENSOR_SCL_1V8",
697 "SCP_I2C_SENSOR_SDA_1V8", 546 "SCP_I2C_SENSOR_SDA_1V8",
698 "", 547 "",
699 "", 548 "",
700 "", 549 "",
701 "", 550 "",
702 "AUD_CLK_MOSI", 551 "AUD_CLK_MOSI",
703 "AUD_SYNC_MOSI", 552 "AUD_SYNC_MOSI",
704 "AUD_DAT_MOSI0", 553 "AUD_DAT_MOSI0",
705 "AUD_DAT_MOSI1", 554 "AUD_DAT_MOSI1",
706 "AUD_DAT_MISO0", 555 "AUD_DAT_MISO0",
707 "AUD_DAT_MISO1", 556 "AUD_DAT_MISO1",
708 "AUD_DAT_MISO2", 557 "AUD_DAT_MISO2",
709 "SCP_VREQ_VAO", 558 "SCP_VREQ_VAO",
710 "AP_SPI_GSC_TPM_CLK", 559 "AP_SPI_GSC_TPM_CLK",
711 "AP_SPI_GSC_TPM_MOSI", 560 "AP_SPI_GSC_TPM_MOSI",
712 "AP_SPI_GSC_TPM_CS_L", 561 "AP_SPI_GSC_TPM_CS_L",
713 "AP_SPI_GSC_TPM_MISO", 562 "AP_SPI_GSC_TPM_MISO",
714 "EN_PP1000_CAM_X", 563 "EN_PP1000_CAM_X",
715 "AP_EDP_BKLTEN", 564 "AP_EDP_BKLTEN",
716 "", 565 "",
717 "USB3_HUB_RST_L", 566 "USB3_HUB_RST_L",
718 "", 567 "",
719 "WLAN_ALERT_ODL", 568 "WLAN_ALERT_ODL",
720 "EC_IN_RW_ODL", 569 "EC_IN_RW_ODL",
721 "GSC_AP_INT_ODL", 570 "GSC_AP_INT_ODL",
722 "HP_INT_ODL", 571 "HP_INT_ODL",
723 "CAM0_RST_L", 572 "CAM0_RST_L",
724 "CAM1_RST_L", 573 "CAM1_RST_L",
725 "TCHSCR_INT_1V8_L", 574 "TCHSCR_INT_1V8_L",
726 "CAM1_DET_L", 575 "CAM1_DET_L",
727 "RST_ALC1011_L", 576 "RST_ALC1011_L",
728 "", 577 "",
729 "", 578 "",
730 "BL_PWM_1V8", 579 "BL_PWM_1V8",
731 "UART_AP_TX_DBG_RX", 580 "UART_AP_TX_DBG_RX",
732 "UART_DBG_TX_AP_RX", 581 "UART_DBG_TX_AP_RX",
733 "EN_SPKR", 582 "EN_SPKR",
734 "AP_EC_WARM_RST_REQ", 583 "AP_EC_WARM_RST_REQ",
735 "UART_SCP_TX_DBGCON_RX", 584 "UART_SCP_TX_DBGCON_RX",
736 "UART_DBGCON_TX_SCP_RX", 585 "UART_DBGCON_TX_SCP_RX",
737 "", 586 "",
738 "", 587 "",
739 "KPCOL0", 588 "KPCOL0",
740 "", 589 "",
741 "MT6315_GPU_INT", 590 "MT6315_GPU_INT",
742 "MT6315_PROC_BC_INT", 591 "MT6315_PROC_BC_INT",
743 "SD_CMD", 592 "SD_CMD",
744 "SD_CLK", 593 "SD_CLK",
745 "SD_DAT0", 594 "SD_DAT0",
746 "SD_DAT1", 595 "SD_DAT1",
747 "SD_DAT2", 596 "SD_DAT2",
748 "SD_DAT3", 597 "SD_DAT3",
749 "EMMC_DAT7", 598 "EMMC_DAT7",
750 "EMMC_DAT6", 599 "EMMC_DAT6",
751 "EMMC_DAT5", 600 "EMMC_DAT5",
752 "EMMC_DAT4", 601 "EMMC_DAT4",
753 "EMMC_RSTB", 602 "EMMC_RSTB",
754 "EMMC_CMD", 603 "EMMC_CMD",
755 "EMMC_CLK", 604 "EMMC_CLK",
756 "EMMC_DAT3", 605 "EMMC_DAT3",
757 "EMMC_DAT2", 606 "EMMC_DAT2",
758 "EMMC_DAT1", 607 "EMMC_DAT1",
759 "EMMC_DAT0", 608 "EMMC_DAT0",
760 "EMMC_DSL", 609 "EMMC_DSL",
761 "", 610 "",
762 "", 611 "",
763 "MT6360_INT_ODL", 612 "MT6360_INT_ODL",
764 "SCP_JTAG0_TRSTN", 613 "SCP_JTAG0_TRSTN",
765 "AP_SPI_EC_CS_L", 614 "AP_SPI_EC_CS_L",
766 "AP_SPI_EC_CLK", 615 "AP_SPI_EC_CLK",
767 "AP_SPI_EC_MOSI", 616 "AP_SPI_EC_MOSI",
768 "AP_SPI_EC_MISO", 617 "AP_SPI_EC_MISO",
769 "SCP_JTAG0_TMS", 618 "SCP_JTAG0_TMS",
770 "SCP_JTAG0_TCK", 619 "SCP_JTAG0_TCK",
771 "SCP_JTAG0_TDO", 620 "SCP_JTAG0_TDO",
772 "SCP_JTAG0_TDI", 621 "SCP_JTAG0_TDI",
773 "AP_SPI_FLASH_CS_L", 622 "AP_SPI_FLASH_CS_L",
774 "AP_SPI_FLASH_CLK", 623 "AP_SPI_FLASH_CLK",
775 "AP_SPI_FLASH_MOSI", 624 "AP_SPI_FLASH_MOSI",
776 "AP_SPI_FLASH_MISO"; 625 "AP_SPI_FLASH_MISO";
777 626
778 aud_pins_default: audio-default-pins { 627 aud_pins_default: audio-default-pins {
779 pins-cmd-dat { 628 pins-cmd-dat {
780 pinmux = <PINMUX_GPIO69__F 629 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
781 <PINMUX_GPIO70__F 630 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
782 <PINMUX_GPIO71__F 631 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
783 <PINMUX_GPIO72__F 632 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
784 <PINMUX_GPIO73__F 633 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
785 <PINMUX_GPIO74__F 634 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
786 <PINMUX_GPIO75__F 635 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>,
787 <PINMUX_GPIO0__FU 636 <PINMUX_GPIO0__FUNC_TDMIN_MCK>,
788 <PINMUX_GPIO1__FU 637 <PINMUX_GPIO1__FUNC_TDMIN_DI>,
789 <PINMUX_GPIO2__FU 638 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>,
790 <PINMUX_GPIO3__FU 639 <PINMUX_GPIO3__FUNC_TDMIN_BCK>,
791 <PINMUX_GPIO60__F 640 <PINMUX_GPIO60__FUNC_I2SO2_D0>,
792 <PINMUX_GPIO49__F 641 <PINMUX_GPIO49__FUNC_I2SIN_D0>,
793 <PINMUX_GPIO50__F 642 <PINMUX_GPIO50__FUNC_I2SO1_MCK>,
794 <PINMUX_GPIO51__F 643 <PINMUX_GPIO51__FUNC_I2SO1_BCK>,
795 <PINMUX_GPIO52__F 644 <PINMUX_GPIO52__FUNC_I2SO1_WS>,
796 <PINMUX_GPIO53__F 645 <PINMUX_GPIO53__FUNC_I2SO1_D0>;
797 }; 646 };
798 647
799 pins-hp-jack-int-odl { 648 pins-hp-jack-int-odl {
800 pinmux = <PINMUX_GPIO8 649 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>;
801 input-enable; 650 input-enable;
802 bias-pull-up = <MTK_PU 651 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
803 }; 652 };
804 }; 653 };
805 654
806 cr50_int: cr50-irq-default-pins { 655 cr50_int: cr50-irq-default-pins {
807 pins-gsc-ap-int-odl { 656 pins-gsc-ap-int-odl {
808 pinmux = <PINMUX_GPIO8 657 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
809 input-enable; 658 input-enable;
810 }; 659 };
811 }; 660 };
812 661
813 cros_ec_int: cros-ec-irq-default-pins 662 cros_ec_int: cros-ec-irq-default-pins {
814 pins-ec-ap-int-odl { 663 pins-ec-ap-int-odl {
815 pinmux = <PINMUX_GPIO4 664 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
816 bias-pull-up = <MTK_PU 665 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
817 input-enable; 666 input-enable;
818 }; 667 };
819 }; 668 };
820 669
821 edptx_pins_default: edptx-default-pins 670 edptx_pins_default: edptx-default-pins {
822 pins-cmd-dat { 671 pins-cmd-dat {
823 pinmux = <PINMUX_GPIO7 672 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
824 bias-pull-up; 673 bias-pull-up;
825 }; 674 };
826 }; 675 };
827 676
828 disp_pwm0_pin_default: disp-pwm0-defau 677 disp_pwm0_pin_default: disp-pwm0-default-pins {
829 pins-disp-pwm { 678 pins-disp-pwm {
830 pinmux = <PINMUX_GPIO8 679 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>,
831 <PINMUX_GPIO9 680 <PINMUX_GPIO97__FUNC_DISP_PWM0>;
832 }; 681 };
833 }; 682 };
834 683
835 dptx_pin: dptx-default-pins { 684 dptx_pin: dptx-default-pins {
836 pins-cmd-dat { 685 pins-cmd-dat {
837 pinmux = <PINMUX_GPIO1 686 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
838 bias-pull-up; 687 bias-pull-up;
839 }; 688 };
840 }; 689 };
841 690
842 i2c0_pins: i2c0-default-pins { 691 i2c0_pins: i2c0-default-pins {
843 pins-bus { 692 pins-bus {
844 pinmux = <PINMUX_GPIO8 693 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
845 <PINMUX_GPIO9 694 <PINMUX_GPIO9__FUNC_SCL0>;
846 bias-disable; 695 bias-disable;
847 drive-strength-microam 696 drive-strength-microamp = <1000>;
848 }; 697 };
849 }; 698 };
850 699
851 i2c1_pins: i2c1-default-pins { 700 i2c1_pins: i2c1-default-pins {
852 pins-bus { 701 pins-bus {
853 pinmux = <PINMUX_GPIO1 702 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
854 <PINMUX_GPIO1 703 <PINMUX_GPIO11__FUNC_SCL1>;
855 bias-pull-up = <1000>; 704 bias-pull-up = <1000>;
856 drive-strength-microam 705 drive-strength-microamp = <1000>;
857 }; 706 };
858 }; 707 };
859 708
860 i2c2_pins: i2c2-default-pins { 709 i2c2_pins: i2c2-default-pins {
861 pins-bus { 710 pins-bus {
862 pinmux = <PINMUX_GPIO1 711 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
863 <PINMUX_GPIO1 712 <PINMUX_GPIO13__FUNC_SCL2>;
864 bias-disable; 713 bias-disable;
865 drive-strength-microam 714 drive-strength-microamp = <1000>;
866 }; 715 };
867 }; 716 };
868 717
869 i2c3_pins: i2c3-default-pins { 718 i2c3_pins: i2c3-default-pins {
870 pins-bus { 719 pins-bus {
871 pinmux = <PINMUX_GPIO1 720 pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
872 <PINMUX_GPIO1 721 <PINMUX_GPIO15__FUNC_SCL3>;
873 bias-pull-up = <1000>; 722 bias-pull-up = <1000>;
874 drive-strength-microam 723 drive-strength-microamp = <1000>;
875 }; 724 };
876 }; 725 };
877 726
878 i2c4_pins: i2c4-default-pins { 727 i2c4_pins: i2c4-default-pins {
879 pins-bus { 728 pins-bus {
880 pinmux = <PINMUX_GPIO1 729 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
881 <PINMUX_GPIO1 730 <PINMUX_GPIO17__FUNC_SCL4>;
882 bias-pull-up = <1000>; 731 bias-pull-up = <1000>;
883 drive-strength = <4>; 732 drive-strength = <4>;
884 }; 733 };
885 }; 734 };
886 735
887 i2c5_pins: i2c5-default-pins { 736 i2c5_pins: i2c5-default-pins {
888 pins-bus { 737 pins-bus {
889 pinmux = <PINMUX_GPIO2 738 pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
890 <PINMUX_GPIO3 739 <PINMUX_GPIO30__FUNC_SDA5>;
891 bias-disable; 740 bias-disable;
892 drive-strength-microam 741 drive-strength-microamp = <1000>;
893 }; 742 };
894 }; 743 };
895 744
896 i2c7_pins: i2c7-default-pins { 745 i2c7_pins: i2c7-default-pins {
897 pins-bus { 746 pins-bus {
898 pinmux = <PINMUX_GPIO2 747 pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
899 <PINMUX_GPIO2 748 <PINMUX_GPIO28__FUNC_SDA7>;
900 bias-disable; 749 bias-disable;
901 }; 750 };
902 }; 751 };
903 752
904 mmc0_pins_default: mmc0-default-pins { 753 mmc0_pins_default: mmc0-default-pins {
905 pins-cmd-dat { 754 pins-cmd-dat {
906 pinmux = <PINMUX_GPIO1 755 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
907 <PINMUX_GPIO1 756 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
908 <PINMUX_GPIO1 757 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
909 <PINMUX_GPIO1 758 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
910 <PINMUX_GPIO1 759 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
911 <PINMUX_GPIO1 760 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
912 <PINMUX_GPIO1 761 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
913 <PINMUX_GPIO1 762 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
914 <PINMUX_GPIO1 763 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
915 input-enable; 764 input-enable;
916 drive-strength = <6>; 765 drive-strength = <6>;
917 bias-pull-up = <MTK_PU 766 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
918 }; 767 };
919 768
920 pins-clk { 769 pins-clk {
921 pinmux = <PINMUX_GPIO1 770 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
922 drive-strength = <6>; 771 drive-strength = <6>;
923 bias-pull-down = <MTK_ 772 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
924 }; 773 };
925 774
926 pins-rst { 775 pins-rst {
927 pinmux = <PINMUX_GPIO1 776 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
928 drive-strength = <6>; 777 drive-strength = <6>;
929 bias-pull-up = <MTK_PU 778 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
930 }; 779 };
931 }; 780 };
932 781
933 mmc0_pins_uhs: mmc0-uhs-pins { 782 mmc0_pins_uhs: mmc0-uhs-pins {
934 pins-cmd-dat { 783 pins-cmd-dat {
935 pinmux = <PINMUX_GPIO1 784 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
936 <PINMUX_GPIO1 785 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
937 <PINMUX_GPIO1 786 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
938 <PINMUX_GPIO1 787 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
939 <PINMUX_GPIO1 788 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
940 <PINMUX_GPIO1 789 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
941 <PINMUX_GPIO1 790 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
942 <PINMUX_GPIO1 791 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
943 <PINMUX_GPIO1 792 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
944 input-enable; 793 input-enable;
945 drive-strength = <8>; 794 drive-strength = <8>;
946 bias-pull-up = <MTK_PU 795 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
947 }; 796 };
948 797
949 pins-clk { 798 pins-clk {
950 pinmux = <PINMUX_GPIO1 799 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
951 drive-strength = <8>; 800 drive-strength = <8>;
952 bias-pull-down = <MTK_ 801 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
953 }; 802 };
954 803
955 pins-ds { 804 pins-ds {
956 pinmux = <PINMUX_GPIO1 805 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
957 drive-strength = <8>; 806 drive-strength = <8>;
958 bias-pull-down = <MTK_ 807 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
959 }; 808 };
960 809
961 pins-rst { 810 pins-rst {
962 pinmux = <PINMUX_GPIO1 811 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
963 drive-strength = <8>; 812 drive-strength = <8>;
964 bias-pull-up = <MTK_PU 813 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
965 }; 814 };
966 }; 815 };
967 816
968 mmc1_pins_detect: mmc1-detect-pins { 817 mmc1_pins_detect: mmc1-detect-pins {
969 pins-insert { 818 pins-insert {
970 pinmux = <PINMUX_GPIO5 819 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
971 bias-pull-up; 820 bias-pull-up;
972 }; 821 };
973 }; 822 };
974 823
975 mmc1_pins_default: mmc1-default-pins { 824 mmc1_pins_default: mmc1-default-pins {
976 pins-cmd-dat { 825 pins-cmd-dat {
977 pinmux = <PINMUX_GPIO1 826 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
978 <PINMUX_GPIO1 827 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
979 <PINMUX_GPIO1 828 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
980 <PINMUX_GPIO1 829 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
981 <PINMUX_GPIO1 830 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
982 input-enable; 831 input-enable;
983 drive-strength = <8>; 832 drive-strength = <8>;
984 bias-pull-up = <MTK_PU 833 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
985 }; 834 };
986 835
987 pins-clk { 836 pins-clk {
988 pinmux = <PINMUX_GPIO1 837 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
989 drive-strength = <8>; 838 drive-strength = <8>;
990 bias-pull-down = <MTK_ 839 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
991 }; 840 };
992 }; 841 };
993 842
994 nor_pins_default: nor-default-pins { 843 nor_pins_default: nor-default-pins {
995 pins-ck-io { 844 pins-ck-io {
996 pinmux = <PINMUX_GPIO1 845 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
997 <PINMUX_GPIO1 846 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
998 <PINMUX_GPIO1 847 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
999 drive-strength = <6>; 848 drive-strength = <6>;
1000 bias-pull-down; 849 bias-pull-down;
1001 }; 850 };
1002 851
1003 pins-cs { 852 pins-cs {
1004 pinmux = <PINMUX_GPIO 853 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
1005 drive-strength = <6>; 854 drive-strength = <6>;
1006 bias-pull-up; 855 bias-pull-up;
1007 }; 856 };
1008 }; 857 };
1009 858
1010 pcie0_pins_default: pcie0-default-pin <<
1011 pins-bus { <<
1012 pinmux = <PINMUX_GPIO <<
1013 <PINMUX_GPIO <<
1014 <PINMUX_GPIO <<
1015 bias-pull-up <<
1016 }; <<
1017 }; <<
1018 <<
1019 pcie1_pins_default: pcie1-default-pin <<
1020 pins-bus { <<
1021 pinmux = <PINMUX_GPIO <<
1022 <PINMUX_GPIO <<
1023 <PINMUX_GPIO <<
1024 bias-pull-up <<
1025 }; <<
1026 }; <<
1027 <<
1028 panel_fixed_pins: panel-pwr-default-p <<
1029 pins-vreg-en { <<
1030 pinmux = <PINMUX_GPIO <<
1031 }; <<
1032 }; <<
1033 <<
1034 pio_default: pio-default-pins { 859 pio_default: pio-default-pins {
1035 pins-wifi-enable { 860 pins-wifi-enable {
1036 pinmux = <PINMUX_GPIO 861 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
1037 output-high; 862 output-high;
1038 drive-strength = <14> 863 drive-strength = <14>;
1039 }; 864 };
1040 865
1041 pins-low-power-pd { 866 pins-low-power-pd {
1042 pinmux = <PINMUX_GPIO 867 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
1043 <PINMUX_GPIO 868 <PINMUX_GPIO26__FUNC_GPIO26>,
1044 <PINMUX_GPIO 869 <PINMUX_GPIO46__FUNC_GPIO46>,
1045 <PINMUX_GPIO 870 <PINMUX_GPIO47__FUNC_GPIO47>,
1046 <PINMUX_GPIO 871 <PINMUX_GPIO48__FUNC_GPIO48>,
1047 <PINMUX_GPIO 872 <PINMUX_GPIO65__FUNC_GPIO65>,
1048 <PINMUX_GPIO 873 <PINMUX_GPIO66__FUNC_GPIO66>,
1049 <PINMUX_GPIO 874 <PINMUX_GPIO67__FUNC_GPIO67>,
1050 <PINMUX_GPIO 875 <PINMUX_GPIO68__FUNC_GPIO68>,
1051 <PINMUX_GPIO 876 <PINMUX_GPIO128__FUNC_GPIO128>,
1052 <PINMUX_GPIO 877 <PINMUX_GPIO129__FUNC_GPIO129>;
1053 input-enable; 878 input-enable;
1054 bias-pull-down; 879 bias-pull-down;
1055 }; 880 };
1056 881
1057 pins-low-power-pupd { 882 pins-low-power-pupd {
1058 pinmux = <PINMUX_GPIO 883 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
1059 <PINMUX_GPIO 884 <PINMUX_GPIO78__FUNC_GPIO78>,
1060 <PINMUX_GPIO 885 <PINMUX_GPIO79__FUNC_GPIO79>,
1061 <PINMUX_GPIO 886 <PINMUX_GPIO80__FUNC_GPIO80>,
1062 <PINMUX_GPIO 887 <PINMUX_GPIO83__FUNC_GPIO83>,
1063 <PINMUX_GPIO 888 <PINMUX_GPIO85__FUNC_GPIO85>,
1064 <PINMUX_GPIO 889 <PINMUX_GPIO90__FUNC_GPIO90>,
1065 <PINMUX_GPIO 890 <PINMUX_GPIO91__FUNC_GPIO91>,
1066 <PINMUX_GPIO 891 <PINMUX_GPIO93__FUNC_GPIO93>,
1067 <PINMUX_GPIO 892 <PINMUX_GPIO94__FUNC_GPIO94>,
1068 <PINMUX_GPIO 893 <PINMUX_GPIO95__FUNC_GPIO95>,
1069 <PINMUX_GPIO 894 <PINMUX_GPIO96__FUNC_GPIO96>,
1070 <PINMUX_GPIO 895 <PINMUX_GPIO104__FUNC_GPIO104>,
1071 <PINMUX_GPIO 896 <PINMUX_GPIO105__FUNC_GPIO105>,
1072 <PINMUX_GPIO 897 <PINMUX_GPIO107__FUNC_GPIO107>;
1073 input-enable; 898 input-enable;
1074 bias-pull-down = <MTK 899 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1075 }; 900 };
1076 }; 901 };
1077 902
1078 rt1019p_pins_default: rt1019p-default 903 rt1019p_pins_default: rt1019p-default-pins {
1079 pins-amp-sdb { 904 pins-amp-sdb {
1080 pinmux = <PINMUX_GPIO 905 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>;
1081 output-low; 906 output-low;
1082 }; 907 };
1083 }; 908 };
1084 909
1085 scp_pins: scp-default-pins { 910 scp_pins: scp-default-pins {
1086 pins-vreq { 911 pins-vreq {
1087 pinmux = <PINMUX_GPIO 912 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
1088 bias-disable; 913 bias-disable;
1089 input-enable; 914 input-enable;
1090 }; 915 };
1091 }; 916 };
1092 917
1093 spi0_pins: spi0-default-pins { 918 spi0_pins: spi0-default-pins {
1094 pins-cs-mosi-clk { 919 pins-cs-mosi-clk {
1095 pinmux = <PINMUX_GPIO 920 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
1096 <PINMUX_GPIO 921 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
1097 <PINMUX_GPIO 922 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
1098 bias-disable; 923 bias-disable;
1099 }; 924 };
1100 925
1101 pins-miso { 926 pins-miso {
1102 pinmux = <PINMUX_GPIO 927 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
1103 bias-pull-down; 928 bias-pull-down;
1104 }; 929 };
1105 }; 930 };
1106 931
1107 subpmic_default: subpmic-default-pins 932 subpmic_default: subpmic-default-pins {
1108 subpmic_pin_irq: pins-subpmic 933 subpmic_pin_irq: pins-subpmic-int-n {
1109 pinmux = <PINMUX_GPIO 934 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
1110 input-enable; 935 input-enable;
1111 bias-pull-up; 936 bias-pull-up;
1112 }; 937 };
1113 }; 938 };
1114 939
1115 trackpad_pins: trackpad-default-pins 940 trackpad_pins: trackpad-default-pins {
1116 pins-int-n { 941 pins-int-n {
1117 pinmux = <PINMUX_GPIO 942 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
1118 input-enable; 943 input-enable;
1119 bias-pull-up; 944 bias-pull-up;
1120 }; 945 };
1121 }; 946 };
1122 947
1123 touchscreen_pins: touchscreen-default 948 touchscreen_pins: touchscreen-default-pins {
1124 pins-int-n { 949 pins-int-n {
1125 pinmux = <PINMUX_GPIO 950 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
1126 input-enable; 951 input-enable;
1127 bias-pull-up = <MTK_P 952 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1128 }; 953 };
1129 pins-rst { 954 pins-rst {
1130 pinmux = <PINMUX_GPIO 955 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
1131 output-high; 956 output-high;
1132 }; 957 };
1133 pins-report-sw { 958 pins-report-sw {
1134 pinmux = <PINMUX_GPIO 959 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
1135 output-low; 960 output-low;
1136 }; 961 };
1137 }; 962 };
1138 }; 963 };
1139 964
1140 &pmic { 965 &pmic {
1141 interrupts-extended = <&pio 222 IRQ_T 966 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1142 }; 967 };
1143 968
1144 &scp { 969 &scp {
1145 status = "okay"; 970 status = "okay";
1146 971
1147 firmware-name = "mediatek/mt8195/scp. 972 firmware-name = "mediatek/mt8195/scp.img";
1148 memory-region = <&scp_mem>; 973 memory-region = <&scp_mem>;
1149 pinctrl-names = "default"; 974 pinctrl-names = "default";
1150 pinctrl-0 = <&scp_pins>; 975 pinctrl-0 = <&scp_pins>;
1151 976
1152 cros-ec-rpmsg { 977 cros-ec-rpmsg {
1153 compatible = "google,cros-ec- 978 compatible = "google,cros-ec-rpmsg";
1154 mediatek,rpmsg-name = "cros-e 979 mediatek,rpmsg-name = "cros-ec-rpmsg";
1155 }; 980 };
1156 }; 981 };
1157 982
1158 &sound { 983 &sound {
1159 status = "okay"; 984 status = "okay";
1160 985
1161 mediatek,adsp = <&adsp>; 986 mediatek,adsp = <&adsp>;
1162 mediatek,dai-link = 987 mediatek,dai-link =
1163 "DL10_FE", "DPTX_BE", "ETDM1_ 988 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",
1164 "ETDM1_OUT_BE", "ETDM2_OUT_BE 989 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",
1165 "AFE_SOF_DL2", "AFE_SOF_DL3", 990 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
1166 pinctrl-names = "default"; 991 pinctrl-names = "default";
1167 pinctrl-0 = <&aud_pins_default>; 992 pinctrl-0 = <&aud_pins_default>;
1168 <<
1169 audio-routing = <<
1170 "Headphone", "HPOL", <<
1171 "Headphone", "HPOR", <<
1172 "IN1P", "Headset Mic", <<
1173 "Ext Spk", "Speaker"; <<
1174 <<
1175 mm-dai-link { <<
1176 link-name = "ETDM1_IN_BE"; <<
1177 mediatek,clk-provider = "cpu" <<
1178 }; <<
1179 <<
1180 hs-playback-dai-link { <<
1181 link-name = "ETDM1_OUT_BE"; <<
1182 mediatek,clk-provider = "cpu" <<
1183 codec { <<
1184 sound-dai = <&audio_c <<
1185 }; <<
1186 }; <<
1187 <<
1188 hs-capture-dai-link { <<
1189 link-name = "ETDM2_IN_BE"; <<
1190 mediatek,clk-provider = "cpu" <<
1191 codec { <<
1192 sound-dai = <&audio_c <<
1193 }; <<
1194 }; <<
1195 <<
1196 spk-playback-dai-link { <<
1197 link-name = "ETDM2_OUT_BE"; <<
1198 mediatek,clk-provider = "cpu" <<
1199 codec { <<
1200 sound-dai = <&spk_amp <<
1201 }; <<
1202 }; <<
1203 <<
1204 displayport-dai-link { <<
1205 link-name = "DPTX_BE"; <<
1206 codec { <<
1207 sound-dai = <&dp_tx>; <<
1208 }; <<
1209 }; <<
1210 }; 993 };
1211 994
1212 &spi0 { 995 &spi0 {
1213 status = "okay"; 996 status = "okay";
1214 997
1215 pinctrl-names = "default"; 998 pinctrl-names = "default";
1216 pinctrl-0 = <&spi0_pins>; 999 pinctrl-0 = <&spi0_pins>;
1217 mediatek,pad-select = <0>; 1000 mediatek,pad-select = <0>;
1218 1001
1219 cros_ec: ec@0 { 1002 cros_ec: ec@0 {
1220 #address-cells = <1>; 1003 #address-cells = <1>;
1221 #size-cells = <0>; 1004 #size-cells = <0>;
1222 1005
1223 compatible = "google,cros-ec- 1006 compatible = "google,cros-ec-spi";
1224 reg = <0>; 1007 reg = <0>;
1225 interrupts-extended = <&pio 4 1008 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
1226 pinctrl-names = "default"; 1009 pinctrl-names = "default";
1227 pinctrl-0 = <&cros_ec_int>; 1010 pinctrl-0 = <&cros_ec_int>;
1228 spi-max-frequency = <3000000> 1011 spi-max-frequency = <3000000>;
1229 wakeup-source; !! 1012
>> 1013 keyboard-backlight {
>> 1014 compatible = "google,cros-kbd-led-backlight";
>> 1015 };
1230 1016
1231 i2c_tunnel: i2c-tunnel { 1017 i2c_tunnel: i2c-tunnel {
1232 compatible = "google, 1018 compatible = "google,cros-ec-i2c-tunnel";
1233 google,remote-bus = < 1019 google,remote-bus = <0>;
1234 #address-cells = <1>; 1020 #address-cells = <1>;
1235 #size-cells = <0>; 1021 #size-cells = <0>;
1236 }; 1022 };
1237 1023
1238 mt_pmic_vmc_ldo_reg: regulato 1024 mt_pmic_vmc_ldo_reg: regulator@0 {
1239 compatible = "google, 1025 compatible = "google,cros-ec-regulator";
1240 reg = <0>; 1026 reg = <0>;
1241 regulator-name = "mt_ 1027 regulator-name = "mt_pmic_vmc_ldo";
1242 regulator-min-microvo 1028 regulator-min-microvolt = <1200000>;
1243 regulator-max-microvo 1029 regulator-max-microvolt = <3600000>;
1244 }; 1030 };
1245 1031
1246 mt_pmic_vmch_ldo_reg: regulat 1032 mt_pmic_vmch_ldo_reg: regulator@1 {
1247 compatible = "google, 1033 compatible = "google,cros-ec-regulator";
1248 reg = <1>; 1034 reg = <1>;
1249 regulator-name = "mt_ 1035 regulator-name = "mt_pmic_vmch_ldo";
1250 regulator-min-microvo 1036 regulator-min-microvolt = <2700000>;
1251 regulator-max-microvo 1037 regulator-max-microvolt = <3600000>;
1252 }; 1038 };
1253 1039
1254 typec { 1040 typec {
1255 compatible = "google, 1041 compatible = "google,cros-ec-typec";
1256 #address-cells = <1>; 1042 #address-cells = <1>;
1257 #size-cells = <0>; 1043 #size-cells = <0>;
1258 1044
1259 usb_c0: connector@0 { 1045 usb_c0: connector@0 {
1260 compatible = 1046 compatible = "usb-c-connector";
1261 reg = <0>; 1047 reg = <0>;
1262 power-role = 1048 power-role = "dual";
1263 data-role = " 1049 data-role = "host";
1264 try-power-rol 1050 try-power-role = "source";
1265 }; 1051 };
1266 1052
1267 usb_c1: connector@1 { 1053 usb_c1: connector@1 {
1268 compatible = 1054 compatible = "usb-c-connector";
1269 reg = <1>; 1055 reg = <1>;
1270 power-role = 1056 power-role = "dual";
1271 data-role = " 1057 data-role = "host";
1272 try-power-rol 1058 try-power-role = "source";
1273 }; 1059 };
1274 }; 1060 };
1275 }; 1061 };
1276 }; 1062 };
1277 1063
1278 &spmi { 1064 &spmi {
1279 #address-cells = <2>; 1065 #address-cells = <2>;
1280 #size-cells = <0>; 1066 #size-cells = <0>;
1281 1067
1282 mt6315@6 { 1068 mt6315@6 {
1283 compatible = "mediatek,mt6315 1069 compatible = "mediatek,mt6315-regulator";
1284 reg = <0x6 SPMI_USID>; 1070 reg = <0x6 SPMI_USID>;
1285 1071
1286 regulators { 1072 regulators {
1287 mt6315_6_vbuck1: vbuc 1073 mt6315_6_vbuck1: vbuck1 {
1288 regulator-com 1074 regulator-compatible = "vbuck1";
1289 regulator-nam 1075 regulator-name = "Vbcpu";
1290 regulator-min !! 1076 regulator-min-microvolt = <300000>;
1291 regulator-max 1077 regulator-max-microvolt = <1193750>;
1292 regulator-ena 1078 regulator-enable-ramp-delay = <256>;
1293 regulator-ram 1079 regulator-ramp-delay = <6250>;
1294 regulator-all 1080 regulator-allowed-modes = <0 1 2>;
1295 regulator-alw 1081 regulator-always-on;
1296 }; 1082 };
1297 }; 1083 };
1298 }; 1084 };
1299 1085
1300 mt6315@7 { 1086 mt6315@7 {
1301 compatible = "mediatek,mt6315 1087 compatible = "mediatek,mt6315-regulator";
1302 reg = <0x7 SPMI_USID>; 1088 reg = <0x7 SPMI_USID>;
1303 1089
1304 regulators { 1090 regulators {
1305 mt6315_7_vbuck1: vbuc 1091 mt6315_7_vbuck1: vbuck1 {
1306 regulator-com 1092 regulator-compatible = "vbuck1";
1307 regulator-nam 1093 regulator-name = "Vgpu";
1308 regulator-min !! 1094 regulator-min-microvolt = <625000>;
1309 regulator-max 1095 regulator-max-microvolt = <1193750>;
1310 regulator-ena 1096 regulator-enable-ramp-delay = <256>;
1311 regulator-ram 1097 regulator-ramp-delay = <6250>;
1312 regulator-all 1098 regulator-allowed-modes = <0 1 2>;
1313 }; !! 1099 regulator-always-on;
1314 }; <<
1315 }; <<
1316 }; <<
1317 <<
1318 &thermal_zones { <<
1319 soc-area-thermal { <<
1320 polling-delay = <1000>; <<
1321 polling-delay-passive = <250> <<
1322 thermal-sensors = <&tboard_th <<
1323 <<
1324 trips { <<
1325 trip-crit { <<
1326 temperature = <<
1327 hysteresis = <<
1328 type = "criti <<
1329 }; <<
1330 }; <<
1331 }; <<
1332 <<
1333 pmic-area-thermal { <<
1334 polling-delay = <1000>; <<
1335 polling-delay-passive = <0>; <<
1336 thermal-sensors = <&tboard_th <<
1337 <<
1338 trips { <<
1339 trip-crit { <<
1340 temperature = <<
1341 hysteresis = <<
1342 type = "criti <<
1343 }; 1100 };
1344 }; 1101 };
1345 }; 1102 };
1346 }; 1103 };
1347 1104
1348 &u3phy0 { 1105 &u3phy0 {
1349 status = "okay"; 1106 status = "okay";
1350 }; 1107 };
1351 1108
1352 &u3phy1 { 1109 &u3phy1 {
1353 status = "okay"; 1110 status = "okay";
1354 }; 1111 };
1355 1112
1356 &u3phy2 { 1113 &u3phy2 {
1357 status = "okay"; 1114 status = "okay";
1358 }; 1115 };
1359 1116
1360 &u3phy3 { 1117 &u3phy3 {
1361 status = "okay"; 1118 status = "okay";
1362 }; 1119 };
1363 1120
1364 &uart0 { 1121 &uart0 {
1365 status = "okay"; 1122 status = "okay";
1366 }; 1123 };
1367 1124
1368 /* <<
1369 * For the USB Type-C ports the role and alte <<
1370 * done by the EC so we set dr_mode to host t <<
1371 */ <<
1372 &ssusb0 { <<
1373 dr_mode = "host"; <<
1374 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1375 status = "okay"; <<
1376 }; <<
1377 <<
1378 &ssusb2 { <<
1379 dr_mode = "host"; <<
1380 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1381 status = "okay"; <<
1382 }; <<
1383 <<
1384 &ssusb3 { <<
1385 dr_mode = "host"; <<
1386 vusb33-supply = <&mt6359_vusb_ldo_reg <<
1387 status = "okay"; <<
1388 }; <<
1389 <<
1390 &xhci0 { 1125 &xhci0 {
1391 status = "okay"; 1126 status = "okay";
1392 1127
1393 rx-fifo-depth = <3072>; !! 1128 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1394 vbus-supply = <&usb_vbus>; 1129 vbus-supply = <&usb_vbus>;
1395 }; 1130 };
1396 1131
1397 &xhci1 { 1132 &xhci1 {
1398 status = "okay"; 1133 status = "okay";
1399 1134
1400 phys = <&u2port1 PHY_TYPE_USB2>; <<
1401 rx-fifo-depth = <3072>; <<
1402 vusb33-supply = <&mt6359_vusb_ldo_reg 1135 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1403 vbus-supply = <&usb_vbus>; 1136 vbus-supply = <&usb_vbus>;
1404 mediatek,u3p-dis-msk = <1>; <<
1405 }; 1137 };
1406 1138
1407 &xhci2 { 1139 &xhci2 {
1408 status = "okay"; 1140 status = "okay";
>> 1141
>> 1142 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1409 vbus-supply = <&usb_vbus>; 1143 vbus-supply = <&usb_vbus>;
1410 }; 1144 };
1411 1145
1412 &xhci3 { 1146 &xhci3 {
1413 status = "okay"; 1147 status = "okay";
1414 1148
1415 /* MT7921's USB Bluetooth has issues 1149 /* MT7921's USB Bluetooth has issues with USB2 LPM */
1416 usb2-lpm-disable; 1150 usb2-lpm-disable;
>> 1151 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1417 vbus-supply = <&usb_vbus>; 1152 vbus-supply = <&usb_vbus>;
1418 }; 1153 };
1419 1154
1420 #include <arm/cros-ec-keyboard.dtsi> 1155 #include <arm/cros-ec-keyboard.dtsi>
1421 #include <arm/cros-ec-sbs.dtsi> 1156 #include <arm/cros-ec-sbs.dtsi>
1422 1157
1423 &keyboard_controller { 1158 &keyboard_controller {
1424 function-row-physmap = < 1159 function-row-physmap = <
1425 MATRIX_KEY(0x00, 0x02, 0) 1160 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
1426 MATRIX_KEY(0x03, 0x02, 0) 1161 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
1427 MATRIX_KEY(0x02, 0x02, 0) 1162 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
1428 MATRIX_KEY(0x01, 0x02, 0) 1163 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
1429 MATRIX_KEY(0x03, 0x04, 0) 1164 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
1430 MATRIX_KEY(0x02, 0x04, 0) 1165 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
1431 MATRIX_KEY(0x01, 0x04, 0) 1166 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
1432 MATRIX_KEY(0x02, 0x09, 0) 1167 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
1433 MATRIX_KEY(0x01, 0x09, 0) 1168 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
1434 MATRIX_KEY(0x00, 0x04, 0) 1169 MATRIX_KEY(0x00, 0x04, 0) /* T10 */
1435 <<
1436 /* T11 to T13 are present onl <<
1437 MATRIX_KEY(0x00, 0x01, 0) <<
1438 MATRIX_KEY(0x01, 0x05, 0) <<
1439 MATRIX_KEY(0x03, 0x05, 0) <<
1440 >; 1170 >;
1441 1171
1442 linux,keymap = < 1172 linux,keymap = <
1443 MATRIX_KEY(0x00, 0x02, KEY_BA 1173 MATRIX_KEY(0x00, 0x02, KEY_BACK)
1444 MATRIX_KEY(0x03, 0x02, KEY_RE 1174 MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
1445 MATRIX_KEY(0x02, 0x02, KEY_ZO 1175 MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
1446 MATRIX_KEY(0x01, 0x02, KEY_SC 1176 MATRIX_KEY(0x01, 0x02, KEY_SCALE)
1447 MATRIX_KEY(0x03, 0x04, KEY_SY 1177 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
1448 MATRIX_KEY(0x02, 0x04, KEY_BR 1178 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
1449 MATRIX_KEY(0x01, 0x04, KEY_BR 1179 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
1450 MATRIX_KEY(0x02, 0x09, KEY_MU 1180 MATRIX_KEY(0x02, 0x09, KEY_MUTE)
1451 MATRIX_KEY(0x01, 0x09, KEY_VO 1181 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
1452 MATRIX_KEY(0x00, 0x04, KEY_VO 1182 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
1453 1183
1454 CROS_STD_MAIN_KEYMAP 1184 CROS_STD_MAIN_KEYMAP
1455 >; 1185 >;
1456 }; 1186 };
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