1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/interrupt-controller/irq
12 #include <dt-bindings/memory/mt8195-memory-por
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-th
19
20 / {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
29 gce0 = &gce0;
30 gce1 = &gce1;
31 ethdr0 = ðdr0;
32 mutex0 = &mutex;
33 mutex1 = &mutex1;
34 merge1 = &merge1;
35 merge2 = &merge2;
36 merge3 = &merge3;
37 merge4 = &merge4;
38 merge5 = &merge5;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cort
56 reg = <0x000>;
57 enable-method = "psci"
58 performance-domains =
59 clock-frequency = <170
60 capacity-dmips-mhz = <
61 cpu-idle-states = <&cp
62 i-cache-size = <32768>
63 i-cache-line-size = <6
64 i-cache-sets = <128>;
65 d-cache-size = <32768>
66 d-cache-line-size = <6
67 d-cache-sets = <128>;
68 next-level-cache = <&l
69 #cooling-cells = <2>;
70 };
71
72 cpu1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cort
75 reg = <0x100>;
76 enable-method = "psci"
77 performance-domains =
78 clock-frequency = <170
79 capacity-dmips-mhz = <
80 cpu-idle-states = <&cp
81 i-cache-size = <32768>
82 i-cache-line-size = <6
83 i-cache-sets = <128>;
84 d-cache-size = <32768>
85 d-cache-line-size = <6
86 d-cache-sets = <128>;
87 next-level-cache = <&l
88 #cooling-cells = <2>;
89 };
90
91 cpu2: cpu@200 {
92 device_type = "cpu";
93 compatible = "arm,cort
94 reg = <0x200>;
95 enable-method = "psci"
96 performance-domains =
97 clock-frequency = <170
98 capacity-dmips-mhz = <
99 cpu-idle-states = <&cp
100 i-cache-size = <32768>
101 i-cache-line-size = <6
102 i-cache-sets = <128>;
103 d-cache-size = <32768>
104 d-cache-line-size = <6
105 d-cache-sets = <128>;
106 next-level-cache = <&l
107 #cooling-cells = <2>;
108 };
109
110 cpu3: cpu@300 {
111 device_type = "cpu";
112 compatible = "arm,cort
113 reg = <0x300>;
114 enable-method = "psci"
115 performance-domains =
116 clock-frequency = <170
117 capacity-dmips-mhz = <
118 cpu-idle-states = <&cp
119 i-cache-size = <32768>
120 i-cache-line-size = <6
121 i-cache-sets = <128>;
122 d-cache-size = <32768>
123 d-cache-line-size = <6
124 d-cache-sets = <128>;
125 next-level-cache = <&l
126 #cooling-cells = <2>;
127 };
128
129 cpu4: cpu@400 {
130 device_type = "cpu";
131 compatible = "arm,cort
132 reg = <0x400>;
133 enable-method = "psci"
134 performance-domains =
135 clock-frequency = <217
136 capacity-dmips-mhz = <
137 cpu-idle-states = <&cp
138 i-cache-size = <65536>
139 i-cache-line-size = <6
140 i-cache-sets = <256>;
141 d-cache-size = <65536>
142 d-cache-line-size = <6
143 d-cache-sets = <256>;
144 next-level-cache = <&l
145 #cooling-cells = <2>;
146 };
147
148 cpu5: cpu@500 {
149 device_type = "cpu";
150 compatible = "arm,cort
151 reg = <0x500>;
152 enable-method = "psci"
153 performance-domains =
154 clock-frequency = <217
155 capacity-dmips-mhz = <
156 cpu-idle-states = <&cp
157 i-cache-size = <65536>
158 i-cache-line-size = <6
159 i-cache-sets = <256>;
160 d-cache-size = <65536>
161 d-cache-line-size = <6
162 d-cache-sets = <256>;
163 next-level-cache = <&l
164 #cooling-cells = <2>;
165 };
166
167 cpu6: cpu@600 {
168 device_type = "cpu";
169 compatible = "arm,cort
170 reg = <0x600>;
171 enable-method = "psci"
172 performance-domains =
173 clock-frequency = <217
174 capacity-dmips-mhz = <
175 cpu-idle-states = <&cp
176 i-cache-size = <65536>
177 i-cache-line-size = <6
178 i-cache-sets = <256>;
179 d-cache-size = <65536>
180 d-cache-line-size = <6
181 d-cache-sets = <256>;
182 next-level-cache = <&l
183 #cooling-cells = <2>;
184 };
185
186 cpu7: cpu@700 {
187 device_type = "cpu";
188 compatible = "arm,cort
189 reg = <0x700>;
190 enable-method = "psci"
191 performance-domains =
192 clock-frequency = <217
193 capacity-dmips-mhz = <
194 cpu-idle-states = <&cp
195 i-cache-size = <65536>
196 i-cache-line-size = <6
197 i-cache-sets = <256>;
198 d-cache-size = <65536>
199 d-cache-line-size = <6
200 d-cache-sets = <256>;
201 next-level-cache = <&l
202 #cooling-cells = <2>;
203 };
204
205 cpu-map {
206 cluster0 {
207 core0 {
208 cpu =
209 };
210
211 core1 {
212 cpu =
213 };
214
215 core2 {
216 cpu =
217 };
218
219 core3 {
220 cpu =
221 };
222
223 core4 {
224 cpu =
225 };
226
227 core5 {
228 cpu =
229 };
230
231 core6 {
232 cpu =
233 };
234
235 core7 {
236 cpu =
237 };
238 };
239 };
240
241 idle-states {
242 entry-method = "psci";
243
244 cpu_ret_l: cpu-retenti
245 compatible = "
246 arm,psci-suspe
247 local-timer-st
248 entry-latency-
249 exit-latency-u
250 min-residency-
251 };
252
253 cpu_ret_b: cpu-retenti
254 compatible = "
255 arm,psci-suspe
256 local-timer-st
257 entry-latency-
258 exit-latency-u
259 min-residency-
260 };
261
262 cpu_off_l: cpu-off-l {
263 compatible = "
264 arm,psci-suspe
265 local-timer-st
266 entry-latency-
267 exit-latency-u
268 min-residency-
269 };
270
271 cpu_off_b: cpu-off-b {
272 compatible = "
273 arm,psci-suspe
274 local-timer-st
275 entry-latency-
276 exit-latency-u
277 min-residency-
278 };
279 };
280
281 l2_0: l2-cache0 {
282 compatible = "cache";
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>
286 cache-sets = <512>;
287 next-level-cache = <&l
288 cache-unified;
289 };
290
291 l2_1: l2-cache1 {
292 compatible = "cache";
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>
296 cache-sets = <512>;
297 next-level-cache = <&l
298 cache-unified;
299 };
300
301 l3_0: l3-cache {
302 compatible = "cache";
303 cache-level = <3>;
304 cache-size = <2097152>
305 cache-line-size = <64>
306 cache-sets = <2048>;
307 cache-unified;
308 };
309 };
310
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_T
314 cpus = <&cpu0>, <&cpu1>, <&cpu
315 <&cpu4>, <&cpu5>, <&cpu
316 status = "fail";
317 };
318
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
323 };
324
325 sound: mt8195-sound {
326 mediatek,platform = <&afe>;
327 status = "disabled";
328 };
329
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clo
332 #clock-cells = <0>;
333 clocks = <&clk26m>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
337 };
338
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
344 };
345
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
351 };
352
353 performance: performance-controller@11
354 compatible = "mediatek,cpufreq
355 reg = <0 0x0011bc10 0 0x120>,
356 #performance-domain-cells = <1
357 };
358
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points
361 opp-shared;
362
363 opp-390000000 {
364 opp-hz = /bits/ 64 <39
365 opp-microvolt = <62500
366 };
367 opp-410000000 {
368 opp-hz = /bits/ 64 <41
369 opp-microvolt = <63125
370 };
371 opp-431000000 {
372 opp-hz = /bits/ 64 <43
373 opp-microvolt = <63125
374 };
375 opp-473000000 {
376 opp-hz = /bits/ 64 <47
377 opp-microvolt = <63750
378 };
379 opp-515000000 {
380 opp-hz = /bits/ 64 <51
381 opp-microvolt = <63750
382 };
383 opp-556000000 {
384 opp-hz = /bits/ 64 <55
385 opp-microvolt = <64375
386 };
387 opp-598000000 {
388 opp-hz = /bits/ 64 <59
389 opp-microvolt = <65000
390 };
391 opp-640000000 {
392 opp-hz = /bits/ 64 <64
393 opp-microvolt = <65000
394 };
395 opp-670000000 {
396 opp-hz = /bits/ 64 <67
397 opp-microvolt = <66250
398 };
399 opp-700000000 {
400 opp-hz = /bits/ 64 <70
401 opp-microvolt = <67500
402 };
403 opp-730000000 {
404 opp-hz = /bits/ 64 <73
405 opp-microvolt = <68750
406 };
407 opp-760000000 {
408 opp-hz = /bits/ 64 <76
409 opp-microvolt = <70000
410 };
411 opp-790000000 {
412 opp-hz = /bits/ 64 <79
413 opp-microvolt = <71250
414 };
415 opp-820000000 {
416 opp-hz = /bits/ 64 <82
417 opp-microvolt = <72500
418 };
419 opp-850000000 {
420 opp-hz = /bits/ 64 <85
421 opp-microvolt = <73750
422 };
423 opp-880000000 {
424 opp-hz = /bits/ 64 <88
425 opp-microvolt = <75000
426 };
427 };
428
429 pmu-a55 {
430 compatible = "arm,cortex-a55-p
431 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TY
433 };
434
435 pmu-a78 {
436 compatible = "arm,cortex-a78-p
437 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TY
439 };
440
441 psci {
442 compatible = "arm,psci-1.0";
443 method = "smc";
444 };
445
446 timer: timer {
447 compatible = "arm,armv8-timer"
448 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_T
450 <GIC_PPI 14 IRQ_T
451 <GIC_PPI 11 IRQ_T
452 <GIC_PPI 10 IRQ_T
453 };
454
455 soc {
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
459 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0
461
462 gic: interrupt-controller@c000
463 compatible = "arm,gic-
464 #interrupt-cells = <4>
465 #redistributor-regions
466 interrupt-parent = <&g
467 interrupt-controller;
468 reg = <0 0x0c000000 0
469 <0 0x0c040000 0
470 interrupts = <GIC_PPI
471
472 ppi-partitions {
473 ppi_cluster0:
474 affini
475 };
476
477 ppi_cluster1:
478 affini
479 };
480 };
481 };
482
483 topckgen: syscon@10000000 {
484 compatible = "mediatek
485 reg = <0 0x10000000 0
486 #clock-cells = <1>;
487 };
488
489 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek
491 reg = <0 0x10001000 0
492 #clock-cells = <1>;
493 #reset-cells = <1>;
494 };
495
496 pericfg: syscon@10003000 {
497 compatible = "mediatek
498 reg = <0 0x10003000 0
499 #clock-cells = <1>;
500 };
501
502 pio: pinctrl@10005000 {
503 compatible = "mediatek
504 reg = <0 0x10005000 0
505 <0 0x11d10000 0
506 <0 0x11d30000 0
507 <0 0x11d40000 0
508 <0 0x11e20000 0
509 <0 0x11eb0000 0
510 <0 0x11f40000 0
511 <0 0x1000b000 0
512 reg-names = "iocfg0",
513 "iocfg_br"
514 "iocfg_tl"
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0
518 interrupt-controller;
519 interrupts = <GIC_SPI
520 #interrupt-cells = <2>
521 };
522
523 scpsys: syscon@10006000 {
524 compatible = "mediatek
525 reg = <0 0x10006000 0
526
527 /* System Power Manage
528 spm: power-controller
529 compatible = "
530 #address-cells
531 #size-cells =
532 #power-domain-
533
534 /* power domai
535 mfg0: power-do
536 reg =
537 #addre
538 #size-
539 #power
540
541 mfg1:
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575 };
576 };
577
578 power-domain@M
579 reg =
580 clocks
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607 clock-
608
609
610
611
612
613
614
615 mediat
616 #addre
617 #size-
618 #power
619
620 power-
621
622
623
624
625
626 };
627
628 power-
629
630
631
632
633
634 };
635
636 power-
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788 };
789 };
790
791 power-domain@M
792 reg =
793 mediat
794 #power
795 };
796
797 power-domain@M
798 reg =
799 mediat
800 #power
801 };
802
803 power-domain@M
804 reg =
805 #power
806 };
807
808 power-domain@M
809 reg =
810 #power
811 };
812
813 power-domain@M
814 reg =
815 clocks
816
817 clock-
818 #power
819 };
820
821 power-domain@M
822 reg =
823 clocks
824 clock-
825 #power
826 };
827
828 power-domain@M
829 reg =
830 clocks
831
832 clock-
833 #addre
834 #size-
835 mediat
836 #power
837
838 power-
839
840
841
842
843
844
845
846
847
848 };
849 };
850 };
851 };
852
853 watchdog: watchdog@10007000 {
854 compatible = "mediatek
855 mediatek,disable-extrs
856 reg = <0 0x10007000 0
857 #reset-cells = <1>;
858 };
859
860 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek
862 reg = <0 0x1000c000 0
863 #clock-cells = <1>;
864 };
865
866 systimer: timer@10017000 {
867 compatible = "mediatek
868 "mediatek
869 reg = <0 0x10017000 0
870 interrupts = <GIC_SPI
871 clocks = <&clk13m>;
872 };
873
874 pwrap: pwrap@10024000 {
875 compatible = "mediatek
876 reg = <0 0x10024000 0
877 reg-names = "pwrap";
878 interrupts = <GIC_SPI
879 clocks = <&infracfg_ao
880 <&infracfg_ao
881 clock-names = "spi", "
882 assigned-clocks = <&to
883 assigned-clock-parents
884 };
885
886 spmi: spmi@10027000 {
887 compatible = "mediatek
888 reg = <0 0x10027000 0
889 <0 0x10029000 0
890 reg-names = "pmif", "s
891 clocks = <&infracfg_ao
892 <&infracfg_ao
893 <&topckgen CL
894 clock-names = "pmif_sy
895 "pmif_tm
896 "spmimst
897 assigned-clocks = <&to
898 assigned-clock-parents
899 };
900
901 iommu_infra: infra-iommu@10315
902 compatible = "mediatek
903 reg = <0 0x10315000 0
904 interrupts = <GIC_SPI
905 <GIC_SPI
906 <GIC_SPI
907 <GIC_SPI
908 <GIC_SPI
909 #iommu-cells = <1>;
910 };
911
912 gce0: mailbox@10320000 {
913 compatible = "mediatek
914 reg = <0 0x10320000 0
915 interrupts = <GIC_SPI
916 #mbox-cells = <2>;
917 clocks = <&infracfg_ao
918 };
919
920 gce1: mailbox@10330000 {
921 compatible = "mediatek
922 reg = <0 0x10330000 0
923 interrupts = <GIC_SPI
924 #mbox-cells = <2>;
925 clocks = <&infracfg_ao
926 };
927
928 scp: scp@10500000 {
929 compatible = "mediatek
930 reg = <0 0x10500000 0
931 <0 0x10720000 0
932 <0 0x10700000 0
933 reg-names = "sram", "c
934 interrupts = <GIC_SPI
935 status = "disabled";
936 };
937
938 scp_adsp: clock-controller@107
939 compatible = "mediatek
940 reg = <0 0x10720000 0
941 #clock-cells = <1>;
942 };
943
944 adsp: dsp@10803000 {
945 compatible = "mediatek
946 reg = <0 0x10803000 0
947 <0 0x10840000 0
948 reg-names = "cfg", "sr
949 clocks = <&topckgen CL
950 <&clk26m>,
951 <&topckgen CL
952 <&topckgen CL
953 <&scp_adsp CL
954 <&topckgen CL
955 clock-names = "adsp_se
956 "clk26m_ck",
957 "audio_local_
958 "mainpll_d7_d
959 "scp_adsp_aud
960 "audio_h";
961 power-domains = <&spm
962 mbox-names = "rx", "tx
963 mboxes = <&adsp_mailbo
964 status = "disabled";
965 };
966
967 adsp_mailbox0: mailbox@1081600
968 compatible = "mediatek
969 #mbox-cells = <0>;
970 reg = <0 0x10816000 0
971 interrupts = <GIC_SPI
972 };
973
974 adsp_mailbox1: mailbox@1081700
975 compatible = "mediatek
976 #mbox-cells = <0>;
977 reg = <0 0x10817000 0
978 interrupts = <GIC_SPI
979 };
980
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek
983 reg = <0 0x10890000 0
984 mediatek,topckgen = <&
985 power-domains = <&spm
986 interrupts = <GIC_SPI
987 resets = <&watchdog 14
988 reset-names = "audiosy
989 clocks = <&clk26m>,
990 <&apmixedsys C
991 <&apmixedsys C
992 <&topckgen CLK
993 <&topckgen CLK
994 <&topckgen CLK
995 <&topckgen CLK
996 <&topckgen CLK
997 <&topckgen CLK
998 <&topckgen CLK
999 <&topckgen CLK
1000 <&topckgen CL
1001 <&topckgen CL
1002 <&topckgen CL
1003 <&topckgen CL
1004 <&topckgen CL
1005 <&topckgen CL
1006 <&infracfg_ao
1007 <&scp_adsp CL
1008 clock-names = "clk26m
1009 "apll1_ck",
1010 "apll2_ck",
1011 "apll12_div0"
1012 "apll12_div1"
1013 "apll12_div2"
1014 "apll12_div3"
1015 "apll12_div9"
1016 "a1sys_hp_sel
1017 "aud_intbus_s
1018 "audio_h_sel"
1019 "audio_local_
1020 "dptx_m_sel",
1021 "i2so1_m_sel"
1022 "i2so2_m_sel"
1023 "i2si1_m_sel"
1024 "i2si2_m_sel"
1025 "infra_ao_aud
1026 "scp_adsp_aud
1027 status = "disabled";
1028 };
1029
1030 uart0: serial@11001100 {
1031 compatible = "mediate
1032 "mediate
1033 reg = <0 0x11001100 0
1034 interrupts = <GIC_SPI
1035 clocks = <&clk26m>, <
1036 clock-names = "baud",
1037 status = "disabled";
1038 };
1039
1040 uart1: serial@11001200 {
1041 compatible = "mediate
1042 "mediate
1043 reg = <0 0x11001200 0
1044 interrupts = <GIC_SPI
1045 clocks = <&clk26m>, <
1046 clock-names = "baud",
1047 status = "disabled";
1048 };
1049
1050 uart2: serial@11001300 {
1051 compatible = "mediate
1052 "mediate
1053 reg = <0 0x11001300 0
1054 interrupts = <GIC_SPI
1055 clocks = <&clk26m>, <
1056 clock-names = "baud",
1057 status = "disabled";
1058 };
1059
1060 uart3: serial@11001400 {
1061 compatible = "mediate
1062 "mediate
1063 reg = <0 0x11001400 0
1064 interrupts = <GIC_SPI
1065 clocks = <&clk26m>, <
1066 clock-names = "baud",
1067 status = "disabled";
1068 };
1069
1070 uart4: serial@11001500 {
1071 compatible = "mediate
1072 "mediate
1073 reg = <0 0x11001500 0
1074 interrupts = <GIC_SPI
1075 clocks = <&clk26m>, <
1076 clock-names = "baud",
1077 status = "disabled";
1078 };
1079
1080 uart5: serial@11001600 {
1081 compatible = "mediate
1082 "mediate
1083 reg = <0 0x11001600 0
1084 interrupts = <GIC_SPI
1085 clocks = <&clk26m>, <
1086 clock-names = "baud",
1087 status = "disabled";
1088 };
1089
1090 auxadc: auxadc@11002000 {
1091 compatible = "mediate
1092 "mediate
1093 reg = <0 0x11002000 0
1094 clocks = <&infracfg_a
1095 clock-names = "main";
1096 #io-channel-cells = <
1097 status = "disabled";
1098 };
1099
1100 pericfg_ao: syscon@11003000 {
1101 compatible = "mediate
1102 reg = <0 0x11003000 0
1103 #clock-cells = <1>;
1104 };
1105
1106 spi0: spi@1100a000 {
1107 compatible = "mediate
1108 "mediate
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 reg = <0 0x1100a000 0
1112 interrupts = <GIC_SPI
1113 clocks = <&topckgen C
1114 <&topckgen C
1115 <&infracfg_a
1116 clock-names = "parent
1117 status = "disabled";
1118 };
1119
1120 lvts_ap: thermal-sensor@1100b
1121 compatible = "mediate
1122 reg = <0 0x1100b000 0
1123 interrupts = <GIC_SPI
1124 clocks = <&infracfg_a
1125 resets = <&infracfg_a
1126 nvmem-cells = <&lvts_
1127 nvmem-cell-names = "l
1128 #thermal-sensor-cells
1129 };
1130
1131 svs: svs@1100bc00 {
1132 compatible = "mediate
1133 reg = <0 0x1100bc00 0
1134 interrupts = <GIC_SPI
1135 clocks = <&infracfg_a
1136 clock-names = "main";
1137 nvmem-cells = <&svs_c
1138 nvmem-cell-names = "s
1139 resets = <&infracfg_a
1140 reset-names = "svs_rs
1141 };
1142
1143 disp_pwm0: pwm@1100e000 {
1144 compatible = "mediate
1145 reg = <0 0x1100e000 0
1146 interrupts = <GIC_SPI
1147 power-domains = <&spm
1148 #pwm-cells = <2>;
1149 clocks = <&topckgen C
1150 <&infracfg_a
1151 clock-names = "main",
1152 status = "disabled";
1153 };
1154
1155 disp_pwm1: pwm@1100f000 {
1156 compatible = "mediate
1157 reg = <0 0x1100f000 0
1158 interrupts = <GIC_SPI
1159 #pwm-cells = <2>;
1160 clocks = <&topckgen C
1161 <&infracfg_a
1162 clock-names = "main",
1163 status = "disabled";
1164 };
1165
1166 spi1: spi@11010000 {
1167 compatible = "mediate
1168 "mediate
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171 reg = <0 0x11010000 0
1172 interrupts = <GIC_SPI
1173 clocks = <&topckgen C
1174 <&topckgen C
1175 <&infracfg_a
1176 clock-names = "parent
1177 status = "disabled";
1178 };
1179
1180 spi2: spi@11012000 {
1181 compatible = "mediate
1182 "mediate
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 reg = <0 0x11012000 0
1186 interrupts = <GIC_SPI
1187 clocks = <&topckgen C
1188 <&topckgen C
1189 <&infracfg_a
1190 clock-names = "parent
1191 status = "disabled";
1192 };
1193
1194 spi3: spi@11013000 {
1195 compatible = "mediate
1196 "mediate
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 reg = <0 0x11013000 0
1200 interrupts = <GIC_SPI
1201 clocks = <&topckgen C
1202 <&topckgen C
1203 <&infracfg_a
1204 clock-names = "parent
1205 status = "disabled";
1206 };
1207
1208 spi4: spi@11018000 {
1209 compatible = "mediate
1210 "mediate
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 reg = <0 0x11018000 0
1214 interrupts = <GIC_SPI
1215 clocks = <&topckgen C
1216 <&topckgen C
1217 <&infracfg_a
1218 clock-names = "parent
1219 status = "disabled";
1220 };
1221
1222 spi5: spi@11019000 {
1223 compatible = "mediate
1224 "mediate
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 reg = <0 0x11019000 0
1228 interrupts = <GIC_SPI
1229 clocks = <&topckgen C
1230 <&topckgen C
1231 <&infracfg_a
1232 clock-names = "parent
1233 status = "disabled";
1234 };
1235
1236 spis0: spi@1101d000 {
1237 compatible = "mediate
1238 reg = <0 0x1101d000 0
1239 interrupts = <GIC_SPI
1240 clocks = <&infracfg_a
1241 clock-names = "spi";
1242 assigned-clocks = <&t
1243 assigned-clock-parent
1244 status = "disabled";
1245 };
1246
1247 spis1: spi@1101e000 {
1248 compatible = "mediate
1249 reg = <0 0x1101e000 0
1250 interrupts = <GIC_SPI
1251 clocks = <&infracfg_a
1252 clock-names = "spi";
1253 assigned-clocks = <&t
1254 assigned-clock-parent
1255 status = "disabled";
1256 };
1257
1258 eth: ethernet@11021000 {
1259 compatible = "mediate
1260 reg = <0 0x11021000 0
1261 interrupts = <GIC_SPI
1262 interrupt-names = "ma
1263 clock-names = "axi",
1264 "apb",
1265 "mac_ma
1266 "ptp_re
1267 "rmii_i
1268 "mac_cg
1269 clocks = <&pericfg_ao
1270 <&pericfg_ao
1271 <&topckgen C
1272 <&topckgen C
1273 <&topckgen C
1274 <&pericfg_ao
1275 assigned-clocks = <&t
1276 <&t
1277 <&t
1278 assigned-clock-parent
1279
1280
1281 power-domains = <&spm
1282 mediatek,pericfg = <&
1283 snps,axi-config = <&s
1284 snps,mtl-rx-config =
1285 snps,mtl-tx-config =
1286 snps,txpbl = <16>;
1287 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>;
1289 status = "disabled";
1290
1291 mdio {
1292 compatible =
1293 #address-cell
1294 #size-cells =
1295 };
1296
1297 stmmac_axi_setup: stm
1298 snps,wr_osr_l
1299 snps,rd_osr_l
1300 snps,blen = <
1301 };
1302
1303 mtl_rx_setup: rx-queu
1304 snps,rx-queue
1305 snps,rx-sched
1306 queue0 {
1307 snps,
1308 snps,
1309 };
1310 queue1 {
1311 snps,
1312 snps,
1313 };
1314 queue2 {
1315 snps,
1316 snps,
1317 };
1318 queue3 {
1319 snps,
1320 snps,
1321 };
1322 };
1323
1324 mtl_tx_setup: tx-queu
1325 snps,tx-queue
1326 snps,tx-sched
1327 queue0 {
1328 snps,
1329 snps,
1330 snps,
1331 };
1332 queue1 {
1333 snps,
1334 snps,
1335 snps,
1336 };
1337 queue2 {
1338 snps,
1339 snps,
1340 snps,
1341 };
1342 queue3 {
1343 snps,
1344 snps,
1345 snps,
1346 };
1347 };
1348 };
1349
1350 ssusb0: usb@11201000 {
1351 compatible = "mediate
1352 reg = <0 0x11201000 0
1353 reg-names = "mac", "i
1354 ranges = <0 0 0 0x112
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1357 interrupts = <GIC_SPI
1358 clocks = <&infracfg_a
1359 <&topckgen C
1360 <&infracfg_a
1361 clock-names = "sys_ck
1362 phys = <&u2port0 PHY_
1363 wakeup-source;
1364 mediatek,syscon-wakeu
1365 status = "disabled";
1366
1367 xhci0: usb@0 {
1368 compatible =
1369 reg = <0 0 0
1370 reg-names = "
1371 interrupts =
1372 assigned-cloc
1373
1374 assigned-cloc
1375
1376 clocks = <&in
1377 <&to
1378 <&ap
1379 <&cl
1380 <&in
1381 clock-names =
1382 status = "dis
1383 };
1384 };
1385
1386 mmc0: mmc@11230000 {
1387 compatible = "mediate
1388 "mediate
1389 reg = <0 0x11230000 0
1390 <0 0x11f50000 0
1391 interrupts = <GIC_SPI
1392 clocks = <&topckgen C
1393 <&infracfg_a
1394 <&infracfg_a
1395 clock-names = "source
1396 status = "disabled";
1397 };
1398
1399 mmc1: mmc@11240000 {
1400 compatible = "mediate
1401 "mediate
1402 reg = <0 0x11240000 0
1403 <0 0x11c70000 0
1404 interrupts = <GIC_SPI
1405 clocks = <&topckgen C
1406 <&infracfg_a
1407 <&infracfg_a
1408 clock-names = "source
1409 assigned-clocks = <&t
1410 assigned-clock-parent
1411 status = "disabled";
1412 };
1413
1414 mmc2: mmc@11250000 {
1415 compatible = "mediate
1416 "mediate
1417 reg = <0 0x11250000 0
1418 <0 0x11e60000 0
1419 interrupts = <GIC_SPI
1420 clocks = <&topckgen C
1421 <&infracfg_a
1422 <&infracfg_a
1423 clock-names = "source
1424 assigned-clocks = <&t
1425 assigned-clock-parent
1426 status = "disabled";
1427 };
1428
1429 lvts_mcu: thermal-sensor@1127
1430 compatible = "mediate
1431 reg = <0 0x11278000 0
1432 interrupts = <GIC_SPI
1433 clocks = <&infracfg_a
1434 resets = <&infracfg_a
1435 nvmem-cells = <&lvts_
1436 nvmem-cell-names = "l
1437 #thermal-sensor-cells
1438 };
1439
1440 xhci1: usb@11290000 {
1441 compatible = "mediate
1442 "mediate
1443 reg = <0 0x11290000 0
1444 <0 0x11293e00 0
1445 reg-names = "mac", "i
1446 interrupts = <GIC_SPI
1447 phys = <&u2port1 PHY_
1448 assigned-clocks = <&t
1449 <&t
1450 assigned-clock-parent
1451
1452 clocks = <&pericfg_ao
1453 <&topckgen C
1454 <&apmixedsys
1455 <&clk26m>,
1456 <&pericfg_ao
1457 clock-names = "sys_ck
1458 "xhci_c
1459 mediatek,syscon-wakeu
1460 wakeup-source;
1461 status = "disabled";
1462 };
1463
1464 ssusb2: usb@112a1000 {
1465 compatible = "mediate
1466 reg = <0 0x112a1000 0
1467 reg-names = "mac", "i
1468 ranges = <0 0 0 0x112
1469 #address-cells = <2>;
1470 #size-cells = <2>;
1471 interrupts = <GIC_SPI
1472 assigned-clocks = <&t
1473 assigned-clock-parent
1474 clocks = <&pericfg_ao
1475 <&topckgen C
1476 <&pericfg_ao
1477 clock-names = "sys_ck
1478 phys = <&u2port2 PHY_
1479 wakeup-source;
1480 mediatek,syscon-wakeu
1481 status = "disabled";
1482
1483 xhci2: usb@0 {
1484 compatible =
1485 reg = <0 0 0
1486 reg-names = "
1487 interrupts =
1488 assigned-cloc
1489 assigned-cloc
1490 clocks = <&pe
1491 clock-names =
1492 status = "dis
1493 };
1494 };
1495
1496 ssusb3: usb@112b1000 {
1497 compatible = "mediate
1498 reg = <0 0x112b1000 0
1499 reg-names = "mac", "i
1500 ranges = <0 0 0 0x112
1501 #address-cells = <2>;
1502 #size-cells = <2>;
1503 interrupts = <GIC_SPI
1504 assigned-clocks = <&t
1505 assigned-clock-parent
1506 clocks = <&pericfg_ao
1507 <&topckgen C
1508 <&pericfg_ao
1509 clock-names = "sys_ck
1510 phys = <&u2port3 PHY_
1511 wakeup-source;
1512 mediatek,syscon-wakeu
1513 status = "disabled";
1514
1515 xhci3: usb@0 {
1516 compatible =
1517 reg = <0 0 0
1518 reg-names = "
1519 interrupts =
1520 assigned-cloc
1521 assigned-cloc
1522 clocks = <&pe
1523 clock-names =
1524 status = "dis
1525 };
1526 };
1527
1528 pcie0: pcie@112f0000 {
1529 compatible = "mediate
1530 "mediate
1531 device_type = "pci";
1532 #address-cells = <3>;
1533 #size-cells = <2>;
1534 reg = <0 0x112f0000 0
1535 reg-names = "pcie-mac
1536 interrupts = <GIC_SPI
1537 bus-range = <0x00 0xf
1538 ranges = <0x81000000
1539 0x0 0x20000
1540 <0x82000000
1541 0x0 0x20200
1542
1543 iommu-map = <0 &iommu
1544 iommu-map-mask = <0x0
1545
1546 clocks = <&infracfg_a
1547 <&infracfg_a
1548 <&infracfg_a
1549 <&infracfg_a
1550 <&infracfg_a
1551 <&pericfg_ao
1552 clock-names = "pl_250
1553 "tl_32k
1554 assigned-clocks = <&t
1555 assigned-clock-parent
1556
1557 phys = <&pciephy>;
1558 phy-names = "pcie-phy
1559
1560 power-domains = <&spm
1561
1562 resets = <&infracfg_a
1563 reset-names = "mac";
1564
1565 #interrupt-cells = <1
1566 interrupt-map-mask =
1567 interrupt-map = <0 0
1568 <0 0
1569 <0 0
1570 <0 0
1571 status = "disabled";
1572
1573 pcie_intc0: interrupt
1574 interrupt-con
1575 #address-cell
1576 #interrupt-ce
1577 };
1578 };
1579
1580 pcie1: pcie@112f8000 {
1581 compatible = "mediate
1582 "mediate
1583 device_type = "pci";
1584 #address-cells = <3>;
1585 #size-cells = <2>;
1586 reg = <0 0x112f8000 0
1587 reg-names = "pcie-mac
1588 interrupts = <GIC_SPI
1589 bus-range = <0x00 0xf
1590 ranges = <0x81000000
1591 0x0 0x24000
1592 <0x82000000
1593 0x0 0x24200
1594
1595 iommu-map = <0 &iommu
1596 iommu-map-mask = <0x0
1597
1598 clocks = <&infracfg_a
1599 <&clk26m>,
1600 <&infracfg_a
1601 <&clk26m>,
1602 <&infracfg_a
1603 /* Designer
1604 <&pericfg_ao
1605 clock-names = "pl_250
1606 "tl_32k
1607 assigned-clocks = <&t
1608 assigned-clock-parent
1609
1610 phys = <&u3port1 PHY_
1611 phy-names = "pcie-phy
1612 power-domains = <&spm
1613
1614 resets = <&infracfg_a
1615 reset-names = "mac";
1616
1617 #interrupt-cells = <1
1618 interrupt-map-mask =
1619 interrupt-map = <0 0
1620 <0 0
1621 <0 0
1622 <0 0
1623 status = "disabled";
1624
1625 pcie_intc1: interrupt
1626 interrupt-con
1627 #address-cell
1628 #interrupt-ce
1629 };
1630 };
1631
1632 nor_flash: spi@1132c000 {
1633 compatible = "mediate
1634 "mediate
1635 reg = <0 0x1132c000 0
1636 interrupts = <GIC_SPI
1637 clocks = <&topckgen C
1638 <&pericfg_ao
1639 <&pericfg_ao
1640 clock-names = "spi",
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643 status = "disabled";
1644 };
1645
1646 efuse: efuse@11c10000 {
1647 compatible = "mediate
1648 reg = <0 0x11c10000 0
1649 #address-cells = <1>;
1650 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx
1652 reg = <0x184
1653 bits = <0 5>;
1654 };
1655 u3_rx_imp_p0: usb3-rx
1656 reg = <0x184
1657 bits = <5 5>;
1658 };
1659 u3_intr_p0: usb3-intr
1660 reg = <0x185
1661 bits = <2 6>;
1662 };
1663 comb_tx_imp_p1: usb3-
1664 reg = <0x186
1665 bits = <0 5>;
1666 };
1667 comb_rx_imp_p1: usb3-
1668 reg = <0x186
1669 bits = <5 5>;
1670 };
1671 comb_intr_p1: usb3-in
1672 reg = <0x187
1673 bits = <2 6>;
1674 };
1675 u2_intr_p0: usb2-intr
1676 reg = <0x188
1677 bits = <0 5>;
1678 };
1679 u2_intr_p1: usb2-intr
1680 reg = <0x188
1681 bits = <5 5>;
1682 };
1683 u2_intr_p2: usb2-intr
1684 reg = <0x189
1685 bits = <2 5>;
1686 };
1687 u2_intr_p3: usb2-intr
1688 reg = <0x189
1689 bits = <7 5>;
1690 };
1691 pciephy_rx_ln1: pciep
1692 reg = <0x190
1693 bits = <0 4>;
1694 };
1695 pciephy_tx_ln1_nmos:
1696 reg = <0x190
1697 bits = <4 4>;
1698 };
1699 pciephy_tx_ln1_pmos:
1700 reg = <0x191
1701 bits = <0 4>;
1702 };
1703 pciephy_rx_ln0: pciep
1704 reg = <0x191
1705 bits = <4 4>;
1706 };
1707 pciephy_tx_ln0_nmos:
1708 reg = <0x192
1709 bits = <0 4>;
1710 };
1711 pciephy_tx_ln0_pmos:
1712 reg = <0x192
1713 bits = <4 4>;
1714 };
1715 pciephy_glb_intr: pci
1716 reg = <0x193
1717 bits = <0 4>;
1718 };
1719 dp_calibration: dp-da
1720 reg = <0x1ac
1721 };
1722 lvts_efuse_data1: lvt
1723 reg = <0x1bc
1724 };
1725 lvts_efuse_data2: lvt
1726 reg = <0x1d0
1727 };
1728 svs_calib_data: svs-c
1729 reg = <0x580
1730 };
1731 socinfo-data1@7a0 {
1732 reg = <0x7a0
1733 };
1734 };
1735
1736 u3phy2: t-phy@11c40000 {
1737 compatible = "mediate
1738 #address-cells = <1>;
1739 #size-cells = <1>;
1740 ranges = <0 0 0x11c40
1741 status = "disabled";
1742
1743 u2port2: usb-phy@0 {
1744 reg = <0x0 0x
1745 clocks = <&to
1746 clock-names =
1747 #phy-cells =
1748 };
1749 };
1750
1751 u3phy3: t-phy@11c50000 {
1752 compatible = "mediate
1753 #address-cells = <1>;
1754 #size-cells = <1>;
1755 ranges = <0 0 0x11c50
1756 status = "disabled";
1757
1758 u2port3: usb-phy@0 {
1759 reg = <0x0 0x
1760 clocks = <&to
1761 clock-names =
1762 #phy-cells =
1763 };
1764 };
1765
1766 mipi_tx0: dsi-phy@11c80000 {
1767 compatible = "mediate
1768 reg = <0 0x11c80000 0
1769 clocks = <&clk26m>;
1770 clock-output-names =
1771 #clock-cells = <0>;
1772 #phy-cells = <0>;
1773 status = "disabled";
1774 };
1775
1776 mipi_tx1: dsi-phy@11c90000 {
1777 compatible = "mediate
1778 reg = <0 0x11c90000 0
1779 clocks = <&clk26m>;
1780 clock-output-names =
1781 #clock-cells = <0>;
1782 #phy-cells = <0>;
1783 status = "disabled";
1784 };
1785
1786 i2c5: i2c@11d00000 {
1787 compatible = "mediate
1788 "mediate
1789 reg = <0 0x11d00000 0
1790 <0 0x10220580 0
1791 interrupts = <GIC_SPI
1792 clock-div = <1>;
1793 clocks = <&imp_iic_wr
1794 <&infracfg_a
1795 clock-names = "main",
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 status = "disabled";
1799 };
1800
1801 i2c6: i2c@11d01000 {
1802 compatible = "mediate
1803 "mediate
1804 reg = <0 0x11d01000 0
1805 <0 0x10220600 0
1806 interrupts = <GIC_SPI
1807 clock-div = <1>;
1808 clocks = <&imp_iic_wr
1809 <&infracfg_a
1810 clock-names = "main",
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1813 status = "disabled";
1814 };
1815
1816 i2c7: i2c@11d02000 {
1817 compatible = "mediate
1818 "mediate
1819 reg = <0 0x11d02000 0
1820 <0 0x10220680 0
1821 interrupts = <GIC_SPI
1822 clock-div = <1>;
1823 clocks = <&imp_iic_wr
1824 <&infracfg_a
1825 clock-names = "main",
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 status = "disabled";
1829 };
1830
1831 imp_iic_wrap_s: clock-control
1832 compatible = "mediate
1833 reg = <0 0x11d03000 0
1834 #clock-cells = <1>;
1835 };
1836
1837 i2c0: i2c@11e00000 {
1838 compatible = "mediate
1839 "mediate
1840 reg = <0 0x11e00000 0
1841 <0 0x10220080 0
1842 interrupts = <GIC_SPI
1843 clock-div = <1>;
1844 clocks = <&imp_iic_wr
1845 <&infracfg_a
1846 clock-names = "main",
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1849 status = "disabled";
1850 };
1851
1852 i2c1: i2c@11e01000 {
1853 compatible = "mediate
1854 "mediate
1855 reg = <0 0x11e01000 0
1856 <0 0x10220200 0
1857 interrupts = <GIC_SPI
1858 clock-div = <1>;
1859 clocks = <&imp_iic_wr
1860 <&infracfg_a
1861 clock-names = "main",
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1864 status = "disabled";
1865 };
1866
1867 i2c2: i2c@11e02000 {
1868 compatible = "mediate
1869 "mediate
1870 reg = <0 0x11e02000 0
1871 <0 0x10220380 0
1872 interrupts = <GIC_SPI
1873 clock-div = <1>;
1874 clocks = <&imp_iic_wr
1875 <&infracfg_a
1876 clock-names = "main",
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1879 status = "disabled";
1880 };
1881
1882 i2c3: i2c@11e03000 {
1883 compatible = "mediate
1884 "mediate
1885 reg = <0 0x11e03000 0
1886 <0 0x10220480 0
1887 interrupts = <GIC_SPI
1888 clock-div = <1>;
1889 clocks = <&imp_iic_wr
1890 <&infracfg_a
1891 clock-names = "main",
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1894 status = "disabled";
1895 };
1896
1897 i2c4: i2c@11e04000 {
1898 compatible = "mediate
1899 "mediate
1900 reg = <0 0x11e04000 0
1901 <0 0x10220500 0
1902 interrupts = <GIC_SPI
1903 clock-div = <1>;
1904 clocks = <&imp_iic_wr
1905 <&infracfg_a
1906 clock-names = "main",
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1909 status = "disabled";
1910 };
1911
1912 imp_iic_wrap_w: clock-control
1913 compatible = "mediate
1914 reg = <0 0x11e05000 0
1915 #clock-cells = <1>;
1916 };
1917
1918 u3phy1: t-phy@11e30000 {
1919 compatible = "mediate
1920 #address-cells = <1>;
1921 #size-cells = <1>;
1922 ranges = <0 0 0x11e30
1923 power-domains = <&spm
1924 status = "disabled";
1925
1926 u2port1: usb-phy@0 {
1927 reg = <0x0 0x
1928 clocks = <&to
1929 <&cl
1930 clock-names =
1931 #phy-cells =
1932 };
1933
1934 u3port1: usb-phy@700
1935 reg = <0x700
1936 clocks = <&ap
1937 <&to
1938 clock-names =
1939 nvmem-cells =
1940
1941
1942 nvmem-cell-na
1943 #phy-cells =
1944 };
1945 };
1946
1947 u3phy0: t-phy@11e40000 {
1948 compatible = "mediate
1949 #address-cells = <1>;
1950 #size-cells = <1>;
1951 ranges = <0 0 0x11e40
1952 status = "disabled";
1953
1954 u2port0: usb-phy@0 {
1955 reg = <0x0 0x
1956 clocks = <&to
1957 <&cl
1958 clock-names =
1959 #phy-cells =
1960 };
1961
1962 u3port0: usb-phy@700
1963 reg = <0x700
1964 clocks = <&ap
1965 <&to
1966 clock-names =
1967 nvmem-cells =
1968
1969
1970 nvmem-cell-na
1971 #phy-cells =
1972 };
1973 };
1974
1975 pciephy: phy@11e80000 {
1976 compatible = "mediate
1977 reg = <0 0x11e80000 0
1978 reg-names = "sif";
1979 nvmem-cells = <&pciep
1980 <&pciep
1981 <&pciep
1982 <&pciep
1983 nvmem-cell-names = "g
1984 "t
1985 "t
1986 "r
1987 power-domains = <&spm
1988 #phy-cells = <0>;
1989 status = "disabled";
1990 };
1991
1992 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediate
1994 reg = <0 0x11fa0000 0
1995 clocks = <&clk26m>, <
1996 clock-names = "unipro
1997 #phy-cells = <0>;
1998 status = "disabled";
1999 };
2000
2001 gpu: gpu@13000000 {
2002 compatible = "mediate
2003 "arm,mal
2004 reg = <0 0x13000000 0
2005
2006 clocks = <&mfgcfg CLK
2007 interrupts = <GIC_SPI
2008 <GIC_SPI
2009 <GIC_SPI
2010 interrupt-names = "jo
2011 operating-points-v2 =
2012 power-domains = <&spm
2013 <&spm
2014 <&spm
2015 <&spm
2016 <&spm
2017 power-domain-names =
2018 status = "disabled";
2019 };
2020
2021 mfgcfg: clock-controller@13fb
2022 compatible = "mediate
2023 reg = <0 0x13fbf000 0
2024 #clock-cells = <1>;
2025 };
2026
2027 vppsys0: syscon@14000000 {
2028 compatible = "mediate
2029 reg = <0 0x14000000 0
2030 #clock-cells = <1>;
2031 mediatek,gce-client-r
2032 };
2033
2034 dma-controller@14001000 {
2035 compatible = "mediate
2036 reg = <0 0x14001000 0
2037 mediatek,gce-client-r
2038 mediatek,gce-events =
2039
2040 mediatek,scp = <&scp>
2041 power-domains = <&spm
2042 iommus = <&iommu_vpp
2043 clocks = <&vppsys0 CL
2044 mboxes = <&gce1 12 CM
2045 <&gce1 13 CM
2046 <&gce1 14 CM
2047 <&gce1 21 CM
2048 <&gce1 22 CM
2049 #dma-cells = <1>;
2050 };
2051
2052 display@14002000 {
2053 compatible = "mediate
2054 reg = <0 0x14002000 0
2055 mediatek,gce-client-r
2056 clocks = <&vppsys0 CL
2057 };
2058
2059 display@14003000 {
2060 compatible = "mediate
2061 reg = <0 0x14003000 0
2062 mediatek,gce-client-r
2063 clocks = <&vppsys0 CL
2064 };
2065
2066 display@14004000 {
2067 compatible = "mediate
2068 reg = <0 0x14004000 0
2069 mediatek,gce-client-r
2070 clocks = <&vppsys0 CL
2071 };
2072
2073 display@14005000 {
2074 compatible = "mediate
2075 reg = <0 0x14005000 0
2076 interrupts = <GIC_SPI
2077 mediatek,gce-client-r
2078 clocks = <&vppsys0 CL
2079 power-domains = <&spm
2080 };
2081
2082 display@14006000 {
2083 compatible = "mediate
2084 reg = <0 0x14006000 0
2085 mediatek,gce-client-r
2086 mediatek,gce-events =
2087
2088 clocks = <&vppsys0 CL
2089 };
2090
2091 display@14007000 {
2092 compatible = "mediate
2093 reg = <0 0x14007000 0
2094 mediatek,gce-client-r
2095 clocks = <&vppsys0 CL
2096 };
2097
2098 display@14008000 {
2099 compatible = "mediate
2100 reg = <0 0x14008000 0
2101 interrupts = <GIC_SPI
2102 mediatek,gce-client-r
2103 clocks = <&vppsys0 CL
2104 power-domains = <&spm
2105 };
2106
2107 display@14009000 {
2108 compatible = "mediate
2109 reg = <0 0x14009000 0
2110 interrupts = <GIC_SPI
2111 mediatek,gce-client-r
2112 clocks = <&vppsys0 CL
2113 power-domains = <&spm
2114 iommus = <&iommu_vpp
2115 };
2116
2117 display@1400a000 {
2118 compatible = "mediate
2119 reg = <0 0x1400a000 0
2120 mediatek,gce-client-r
2121 clocks = <&vppsys0 CL
2122 power-domains = <&spm
2123 };
2124
2125 display@1400b000 {
2126 compatible = "mediate
2127 reg = <0 0x1400b000 0
2128 mediatek,gce-client-r
2129 clocks = <&vppsys0 CL
2130 };
2131
2132 dma-controller@1400c000 {
2133 compatible = "mediate
2134 reg = <0 0x1400c000 0
2135 mediatek,gce-client-r
2136 mediatek,gce-events =
2137
2138 clocks = <&vppsys0 CL
2139 iommus = <&iommu_vpp
2140 power-domains = <&spm
2141 #dma-cells = <1>;
2142 };
2143
2144 mutex@1400f000 {
2145 compatible = "mediate
2146 reg = <0 0x1400f000 0
2147 interrupts = <GIC_SPI
2148 mediatek,gce-client-r
2149 clocks = <&vppsys0 CL
2150 power-domains = <&spm
2151 };
2152
2153 smi_sub_common_vpp0_vpp1_2x1:
2154 compatible = "mediate
2155 reg = <0 0x14010000 0
2156 clocks = <&vppsys0 CL
2157 <&vppsys0 CLK_
2158 <&vppsys0 CLK_
2159 clock-names = "apb",
2160 mediatek,smi = <&smi_
2161 power-domains = <&spm
2162 };
2163
2164 smi_sub_common_vdec_vpp0_2x1:
2165 compatible = "mediate
2166 reg = <0 0x14011000 0
2167 clocks = <&vppsys0 CL
2168 <&vppsys0 CL
2169 <&vppsys0 CL
2170 clock-names = "apb",
2171 mediatek,smi = <&smi_
2172 power-domains = <&spm
2173 };
2174
2175 smi_common_vpp: smi@14012000
2176 compatible = "mediate
2177 reg = <0 0x14012000 0
2178 clocks = <&vppsys0 CL
2179 <&vppsys0 CLK_
2180 <&vppsys0 CLK_
2181 <&vppsys0 CLK_
2182 clock-names = "apb",
2183 power-domains = <&spm
2184 };
2185
2186 larb4: larb@14013000 {
2187 compatible = "mediate
2188 reg = <0 0x14013000 0
2189 mediatek,larb-id = <4
2190 mediatek,smi = <&smi_
2191 clocks = <&vppsys0 CL
2192 <&vppsys0 CLK_
2193 clock-names = "apb",
2194 power-domains = <&spm
2195 };
2196
2197 iommu_vpp: iommu@14018000 {
2198 compatible = "mediate
2199 reg = <0 0x14018000 0
2200 mediatek,larbs = <&la
2201 &la
2202 &la
2203 &la
2204 interrupts = <GIC_SPI
2205 clocks = <&vppsys0 CL
2206 clock-names = "bclk";
2207 #iommu-cells = <1>;
2208 power-domains = <&spm
2209 };
2210
2211 wpesys: clock-controller@14e0
2212 compatible = "mediate
2213 reg = <0 0x14e00000 0
2214 #clock-cells = <1>;
2215 };
2216
2217 wpesys_vpp0: clock-controller
2218 compatible = "mediate
2219 reg = <0 0x14e02000 0
2220 #clock-cells = <1>;
2221 };
2222
2223 wpesys_vpp1: clock-controller
2224 compatible = "mediate
2225 reg = <0 0x14e03000 0
2226 #clock-cells = <1>;
2227 };
2228
2229 larb7: larb@14e04000 {
2230 compatible = "mediate
2231 reg = <0 0x14e04000 0
2232 mediatek,larb-id = <7
2233 mediatek,smi = <&smi_
2234 clocks = <&wpesys CLK
2235 <&wpesys CLK
2236 clock-names = "apb",
2237 power-domains = <&spm
2238 };
2239
2240 larb8: larb@14e05000 {
2241 compatible = "mediate
2242 reg = <0 0x14e05000 0
2243 mediatek,larb-id = <8
2244 mediatek,smi = <&smi_
2245 clocks = <&wpesys CLK
2246 <&wpesys CLK_W
2247 <&vppsys0 CLK_
2248 clock-names = "apb",
2249 power-domains = <&spm
2250 };
2251
2252 vppsys1: syscon@14f00000 {
2253 compatible = "mediate
2254 reg = <0 0x14f00000 0
2255 #clock-cells = <1>;
2256 mediatek,gce-client-r
2257 };
2258
2259 mutex@14f01000 {
2260 compatible = "mediate
2261 reg = <0 0x14f01000 0
2262 interrupts = <GIC_SPI
2263 mediatek,gce-client-r
2264 clocks = <&vppsys1 CL
2265 power-domains = <&spm
2266 };
2267
2268 larb5: larb@14f02000 {
2269 compatible = "mediate
2270 reg = <0 0x14f02000 0
2271 mediatek,larb-id = <5
2272 mediatek,smi = <&smi_
2273 clocks = <&vppsys1 CL
2274 <&vppsys1 CLK_
2275 <&vppsys0 CLK_
2276 clock-names = "apb",
2277 power-domains = <&spm
2278 };
2279
2280 larb6: larb@14f03000 {
2281 compatible = "mediate
2282 reg = <0 0x14f03000 0
2283 mediatek,larb-id = <6
2284 mediatek,smi = <&smi_
2285 clocks = <&vppsys1 CL
2286 <&vppsys1 CLK_
2287 <&vppsys0 CLK_
2288 clock-names = "apb",
2289 power-domains = <&spm
2290 };
2291
2292 display@14f06000 {
2293 compatible = "mediate
2294 reg = <0 0x14f06000 0
2295 mediatek,gce-client-r
2296 clocks = <&vppsys1 CL
2297 <&vppsys1 CL
2298 <&vppsys1 CL
2299 power-domains = <&spm
2300 };
2301
2302 display@14f07000 {
2303 compatible = "mediate
2304 reg = <0 0x14f07000 0
2305 mediatek,gce-client-r
2306 clocks = <&vppsys1 CL
2307 };
2308
2309 dma-controller@14f08000 {
2310 compatible = "mediate
2311 reg = <0 0x14f08000 0
2312 mediatek,gce-client-r
2313 mediatek,gce-events =
2314
2315 clocks = <&vppsys1 CL
2316 iommus = <&iommu_vdo
2317 power-domains = <&spm
2318 #dma-cells = <1>;
2319 };
2320
2321 dma-controller@14f09000 {
2322 compatible = "mediate
2323 reg = <0 0x14f09000 0
2324 mediatek,gce-client-r
2325 mediatek,gce-events =
2326
2327 clocks = <&vppsys1 CL
2328 iommus = <&iommu_vdo
2329 power-domains = <&spm
2330 #dma-cells = <1>;
2331 };
2332
2333 dma-controller@14f0a000 {
2334 compatible = "mediate
2335 reg = <0 0x14f0a000 0
2336 mediatek,gce-client-r
2337 mediatek,gce-events =
2338
2339 clocks = <&vppsys1 CL
2340 iommus = <&iommu_vpp
2341 power-domains = <&spm
2342 #dma-cells = <1>;
2343 };
2344
2345 display@14f0b000 {
2346 compatible = "mediate
2347 reg = <0 0x14f0b000 0
2348 mediatek,gce-client-r
2349 clocks = <&vppsys1 CL
2350 };
2351
2352 display@14f0c000 {
2353 compatible = "mediate
2354 reg = <0 0x14f0c000 0
2355 mediatek,gce-client-r
2356 clocks = <&vppsys1 CL
2357 };
2358
2359 display@14f0d000 {
2360 compatible = "mediate
2361 reg = <0 0x14f0d000 0
2362 mediatek,gce-client-r
2363 clocks = <&vppsys1 CL
2364 };
2365
2366 display@14f0e000 {
2367 compatible = "mediate
2368 reg = <0 0x14f0e000 0
2369 mediatek,gce-client-r
2370 clocks = <&vppsys1 CL
2371 };
2372
2373 display@14f0f000 {
2374 compatible = "mediate
2375 reg = <0 0x14f0f000 0
2376 mediatek,gce-client-r
2377 clocks = <&vppsys1 CL
2378 };
2379
2380 display@14f10000 {
2381 compatible = "mediate
2382 reg = <0 0x14f10000 0
2383 mediatek,gce-client-r
2384 clocks = <&vppsys1 CL
2385 };
2386
2387 display@14f11000 {
2388 compatible = "mediate
2389 reg = <0 0x14f11000 0
2390 interrupts = <GIC_SPI
2391 mediatek,gce-client-r
2392 clocks = <&vppsys1 CL
2393 power-domains = <&spm
2394 };
2395
2396 display@14f12000 {
2397 compatible = "mediate
2398 reg = <0 0x14f12000 0
2399 interrupts = <GIC_SPI
2400 mediatek,gce-client-r
2401 clocks = <&vppsys1 CL
2402 power-domains = <&spm
2403 };
2404
2405 display@14f13000 {
2406 compatible = "mediate
2407 reg = <0 0x14f13000 0
2408 interrupts = <GIC_SPI
2409 mediatek,gce-client-r
2410 clocks = <&vppsys1 CL
2411 power-domains = <&spm
2412 };
2413
2414 display@14f14000 {
2415 compatible = "mediate
2416 reg = <0 0x14f14000 0
2417 mediatek,gce-client-r
2418 mediatek,gce-events =
2419
2420 clocks = <&vppsys1 CL
2421 };
2422
2423 display@14f15000 {
2424 compatible = "mediate
2425 reg = <0 0x14f15000 0
2426 mediatek,gce-client-r
2427 mediatek,gce-events =
2428
2429 clocks = <&vppsys1 CL
2430 };
2431
2432 display@14f16000 {
2433 compatible = "mediate
2434 reg = <0 0x14f16000 0
2435 mediatek,gce-client-r
2436 mediatek,gce-events =
2437
2438 clocks = <&vppsys1 CL
2439 };
2440
2441 display@14f17000 {
2442 compatible = "mediate
2443 reg = <0 0x14f17000 0
2444 mediatek,gce-client-r
2445 clocks = <&vppsys1 CL
2446 };
2447
2448 display@14f18000 {
2449 compatible = "mediate
2450 reg = <0 0x14f18000 0
2451 mediatek,gce-client-r
2452 clocks = <&vppsys1 CL
2453 };
2454
2455 display@14f19000 {
2456 compatible = "mediate
2457 reg = <0 0x14f19000 0
2458 mediatek,gce-client-r
2459 clocks = <&vppsys1 CL
2460 };
2461
2462 display@14f1a000 {
2463 compatible = "mediate
2464 reg = <0 0x14f1a000 0
2465 mediatek,gce-client-r
2466 clocks = <&vppsys1 CL
2467 power-domains = <&spm
2468 };
2469
2470 display@14f1b000 {
2471 compatible = "mediate
2472 reg = <0 0x14f1b000 0
2473 mediatek,gce-client-r
2474 clocks = <&vppsys1 CL
2475 power-domains = <&spm
2476 };
2477
2478 display@14f1c000 {
2479 compatible = "mediate
2480 reg = <0 0x14f1c000 0
2481 interrupts = <GIC_SPI
2482 mediatek,gce-client-r
2483 clocks = <&vppsys1 CL
2484 power-domains = <&spm
2485 };
2486
2487 display@14f1d000 {
2488 compatible = "mediate
2489 reg = <0 0x14f1d000 0
2490 mediatek,gce-client-r
2491 interrupts = <GIC_SPI
2492 clocks = <&vppsys1 CL
2493 power-domains = <&spm
2494 };
2495
2496 display@14f1e000 {
2497 compatible = "mediate
2498 reg = <0 0x14f1e000 0
2499 interrupts = <GIC_SPI
2500 mediatek,gce-client-r
2501 clocks = <&vppsys1 CL
2502 power-domains = <&spm
2503 };
2504
2505 display@14f1f000 {
2506 compatible = "mediate
2507 reg = <0 0x14f1f000 0
2508 interrupts = <GIC_SPI
2509 mediatek,gce-client-r
2510 clocks = <&vppsys1 CL
2511 power-domains = <&spm
2512 iommus = <&iommu_vdo
2513 };
2514
2515 display@14f20000 {
2516 compatible = "mediate
2517 reg = <0 0x14f20000 0
2518 mediatek,gce-client-r
2519 clocks = <&vppsys1 CL
2520 power-domains = <&spm
2521 };
2522
2523 display@14f21000 {
2524 compatible = "mediate
2525 reg = <0 0x14f21000 0
2526 mediatek,gce-client-r
2527 clocks = <&vppsys1 CL
2528 power-domains = <&spm
2529 };
2530
2531 display@14f22000 {
2532 compatible = "mediate
2533 reg = <0 0x14f22000 0
2534 mediatek,gce-client-r
2535 clocks = <&vppsys1 CL
2536 power-domains = <&spm
2537 };
2538
2539 dma-controller@14f23000 {
2540 compatible = "mediate
2541 reg = <0 0x14f23000 0
2542 mediatek,gce-client-r
2543 mediatek,gce-events =
2544
2545 clocks = <&vppsys1 CL
2546 iommus = <&iommu_vdo
2547 power-domains = <&spm
2548 #dma-cells = <1>;
2549 };
2550
2551 dma-controller@14f24000 {
2552 compatible = "mediate
2553 reg = <0 0x14f24000 0
2554 mediatek,gce-client-r
2555 mediatek,gce-events =
2556 <CMDQ
2557 clocks = <&vppsys1 CL
2558 iommus = <&iommu_vdo
2559 power-domains = <&spm
2560 #dma-cells = <1>;
2561 };
2562
2563 dma-controller@14f25000 {
2564 compatible = "mediate
2565 reg = <0 0x14f25000 0
2566 mediatek,gce-client-r
2567 mediatek,gce-events =
2568 <CMDQ
2569 clocks = <&vppsys1 CL
2570 iommus = <&iommu_vpp
2571 power-domains = <&spm
2572 #dma-cells = <1>;
2573 };
2574
2575 imgsys: clock-controller@1500
2576 compatible = "mediate
2577 reg = <0 0x15000000 0
2578 #clock-cells = <1>;
2579 };
2580
2581 larb9: larb@15001000 {
2582 compatible = "mediate
2583 reg = <0 0x15001000 0
2584 mediatek,larb-id = <9
2585 mediatek,smi = <&smi_
2586 clocks = <&imgsys CLK
2587 <&imgsys CLK
2588 <&imgsys CLK
2589 clock-names = "apb",
2590 power-domains = <&spm
2591 };
2592
2593 smi_sub_common_img0_3x1: smi@
2594 compatible = "mediate
2595 reg = <0 0x15002000 0
2596 clocks = <&imgsys CLK
2597 <&imgsys CLK
2598 <&vppsys0 CL
2599 clock-names = "apb",
2600 mediatek,smi = <&smi_
2601 power-domains = <&spm
2602 };
2603
2604 smi_sub_common_img1_3x1: smi@
2605 compatible = "mediate
2606 reg = <0 0x15003000 0
2607 clocks = <&imgsys CLK
2608 <&imgsys CLK
2609 <&imgsys CLK
2610 clock-names = "apb",
2611 mediatek,smi = <&smi_
2612 power-domains = <&spm
2613 };
2614
2615 imgsys1_dip_top: clock-contro
2616 compatible = "mediate
2617 reg = <0 0x15110000 0
2618 #clock-cells = <1>;
2619 };
2620
2621 larb10: larb@15120000 {
2622 compatible = "mediate
2623 reg = <0 0x15120000 0
2624 mediatek,larb-id = <1
2625 mediatek,smi = <&smi_
2626 clocks = <&imgsys CLK
2627 <&imgsys1_dip_
2628 clock-names = "apb",
2629 power-domains = <&spm
2630 };
2631
2632 imgsys1_dip_nr: clock-control
2633 compatible = "mediate
2634 reg = <0 0x15130000 0
2635 #clock-cells = <1>;
2636 };
2637
2638 imgsys1_wpe: clock-controller
2639 compatible = "mediate
2640 reg = <0 0x15220000 0
2641 #clock-cells = <1>;
2642 };
2643
2644 larb11: larb@15230000 {
2645 compatible = "mediate
2646 reg = <0 0x15230000 0
2647 mediatek,larb-id = <1
2648 mediatek,smi = <&smi_
2649 clocks = <&imgsys CLK
2650 <&imgsys1_wpe
2651 clock-names = "apb",
2652 power-domains = <&spm
2653 };
2654
2655 ipesys: clock-controller@1533
2656 compatible = "mediate
2657 reg = <0 0x15330000 0
2658 #clock-cells = <1>;
2659 };
2660
2661 larb12: larb@15340000 {
2662 compatible = "mediate
2663 reg = <0 0x15340000 0
2664 mediatek,larb-id = <1
2665 mediatek,smi = <&smi_
2666 clocks = <&ipesys CLK
2667 <&ipesys CLK
2668 clock-names = "apb",
2669 power-domains = <&spm
2670 };
2671
2672 camsys: clock-controller@1600
2673 compatible = "mediate
2674 reg = <0 0x16000000 0
2675 #clock-cells = <1>;
2676 };
2677
2678 larb13: larb@16001000 {
2679 compatible = "mediate
2680 reg = <0 0x16001000 0
2681 mediatek,larb-id = <1
2682 mediatek,smi = <&smi_
2683 clocks = <&camsys CLK
2684 <&camsys CLK_C
2685 <&camsys CLK_C
2686 clock-names = "apb",
2687 power-domains = <&spm
2688 };
2689
2690 larb14: larb@16002000 {
2691 compatible = "mediate
2692 reg = <0 0x16002000 0
2693 mediatek,larb-id = <1
2694 mediatek,smi = <&smi_
2695 clocks = <&camsys CLK
2696 <&camsys CLK
2697 clock-names = "apb",
2698 power-domains = <&spm
2699 };
2700
2701 smi_sub_common_cam_4x1: smi@1
2702 compatible = "mediate
2703 reg = <0 0x16004000 0
2704 clocks = <&camsys CLK
2705 <&camsys CLK
2706 <&camsys CLK
2707 clock-names = "apb",
2708 mediatek,smi = <&smi_
2709 power-domains = <&spm
2710 };
2711
2712 smi_sub_common_cam_7x1: smi@1
2713 compatible = "mediate
2714 reg = <0 0x16005000 0
2715 clocks = <&camsys CLK
2716 <&camsys CLK
2717 <&vppsys0 CL
2718 clock-names = "apb",
2719 mediatek,smi = <&smi_
2720 power-domains = <&spm
2721 };
2722
2723 larb16: larb@16012000 {
2724 compatible = "mediate
2725 reg = <0 0x16012000 0
2726 mediatek,larb-id = <1
2727 mediatek,smi = <&smi_
2728 clocks = <&camsys_raw
2729 <&camsys_raw
2730 clock-names = "apb",
2731 power-domains = <&spm
2732 };
2733
2734 larb17: larb@16013000 {
2735 compatible = "mediate
2736 reg = <0 0x16013000 0
2737 mediatek,larb-id = <1
2738 mediatek,smi = <&smi_
2739 clocks = <&camsys_yuv
2740 <&camsys_yuv
2741 clock-names = "apb",
2742 power-domains = <&spm
2743 };
2744
2745 larb27: larb@16014000 {
2746 compatible = "mediate
2747 reg = <0 0x16014000 0
2748 mediatek,larb-id = <2
2749 mediatek,smi = <&smi_
2750 clocks = <&camsys_raw
2751 <&camsys_raw
2752 clock-names = "apb",
2753 power-domains = <&spm
2754 };
2755
2756 larb28: larb@16015000 {
2757 compatible = "mediate
2758 reg = <0 0x16015000 0
2759 mediatek,larb-id = <2
2760 mediatek,smi = <&smi_
2761 clocks = <&camsys_yuv
2762 <&camsys_yuv
2763 clock-names = "apb",
2764 power-domains = <&spm
2765 };
2766
2767 camsys_rawa: clock-controller
2768 compatible = "mediate
2769 reg = <0 0x1604f000 0
2770 #clock-cells = <1>;
2771 };
2772
2773 camsys_yuva: clock-controller
2774 compatible = "mediate
2775 reg = <0 0x1606f000 0
2776 #clock-cells = <1>;
2777 };
2778
2779 camsys_rawb: clock-controller
2780 compatible = "mediate
2781 reg = <0 0x1608f000 0
2782 #clock-cells = <1>;
2783 };
2784
2785 camsys_yuvb: clock-controller
2786 compatible = "mediate
2787 reg = <0 0x160af000 0
2788 #clock-cells = <1>;
2789 };
2790
2791 camsys_mraw: clock-controller
2792 compatible = "mediate
2793 reg = <0 0x16140000 0
2794 #clock-cells = <1>;
2795 };
2796
2797 larb25: larb@16141000 {
2798 compatible = "mediate
2799 reg = <0 0x16141000 0
2800 mediatek,larb-id = <2
2801 mediatek,smi = <&smi_
2802 clocks = <&camsys CLK
2803 <&camsys_mra
2804 <&camsys CLK
2805 clock-names = "apb",
2806 power-domains = <&spm
2807 };
2808
2809 larb26: larb@16142000 {
2810 compatible = "mediate
2811 reg = <0 0x16142000 0
2812 mediatek,larb-id = <2
2813 mediatek,smi = <&smi_
2814 clocks = <&camsys_mra
2815 <&camsys_mra
2816 clock-names = "apb",
2817 power-domains = <&spm
2818
2819 };
2820
2821 ccusys: clock-controller@1720
2822 compatible = "mediate
2823 reg = <0 0x17200000 0
2824 #clock-cells = <1>;
2825 };
2826
2827 larb18: larb@17201000 {
2828 compatible = "mediate
2829 reg = <0 0x17201000 0
2830 mediatek,larb-id = <1
2831 mediatek,smi = <&smi_
2832 clocks = <&ccusys CLK
2833 <&ccusys CLK
2834 clock-names = "apb",
2835 power-domains = <&spm
2836 };
2837
2838 video-codec@18000000 {
2839 compatible = "mediate
2840 mediatek,scp = <&scp>
2841 iommus = <&iommu_vdo
2842 #address-cells = <2>;
2843 #size-cells = <2>;
2844 reg = <0 0x18000000 0
2845 <0 0x18004000 0
2846 ranges = <0 0 0 0x180
2847
2848 video-codec@2000 {
2849 compatible =
2850 reg = <0 0x20
2851 iommus = <&io
2852 <&io
2853 clocks = <&to
2854 <&vd
2855 <&vd
2856 <&to
2857 clock-names =
2858 assigned-cloc
2859 assigned-cloc
2860 power-domains
2861 };
2862
2863 video-codec@10000 {
2864 compatible =
2865 reg = <0 0x10
2866 interrupts =
2867 iommus = <&io
2868 <&io
2869 <&io
2870 <&io
2871 <&io
2872 <&io
2873 clocks = <&to
2874 <&vd
2875 <&vd
2876 <&to
2877 clock-names =
2878 assigned-cloc
2879 assigned-cloc
2880 power-domains
2881 };
2882
2883 video-codec@25000 {
2884 compatible =
2885 reg = <0 0x25
2886 interrupts =
2887 iommus = <&io
2888 <&io
2889 <&io
2890 <&io
2891 <&io
2892 <&io
2893 <&io
2894 <&io
2895 <&io
2896 <&io
2897 clocks = <&to
2898 <&vd
2899 <&vd
2900 <&to
2901 clock-names =
2902 assigned-cloc
2903 assigned-cloc
2904 power-domains
2905 };
2906 };
2907
2908 larb24: larb@1800d000 {
2909 compatible = "mediate
2910 reg = <0 0x1800d000 0
2911 mediatek,larb-id = <2
2912 mediatek,smi = <&smi_
2913 clocks = <&vdecsys_so
2914 <&vdecsys_so
2915 clock-names = "apb",
2916 power-domains = <&spm
2917 };
2918
2919 larb23: larb@1800e000 {
2920 compatible = "mediate
2921 reg = <0 0x1800e000 0
2922 mediatek,larb-id = <2
2923 mediatek,smi = <&smi_
2924 clocks = <&vppsys0 CL
2925 <&vdecsys_so
2926 clock-names = "apb",
2927 power-domains = <&spm
2928 };
2929
2930 vdecsys_soc: clock-controller
2931 compatible = "mediate
2932 reg = <0 0x1800f000 0
2933 #clock-cells = <1>;
2934 };
2935
2936 larb21: larb@1802e000 {
2937 compatible = "mediate
2938 reg = <0 0x1802e000 0
2939 mediatek,larb-id = <2
2940 mediatek,smi = <&smi_
2941 clocks = <&vdecsys CL
2942 <&vdecsys CL
2943 clock-names = "apb",
2944 power-domains = <&spm
2945 };
2946
2947 vdecsys: clock-controller@180
2948 compatible = "mediate
2949 reg = <0 0x1802f000 0
2950 #clock-cells = <1>;
2951 };
2952
2953 larb22: larb@1803e000 {
2954 compatible = "mediate
2955 reg = <0 0x1803e000 0
2956 mediatek,larb-id = <2
2957 mediatek,smi = <&smi_
2958 clocks = <&vppsys0 CL
2959 <&vdecsys_co
2960 clock-names = "apb",
2961 power-domains = <&spm
2962 };
2963
2964 vdecsys_core1: clock-controll
2965 compatible = "mediate
2966 reg = <0 0x1803f000 0
2967 #clock-cells = <1>;
2968 };
2969
2970 apusys_pll: clock-controller@
2971 compatible = "mediate
2972 reg = <0 0x190f3000 0
2973 #clock-cells = <1>;
2974 };
2975
2976 vencsys: clock-controller@1a0
2977 compatible = "mediate
2978 reg = <0 0x1a000000 0
2979 #clock-cells = <1>;
2980 };
2981
2982 larb19: larb@1a010000 {
2983 compatible = "mediate
2984 reg = <0 0x1a010000 0
2985 mediatek,larb-id = <1
2986 mediatek,smi = <&smi_
2987 clocks = <&vencsys CL
2988 <&vencsys CL
2989 clock-names = "apb",
2990 power-domains = <&spm
2991 };
2992
2993 venc: video-codec@1a020000 {
2994 compatible = "mediate
2995 reg = <0 0x1a020000 0
2996 iommus = <&iommu_vdo
2997 <&iommu_vdo
2998 <&iommu_vdo
2999 <&iommu_vdo
3000 <&iommu_vdo
3001 <&iommu_vdo
3002 <&iommu_vdo
3003 <&iommu_vdo
3004 <&iommu_vdo
3005 interrupts = <GIC_SPI
3006 mediatek,scp = <&scp>
3007 clocks = <&vencsys CL
3008 clock-names = "venc_s
3009 assigned-clocks = <&t
3010 assigned-clock-parent
3011 power-domains = <&spm
3012 #address-cells = <2>;
3013 #size-cells = <2>;
3014 };
3015
3016 jpgdec-master {
3017 compatible = "mediate
3018 power-domains = <&spm
3019 iommus = <&iommu_vdo
3020 <&iommu_vdo
3021 <&iommu_vdo
3022 <&iommu_vdo
3023 <&iommu_vdo
3024 <&iommu_vdo
3025 #address-cells = <2>;
3026 #size-cells = <2>;
3027 ranges;
3028
3029 jpgdec@1a040000 {
3030 compatible =
3031 reg = <0 0x1a
3032 iommus = <&io
3033 <&io
3034 <&io
3035 <&io
3036 <&io
3037 <&io
3038 interrupts =
3039 clocks = <&ve
3040 clock-names =
3041 power-domains
3042 };
3043
3044 jpgdec@1a050000 {
3045 compatible =
3046 reg = <0 0x1a
3047 iommus = <&io
3048 <&io
3049 <&io
3050 <&io
3051 <&io
3052 <&io
3053 interrupts =
3054 clocks = <&ve
3055 clock-names =
3056 power-domains
3057 };
3058
3059 jpgdec@1b040000 {
3060 compatible =
3061 reg = <0 0x1b
3062 iommus = <&io
3063 <&io
3064 <&io
3065 <&io
3066 <&io
3067 <&io
3068 interrupts =
3069 clocks = <&ve
3070 clock-names =
3071 power-domains
3072 };
3073 };
3074
3075 vencsys_core1: clock-controll
3076 compatible = "mediate
3077 reg = <0 0x1b000000 0
3078 #clock-cells = <1>;
3079 };
3080
3081 vdosys0: syscon@1c01a000 {
3082 compatible = "mediate
3083 reg = <0 0x1c01a000 0
3084 mboxes = <&gce0 0 CMD
3085 #clock-cells = <1>;
3086 mediatek,gce-client-r
3087 };
3088
3089
3090 jpgenc-master {
3091 compatible = "mediate
3092 power-domains = <&spm
3093 iommus = <&iommu_vpp
3094 <&iom
3095 <&iom
3096 <&iom
3097 #address-cells = <2>;
3098 #size-cells = <2>;
3099 ranges;
3100
3101 jpgenc@1a030000 {
3102 compatible =
3103 reg = <0 0x1a
3104 iommus = <&io
3105
3106
3107
3108 interrupts =
3109 clocks = <&ve
3110 clock-names =
3111 power-domains
3112 };
3113
3114 jpgenc@1b030000 {
3115 compatible =
3116 reg = <0 0x1b
3117 iommus = <&io
3118
3119
3120
3121 interrupts =
3122 clocks = <&ve
3123 clock-names =
3124 power-domains
3125 };
3126 };
3127
3128 larb20: larb@1b010000 {
3129 compatible = "mediate
3130 reg = <0 0x1b010000 0
3131 mediatek,larb-id = <2
3132 mediatek,smi = <&smi_
3133 clocks = <&vencsys_co
3134 <&vencsys_co
3135 <&vppsys0 CL
3136 clock-names = "apb",
3137 power-domains = <&spm
3138 };
3139
3140 ovl0: ovl@1c000000 {
3141 compatible = "mediate
3142 reg = <0 0x1c000000 0
3143 interrupts = <GIC_SPI
3144 power-domains = <&spm
3145 clocks = <&vdosys0 CL
3146 iommus = <&iommu_vdo
3147 mediatek,gce-client-r
3148 };
3149
3150 rdma0: rdma@1c002000 {
3151 compatible = "mediate
3152 reg = <0 0x1c002000 0
3153 interrupts = <GIC_SPI
3154 power-domains = <&spm
3155 clocks = <&vdosys0 CL
3156 iommus = <&iommu_vdo
3157 mediatek,gce-client-r
3158 };
3159
3160 color0: color@1c003000 {
3161 compatible = "mediate
3162 reg = <0 0x1c003000 0
3163 interrupts = <GIC_SPI
3164 power-domains = <&spm
3165 clocks = <&vdosys0 CL
3166 mediatek,gce-client-r
3167 };
3168
3169 ccorr0: ccorr@1c004000 {
3170 compatible = "mediate
3171 reg = <0 0x1c004000 0
3172 interrupts = <GIC_SPI
3173 power-domains = <&spm
3174 clocks = <&vdosys0 CL
3175 mediatek,gce-client-r
3176 };
3177
3178 aal0: aal@1c005000 {
3179 compatible = "mediate
3180 reg = <0 0x1c005000 0
3181 interrupts = <GIC_SPI
3182 power-domains = <&spm
3183 clocks = <&vdosys0 CL
3184 mediatek,gce-client-r
3185 };
3186
3187 gamma0: gamma@1c006000 {
3188 compatible = "mediate
3189 reg = <0 0x1c006000 0
3190 interrupts = <GIC_SPI
3191 power-domains = <&spm
3192 clocks = <&vdosys0 CL
3193 mediatek,gce-client-r
3194 };
3195
3196 dither0: dither@1c007000 {
3197 compatible = "mediate
3198 reg = <0 0x1c007000 0
3199 interrupts = <GIC_SPI
3200 power-domains = <&spm
3201 clocks = <&vdosys0 CL
3202 mediatek,gce-client-r
3203 };
3204
3205 dsi0: dsi@1c008000 {
3206 compatible = "mediate
3207 reg = <0 0x1c008000 0
3208 interrupts = <GIC_SPI
3209 power-domains = <&spm
3210 clocks = <&vdosys0 CL
3211 <&vdosys0 CL
3212 <&mipi_tx0>;
3213 clock-names = "engine
3214 phys = <&mipi_tx0>;
3215 phy-names = "dphy";
3216 status = "disabled";
3217 };
3218
3219 dsc0: dsc@1c009000 {
3220 compatible = "mediate
3221 reg = <0 0x1c009000 0
3222 interrupts = <GIC_SPI
3223 power-domains = <&spm
3224 clocks = <&vdosys0 CL
3225 mediatek,gce-client-r
3226 };
3227
3228 dsi1: dsi@1c012000 {
3229 compatible = "mediate
3230 reg = <0 0x1c012000 0
3231 interrupts = <GIC_SPI
3232 power-domains = <&spm
3233 clocks = <&vdosys0 CL
3234 <&vdosys0 CL
3235 <&mipi_tx1>;
3236 clock-names = "engine
3237 phys = <&mipi_tx1>;
3238 phy-names = "dphy";
3239 status = "disabled";
3240 };
3241
3242 merge0: merge@1c014000 {
3243 compatible = "mediate
3244 reg = <0 0x1c014000 0
3245 interrupts = <GIC_SPI
3246 power-domains = <&spm
3247 clocks = <&vdosys0 CL
3248 mediatek,gce-client-r
3249 };
3250
3251 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediate
3253 reg = <0 0x1c015000 0
3254 interrupts = <GIC_SPI
3255 clocks = <&vdosys0 CL
3256 <&vdosys0 C
3257 <&apmixedsys
3258 clock-names = "pixel"
3259 status = "disabled";
3260 };
3261
3262 mutex: mutex@1c016000 {
3263 compatible = "mediate
3264 reg = <0 0x1c016000 0
3265 interrupts = <GIC_SPI
3266 power-domains = <&spm
3267 clocks = <&vdosys0 CL
3268 mediatek,gce-client-r
3269 mediatek,gce-events =
3270 };
3271
3272 larb0: larb@1c018000 {
3273 compatible = "mediate
3274 reg = <0 0x1c018000 0
3275 mediatek,larb-id = <0
3276 mediatek,smi = <&smi_
3277 clocks = <&vdosys0 CL
3278 <&vdosys0 CL
3279 <&vppsys0 CL
3280 clock-names = "apb",
3281 power-domains = <&spm
3282 };
3283
3284 larb1: larb@1c019000 {
3285 compatible = "mediate
3286 reg = <0 0x1c019000 0
3287 mediatek,larb-id = <1
3288 mediatek,smi = <&smi_
3289 clocks = <&vdosys0 CL
3290 <&vppsys0 CL
3291 <&vppsys0 CL
3292 clock-names = "apb",
3293 power-domains = <&spm
3294 };
3295
3296 vdosys1: syscon@1c100000 {
3297 compatible = "mediate
3298 reg = <0 0x1c100000 0
3299 mboxes = <&gce0 1 CMD
3300 mediatek,gce-client-r
3301 #clock-cells = <1>;
3302 #reset-cells = <1>;
3303 };
3304
3305 smi_common_vdo: smi@1c01b000
3306 compatible = "mediate
3307 reg = <0 0x1c01b000 0
3308 clocks = <&vdosys0 CL
3309 <&vdosys0 CL
3310 <&vdosys0 CL
3311 <&vdosys0 CL
3312 clock-names = "apb",
3313 power-domains = <&spm
3314
3315 };
3316
3317 iommu_vdo: iommu@1c01f000 {
3318 compatible = "mediate
3319 reg = <0 0x1c01f000 0
3320 mediatek,larbs = <&la
3321 &la
3322 &la
3323 &la
3324 interrupts = <GIC_SPI
3325 #iommu-cells = <1>;
3326 clocks = <&vdosys0 CL
3327 clock-names = "bclk";
3328 power-domains = <&spm
3329 };
3330
3331 mutex1: mutex@1c101000 {
3332 compatible = "mediate
3333 reg = <0 0x1c101000 0
3334 reg-names = "vdo1_mut
3335 interrupts = <GIC_SPI
3336 power-domains = <&spm
3337 clocks = <&vdosys1 CL
3338 clock-names = "vdo1_m
3339 mediatek,gce-client-r
3340 mediatek,gce-events =
3341 };
3342
3343 larb2: larb@1c102000 {
3344 compatible = "mediate
3345 reg = <0 0x1c102000 0
3346 mediatek,larb-id = <2
3347 mediatek,smi = <&smi_
3348 clocks = <&vdosys1 CL
3349 <&vdosys1 CL
3350 <&vdosys1 CL
3351 clock-names = "apb",
3352 power-domains = <&spm
3353 };
3354
3355 larb3: larb@1c103000 {
3356 compatible = "mediate
3357 reg = <0 0x1c103000 0
3358 mediatek,larb-id = <3
3359 mediatek,smi = <&smi_
3360 clocks = <&vdosys1 CL
3361 <&vdosys1 CL
3362 <&vppsys0 CL
3363 clock-names = "apb",
3364 power-domains = <&spm
3365 };
3366
3367 vdo1_rdma0: dma-controller@1c
3368 compatible = "mediate
3369 reg = <0 0x1c104000 0
3370 interrupts = <GIC_SPI
3371 clocks = <&vdosys1 CL
3372 power-domains = <&spm
3373 iommus = <&iommu_vdo
3374 mediatek,gce-client-r
3375 #dma-cells = <1>;
3376 };
3377
3378 vdo1_rdma1: dma-controller@1c
3379 compatible = "mediate
3380 reg = <0 0x1c105000 0
3381 interrupts = <GIC_SPI
3382 clocks = <&vdosys1 CL
3383 power-domains = <&spm
3384 iommus = <&iommu_vpp
3385 mediatek,gce-client-r
3386 #dma-cells = <1>;
3387 };
3388
3389 vdo1_rdma2: dma-controller@1c
3390 compatible = "mediate
3391 reg = <0 0x1c106000 0
3392 interrupts = <GIC_SPI
3393 clocks = <&vdosys1 CL
3394 power-domains = <&spm
3395 iommus = <&iommu_vdo
3396 mediatek,gce-client-r
3397 #dma-cells = <1>;
3398 };
3399
3400 vdo1_rdma3: dma-controller@1c
3401 compatible = "mediate
3402 reg = <0 0x1c107000 0
3403 interrupts = <GIC_SPI
3404 clocks = <&vdosys1 CL
3405 power-domains = <&spm
3406 iommus = <&iommu_vpp
3407 mediatek,gce-client-r
3408 #dma-cells = <1>;
3409 };
3410
3411 vdo1_rdma4: dma-controller@1c
3412 compatible = "mediate
3413 reg = <0 0x1c108000 0
3414 interrupts = <GIC_SPI
3415 clocks = <&vdosys1 CL
3416 power-domains = <&spm
3417 iommus = <&iommu_vdo
3418 mediatek,gce-client-r
3419 #dma-cells = <1>;
3420 };
3421
3422 vdo1_rdma5: dma-controller@1c
3423 compatible = "mediate
3424 reg = <0 0x1c109000 0
3425 interrupts = <GIC_SPI
3426 clocks = <&vdosys1 CL
3427 power-domains = <&spm
3428 iommus = <&iommu_vpp
3429 mediatek,gce-client-r
3430 #dma-cells = <1>;
3431 };
3432
3433 vdo1_rdma6: dma-controller@1c
3434 compatible = "mediate
3435 reg = <0 0x1c10a000 0
3436 interrupts = <GIC_SPI
3437 clocks = <&vdosys1 CL
3438 power-domains = <&spm
3439 iommus = <&iommu_vdo
3440 mediatek,gce-client-r
3441 #dma-cells = <1>;
3442 };
3443
3444 vdo1_rdma7: dma-controller@1c
3445 compatible = "mediate
3446 reg = <0 0x1c10b000 0
3447 interrupts = <GIC_SPI
3448 clocks = <&vdosys1 CL
3449 power-domains = <&spm
3450 iommus = <&iommu_vpp
3451 mediatek,gce-client-r
3452 #dma-cells = <1>;
3453 };
3454
3455 merge1: vpp-merge@1c10c000 {
3456 compatible = "mediate
3457 reg = <0 0x1c10c000 0
3458 interrupts = <GIC_SPI
3459 clocks = <&vdosys1 CL
3460 <&vdosys1 CL
3461 clock-names = "merge"
3462 power-domains = <&spm
3463 mediatek,gce-client-r
3464 mediatek,merge-mute;
3465 resets = <&vdosys1 MT
3466 };
3467
3468 merge2: vpp-merge@1c10d000 {
3469 compatible = "mediate
3470 reg = <0 0x1c10d000 0
3471 interrupts = <GIC_SPI
3472 clocks = <&vdosys1 CL
3473 <&vdosys1 CL
3474 clock-names = "merge"
3475 power-domains = <&spm
3476 mediatek,gce-client-r
3477 mediatek,merge-mute;
3478 resets = <&vdosys1 MT
3479 };
3480
3481 merge3: vpp-merge@1c10e000 {
3482 compatible = "mediate
3483 reg = <0 0x1c10e000 0
3484 interrupts = <GIC_SPI
3485 clocks = <&vdosys1 CL
3486 <&vdosys1 CL
3487 clock-names = "merge"
3488 power-domains = <&spm
3489 mediatek,gce-client-r
3490 mediatek,merge-mute;
3491 resets = <&vdosys1 MT
3492 };
3493
3494 merge4: vpp-merge@1c10f000 {
3495 compatible = "mediate
3496 reg = <0 0x1c10f000 0
3497 interrupts = <GIC_SPI
3498 clocks = <&vdosys1 CL
3499 <&vdosys1 CL
3500 clock-names = "merge"
3501 power-domains = <&spm
3502 mediatek,gce-client-r
3503 mediatek,merge-mute;
3504 resets = <&vdosys1 MT
3505 };
3506
3507 merge5: vpp-merge@1c110000 {
3508 compatible = "mediate
3509 reg = <0 0x1c110000 0
3510 interrupts = <GIC_SPI
3511 clocks = <&vdosys1 CL
3512 <&vdosys1 CL
3513 clock-names = "merge"
3514 power-domains = <&spm
3515 mediatek,gce-client-r
3516 mediatek,merge-fifo-e
3517 resets = <&vdosys1 MT
3518 };
3519
3520 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediate
3522 reg = <0 0x1c113000 0
3523 interrupts = <GIC_SPI
3524 power-domains = <&spm
3525 clocks = <&vdosys1 CL
3526 <&vdosys1 CL
3527 <&apmixedsys
3528 clock-names = "pixel"
3529 status = "disabled";
3530 };
3531
3532 ethdr0: hdr-engine@1c114000 {
3533 compatible = "mediate
3534 reg = <0 0x1c114000 0
3535 <0 0x1c115000 0
3536 <0 0x1c117000 0
3537 <0 0x1c119000 0
3538 <0 0x1c11a000 0
3539 <0 0x1c11b000 0
3540 <0 0x1c11c000 0
3541 reg-names = "mixer",
3542 "vdo_be",
3543 mediatek,gce-client-r
3544
3545
3546
3547
3548
3549
3550 clocks = <&vdosys1 CL
3551 <&vdosys1 CL
3552 <&vdosys1 CL
3553 <&vdosys1 CL
3554 <&vdosys1 CL
3555 <&vdosys1 CL
3556 <&vdosys1 CL
3557 <&vdosys1 CL
3558 <&vdosys1 CL
3559 <&vdosys1 CL
3560 <&vdosys1 CL
3561 <&vdosys1 CL
3562 <&topckgen C
3563 clock-names = "mixer"
3564 "vdo_be
3565 "gfx_fe
3566 "ethdr_
3567 power-domains = <&spm
3568 iommus = <&iommu_vpp
3569 <&iommu_vpp
3570 interrupts = <GIC_SPI
3571 resets = <&vdosys1 MT
3572 <&vdosys1 MT
3573 <&vdosys1 MT
3574 <&vdosys1 MT
3575 <&vdosys1 MT
3576 reset-names = "vdo_fe
3577 "gfx_fe
3578 };
3579
3580 edp_tx: edp-tx@1c500000 {
3581 compatible = "mediate
3582 reg = <0 0x1c500000 0
3583 nvmem-cells = <&dp_ca
3584 nvmem-cell-names = "d
3585 power-domains = <&spm
3586 interrupts = <GIC_SPI
3587 max-linkrate-mhz = <8
3588 status = "disabled";
3589 };
3590
3591 dp_tx: dp-tx@1c600000 {
3592 compatible = "mediate
3593 reg = <0 0x1c600000 0
3594 nvmem-cells = <&dp_ca
3595 nvmem-cell-names = "d
3596 power-domains = <&spm
3597 interrupts = <GIC_SPI
3598 max-linkrate-mhz = <8
3599 status = "disabled";
3600 };
3601 };
3602
3603 thermal_zones: thermal-zones {
3604 cpu0-thermal {
3605 polling-delay = <1000
3606 polling-delay-passive
3607 thermal-sensors = <&l
3608
3609 trips {
3610 cpu0_alert: t
3611 tempe
3612 hyste
3613 type
3614 };
3615
3616 cpu0_crit: tr
3617 tempe
3618 hyste
3619 type
3620 };
3621 };
3622
3623 cooling-maps {
3624 map0 {
3625 trip
3626 cooli
3627
3628
3629
3630 };
3631 };
3632 };
3633
3634 cpu1-thermal {
3635 polling-delay = <1000
3636 polling-delay-passive
3637 thermal-sensors = <&l
3638
3639 trips {
3640 cpu1_alert: t
3641 tempe
3642 hyste
3643 type
3644 };
3645
3646 cpu1_crit: tr
3647 tempe
3648 hyste
3649 type
3650 };
3651 };
3652
3653 cooling-maps {
3654 map0 {
3655 trip
3656 cooli
3657
3658
3659
3660 };
3661 };
3662 };
3663
3664 cpu2-thermal {
3665 polling-delay = <1000
3666 polling-delay-passive
3667 thermal-sensors = <&l
3668
3669 trips {
3670 cpu2_alert: t
3671 tempe
3672 hyste
3673 type
3674 };
3675
3676 cpu2_crit: tr
3677 tempe
3678 hyste
3679 type
3680 };
3681 };
3682
3683 cooling-maps {
3684 map0 {
3685 trip
3686 cooli
3687
3688
3689
3690 };
3691 };
3692 };
3693
3694 cpu3-thermal {
3695 polling-delay = <1000
3696 polling-delay-passive
3697 thermal-sensors = <&l
3698
3699 trips {
3700 cpu3_alert: t
3701 tempe
3702 hyste
3703 type
3704 };
3705
3706 cpu3_crit: tr
3707 tempe
3708 hyste
3709 type
3710 };
3711 };
3712
3713 cooling-maps {
3714 map0 {
3715 trip
3716 cooli
3717
3718
3719
3720 };
3721 };
3722 };
3723
3724 cpu4-thermal {
3725 polling-delay = <1000
3726 polling-delay-passive
3727 thermal-sensors = <&l
3728
3729 trips {
3730 cpu4_alert: t
3731 tempe
3732 hyste
3733 type
3734 };
3735
3736 cpu4_crit: tr
3737 tempe
3738 hyste
3739 type
3740 };
3741 };
3742
3743 cooling-maps {
3744 map0 {
3745 trip
3746 cooli
3747
3748
3749
3750 };
3751 };
3752 };
3753
3754 cpu5-thermal {
3755 polling-delay = <1000
3756 polling-delay-passive
3757 thermal-sensors = <&l
3758
3759 trips {
3760 cpu5_alert: t
3761 tempe
3762 hyste
3763 type
3764 };
3765
3766 cpu5_crit: tr
3767 tempe
3768 hyste
3769 type
3770 };
3771 };
3772
3773 cooling-maps {
3774 map0 {
3775 trip
3776 cooli
3777
3778
3779
3780 };
3781 };
3782 };
3783
3784 cpu6-thermal {
3785 polling-delay = <1000
3786 polling-delay-passive
3787 thermal-sensors = <&l
3788
3789 trips {
3790 cpu6_alert: t
3791 tempe
3792 hyste
3793 type
3794 };
3795
3796 cpu6_crit: tr
3797 tempe
3798 hyste
3799 type
3800 };
3801 };
3802
3803 cooling-maps {
3804 map0 {
3805 trip
3806 cooli
3807
3808
3809
3810 };
3811 };
3812 };
3813
3814 cpu7-thermal {
3815 polling-delay = <1000
3816 polling-delay-passive
3817 thermal-sensors = <&l
3818
3819 trips {
3820 cpu7_alert: t
3821 tempe
3822 hyste
3823 type
3824 };
3825
3826 cpu7_crit: tr
3827 tempe
3828 hyste
3829 type
3830 };
3831 };
3832
3833 cooling-maps {
3834 map0 {
3835 trip
3836 cooli
3837
3838
3839
3840 };
3841 };
3842 };
3843
3844 vpu0-thermal {
3845 polling-delay = <1000
3846 polling-delay-passive
3847 thermal-sensors = <&l
3848
3849 trips {
3850 vpu0_alert: t
3851 tempe
3852 hyste
3853 type
3854 };
3855
3856 vpu0_crit: tr
3857 tempe
3858 hyste
3859 type
3860 };
3861 };
3862 };
3863
3864 vpu1-thermal {
3865 polling-delay = <1000
3866 polling-delay-passive
3867 thermal-sensors = <&l
3868
3869 trips {
3870 vpu1_alert: t
3871 tempe
3872 hyste
3873 type
3874 };
3875
3876 vpu1_crit: tr
3877 tempe
3878 hyste
3879 type
3880 };
3881 };
3882 };
3883
3884 gpu-thermal {
3885 polling-delay = <1000
3886 polling-delay-passive
3887 thermal-sensors = <&l
3888
3889 trips {
3890 gpu0_alert: t
3891 tempe
3892 hyste
3893 type
3894 };
3895
3896 gpu0_crit: tr
3897 tempe
3898 hyste
3899 type
3900 };
3901 };
3902 };
3903
3904 gpu1-thermal {
3905 polling-delay = <1000
3906 polling-delay-passive
3907 thermal-sensors = <&l
3908
3909 trips {
3910 gpu1_alert: t
3911 tempe
3912 hyste
3913 type
3914 };
3915
3916 gpu1_crit: tr
3917 tempe
3918 hyste
3919 type
3920 };
3921 };
3922 };
3923
3924 vdec-thermal {
3925 polling-delay = <1000
3926 polling-delay-passive
3927 thermal-sensors = <&l
3928
3929 trips {
3930 vdec_alert: t
3931 tempe
3932 hyste
3933 type
3934 };
3935
3936 vdec_crit: tr
3937 tempe
3938 hyste
3939 type
3940 };
3941 };
3942 };
3943
3944 img-thermal {
3945 polling-delay = <1000
3946 polling-delay-passive
3947 thermal-sensors = <&l
3948
3949 trips {
3950 img_alert: tr
3951 tempe
3952 hyste
3953 type
3954 };
3955
3956 img_crit: tri
3957 tempe
3958 hyste
3959 type
3960 };
3961 };
3962 };
3963
3964 infra-thermal {
3965 polling-delay = <1000
3966 polling-delay-passive
3967 thermal-sensors = <&l
3968
3969 trips {
3970 infra_alert:
3971 tempe
3972 hyste
3973 type
3974 };
3975
3976 infra_crit: t
3977 tempe
3978 hyste
3979 type
3980 };
3981 };
3982 };
3983
3984 cam0-thermal {
3985 polling-delay = <1000
3986 polling-delay-passive
3987 thermal-sensors = <&l
3988
3989 trips {
3990 cam0_alert: t
3991 tempe
3992 hyste
3993 type
3994 };
3995
3996 cam0_crit: tr
3997 tempe
3998 hyste
3999 type
4000 };
4001 };
4002 };
4003
4004 cam1-thermal {
4005 polling-delay = <1000
4006 polling-delay-passive
4007 thermal-sensors = <&l
4008
4009 trips {
4010 cam1_alert: t
4011 tempe
4012 hyste
4013 type
4014 };
4015
4016 cam1_crit: tr
4017 tempe
4018 hyste
4019 type
4020 };
4021 };
4022 };
4023 };
4024 };
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