1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 MediaTek Inc. 3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com> 4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h> 8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h> 9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-por 12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h> 15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h> <<
17 #include <dt-bindings/thermal/thermal.h> <<
18 #include <dt-bindings/thermal/mediatek,lvts-th <<
19 16
20 / { 17 / {
21 compatible = "mediatek,mt8195"; 18 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
23 #address-cells = <2>; 20 #address-cells = <2>;
24 #size-cells = <2>; 21 #size-cells = <2>;
25 22
26 aliases { 23 aliases {
27 dp-intf0 = &dp_intf0; <<
28 dp-intf1 = &dp_intf1; <<
29 gce0 = &gce0; 24 gce0 = &gce0;
30 gce1 = &gce1; 25 gce1 = &gce1;
31 ethdr0 = ðdr0; <<
32 mutex0 = &mutex; <<
33 mutex1 = &mutex1; <<
34 merge1 = &merge1; <<
35 merge2 = &merge2; <<
36 merge3 = &merge3; <<
37 merge4 = &merge4; <<
38 merge5 = &merge5; <<
39 vdo1-rdma0 = &vdo1_rdma0; <<
40 vdo1-rdma1 = &vdo1_rdma1; <<
41 vdo1-rdma2 = &vdo1_rdma2; <<
42 vdo1-rdma3 = &vdo1_rdma3; <<
43 vdo1-rdma4 = &vdo1_rdma4; <<
44 vdo1-rdma5 = &vdo1_rdma5; <<
45 vdo1-rdma6 = &vdo1_rdma6; <<
46 vdo1-rdma7 = &vdo1_rdma7; <<
47 }; 26 };
48 27
49 cpus { 28 cpus {
50 #address-cells = <1>; 29 #address-cells = <1>;
51 #size-cells = <0>; 30 #size-cells = <0>;
52 31
53 cpu0: cpu@0 { 32 cpu0: cpu@0 {
54 device_type = "cpu"; 33 device_type = "cpu";
55 compatible = "arm,cort 34 compatible = "arm,cortex-a55";
56 reg = <0x000>; 35 reg = <0x000>;
57 enable-method = "psci" 36 enable-method = "psci";
58 performance-domains = 37 performance-domains = <&performance 0>;
59 clock-frequency = <170 38 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = < 39 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cp !! 40 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
62 i-cache-size = <32768> <<
63 i-cache-line-size = <6 <<
64 i-cache-sets = <128>; <<
65 d-cache-size = <32768> <<
66 d-cache-line-size = <6 <<
67 d-cache-sets = <128>; <<
68 next-level-cache = <&l 41 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>; 42 #cooling-cells = <2>;
70 }; 43 };
71 44
72 cpu1: cpu@100 { 45 cpu1: cpu@100 {
73 device_type = "cpu"; 46 device_type = "cpu";
74 compatible = "arm,cort 47 compatible = "arm,cortex-a55";
75 reg = <0x100>; 48 reg = <0x100>;
76 enable-method = "psci" 49 enable-method = "psci";
77 performance-domains = 50 performance-domains = <&performance 0>;
78 clock-frequency = <170 51 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cp !! 53 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
81 i-cache-size = <32768> <<
82 i-cache-line-size = <6 <<
83 i-cache-sets = <128>; <<
84 d-cache-size = <32768> <<
85 d-cache-line-size = <6 <<
86 d-cache-sets = <128>; <<
87 next-level-cache = <&l 54 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>; 55 #cooling-cells = <2>;
89 }; 56 };
90 57
91 cpu2: cpu@200 { 58 cpu2: cpu@200 {
92 device_type = "cpu"; 59 device_type = "cpu";
93 compatible = "arm,cort 60 compatible = "arm,cortex-a55";
94 reg = <0x200>; 61 reg = <0x200>;
95 enable-method = "psci" 62 enable-method = "psci";
96 performance-domains = 63 performance-domains = <&performance 0>;
97 clock-frequency = <170 64 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = < 65 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cp !! 66 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
100 i-cache-size = <32768> <<
101 i-cache-line-size = <6 <<
102 i-cache-sets = <128>; <<
103 d-cache-size = <32768> <<
104 d-cache-line-size = <6 <<
105 d-cache-sets = <128>; <<
106 next-level-cache = <&l 67 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>; 68 #cooling-cells = <2>;
108 }; 69 };
109 70
110 cpu3: cpu@300 { 71 cpu3: cpu@300 {
111 device_type = "cpu"; 72 device_type = "cpu";
112 compatible = "arm,cort 73 compatible = "arm,cortex-a55";
113 reg = <0x300>; 74 reg = <0x300>;
114 enable-method = "psci" 75 enable-method = "psci";
115 performance-domains = 76 performance-domains = <&performance 0>;
116 clock-frequency = <170 77 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cp !! 79 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
119 i-cache-size = <32768> <<
120 i-cache-line-size = <6 <<
121 i-cache-sets = <128>; <<
122 d-cache-size = <32768> <<
123 d-cache-line-size = <6 <<
124 d-cache-sets = <128>; <<
125 next-level-cache = <&l 80 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>; 81 #cooling-cells = <2>;
127 }; 82 };
128 83
129 cpu4: cpu@400 { 84 cpu4: cpu@400 {
130 device_type = "cpu"; 85 device_type = "cpu";
131 compatible = "arm,cort 86 compatible = "arm,cortex-a78";
132 reg = <0x400>; 87 reg = <0x400>;
133 enable-method = "psci" 88 enable-method = "psci";
134 performance-domains = 89 performance-domains = <&performance 1>;
135 clock-frequency = <217 90 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = < 91 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cp !! 92 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
138 i-cache-size = <65536> <<
139 i-cache-line-size = <6 <<
140 i-cache-sets = <256>; <<
141 d-cache-size = <65536> <<
142 d-cache-line-size = <6 <<
143 d-cache-sets = <256>; <<
144 next-level-cache = <&l 93 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>; 94 #cooling-cells = <2>;
146 }; 95 };
147 96
148 cpu5: cpu@500 { 97 cpu5: cpu@500 {
149 device_type = "cpu"; 98 device_type = "cpu";
150 compatible = "arm,cort 99 compatible = "arm,cortex-a78";
151 reg = <0x500>; 100 reg = <0x500>;
152 enable-method = "psci" 101 enable-method = "psci";
153 performance-domains = 102 performance-domains = <&performance 1>;
154 clock-frequency = <217 103 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cp !! 105 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
157 i-cache-size = <65536> <<
158 i-cache-line-size = <6 <<
159 i-cache-sets = <256>; <<
160 d-cache-size = <65536> <<
161 d-cache-line-size = <6 <<
162 d-cache-sets = <256>; <<
163 next-level-cache = <&l 106 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>; 107 #cooling-cells = <2>;
165 }; 108 };
166 109
167 cpu6: cpu@600 { 110 cpu6: cpu@600 {
168 device_type = "cpu"; 111 device_type = "cpu";
169 compatible = "arm,cort 112 compatible = "arm,cortex-a78";
170 reg = <0x600>; 113 reg = <0x600>;
171 enable-method = "psci" 114 enable-method = "psci";
172 performance-domains = 115 performance-domains = <&performance 1>;
173 clock-frequency = <217 116 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = < 117 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cp !! 118 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
176 i-cache-size = <65536> <<
177 i-cache-line-size = <6 <<
178 i-cache-sets = <256>; <<
179 d-cache-size = <65536> <<
180 d-cache-line-size = <6 <<
181 d-cache-sets = <256>; <<
182 next-level-cache = <&l 119 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>; 120 #cooling-cells = <2>;
184 }; 121 };
185 122
186 cpu7: cpu@700 { 123 cpu7: cpu@700 {
187 device_type = "cpu"; 124 device_type = "cpu";
188 compatible = "arm,cort 125 compatible = "arm,cortex-a78";
189 reg = <0x700>; 126 reg = <0x700>;
190 enable-method = "psci" 127 enable-method = "psci";
191 performance-domains = 128 performance-domains = <&performance 1>;
192 clock-frequency = <217 129 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = < 130 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cp !! 131 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
195 i-cache-size = <65536> <<
196 i-cache-line-size = <6 <<
197 i-cache-sets = <256>; <<
198 d-cache-size = <65536> <<
199 d-cache-line-size = <6 <<
200 d-cache-sets = <256>; <<
201 next-level-cache = <&l 132 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>; 133 #cooling-cells = <2>;
203 }; 134 };
204 135
205 cpu-map { 136 cpu-map {
206 cluster0 { 137 cluster0 {
207 core0 { 138 core0 {
208 cpu = 139 cpu = <&cpu0>;
209 }; 140 };
210 141
211 core1 { 142 core1 {
212 cpu = 143 cpu = <&cpu1>;
213 }; 144 };
214 145
215 core2 { 146 core2 {
216 cpu = 147 cpu = <&cpu2>;
217 }; 148 };
218 149
219 core3 { 150 core3 {
220 cpu = 151 cpu = <&cpu3>;
221 }; 152 };
222 153
223 core4 { 154 core4 {
224 cpu = 155 cpu = <&cpu4>;
225 }; 156 };
226 157
227 core5 { 158 core5 {
228 cpu = 159 cpu = <&cpu5>;
229 }; 160 };
230 161
231 core6 { 162 core6 {
232 cpu = 163 cpu = <&cpu6>;
233 }; 164 };
234 165
235 core7 { 166 core7 {
236 cpu = 167 cpu = <&cpu7>;
237 }; 168 };
238 }; 169 };
239 }; 170 };
240 171
241 idle-states { 172 idle-states {
242 entry-method = "psci"; 173 entry-method = "psci";
243 174
244 cpu_ret_l: cpu-retenti !! 175 cpu_off_l: cpu-off-l {
245 compatible = " 176 compatible = "arm,idle-state";
246 arm,psci-suspe 177 arm,psci-suspend-param = <0x00010001>;
247 local-timer-st 178 local-timer-stop;
248 entry-latency- 179 entry-latency-us = <50>;
249 exit-latency-u 180 exit-latency-us = <95>;
250 min-residency- 181 min-residency-us = <580>;
251 }; 182 };
252 183
253 cpu_ret_b: cpu-retenti !! 184 cpu_off_b: cpu-off-b {
254 compatible = " 185 compatible = "arm,idle-state";
255 arm,psci-suspe 186 arm,psci-suspend-param = <0x00010001>;
256 local-timer-st 187 local-timer-stop;
257 entry-latency- 188 entry-latency-us = <45>;
258 exit-latency-u 189 exit-latency-us = <140>;
259 min-residency- 190 min-residency-us = <740>;
260 }; 191 };
261 192
262 cpu_off_l: cpu-off-l { !! 193 cluster_off_l: cluster-off-l {
263 compatible = " 194 compatible = "arm,idle-state";
264 arm,psci-suspe 195 arm,psci-suspend-param = <0x01010002>;
265 local-timer-st 196 local-timer-stop;
266 entry-latency- 197 entry-latency-us = <55>;
267 exit-latency-u 198 exit-latency-us = <155>;
268 min-residency- 199 min-residency-us = <840>;
269 }; 200 };
270 201
271 cpu_off_b: cpu-off-b { !! 202 cluster_off_b: cluster-off-b {
272 compatible = " 203 compatible = "arm,idle-state";
273 arm,psci-suspe 204 arm,psci-suspend-param = <0x01010002>;
274 local-timer-st 205 local-timer-stop;
275 entry-latency- 206 entry-latency-us = <50>;
276 exit-latency-u 207 exit-latency-us = <200>;
277 min-residency- 208 min-residency-us = <1000>;
278 }; 209 };
279 }; 210 };
280 211
281 l2_0: l2-cache0 { 212 l2_0: l2-cache0 {
282 compatible = "cache"; 213 compatible = "cache";
283 cache-level = <2>; <<
284 cache-size = <131072>; <<
285 cache-line-size = <64> <<
286 cache-sets = <512>; <<
287 next-level-cache = <&l 214 next-level-cache = <&l3_0>;
288 cache-unified; <<
289 }; 215 };
290 216
291 l2_1: l2-cache1 { 217 l2_1: l2-cache1 {
292 compatible = "cache"; 218 compatible = "cache";
293 cache-level = <2>; <<
294 cache-size = <262144>; <<
295 cache-line-size = <64> <<
296 cache-sets = <512>; <<
297 next-level-cache = <&l 219 next-level-cache = <&l3_0>;
298 cache-unified; <<
299 }; 220 };
300 221
301 l3_0: l3-cache { 222 l3_0: l3-cache {
302 compatible = "cache"; 223 compatible = "cache";
303 cache-level = <3>; <<
304 cache-size = <2097152> <<
305 cache-line-size = <64> <<
306 cache-sets = <2048>; <<
307 cache-unified; <<
308 }; 224 };
309 }; 225 };
310 226
311 dsu-pmu { 227 dsu-pmu {
312 compatible = "arm,dsu-pmu"; 228 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_T 229 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu 230 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu 231 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail"; 232 status = "fail";
317 }; 233 };
318 234
319 dmic_codec: dmic-codec { 235 dmic_codec: dmic-codec {
320 compatible = "dmic-codec"; 236 compatible = "dmic-codec";
321 num-channels = <2>; 237 num-channels = <2>;
322 wakeup-delay-ms = <50>; 238 wakeup-delay-ms = <50>;
323 }; 239 };
324 240
325 sound: mt8195-sound { 241 sound: mt8195-sound {
326 mediatek,platform = <&afe>; 242 mediatek,platform = <&afe>;
327 status = "disabled"; 243 status = "disabled";
328 }; 244 };
329 245
330 clk13m: fixed-factor-clock-13m { 246 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clo 247 compatible = "fixed-factor-clock";
332 #clock-cells = <0>; 248 #clock-cells = <0>;
333 clocks = <&clk26m>; 249 clocks = <&clk26m>;
334 clock-div = <2>; 250 clock-div = <2>;
335 clock-mult = <1>; 251 clock-mult = <1>;
336 clock-output-names = "clk13m"; 252 clock-output-names = "clk13m";
337 }; 253 };
338 254
339 clk26m: oscillator-26m { 255 clk26m: oscillator-26m {
340 compatible = "fixed-clock"; 256 compatible = "fixed-clock";
341 #clock-cells = <0>; 257 #clock-cells = <0>;
342 clock-frequency = <26000000>; 258 clock-frequency = <26000000>;
343 clock-output-names = "clk26m"; 259 clock-output-names = "clk26m";
344 }; 260 };
345 261
346 clk32k: oscillator-32k { 262 clk32k: oscillator-32k {
347 compatible = "fixed-clock"; 263 compatible = "fixed-clock";
348 #clock-cells = <0>; 264 #clock-cells = <0>;
349 clock-frequency = <32768>; 265 clock-frequency = <32768>;
350 clock-output-names = "clk32k"; 266 clock-output-names = "clk32k";
351 }; 267 };
352 268
353 performance: performance-controller@11 269 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq 270 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, 271 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1 272 #performance-domain-cells = <1>;
357 }; 273 };
358 274
359 gpu_opp_table: opp-table-gpu { <<
360 compatible = "operating-points <<
361 opp-shared; <<
362 <<
363 opp-390000000 { <<
364 opp-hz = /bits/ 64 <39 <<
365 opp-microvolt = <62500 <<
366 }; <<
367 opp-410000000 { <<
368 opp-hz = /bits/ 64 <41 <<
369 opp-microvolt = <63125 <<
370 }; <<
371 opp-431000000 { <<
372 opp-hz = /bits/ 64 <43 <<
373 opp-microvolt = <63125 <<
374 }; <<
375 opp-473000000 { <<
376 opp-hz = /bits/ 64 <47 <<
377 opp-microvolt = <63750 <<
378 }; <<
379 opp-515000000 { <<
380 opp-hz = /bits/ 64 <51 <<
381 opp-microvolt = <63750 <<
382 }; <<
383 opp-556000000 { <<
384 opp-hz = /bits/ 64 <55 <<
385 opp-microvolt = <64375 <<
386 }; <<
387 opp-598000000 { <<
388 opp-hz = /bits/ 64 <59 <<
389 opp-microvolt = <65000 <<
390 }; <<
391 opp-640000000 { <<
392 opp-hz = /bits/ 64 <64 <<
393 opp-microvolt = <65000 <<
394 }; <<
395 opp-670000000 { <<
396 opp-hz = /bits/ 64 <67 <<
397 opp-microvolt = <66250 <<
398 }; <<
399 opp-700000000 { <<
400 opp-hz = /bits/ 64 <70 <<
401 opp-microvolt = <67500 <<
402 }; <<
403 opp-730000000 { <<
404 opp-hz = /bits/ 64 <73 <<
405 opp-microvolt = <68750 <<
406 }; <<
407 opp-760000000 { <<
408 opp-hz = /bits/ 64 <76 <<
409 opp-microvolt = <70000 <<
410 }; <<
411 opp-790000000 { <<
412 opp-hz = /bits/ 64 <79 <<
413 opp-microvolt = <71250 <<
414 }; <<
415 opp-820000000 { <<
416 opp-hz = /bits/ 64 <82 <<
417 opp-microvolt = <72500 <<
418 }; <<
419 opp-850000000 { <<
420 opp-hz = /bits/ 64 <85 <<
421 opp-microvolt = <73750 <<
422 }; <<
423 opp-880000000 { <<
424 opp-hz = /bits/ 64 <88 <<
425 opp-microvolt = <75000 <<
426 }; <<
427 }; <<
428 <<
429 pmu-a55 { 275 pmu-a55 {
430 compatible = "arm,cortex-a55-p 276 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>; 277 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TY 278 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 }; 279 };
434 280
435 pmu-a78 { 281 pmu-a78 {
436 compatible = "arm,cortex-a78-p 282 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>; 283 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TY 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 }; 285 };
440 286
441 psci { 287 psci {
442 compatible = "arm,psci-1.0"; 288 compatible = "arm,psci-1.0";
443 method = "smc"; 289 method = "smc";
444 }; 290 };
445 291
446 timer: timer { 292 timer: timer {
447 compatible = "arm,armv8-timer" 293 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>; 294 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_T 295 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_T 296 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_T 297 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_T 298 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 }; 299 };
454 300
455 soc { 301 soc {
456 #address-cells = <2>; 302 #address-cells = <2>;
457 #size-cells = <2>; 303 #size-cells = <2>;
458 compatible = "simple-bus"; 304 compatible = "simple-bus";
459 ranges; 305 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 <<
461 306
462 gic: interrupt-controller@c000 307 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic- 308 compatible = "arm,gic-v3";
464 #interrupt-cells = <4> 309 #interrupt-cells = <4>;
465 #redistributor-regions 310 #redistributor-regions = <1>;
466 interrupt-parent = <&g 311 interrupt-parent = <&gic>;
467 interrupt-controller; 312 interrupt-controller;
468 reg = <0 0x0c000000 0 313 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 314 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 315 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471 316
472 ppi-partitions { 317 ppi-partitions {
473 ppi_cluster0: 318 ppi_cluster0: interrupt-partition-0 {
474 affini 319 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 }; 320 };
476 321
477 ppi_cluster1: 322 ppi_cluster1: interrupt-partition-1 {
478 affini 323 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 }; 324 };
480 }; 325 };
481 }; 326 };
482 327
483 topckgen: syscon@10000000 { 328 topckgen: syscon@10000000 {
484 compatible = "mediatek 329 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 330 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>; 331 #clock-cells = <1>;
487 }; 332 };
488 333
489 infracfg_ao: syscon@10001000 { 334 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek 335 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
491 reg = <0 0x10001000 0 336 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>; 337 #clock-cells = <1>;
493 #reset-cells = <1>; 338 #reset-cells = <1>;
494 }; 339 };
495 340
496 pericfg: syscon@10003000 { 341 pericfg: syscon@10003000 {
497 compatible = "mediatek 342 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 343 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>; 344 #clock-cells = <1>;
500 }; 345 };
501 346
502 pio: pinctrl@10005000 { 347 pio: pinctrl@10005000 {
503 compatible = "mediatek 348 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 349 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 350 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 351 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 352 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 353 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 354 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 355 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 356 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", 357 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br" 358 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl" 359 "iocfg_tl", "eint";
515 gpio-controller; 360 gpio-controller;
516 #gpio-cells = <2>; 361 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 362 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller; 363 interrupt-controller;
519 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2> 365 #interrupt-cells = <2>;
521 }; 366 };
522 367
523 scpsys: syscon@10006000 { 368 scpsys: syscon@10006000 {
524 compatible = "mediatek 369 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 370 reg = <0 0x10006000 0 0x1000>;
526 371
527 /* System Power Manage 372 /* System Power Manager */
528 spm: power-controller 373 spm: power-controller {
529 compatible = " 374 compatible = "mediatek,mt8195-power-controller";
530 #address-cells 375 #address-cells = <1>;
531 #size-cells = 376 #size-cells = <0>;
532 #power-domain- 377 #power-domain-cells = <1>;
533 378
534 /* power domai 379 /* power domain of the SoC */
535 mfg0: power-do 380 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = 381 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #addre 382 #address-cells = <1>;
538 #size- 383 #size-cells = <0>;
539 #power 384 #power-domain-cells = <1>;
540 385
541 mfg1: !! 386 power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 387 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 !! 388 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
544 !! 389 clock-names = "mfg";
545 <<
546 390 mediatek,infracfg = <&infracfg_ao>;
547 391 #address-cells = <1>;
548 392 #size-cells = <0>;
549 393 #power-domain-cells = <1>;
550 394
551 395 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 396 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 397 #power-domain-cells = <0>;
554 398 };
555 399
556 400 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 401 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 402 #power-domain-cells = <0>;
559 403 };
560 404
561 405 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 406 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 407 #power-domain-cells = <0>;
564 408 };
565 409
566 410 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 411 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 412 #power-domain-cells = <0>;
569 413 };
570 414
571 415 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 416 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 417 #power-domain-cells = <0>;
574 418 };
575 }; 419 };
576 }; 420 };
577 421
578 power-domain@M 422 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = 423 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks 424 clocks = <&topckgen CLK_TOP_VPP>,
581 425 <&topckgen CLK_TOP_CAM>,
582 426 <&topckgen CLK_TOP_CCU>,
583 427 <&topckgen CLK_TOP_IMG>,
584 428 <&topckgen CLK_TOP_VENC>,
585 429 <&topckgen CLK_TOP_VDEC>,
586 430 <&topckgen CLK_TOP_WPE_VPP>,
587 431 <&topckgen CLK_TOP_CFG_VPP0>,
588 432 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 433 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 434 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 435 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 436 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 437 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 438 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 439 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 440 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 441 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 442 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 443 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 444 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 445 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 446 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 447 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 448 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 449 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 450 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock- 451 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 452 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 453 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 454 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 455 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 456 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 457 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 458 "vppsys0-18";
615 mediat 459 mediatek,infracfg = <&infracfg_ao>;
616 #addre 460 #address-cells = <1>;
617 #size- 461 #size-cells = <0>;
618 #power 462 #power-domain-cells = <1>;
619 463
620 power- 464 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 465 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 466 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 467 clock-names = "vdec1-0";
624 468 mediatek,infracfg = <&infracfg_ao>;
625 469 #power-domain-cells = <0>;
626 }; 470 };
627 471
628 power- 472 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 473 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 474 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
631 475 clock-names = "venc1-larb";
632 476 mediatek,infracfg = <&infracfg_ao>;
633 477 #power-domain-cells = <0>;
634 }; 478 };
635 479
636 power- 480 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 481 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 482 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 483 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 484 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 485 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 486 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 487 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 488 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 489 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 490 "vdosys0-2", "vdosys0-3",
647 491 "vdosys0-4", "vdosys0-5";
648 492 mediatek,infracfg = <&infracfg_ao>;
649 493 #address-cells = <1>;
650 494 #size-cells = <0>;
651 495 #power-domain-cells = <1>;
652 496
653 497 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 498 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 499 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 500 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 501 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 502 clock-names = "vppsys1", "vppsys1-0",
659 503 "vppsys1-1";
660 504 mediatek,infracfg = <&infracfg_ao>;
661 505 #power-domain-cells = <0>;
662 506 };
663 507
664 508 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 509 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 510 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 511 <&wpesys CLK_WPE_SMI_LARB8>,
668 512 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 513 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 514 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 515 "wepsys-3";
672 516 mediatek,infracfg = <&infracfg_ao>;
673 517 #power-domain-cells = <0>;
674 518 };
675 519
676 520 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 521 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 522 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 523 clock-names = "vdec0-0";
680 524 mediatek,infracfg = <&infracfg_ao>;
681 525 #power-domain-cells = <0>;
682 526 };
683 527
684 528 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 529 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 530 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 531 clock-names = "vdec2-0";
688 532 mediatek,infracfg = <&infracfg_ao>;
689 533 #power-domain-cells = <0>;
690 534 };
691 535
692 536 power-domain@MT8195_POWER_DOMAIN_VENC {
693 537 reg = <MT8195_POWER_DOMAIN_VENC>;
694 538 clocks = <&vencsys CLK_VENC_LARB>;
695 539 clock-names = "venc0-larb";
696 540 mediatek,infracfg = <&infracfg_ao>;
697 541 #power-domain-cells = <0>;
698 542 };
699 543
700 544 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 545 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 546 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 547 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 548 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 549 <&vdosys1 CLK_VDO1_GALS>;
706 550 clock-names = "vdosys1", "vdosys1-0",
707 551 "vdosys1-1", "vdosys1-2";
708 552 mediatek,infracfg = <&infracfg_ao>;
709 553 #address-cells = <1>;
710 554 #size-cells = <0>;
711 555 #power-domain-cells = <1>;
712 556
713 557 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 558 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 559 mediatek,infracfg = <&infracfg_ao>;
716 560 #power-domain-cells = <0>;
717 561 };
718 562
719 563 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 564 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 565 mediatek,infracfg = <&infracfg_ao>;
722 566 #power-domain-cells = <0>;
723 567 };
724 568
725 569 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 570 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 571 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 572 clock-names = "hdmi_tx";
729 573 #power-domain-cells = <0>;
730 574 };
731 575 };
732 576
733 577 power-domain@MT8195_POWER_DOMAIN_IMG {
734 578 reg = <MT8195_POWER_DOMAIN_IMG>;
735 579 clocks = <&imgsys CLK_IMG_LARB9>,
736 580 <&imgsys CLK_IMG_GALS>;
737 581 clock-names = "img-0", "img-1";
738 582 mediatek,infracfg = <&infracfg_ao>;
739 583 #address-cells = <1>;
740 584 #size-cells = <0>;
741 585 #power-domain-cells = <1>;
742 586
743 587 power-domain@MT8195_POWER_DOMAIN_DIP {
744 588 reg = <MT8195_POWER_DOMAIN_DIP>;
745 589 #power-domain-cells = <0>;
746 590 };
747 591
748 592 power-domain@MT8195_POWER_DOMAIN_IPE {
749 593 reg = <MT8195_POWER_DOMAIN_IPE>;
750 594 clocks = <&topckgen CLK_TOP_IPE>,
751 595 <&imgsys CLK_IMG_IPE>,
752 596 <&ipesys CLK_IPE_SMI_LARB12>;
753 597 clock-names = "ipe", "ipe-0", "ipe-1";
754 598 mediatek,infracfg = <&infracfg_ao>;
755 599 #power-domain-cells = <0>;
756 600 };
757 601 };
758 602
759 603 power-domain@MT8195_POWER_DOMAIN_CAM {
760 604 reg = <MT8195_POWER_DOMAIN_CAM>;
761 605 clocks = <&camsys CLK_CAM_LARB13>,
762 606 <&camsys CLK_CAM_LARB14>,
763 607 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 608 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 609 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 610 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 611 "cam-4";
768 612 mediatek,infracfg = <&infracfg_ao>;
769 613 #address-cells = <1>;
770 614 #size-cells = <0>;
771 615 #power-domain-cells = <1>;
772 616
773 617 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 618 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 619 #power-domain-cells = <0>;
776 620 };
777 621
778 622 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 623 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 624 #power-domain-cells = <0>;
781 625 };
782 626
783 627 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 628 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 629 #power-domain-cells = <0>;
786 630 };
787 631 };
788 }; 632 };
789 }; 633 };
790 634
791 power-domain@M 635 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = 636 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediat 637 mediatek,infracfg = <&infracfg_ao>;
794 #power 638 #power-domain-cells = <0>;
795 }; 639 };
796 640
797 power-domain@M 641 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = 642 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediat 643 mediatek,infracfg = <&infracfg_ao>;
800 #power 644 #power-domain-cells = <0>;
801 }; 645 };
802 646
803 power-domain@M 647 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = 648 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power 649 #power-domain-cells = <0>;
806 }; 650 };
807 651
808 power-domain@M 652 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = 653 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power 654 #power-domain-cells = <0>;
811 }; 655 };
812 656
813 power-domain@M 657 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = 658 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks 659 clocks = <&topckgen CLK_TOP_SENINF>,
816 660 <&topckgen CLK_TOP_SENINF2>;
817 clock- 661 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power 662 #power-domain-cells = <0>;
819 }; 663 };
820 664
821 power-domain@M 665 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = 666 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks 667 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock- 668 clock-names = "ether";
825 #power 669 #power-domain-cells = <0>;
826 }; 670 };
827 671
828 power-domain@M 672 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = 673 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks 674 clocks = <&topckgen CLK_TOP_ADSP>,
831 675 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock- 676 clock-names = "adsp", "adsp1";
833 #addre 677 #address-cells = <1>;
834 #size- 678 #size-cells = <0>;
835 mediat 679 mediatek,infracfg = <&infracfg_ao>;
836 #power 680 #power-domain-cells = <1>;
837 681
838 power- 682 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 683 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 684 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 685 <&topckgen CLK_TOP_AUD_INTBUS>,
842 686 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 687 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 688 clock-names = "audio", "audio1", "audio2",
845 689 "audio3";
846 690 mediatek,infracfg = <&infracfg_ao>;
847 691 #power-domain-cells = <0>;
848 }; 692 };
849 }; 693 };
850 }; 694 };
851 }; 695 };
852 696
853 watchdog: watchdog@10007000 { 697 watchdog: watchdog@10007000 {
854 compatible = "mediatek 698 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrs 699 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 700 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>; 701 #reset-cells = <1>;
858 }; 702 };
859 703
860 apmixedsys: syscon@1000c000 { 704 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek 705 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 706 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>; 707 #clock-cells = <1>;
864 }; 708 };
865 709
866 systimer: timer@10017000 { 710 systimer: timer@10017000 {
867 compatible = "mediatek 711 compatible = "mediatek,mt8195-timer",
868 "mediatek 712 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 713 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 714 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>; 715 clocks = <&clk13m>;
872 }; 716 };
873 717
874 pwrap: pwrap@10024000 { 718 pwrap: pwrap@10024000 {
875 compatible = "mediatek 719 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 720 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap"; 721 reg-names = "pwrap";
878 interrupts = <GIC_SPI 722 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao 723 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao 724 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", " 725 clock-names = "spi", "wrap";
882 assigned-clocks = <&to 726 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents 727 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 }; 728 };
885 729
886 spmi: spmi@10027000 { 730 spmi: spmi@10027000 {
887 compatible = "mediatek 731 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 732 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 733 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "s 734 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao 735 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao 736 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CL 737 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sy 738 clock-names = "pmif_sys_ck",
895 "pmif_tm 739 "pmif_tmr_ck",
896 "spmimst 740 "spmimst_clk_mux";
897 assigned-clocks = <&to 741 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents 742 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 }; 743 };
900 744
901 iommu_infra: infra-iommu@10315 745 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek 746 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 747 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 748 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 749 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 750 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 751 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 752 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>; 753 #iommu-cells = <1>;
910 }; 754 };
911 755
912 gce0: mailbox@10320000 { 756 gce0: mailbox@10320000 {
913 compatible = "mediatek 757 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 758 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 759 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>; 760 #mbox-cells = <2>;
917 clocks = <&infracfg_ao 761 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 }; 762 };
919 763
920 gce1: mailbox@10330000 { 764 gce1: mailbox@10330000 {
921 compatible = "mediatek 765 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 766 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 767 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>; 768 #mbox-cells = <2>;
925 clocks = <&infracfg_ao 769 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 }; 770 };
927 771
928 scp: scp@10500000 { 772 scp: scp@10500000 {
929 compatible = "mediatek 773 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 774 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 775 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 776 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "c 777 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled"; 779 status = "disabled";
936 }; 780 };
937 781
938 scp_adsp: clock-controller@107 782 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek 783 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 784 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>; 785 #clock-cells = <1>;
942 }; 786 };
943 787
944 adsp: dsp@10803000 { 788 adsp: dsp@10803000 {
945 compatible = "mediatek 789 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 790 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 791 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sr 792 reg-names = "cfg", "sram";
949 clocks = <&topckgen CL 793 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>, 794 <&clk26m>,
951 <&topckgen CL 795 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CL 796 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CL 797 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CL 798 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_se 799 clock-names = "adsp_sel",
956 "clk26m_ck", 800 "clk26m_ck",
957 "audio_local_ 801 "audio_local_bus",
958 "mainpll_d7_d 802 "mainpll_d7_d2",
959 "scp_adsp_aud 803 "scp_adsp_audiodsp",
960 "audio_h"; 804 "audio_h";
961 power-domains = <&spm 805 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx 806 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbo 807 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled"; 808 status = "disabled";
965 }; 809 };
966 810
967 adsp_mailbox0: mailbox@1081600 811 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek 812 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>; 813 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 814 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 815 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 }; 816 };
973 817
974 adsp_mailbox1: mailbox@1081700 818 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek 819 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>; 820 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 821 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 822 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 }; 823 };
980 824
981 afe: mt8195-afe-pcm@10890000 { 825 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek 826 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 827 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <& 828 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm 829 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 830 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14 831 resets = <&watchdog 14>;
988 reset-names = "audiosy 832 reset-names = "audiosys";
989 clocks = <&clk26m>, 833 clocks = <&clk26m>,
990 <&apmixedsys C 834 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys C 835 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK 836 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK 837 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK 838 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK 839 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK 840 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK 841 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK 842 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK 843 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CL 844 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CL 845 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CL 846 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CL 847 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CL 848 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CL 849 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao 850 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CL 851 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m 852 clock-names = "clk26m",
1009 "apll1_ck", 853 "apll1_ck",
1010 "apll2_ck", 854 "apll2_ck",
1011 "apll12_div0" 855 "apll12_div0",
1012 "apll12_div1" 856 "apll12_div1",
1013 "apll12_div2" 857 "apll12_div2",
1014 "apll12_div3" 858 "apll12_div3",
1015 "apll12_div9" 859 "apll12_div9",
1016 "a1sys_hp_sel 860 "a1sys_hp_sel",
1017 "aud_intbus_s 861 "aud_intbus_sel",
1018 "audio_h_sel" 862 "audio_h_sel",
1019 "audio_local_ 863 "audio_local_bus_sel",
1020 "dptx_m_sel", 864 "dptx_m_sel",
1021 "i2so1_m_sel" 865 "i2so1_m_sel",
1022 "i2so2_m_sel" 866 "i2so2_m_sel",
1023 "i2si1_m_sel" 867 "i2si1_m_sel",
1024 "i2si2_m_sel" 868 "i2si2_m_sel",
1025 "infra_ao_aud 869 "infra_ao_audio_26m_b",
1026 "scp_adsp_aud 870 "scp_adsp_audiodsp";
1027 status = "disabled"; 871 status = "disabled";
1028 }; 872 };
1029 873
1030 uart0: serial@11001100 { 874 uart0: serial@11001100 {
1031 compatible = "mediate 875 compatible = "mediatek,mt8195-uart",
1032 "mediate 876 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 877 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, < 879 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", 880 clock-names = "baud", "bus";
1037 status = "disabled"; 881 status = "disabled";
1038 }; 882 };
1039 883
1040 uart1: serial@11001200 { 884 uart1: serial@11001200 {
1041 compatible = "mediate 885 compatible = "mediatek,mt8195-uart",
1042 "mediate 886 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 887 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 888 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, < 889 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", 890 clock-names = "baud", "bus";
1047 status = "disabled"; 891 status = "disabled";
1048 }; 892 };
1049 893
1050 uart2: serial@11001300 { 894 uart2: serial@11001300 {
1051 compatible = "mediate 895 compatible = "mediatek,mt8195-uart",
1052 "mediate 896 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 897 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, < 899 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", 900 clock-names = "baud", "bus";
1057 status = "disabled"; 901 status = "disabled";
1058 }; 902 };
1059 903
1060 uart3: serial@11001400 { 904 uart3: serial@11001400 {
1061 compatible = "mediate 905 compatible = "mediatek,mt8195-uart",
1062 "mediate 906 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 907 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 908 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, < 909 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", 910 clock-names = "baud", "bus";
1067 status = "disabled"; 911 status = "disabled";
1068 }; 912 };
1069 913
1070 uart4: serial@11001500 { 914 uart4: serial@11001500 {
1071 compatible = "mediate 915 compatible = "mediatek,mt8195-uart",
1072 "mediate 916 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 917 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 918 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, < 919 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", 920 clock-names = "baud", "bus";
1077 status = "disabled"; 921 status = "disabled";
1078 }; 922 };
1079 923
1080 uart5: serial@11001600 { 924 uart5: serial@11001600 {
1081 compatible = "mediate 925 compatible = "mediatek,mt8195-uart",
1082 "mediate 926 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 927 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 928 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, < 929 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", 930 clock-names = "baud", "bus";
1087 status = "disabled"; 931 status = "disabled";
1088 }; 932 };
1089 933
1090 auxadc: auxadc@11002000 { 934 auxadc: auxadc@11002000 {
1091 compatible = "mediate 935 compatible = "mediatek,mt8195-auxadc",
1092 "mediate 936 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 937 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_a 938 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main"; 939 clock-names = "main";
1096 #io-channel-cells = < 940 #io-channel-cells = <1>;
1097 status = "disabled"; 941 status = "disabled";
1098 }; 942 };
1099 943
1100 pericfg_ao: syscon@11003000 { 944 pericfg_ao: syscon@11003000 {
1101 compatible = "mediate 945 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 946 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>; 947 #clock-cells = <1>;
1104 }; 948 };
1105 949
1106 spi0: spi@1100a000 { 950 spi0: spi@1100a000 {
1107 compatible = "mediate 951 compatible = "mediatek,mt8195-spi",
1108 "mediate 952 "mediatek,mt6765-spi";
1109 #address-cells = <1>; 953 #address-cells = <1>;
1110 #size-cells = <0>; 954 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 955 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 956 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen C 957 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen C 958 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_a 959 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent 960 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled"; 961 status = "disabled";
1118 }; 962 };
1119 963
1120 lvts_ap: thermal-sensor@1100b <<
1121 compatible = "mediate <<
1122 reg = <0 0x1100b000 0 <<
1123 interrupts = <GIC_SPI <<
1124 clocks = <&infracfg_a <<
1125 resets = <&infracfg_a <<
1126 nvmem-cells = <&lvts_ <<
1127 nvmem-cell-names = "l <<
1128 #thermal-sensor-cells <<
1129 }; <<
1130 <<
1131 svs: svs@1100bc00 { <<
1132 compatible = "mediate <<
1133 reg = <0 0x1100bc00 0 <<
1134 interrupts = <GIC_SPI <<
1135 clocks = <&infracfg_a <<
1136 clock-names = "main"; <<
1137 nvmem-cells = <&svs_c <<
1138 nvmem-cell-names = "s <<
1139 resets = <&infracfg_a <<
1140 reset-names = "svs_rs <<
1141 }; <<
1142 <<
1143 disp_pwm0: pwm@1100e000 { <<
1144 compatible = "mediate <<
1145 reg = <0 0x1100e000 0 <<
1146 interrupts = <GIC_SPI <<
1147 power-domains = <&spm <<
1148 #pwm-cells = <2>; <<
1149 clocks = <&topckgen C <<
1150 <&infracfg_a <<
1151 clock-names = "main", <<
1152 status = "disabled"; <<
1153 }; <<
1154 <<
1155 disp_pwm1: pwm@1100f000 { <<
1156 compatible = "mediate <<
1157 reg = <0 0x1100f000 0 <<
1158 interrupts = <GIC_SPI <<
1159 #pwm-cells = <2>; <<
1160 clocks = <&topckgen C <<
1161 <&infracfg_a <<
1162 clock-names = "main", <<
1163 status = "disabled"; <<
1164 }; <<
1165 <<
1166 spi1: spi@11010000 { 964 spi1: spi@11010000 {
1167 compatible = "mediate 965 compatible = "mediatek,mt8195-spi",
1168 "mediate 966 "mediatek,mt6765-spi";
1169 #address-cells = <1>; 967 #address-cells = <1>;
1170 #size-cells = <0>; 968 #size-cells = <0>;
1171 reg = <0 0x11010000 0 969 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 970 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen C 971 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen C 972 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_a 973 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent 974 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled"; 975 status = "disabled";
1178 }; 976 };
1179 977
1180 spi2: spi@11012000 { 978 spi2: spi@11012000 {
1181 compatible = "mediate 979 compatible = "mediatek,mt8195-spi",
1182 "mediate 980 "mediatek,mt6765-spi";
1183 #address-cells = <1>; 981 #address-cells = <1>;
1184 #size-cells = <0>; 982 #size-cells = <0>;
1185 reg = <0 0x11012000 0 983 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 984 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen C 985 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen C 986 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_a 987 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent 988 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled"; 989 status = "disabled";
1192 }; 990 };
1193 991
1194 spi3: spi@11013000 { 992 spi3: spi@11013000 {
1195 compatible = "mediate 993 compatible = "mediatek,mt8195-spi",
1196 "mediate 994 "mediatek,mt6765-spi";
1197 #address-cells = <1>; 995 #address-cells = <1>;
1198 #size-cells = <0>; 996 #size-cells = <0>;
1199 reg = <0 0x11013000 0 997 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 998 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen C 999 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen C 1000 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_a 1001 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent 1002 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled"; 1003 status = "disabled";
1206 }; 1004 };
1207 1005
1208 spi4: spi@11018000 { 1006 spi4: spi@11018000 {
1209 compatible = "mediate 1007 compatible = "mediatek,mt8195-spi",
1210 "mediate 1008 "mediatek,mt6765-spi";
1211 #address-cells = <1>; 1009 #address-cells = <1>;
1212 #size-cells = <0>; 1010 #size-cells = <0>;
1213 reg = <0 0x11018000 0 1011 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 1012 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen C 1013 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen C 1014 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_a 1015 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent 1016 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled"; 1017 status = "disabled";
1220 }; 1018 };
1221 1019
1222 spi5: spi@11019000 { 1020 spi5: spi@11019000 {
1223 compatible = "mediate 1021 compatible = "mediatek,mt8195-spi",
1224 "mediate 1022 "mediatek,mt6765-spi";
1225 #address-cells = <1>; 1023 #address-cells = <1>;
1226 #size-cells = <0>; 1024 #size-cells = <0>;
1227 reg = <0 0x11019000 0 1025 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen C 1027 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen C 1028 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_a 1029 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent 1030 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled"; 1031 status = "disabled";
1234 }; 1032 };
1235 1033
1236 spis0: spi@1101d000 { 1034 spis0: spi@1101d000 {
1237 compatible = "mediate 1035 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 1036 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 1037 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_a 1038 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi"; 1039 clock-names = "spi";
1242 assigned-clocks = <&t 1040 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parent 1041 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled"; 1042 status = "disabled";
1245 }; 1043 };
1246 1044
1247 spis1: spi@1101e000 { 1045 spis1: spi@1101e000 {
1248 compatible = "mediate 1046 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 1047 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 1048 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_a 1049 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi"; 1050 clock-names = "spi";
1253 assigned-clocks = <&t 1051 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parent 1052 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled"; 1053 status = "disabled";
1256 }; 1054 };
1257 1055
1258 eth: ethernet@11021000 { !! 1056 xhci0: usb@11200000 {
1259 compatible = "mediate !! 1057 compatible = "mediatek,mt8195-xhci",
1260 reg = <0 0x11021000 0 !! 1058 "mediatek,mtk-xhci";
1261 interrupts = <GIC_SPI !! 1059 reg = <0 0x11200000 0 0x1000>,
1262 interrupt-names = "ma !! 1060 <0 0x11203e00 0 0x0100>;
1263 clock-names = "axi", <<
1264 "apb", <<
1265 "mac_ma <<
1266 "ptp_re <<
1267 "rmii_i <<
1268 "mac_cg <<
1269 clocks = <&pericfg_ao <<
1270 <&pericfg_ao <<
1271 <&topckgen C <<
1272 <&topckgen C <<
1273 <&topckgen C <<
1274 <&pericfg_ao <<
1275 assigned-clocks = <&t <<
1276 <&t <<
1277 <&t <<
1278 assigned-clock-parent <<
1279 <<
1280 <<
1281 power-domains = <&spm <<
1282 mediatek,pericfg = <& <<
1283 snps,axi-config = <&s <<
1284 snps,mtl-rx-config = <<
1285 snps,mtl-tx-config = <<
1286 snps,txpbl = <16>; <<
1287 snps,rxpbl = <16>; <<
1288 snps,clk-csr = <0>; <<
1289 status = "disabled"; <<
1290 <<
1291 mdio { <<
1292 compatible = <<
1293 #address-cell <<
1294 #size-cells = <<
1295 }; <<
1296 <<
1297 stmmac_axi_setup: stm <<
1298 snps,wr_osr_l <<
1299 snps,rd_osr_l <<
1300 snps,blen = < <<
1301 }; <<
1302 <<
1303 mtl_rx_setup: rx-queu <<
1304 snps,rx-queue <<
1305 snps,rx-sched <<
1306 queue0 { <<
1307 snps, <<
1308 snps, <<
1309 }; <<
1310 queue1 { <<
1311 snps, <<
1312 snps, <<
1313 }; <<
1314 queue2 { <<
1315 snps, <<
1316 snps, <<
1317 }; <<
1318 queue3 { <<
1319 snps, <<
1320 snps, <<
1321 }; <<
1322 }; <<
1323 <<
1324 mtl_tx_setup: tx-queu <<
1325 snps,tx-queue <<
1326 snps,tx-sched <<
1327 queue0 { <<
1328 snps, <<
1329 snps, <<
1330 snps, <<
1331 }; <<
1332 queue1 { <<
1333 snps, <<
1334 snps, <<
1335 snps, <<
1336 }; <<
1337 queue2 { <<
1338 snps, <<
1339 snps, <<
1340 snps, <<
1341 }; <<
1342 queue3 { <<
1343 snps, <<
1344 snps, <<
1345 snps, <<
1346 }; <<
1347 }; <<
1348 }; <<
1349 <<
1350 ssusb0: usb@11201000 { <<
1351 compatible = "mediate <<
1352 reg = <0 0x11201000 0 <<
1353 reg-names = "mac", "i 1061 reg-names = "mac", "ippc";
1354 ranges = <0 0 0 0x112 !! 1062 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1355 #address-cells = <2>; !! 1063 phys = <&u2port0 PHY_TYPE_USB2>,
1356 #size-cells = <2>; !! 1064 <&u3port0 PHY_TYPE_USB3>;
1357 interrupts = <GIC_SPI !! 1065 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
>> 1066 <&topckgen CLK_TOP_SSUSB_XHCI>;
>> 1067 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
>> 1068 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1358 clocks = <&infracfg_a 1069 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen C 1070 <&topckgen CLK_TOP_SSUSB_REF>,
>> 1071 <&apmixedsys CLK_APMIXED_USB1PLL>,
>> 1072 <&clk26m>,
1360 <&infracfg_a 1073 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1361 clock-names = "sys_ck !! 1074 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1362 phys = <&u2port0 PHY_ !! 1075 "xhci_ck";
1363 wakeup-source; <<
1364 mediatek,syscon-wakeu 1076 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
>> 1077 wakeup-source;
1365 status = "disabled"; 1078 status = "disabled";
1366 <<
1367 xhci0: usb@0 { <<
1368 compatible = <<
1369 reg = <0 0 0 <<
1370 reg-names = " <<
1371 interrupts = <<
1372 assigned-cloc <<
1373 <<
1374 assigned-cloc <<
1375 <<
1376 clocks = <&in <<
1377 <&to <<
1378 <&ap <<
1379 <&cl <<
1380 <&in <<
1381 clock-names = <<
1382 status = "dis <<
1383 }; <<
1384 }; 1079 };
1385 1080
1386 mmc0: mmc@11230000 { 1081 mmc0: mmc@11230000 {
1387 compatible = "mediate 1082 compatible = "mediatek,mt8195-mmc",
1388 "mediate 1083 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 1084 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 1085 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 1086 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen C 1087 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_a 1088 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_a 1089 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source 1090 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled"; 1091 status = "disabled";
1397 }; 1092 };
1398 1093
1399 mmc1: mmc@11240000 { 1094 mmc1: mmc@11240000 {
1400 compatible = "mediate 1095 compatible = "mediatek,mt8195-mmc",
1401 "mediate 1096 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 1097 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 1098 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 1099 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen C 1100 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_a 1101 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_a 1102 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source 1103 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&t 1104 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parent 1105 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled"; 1106 status = "disabled";
1412 }; 1107 };
1413 1108
1414 mmc2: mmc@11250000 { 1109 mmc2: mmc@11250000 {
1415 compatible = "mediate 1110 compatible = "mediatek,mt8195-mmc",
1416 "mediate 1111 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 1112 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 1113 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 1114 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen C 1115 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_a 1116 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_a 1117 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source 1118 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&t 1119 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parent 1120 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled"; 1121 status = "disabled";
1427 }; 1122 };
1428 1123
1429 lvts_mcu: thermal-sensor@1127 <<
1430 compatible = "mediate <<
1431 reg = <0 0x11278000 0 <<
1432 interrupts = <GIC_SPI <<
1433 clocks = <&infracfg_a <<
1434 resets = <&infracfg_a <<
1435 nvmem-cells = <&lvts_ <<
1436 nvmem-cell-names = "l <<
1437 #thermal-sensor-cells <<
1438 }; <<
1439 <<
1440 xhci1: usb@11290000 { 1124 xhci1: usb@11290000 {
1441 compatible = "mediate 1125 compatible = "mediatek,mt8195-xhci",
1442 "mediate 1126 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 1127 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 1128 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "i 1129 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 1130 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_ !! 1131 phys = <&u2port1 PHY_TYPE_USB2>;
1448 assigned-clocks = <&t 1132 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&t 1133 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parent 1134 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 1135 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao 1136 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen C 1137 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys 1138 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>, 1139 <&clk26m>,
1456 <&pericfg_ao 1140 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck 1141 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_c 1142 "xhci_ck";
1459 mediatek,syscon-wakeu 1143 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source; 1144 wakeup-source;
1461 status = "disabled"; 1145 status = "disabled";
1462 }; 1146 };
1463 1147
1464 ssusb2: usb@112a1000 { !! 1148 xhci2: usb@112a0000 {
1465 compatible = "mediate !! 1149 compatible = "mediatek,mt8195-xhci",
1466 reg = <0 0x112a1000 0 !! 1150 "mediatek,mtk-xhci";
>> 1151 reg = <0 0x112a0000 0 0x1000>,
>> 1152 <0 0x112a3e00 0 0x0100>;
1467 reg-names = "mac", "i 1153 reg-names = "mac", "ippc";
1468 ranges = <0 0 0 0x112 !! 1154 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1469 #address-cells = <2>; !! 1155 phys = <&u2port2 PHY_TYPE_USB2>;
1470 #size-cells = <2>; !! 1156 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1471 interrupts = <GIC_SPI !! 1157 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1472 assigned-clocks = <&t !! 1158 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1473 assigned-clock-parent !! 1159 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1474 clocks = <&pericfg_ao 1160 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen C 1161 <&topckgen CLK_TOP_SSUSB_P2_REF>,
>> 1162 <&clk26m>,
>> 1163 <&clk26m>,
1476 <&pericfg_ao 1164 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1477 clock-names = "sys_ck !! 1165 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1478 phys = <&u2port2 PHY_ !! 1166 "xhci_ck";
1479 wakeup-source; <<
1480 mediatek,syscon-wakeu 1167 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
>> 1168 wakeup-source;
1481 status = "disabled"; 1169 status = "disabled";
1482 <<
1483 xhci2: usb@0 { <<
1484 compatible = <<
1485 reg = <0 0 0 <<
1486 reg-names = " <<
1487 interrupts = <<
1488 assigned-cloc <<
1489 assigned-cloc <<
1490 clocks = <&pe <<
1491 clock-names = <<
1492 status = "dis <<
1493 }; <<
1494 }; 1170 };
1495 1171
1496 ssusb3: usb@112b1000 { !! 1172 xhci3: usb@112b0000 {
1497 compatible = "mediate !! 1173 compatible = "mediatek,mt8195-xhci",
1498 reg = <0 0x112b1000 0 !! 1174 "mediatek,mtk-xhci";
>> 1175 reg = <0 0x112b0000 0 0x1000>,
>> 1176 <0 0x112b3e00 0 0x0100>;
1499 reg-names = "mac", "i 1177 reg-names = "mac", "ippc";
1500 ranges = <0 0 0 0x112 !! 1178 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1501 #address-cells = <2>; !! 1179 phys = <&u2port3 PHY_TYPE_USB2>;
1502 #size-cells = <2>; !! 1180 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1503 interrupts = <GIC_SPI !! 1181 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1504 assigned-clocks = <&t !! 1182 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1505 assigned-clock-parent !! 1183 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clocks = <&pericfg_ao 1184 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen C 1185 <&topckgen CLK_TOP_SSUSB_P3_REF>,
>> 1186 <&clk26m>,
>> 1187 <&clk26m>,
1508 <&pericfg_ao 1188 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1509 clock-names = "sys_ck !! 1189 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1510 phys = <&u2port3 PHY_ !! 1190 "xhci_ck";
1511 wakeup-source; <<
1512 mediatek,syscon-wakeu 1191 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
>> 1192 wakeup-source;
1513 status = "disabled"; 1193 status = "disabled";
1514 <<
1515 xhci3: usb@0 { <<
1516 compatible = <<
1517 reg = <0 0 0 <<
1518 reg-names = " <<
1519 interrupts = <<
1520 assigned-cloc <<
1521 assigned-cloc <<
1522 clocks = <&pe <<
1523 clock-names = <<
1524 status = "dis <<
1525 }; <<
1526 }; <<
1527 <<
1528 pcie0: pcie@112f0000 { <<
1529 compatible = "mediate <<
1530 "mediate <<
1531 device_type = "pci"; <<
1532 #address-cells = <3>; <<
1533 #size-cells = <2>; <<
1534 reg = <0 0x112f0000 0 <<
1535 reg-names = "pcie-mac <<
1536 interrupts = <GIC_SPI <<
1537 bus-range = <0x00 0xf <<
1538 ranges = <0x81000000 <<
1539 0x0 0x20000 <<
1540 <0x82000000 <<
1541 0x0 0x20200 <<
1542 <<
1543 iommu-map = <0 &iommu <<
1544 iommu-map-mask = <0x0 <<
1545 <<
1546 clocks = <&infracfg_a <<
1547 <&infracfg_a <<
1548 <&infracfg_a <<
1549 <&infracfg_a <<
1550 <&infracfg_a <<
1551 <&pericfg_ao <<
1552 clock-names = "pl_250 <<
1553 "tl_32k <<
1554 assigned-clocks = <&t <<
1555 assigned-clock-parent <<
1556 <<
1557 phys = <&pciephy>; <<
1558 phy-names = "pcie-phy <<
1559 <<
1560 power-domains = <&spm <<
1561 <<
1562 resets = <&infracfg_a <<
1563 reset-names = "mac"; <<
1564 <<
1565 #interrupt-cells = <1 <<
1566 interrupt-map-mask = <<
1567 interrupt-map = <0 0 <<
1568 <0 0 <<
1569 <0 0 <<
1570 <0 0 <<
1571 status = "disabled"; <<
1572 <<
1573 pcie_intc0: interrupt <<
1574 interrupt-con <<
1575 #address-cell <<
1576 #interrupt-ce <<
1577 }; <<
1578 }; <<
1579 <<
1580 pcie1: pcie@112f8000 { <<
1581 compatible = "mediate <<
1582 "mediate <<
1583 device_type = "pci"; <<
1584 #address-cells = <3>; <<
1585 #size-cells = <2>; <<
1586 reg = <0 0x112f8000 0 <<
1587 reg-names = "pcie-mac <<
1588 interrupts = <GIC_SPI <<
1589 bus-range = <0x00 0xf <<
1590 ranges = <0x81000000 <<
1591 0x0 0x24000 <<
1592 <0x82000000 <<
1593 0x0 0x24200 <<
1594 <<
1595 iommu-map = <0 &iommu <<
1596 iommu-map-mask = <0x0 <<
1597 <<
1598 clocks = <&infracfg_a <<
1599 <&clk26m>, <<
1600 <&infracfg_a <<
1601 <&clk26m>, <<
1602 <&infracfg_a <<
1603 /* Designer <<
1604 <&pericfg_ao <<
1605 clock-names = "pl_250 <<
1606 "tl_32k <<
1607 assigned-clocks = <&t <<
1608 assigned-clock-parent <<
1609 <<
1610 phys = <&u3port1 PHY_ <<
1611 phy-names = "pcie-phy <<
1612 power-domains = <&spm <<
1613 <<
1614 resets = <&infracfg_a <<
1615 reset-names = "mac"; <<
1616 <<
1617 #interrupt-cells = <1 <<
1618 interrupt-map-mask = <<
1619 interrupt-map = <0 0 <<
1620 <0 0 <<
1621 <0 0 <<
1622 <0 0 <<
1623 status = "disabled"; <<
1624 <<
1625 pcie_intc1: interrupt <<
1626 interrupt-con <<
1627 #address-cell <<
1628 #interrupt-ce <<
1629 }; <<
1630 }; 1194 };
1631 1195
1632 nor_flash: spi@1132c000 { 1196 nor_flash: spi@1132c000 {
1633 compatible = "mediate 1197 compatible = "mediatek,mt8195-nor",
1634 "mediate 1198 "mediatek,mt8173-nor";
1635 reg = <0 0x1132c000 0 1199 reg = <0 0x1132c000 0 0x1000>;
1636 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1637 clocks = <&topckgen C 1201 clocks = <&topckgen CLK_TOP_SPINOR>,
1638 <&pericfg_ao 1202 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1639 <&pericfg_ao 1203 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1640 clock-names = "spi", 1204 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>; 1205 #address-cells = <1>;
1642 #size-cells = <0>; 1206 #size-cells = <0>;
1643 status = "disabled"; 1207 status = "disabled";
1644 }; 1208 };
1645 1209
1646 efuse: efuse@11c10000 { 1210 efuse: efuse@11c10000 {
1647 compatible = "mediate 1211 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1648 reg = <0 0x11c10000 0 1212 reg = <0 0x11c10000 0 0x1000>;
1649 #address-cells = <1>; 1213 #address-cells = <1>;
1650 #size-cells = <1>; 1214 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx 1215 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 reg = <0x184 1216 reg = <0x184 0x1>;
1653 bits = <0 5>; 1217 bits = <0 5>;
1654 }; 1218 };
1655 u3_rx_imp_p0: usb3-rx 1219 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 reg = <0x184 1220 reg = <0x184 0x2>;
1657 bits = <5 5>; 1221 bits = <5 5>;
1658 }; 1222 };
1659 u3_intr_p0: usb3-intr 1223 u3_intr_p0: usb3-intr@185 {
1660 reg = <0x185 1224 reg = <0x185 0x1>;
1661 bits = <2 6>; 1225 bits = <2 6>;
1662 }; 1226 };
1663 comb_tx_imp_p1: usb3- 1227 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 reg = <0x186 1228 reg = <0x186 0x1>;
1665 bits = <0 5>; 1229 bits = <0 5>;
1666 }; 1230 };
1667 comb_rx_imp_p1: usb3- 1231 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 reg = <0x186 1232 reg = <0x186 0x2>;
1669 bits = <5 5>; 1233 bits = <5 5>;
1670 }; 1234 };
1671 comb_intr_p1: usb3-in 1235 comb_intr_p1: usb3-intr@187 {
1672 reg = <0x187 1236 reg = <0x187 0x1>;
1673 bits = <2 6>; 1237 bits = <2 6>;
1674 }; 1238 };
1675 u2_intr_p0: usb2-intr 1239 u2_intr_p0: usb2-intr-p0@188,1 {
1676 reg = <0x188 1240 reg = <0x188 0x1>;
1677 bits = <0 5>; 1241 bits = <0 5>;
1678 }; 1242 };
1679 u2_intr_p1: usb2-intr 1243 u2_intr_p1: usb2-intr-p1@188,2 {
1680 reg = <0x188 1244 reg = <0x188 0x2>;
1681 bits = <5 5>; 1245 bits = <5 5>;
1682 }; 1246 };
1683 u2_intr_p2: usb2-intr 1247 u2_intr_p2: usb2-intr-p2@189,1 {
1684 reg = <0x189 1248 reg = <0x189 0x1>;
1685 bits = <2 5>; 1249 bits = <2 5>;
1686 }; 1250 };
1687 u2_intr_p3: usb2-intr 1251 u2_intr_p3: usb2-intr-p3@189,2 {
1688 reg = <0x189 1252 reg = <0x189 0x2>;
1689 bits = <7 5>; 1253 bits = <7 5>;
1690 }; 1254 };
1691 pciephy_rx_ln1: pciep <<
1692 reg = <0x190 <<
1693 bits = <0 4>; <<
1694 }; <<
1695 pciephy_tx_ln1_nmos: <<
1696 reg = <0x190 <<
1697 bits = <4 4>; <<
1698 }; <<
1699 pciephy_tx_ln1_pmos: <<
1700 reg = <0x191 <<
1701 bits = <0 4>; <<
1702 }; <<
1703 pciephy_rx_ln0: pciep <<
1704 reg = <0x191 <<
1705 bits = <4 4>; <<
1706 }; <<
1707 pciephy_tx_ln0_nmos: <<
1708 reg = <0x192 <<
1709 bits = <0 4>; <<
1710 }; <<
1711 pciephy_tx_ln0_pmos: <<
1712 reg = <0x192 <<
1713 bits = <4 4>; <<
1714 }; <<
1715 pciephy_glb_intr: pci <<
1716 reg = <0x193 <<
1717 bits = <0 4>; <<
1718 }; <<
1719 dp_calibration: dp-da <<
1720 reg = <0x1ac <<
1721 }; <<
1722 lvts_efuse_data1: lvt <<
1723 reg = <0x1bc <<
1724 }; <<
1725 lvts_efuse_data2: lvt <<
1726 reg = <0x1d0 <<
1727 }; <<
1728 svs_calib_data: svs-c <<
1729 reg = <0x580 <<
1730 }; <<
1731 socinfo-data1@7a0 { <<
1732 reg = <0x7a0 <<
1733 }; <<
1734 }; 1255 };
1735 1256
1736 u3phy2: t-phy@11c40000 { 1257 u3phy2: t-phy@11c40000 {
1737 compatible = "mediate 1258 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>; 1259 #address-cells = <1>;
1739 #size-cells = <1>; 1260 #size-cells = <1>;
1740 ranges = <0 0 0x11c40 1261 ranges = <0 0 0x11c40000 0x700>;
1741 status = "disabled"; 1262 status = "disabled";
1742 1263
1743 u2port2: usb-phy@0 { 1264 u2port2: usb-phy@0 {
1744 reg = <0x0 0x 1265 reg = <0x0 0x700>;
1745 clocks = <&to 1266 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1746 clock-names = 1267 clock-names = "ref";
1747 #phy-cells = 1268 #phy-cells = <1>;
1748 }; 1269 };
1749 }; 1270 };
1750 1271
1751 u3phy3: t-phy@11c50000 { 1272 u3phy3: t-phy@11c50000 {
1752 compatible = "mediate 1273 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>; 1274 #address-cells = <1>;
1754 #size-cells = <1>; 1275 #size-cells = <1>;
1755 ranges = <0 0 0x11c50 1276 ranges = <0 0 0x11c50000 0x700>;
1756 status = "disabled"; 1277 status = "disabled";
1757 1278
1758 u2port3: usb-phy@0 { 1279 u2port3: usb-phy@0 {
1759 reg = <0x0 0x 1280 reg = <0x0 0x700>;
1760 clocks = <&to 1281 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1761 clock-names = 1282 clock-names = "ref";
1762 #phy-cells = 1283 #phy-cells = <1>;
1763 }; 1284 };
1764 }; 1285 };
1765 1286
1766 mipi_tx0: dsi-phy@11c80000 { <<
1767 compatible = "mediate <<
1768 reg = <0 0x11c80000 0 <<
1769 clocks = <&clk26m>; <<
1770 clock-output-names = <<
1771 #clock-cells = <0>; <<
1772 #phy-cells = <0>; <<
1773 status = "disabled"; <<
1774 }; <<
1775 <<
1776 mipi_tx1: dsi-phy@11c90000 { <<
1777 compatible = "mediate <<
1778 reg = <0 0x11c90000 0 <<
1779 clocks = <&clk26m>; <<
1780 clock-output-names = <<
1781 #clock-cells = <0>; <<
1782 #phy-cells = <0>; <<
1783 status = "disabled"; <<
1784 }; <<
1785 <<
1786 i2c5: i2c@11d00000 { 1287 i2c5: i2c@11d00000 {
1787 compatible = "mediate 1288 compatible = "mediatek,mt8195-i2c",
1788 "mediate 1289 "mediatek,mt8192-i2c";
1789 reg = <0 0x11d00000 0 1290 reg = <0 0x11d00000 0 0x1000>,
1790 <0 0x10220580 0 1291 <0 0x10220580 0 0x80>;
1791 interrupts = <GIC_SPI 1292 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1792 clock-div = <1>; 1293 clock-div = <1>;
1793 clocks = <&imp_iic_wr 1294 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1794 <&infracfg_a 1295 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795 clock-names = "main", 1296 clock-names = "main", "dma";
1796 #address-cells = <1>; 1297 #address-cells = <1>;
1797 #size-cells = <0>; 1298 #size-cells = <0>;
1798 status = "disabled"; 1299 status = "disabled";
1799 }; 1300 };
1800 1301
1801 i2c6: i2c@11d01000 { 1302 i2c6: i2c@11d01000 {
1802 compatible = "mediate 1303 compatible = "mediatek,mt8195-i2c",
1803 "mediate 1304 "mediatek,mt8192-i2c";
1804 reg = <0 0x11d01000 0 1305 reg = <0 0x11d01000 0 0x1000>,
1805 <0 0x10220600 0 1306 <0 0x10220600 0 0x80>;
1806 interrupts = <GIC_SPI 1307 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1807 clock-div = <1>; 1308 clock-div = <1>;
1808 clocks = <&imp_iic_wr 1309 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1809 <&infracfg_a 1310 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1810 clock-names = "main", 1311 clock-names = "main", "dma";
1811 #address-cells = <1>; 1312 #address-cells = <1>;
1812 #size-cells = <0>; 1313 #size-cells = <0>;
1813 status = "disabled"; 1314 status = "disabled";
1814 }; 1315 };
1815 1316
1816 i2c7: i2c@11d02000 { 1317 i2c7: i2c@11d02000 {
1817 compatible = "mediate 1318 compatible = "mediatek,mt8195-i2c",
1818 "mediate 1319 "mediatek,mt8192-i2c";
1819 reg = <0 0x11d02000 0 1320 reg = <0 0x11d02000 0 0x1000>,
1820 <0 0x10220680 0 1321 <0 0x10220680 0 0x80>;
1821 interrupts = <GIC_SPI 1322 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1822 clock-div = <1>; 1323 clock-div = <1>;
1823 clocks = <&imp_iic_wr 1324 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1824 <&infracfg_a 1325 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1825 clock-names = "main", 1326 clock-names = "main", "dma";
1826 #address-cells = <1>; 1327 #address-cells = <1>;
1827 #size-cells = <0>; 1328 #size-cells = <0>;
1828 status = "disabled"; 1329 status = "disabled";
1829 }; 1330 };
1830 1331
1831 imp_iic_wrap_s: clock-control 1332 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediate 1333 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1833 reg = <0 0x11d03000 0 1334 reg = <0 0x11d03000 0 0x1000>;
1834 #clock-cells = <1>; 1335 #clock-cells = <1>;
1835 }; 1336 };
1836 1337
1837 i2c0: i2c@11e00000 { 1338 i2c0: i2c@11e00000 {
1838 compatible = "mediate 1339 compatible = "mediatek,mt8195-i2c",
1839 "mediate 1340 "mediatek,mt8192-i2c";
1840 reg = <0 0x11e00000 0 1341 reg = <0 0x11e00000 0 0x1000>,
1841 <0 0x10220080 0 1342 <0 0x10220080 0 0x80>;
1842 interrupts = <GIC_SPI 1343 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1843 clock-div = <1>; 1344 clock-div = <1>;
1844 clocks = <&imp_iic_wr 1345 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1845 <&infracfg_a 1346 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846 clock-names = "main", 1347 clock-names = "main", "dma";
1847 #address-cells = <1>; 1348 #address-cells = <1>;
1848 #size-cells = <0>; 1349 #size-cells = <0>;
1849 status = "disabled"; 1350 status = "disabled";
1850 }; 1351 };
1851 1352
1852 i2c1: i2c@11e01000 { 1353 i2c1: i2c@11e01000 {
1853 compatible = "mediate 1354 compatible = "mediatek,mt8195-i2c",
1854 "mediate 1355 "mediatek,mt8192-i2c";
1855 reg = <0 0x11e01000 0 1356 reg = <0 0x11e01000 0 0x1000>,
1856 <0 0x10220200 0 1357 <0 0x10220200 0 0x80>;
1857 interrupts = <GIC_SPI 1358 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clock-div = <1>; 1359 clock-div = <1>;
1859 clocks = <&imp_iic_wr 1360 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1860 <&infracfg_a 1361 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861 clock-names = "main", 1362 clock-names = "main", "dma";
1862 #address-cells = <1>; 1363 #address-cells = <1>;
1863 #size-cells = <0>; 1364 #size-cells = <0>;
1864 status = "disabled"; 1365 status = "disabled";
1865 }; 1366 };
1866 1367
1867 i2c2: i2c@11e02000 { 1368 i2c2: i2c@11e02000 {
1868 compatible = "mediate 1369 compatible = "mediatek,mt8195-i2c",
1869 "mediate 1370 "mediatek,mt8192-i2c";
1870 reg = <0 0x11e02000 0 1371 reg = <0 0x11e02000 0 0x1000>,
1871 <0 0x10220380 0 1372 <0 0x10220380 0 0x80>;
1872 interrupts = <GIC_SPI 1373 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1873 clock-div = <1>; 1374 clock-div = <1>;
1874 clocks = <&imp_iic_wr 1375 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1875 <&infracfg_a 1376 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876 clock-names = "main", 1377 clock-names = "main", "dma";
1877 #address-cells = <1>; 1378 #address-cells = <1>;
1878 #size-cells = <0>; 1379 #size-cells = <0>;
1879 status = "disabled"; 1380 status = "disabled";
1880 }; 1381 };
1881 1382
1882 i2c3: i2c@11e03000 { 1383 i2c3: i2c@11e03000 {
1883 compatible = "mediate 1384 compatible = "mediatek,mt8195-i2c",
1884 "mediate 1385 "mediatek,mt8192-i2c";
1885 reg = <0 0x11e03000 0 1386 reg = <0 0x11e03000 0 0x1000>,
1886 <0 0x10220480 0 1387 <0 0x10220480 0 0x80>;
1887 interrupts = <GIC_SPI 1388 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clock-div = <1>; 1389 clock-div = <1>;
1889 clocks = <&imp_iic_wr 1390 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1890 <&infracfg_a 1391 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1891 clock-names = "main", 1392 clock-names = "main", "dma";
1892 #address-cells = <1>; 1393 #address-cells = <1>;
1893 #size-cells = <0>; 1394 #size-cells = <0>;
1894 status = "disabled"; 1395 status = "disabled";
1895 }; 1396 };
1896 1397
1897 i2c4: i2c@11e04000 { 1398 i2c4: i2c@11e04000 {
1898 compatible = "mediate 1399 compatible = "mediatek,mt8195-i2c",
1899 "mediate 1400 "mediatek,mt8192-i2c";
1900 reg = <0 0x11e04000 0 1401 reg = <0 0x11e04000 0 0x1000>,
1901 <0 0x10220500 0 1402 <0 0x10220500 0 0x80>;
1902 interrupts = <GIC_SPI 1403 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1903 clock-div = <1>; 1404 clock-div = <1>;
1904 clocks = <&imp_iic_wr 1405 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1905 <&infracfg_a 1406 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1906 clock-names = "main", 1407 clock-names = "main", "dma";
1907 #address-cells = <1>; 1408 #address-cells = <1>;
1908 #size-cells = <0>; 1409 #size-cells = <0>;
1909 status = "disabled"; 1410 status = "disabled";
1910 }; 1411 };
1911 1412
1912 imp_iic_wrap_w: clock-control 1413 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediate 1414 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1914 reg = <0 0x11e05000 0 1415 reg = <0 0x11e05000 0 0x1000>;
1915 #clock-cells = <1>; 1416 #clock-cells = <1>;
1916 }; 1417 };
1917 1418
1918 u3phy1: t-phy@11e30000 { 1419 u3phy1: t-phy@11e30000 {
1919 compatible = "mediate 1420 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>; 1421 #address-cells = <1>;
1921 #size-cells = <1>; 1422 #size-cells = <1>;
1922 ranges = <0 0 0x11e30 1423 ranges = <0 0 0x11e30000 0xe00>;
1923 power-domains = <&spm 1424 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1924 status = "disabled"; 1425 status = "disabled";
1925 1426
1926 u2port1: usb-phy@0 { 1427 u2port1: usb-phy@0 {
1927 reg = <0x0 0x 1428 reg = <0x0 0x700>;
1928 clocks = <&to 1429 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1929 <&cl 1430 <&clk26m>;
1930 clock-names = 1431 clock-names = "ref", "da_ref";
1931 #phy-cells = 1432 #phy-cells = <1>;
1932 }; 1433 };
1933 1434
1934 u3port1: usb-phy@700 1435 u3port1: usb-phy@700 {
1935 reg = <0x700 1436 reg = <0x700 0x700>;
1936 clocks = <&ap 1437 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1937 <&to 1438 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1938 clock-names = 1439 clock-names = "ref", "da_ref";
1939 nvmem-cells = 1440 nvmem-cells = <&comb_intr_p1>,
1940 1441 <&comb_rx_imp_p1>,
1941 1442 <&comb_tx_imp_p1>;
1942 nvmem-cell-na 1443 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = 1444 #phy-cells = <1>;
1944 }; 1445 };
1945 }; 1446 };
1946 1447
1947 u3phy0: t-phy@11e40000 { 1448 u3phy0: t-phy@11e40000 {
1948 compatible = "mediate 1449 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>; 1450 #address-cells = <1>;
1950 #size-cells = <1>; 1451 #size-cells = <1>;
1951 ranges = <0 0 0x11e40 1452 ranges = <0 0 0x11e40000 0xe00>;
1952 status = "disabled"; 1453 status = "disabled";
1953 1454
1954 u2port0: usb-phy@0 { 1455 u2port0: usb-phy@0 {
1955 reg = <0x0 0x 1456 reg = <0x0 0x700>;
1956 clocks = <&to 1457 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1957 <&cl 1458 <&clk26m>;
1958 clock-names = 1459 clock-names = "ref", "da_ref";
1959 #phy-cells = 1460 #phy-cells = <1>;
1960 }; 1461 };
1961 1462
1962 u3port0: usb-phy@700 1463 u3port0: usb-phy@700 {
1963 reg = <0x700 1464 reg = <0x700 0x700>;
1964 clocks = <&ap 1465 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1965 <&to 1466 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1966 clock-names = 1467 clock-names = "ref", "da_ref";
1967 nvmem-cells = 1468 nvmem-cells = <&u3_intr_p0>,
1968 1469 <&u3_rx_imp_p0>,
1969 1470 <&u3_tx_imp_p0>;
1970 nvmem-cell-na 1471 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = 1472 #phy-cells = <1>;
1972 }; 1473 };
1973 }; 1474 };
1974 1475
1975 pciephy: phy@11e80000 { <<
1976 compatible = "mediate <<
1977 reg = <0 0x11e80000 0 <<
1978 reg-names = "sif"; <<
1979 nvmem-cells = <&pciep <<
1980 <&pciep <<
1981 <&pciep <<
1982 <&pciep <<
1983 nvmem-cell-names = "g <<
1984 "t <<
1985 "t <<
1986 "r <<
1987 power-domains = <&spm <<
1988 #phy-cells = <0>; <<
1989 status = "disabled"; <<
1990 }; <<
1991 <<
1992 ufsphy: ufs-phy@11fa0000 { 1476 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediate 1477 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1994 reg = <0 0x11fa0000 0 1478 reg = <0 0x11fa0000 0 0xc000>;
1995 clocks = <&clk26m>, < 1479 clocks = <&clk26m>, <&clk26m>;
1996 clock-names = "unipro 1480 clock-names = "unipro", "mp";
1997 #phy-cells = <0>; 1481 #phy-cells = <0>;
1998 status = "disabled"; 1482 status = "disabled";
1999 }; 1483 };
2000 1484
2001 gpu: gpu@13000000 { <<
2002 compatible = "mediate <<
2003 "arm,mal <<
2004 reg = <0 0x13000000 0 <<
2005 <<
2006 clocks = <&mfgcfg CLK <<
2007 interrupts = <GIC_SPI <<
2008 <GIC_SPI <<
2009 <GIC_SPI <<
2010 interrupt-names = "jo <<
2011 operating-points-v2 = <<
2012 power-domains = <&spm <<
2013 <&spm <<
2014 <&spm <<
2015 <&spm <<
2016 <&spm <<
2017 power-domain-names = <<
2018 status = "disabled"; <<
2019 }; <<
2020 <<
2021 mfgcfg: clock-controller@13fb 1485 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediate 1486 compatible = "mediatek,mt8195-mfgcfg";
2023 reg = <0 0x13fbf000 0 1487 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>; 1488 #clock-cells = <1>;
2025 }; 1489 };
2026 1490
2027 vppsys0: syscon@14000000 { !! 1491 vppsys0: clock-controller@14000000 {
2028 compatible = "mediate !! 1492 compatible = "mediatek,mt8195-vppsys0";
2029 reg = <0 0x14000000 0 1493 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>; 1494 #clock-cells = <1>;
2031 mediatek,gce-client-r 1495 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2032 }; 1496 };
2033 1497
2034 dma-controller@14001000 { <<
2035 compatible = "mediate <<
2036 reg = <0 0x14001000 0 <<
2037 mediatek,gce-client-r <<
2038 mediatek,gce-events = <<
2039 <<
2040 mediatek,scp = <&scp> <<
2041 power-domains = <&spm <<
2042 iommus = <&iommu_vpp <<
2043 clocks = <&vppsys0 CL <<
2044 mboxes = <&gce1 12 CM <<
2045 <&gce1 13 CM <<
2046 <&gce1 14 CM <<
2047 <&gce1 21 CM <<
2048 <&gce1 22 CM <<
2049 #dma-cells = <1>; <<
2050 }; <<
2051 <<
2052 display@14002000 { <<
2053 compatible = "mediate <<
2054 reg = <0 0x14002000 0 <<
2055 mediatek,gce-client-r <<
2056 clocks = <&vppsys0 CL <<
2057 }; <<
2058 <<
2059 display@14003000 { <<
2060 compatible = "mediate <<
2061 reg = <0 0x14003000 0 <<
2062 mediatek,gce-client-r <<
2063 clocks = <&vppsys0 CL <<
2064 }; <<
2065 <<
2066 display@14004000 { <<
2067 compatible = "mediate <<
2068 reg = <0 0x14004000 0 <<
2069 mediatek,gce-client-r <<
2070 clocks = <&vppsys0 CL <<
2071 }; <<
2072 <<
2073 display@14005000 { <<
2074 compatible = "mediate <<
2075 reg = <0 0x14005000 0 <<
2076 interrupts = <GIC_SPI <<
2077 mediatek,gce-client-r <<
2078 clocks = <&vppsys0 CL <<
2079 power-domains = <&spm <<
2080 }; <<
2081 <<
2082 display@14006000 { <<
2083 compatible = "mediate <<
2084 reg = <0 0x14006000 0 <<
2085 mediatek,gce-client-r <<
2086 mediatek,gce-events = <<
2087 <<
2088 clocks = <&vppsys0 CL <<
2089 }; <<
2090 <<
2091 display@14007000 { <<
2092 compatible = "mediate <<
2093 reg = <0 0x14007000 0 <<
2094 mediatek,gce-client-r <<
2095 clocks = <&vppsys0 CL <<
2096 }; <<
2097 <<
2098 display@14008000 { <<
2099 compatible = "mediate <<
2100 reg = <0 0x14008000 0 <<
2101 interrupts = <GIC_SPI <<
2102 mediatek,gce-client-r <<
2103 clocks = <&vppsys0 CL <<
2104 power-domains = <&spm <<
2105 }; <<
2106 <<
2107 display@14009000 { <<
2108 compatible = "mediate <<
2109 reg = <0 0x14009000 0 <<
2110 interrupts = <GIC_SPI <<
2111 mediatek,gce-client-r <<
2112 clocks = <&vppsys0 CL <<
2113 power-domains = <&spm <<
2114 iommus = <&iommu_vpp <<
2115 }; <<
2116 <<
2117 display@1400a000 { <<
2118 compatible = "mediate <<
2119 reg = <0 0x1400a000 0 <<
2120 mediatek,gce-client-r <<
2121 clocks = <&vppsys0 CL <<
2122 power-domains = <&spm <<
2123 }; <<
2124 <<
2125 display@1400b000 { <<
2126 compatible = "mediate <<
2127 reg = <0 0x1400b000 0 <<
2128 mediatek,gce-client-r <<
2129 clocks = <&vppsys0 CL <<
2130 }; <<
2131 <<
2132 dma-controller@1400c000 { <<
2133 compatible = "mediate <<
2134 reg = <0 0x1400c000 0 <<
2135 mediatek,gce-client-r <<
2136 mediatek,gce-events = <<
2137 <<
2138 clocks = <&vppsys0 CL <<
2139 iommus = <&iommu_vpp <<
2140 power-domains = <&spm <<
2141 #dma-cells = <1>; <<
2142 }; <<
2143 <<
2144 mutex@1400f000 { <<
2145 compatible = "mediate <<
2146 reg = <0 0x1400f000 0 <<
2147 interrupts = <GIC_SPI <<
2148 mediatek,gce-client-r <<
2149 clocks = <&vppsys0 CL <<
2150 power-domains = <&spm <<
2151 }; <<
2152 <<
2153 smi_sub_common_vpp0_vpp1_2x1: 1498 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2154 compatible = "mediate 1499 compatible = "mediatek,mt8195-smi-sub-common";
2155 reg = <0 0x14010000 0 1500 reg = <0 0x14010000 0 0x1000>;
2156 clocks = <&vppsys0 CL 1501 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_ 1502 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2158 <&vppsys0 CLK_ 1503 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2159 clock-names = "apb", 1504 clock-names = "apb", "smi", "gals0";
2160 mediatek,smi = <&smi_ 1505 mediatek,smi = <&smi_common_vpp>;
2161 power-domains = <&spm 1506 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2162 }; 1507 };
2163 1508
2164 smi_sub_common_vdec_vpp0_2x1: 1509 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2165 compatible = "mediate 1510 compatible = "mediatek,mt8195-smi-sub-common";
2166 reg = <0 0x14011000 0 1511 reg = <0 0x14011000 0 0x1000>;
2167 clocks = <&vppsys0 CL 1512 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CL 1513 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2169 <&vppsys0 CL 1514 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2170 clock-names = "apb", 1515 clock-names = "apb", "smi", "gals0";
2171 mediatek,smi = <&smi_ 1516 mediatek,smi = <&smi_common_vpp>;
2172 power-domains = <&spm 1517 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2173 }; 1518 };
2174 1519
2175 smi_common_vpp: smi@14012000 1520 smi_common_vpp: smi@14012000 {
2176 compatible = "mediate 1521 compatible = "mediatek,mt8195-smi-common-vpp";
2177 reg = <0 0x14012000 0 1522 reg = <0 0x14012000 0 0x1000>;
2178 clocks = <&vppsys0 CL 1523 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_ 1524 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2180 <&vppsys0 CLK_ 1525 <&vppsys0 CLK_VPP0_SMI_RSI>,
2181 <&vppsys0 CLK_ 1526 <&vppsys0 CLK_VPP0_SMI_RSI>;
2182 clock-names = "apb", 1527 clock-names = "apb", "smi", "gals0", "gals1";
2183 power-domains = <&spm 1528 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2184 }; 1529 };
2185 1530
2186 larb4: larb@14013000 { 1531 larb4: larb@14013000 {
2187 compatible = "mediate 1532 compatible = "mediatek,mt8195-smi-larb";
2188 reg = <0 0x14013000 0 1533 reg = <0 0x14013000 0 0x1000>;
2189 mediatek,larb-id = <4 1534 mediatek,larb-id = <4>;
2190 mediatek,smi = <&smi_ 1535 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2191 clocks = <&vppsys0 CL 1536 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2192 <&vppsys0 CLK_ 1537 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2193 clock-names = "apb", 1538 clock-names = "apb", "smi";
2194 power-domains = <&spm 1539 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2195 }; 1540 };
2196 1541
2197 iommu_vpp: iommu@14018000 { 1542 iommu_vpp: iommu@14018000 {
2198 compatible = "mediate 1543 compatible = "mediatek,mt8195-iommu-vpp";
2199 reg = <0 0x14018000 0 1544 reg = <0 0x14018000 0 0x1000>;
2200 mediatek,larbs = <&la 1545 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2201 &la 1546 &larb12 &larb14 &larb16 &larb18
2202 &la 1547 &larb20 &larb22 &larb23 &larb26
2203 &la 1548 &larb27>;
2204 interrupts = <GIC_SPI 1549 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2205 clocks = <&vppsys0 CL 1550 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2206 clock-names = "bclk"; 1551 clock-names = "bclk";
2207 #iommu-cells = <1>; 1552 #iommu-cells = <1>;
2208 power-domains = <&spm 1553 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2209 }; 1554 };
2210 1555
2211 wpesys: clock-controller@14e0 1556 wpesys: clock-controller@14e00000 {
2212 compatible = "mediate 1557 compatible = "mediatek,mt8195-wpesys";
2213 reg = <0 0x14e00000 0 1558 reg = <0 0x14e00000 0 0x1000>;
2214 #clock-cells = <1>; 1559 #clock-cells = <1>;
2215 }; 1560 };
2216 1561
2217 wpesys_vpp0: clock-controller 1562 wpesys_vpp0: clock-controller@14e02000 {
2218 compatible = "mediate 1563 compatible = "mediatek,mt8195-wpesys_vpp0";
2219 reg = <0 0x14e02000 0 1564 reg = <0 0x14e02000 0 0x1000>;
2220 #clock-cells = <1>; 1565 #clock-cells = <1>;
2221 }; 1566 };
2222 1567
2223 wpesys_vpp1: clock-controller 1568 wpesys_vpp1: clock-controller@14e03000 {
2224 compatible = "mediate 1569 compatible = "mediatek,mt8195-wpesys_vpp1";
2225 reg = <0 0x14e03000 0 1570 reg = <0 0x14e03000 0 0x1000>;
2226 #clock-cells = <1>; 1571 #clock-cells = <1>;
2227 }; 1572 };
2228 1573
2229 larb7: larb@14e04000 { 1574 larb7: larb@14e04000 {
2230 compatible = "mediate 1575 compatible = "mediatek,mt8195-smi-larb";
2231 reg = <0 0x14e04000 0 1576 reg = <0 0x14e04000 0 0x1000>;
2232 mediatek,larb-id = <7 1577 mediatek,larb-id = <7>;
2233 mediatek,smi = <&smi_ 1578 mediatek,smi = <&smi_common_vdo>;
2234 clocks = <&wpesys CLK 1579 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2235 <&wpesys CLK 1580 <&wpesys CLK_WPE_SMI_LARB7>;
2236 clock-names = "apb", 1581 clock-names = "apb", "smi";
2237 power-domains = <&spm 1582 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2238 }; 1583 };
2239 1584
2240 larb8: larb@14e05000 { 1585 larb8: larb@14e05000 {
2241 compatible = "mediate 1586 compatible = "mediatek,mt8195-smi-larb";
2242 reg = <0 0x14e05000 0 1587 reg = <0 0x14e05000 0 0x1000>;
2243 mediatek,larb-id = <8 1588 mediatek,larb-id = <8>;
2244 mediatek,smi = <&smi_ 1589 mediatek,smi = <&smi_common_vpp>;
2245 clocks = <&wpesys CLK 1590 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2246 <&wpesys CLK_W 1591 <&wpesys CLK_WPE_SMI_LARB8>,
2247 <&vppsys0 CLK_ 1592 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2248 clock-names = "apb", 1593 clock-names = "apb", "smi", "gals";
2249 power-domains = <&spm 1594 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2250 }; 1595 };
2251 1596
2252 vppsys1: syscon@14f00000 { !! 1597 vppsys1: clock-controller@14f00000 {
2253 compatible = "mediate !! 1598 compatible = "mediatek,mt8195-vppsys1";
2254 reg = <0 0x14f00000 0 1599 reg = <0 0x14f00000 0 0x1000>;
2255 #clock-cells = <1>; 1600 #clock-cells = <1>;
2256 mediatek,gce-client-r 1601 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2257 }; 1602 };
2258 1603
2259 mutex@14f01000 { <<
2260 compatible = "mediate <<
2261 reg = <0 0x14f01000 0 <<
2262 interrupts = <GIC_SPI <<
2263 mediatek,gce-client-r <<
2264 clocks = <&vppsys1 CL <<
2265 power-domains = <&spm <<
2266 }; <<
2267 <<
2268 larb5: larb@14f02000 { 1604 larb5: larb@14f02000 {
2269 compatible = "mediate 1605 compatible = "mediatek,mt8195-smi-larb";
2270 reg = <0 0x14f02000 0 1606 reg = <0 0x14f02000 0 0x1000>;
2271 mediatek,larb-id = <5 1607 mediatek,larb-id = <5>;
2272 mediatek,smi = <&smi_ 1608 mediatek,smi = <&smi_common_vdo>;
2273 clocks = <&vppsys1 CL 1609 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2274 <&vppsys1 CLK_ 1610 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2275 <&vppsys0 CLK_ 1611 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2276 clock-names = "apb", 1612 clock-names = "apb", "smi", "gals";
2277 power-domains = <&spm 1613 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2278 }; 1614 };
2279 1615
2280 larb6: larb@14f03000 { 1616 larb6: larb@14f03000 {
2281 compatible = "mediate 1617 compatible = "mediatek,mt8195-smi-larb";
2282 reg = <0 0x14f03000 0 1618 reg = <0 0x14f03000 0 0x1000>;
2283 mediatek,larb-id = <6 1619 mediatek,larb-id = <6>;
2284 mediatek,smi = <&smi_ 1620 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2285 clocks = <&vppsys1 CL 1621 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2286 <&vppsys1 CLK_ 1622 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2287 <&vppsys0 CLK_ 1623 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2288 clock-names = "apb", 1624 clock-names = "apb", "smi", "gals";
2289 power-domains = <&spm 1625 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2290 }; 1626 };
2291 1627
2292 display@14f06000 { <<
2293 compatible = "mediate <<
2294 reg = <0 0x14f06000 0 <<
2295 mediatek,gce-client-r <<
2296 clocks = <&vppsys1 CL <<
2297 <&vppsys1 CL <<
2298 <&vppsys1 CL <<
2299 power-domains = <&spm <<
2300 }; <<
2301 <<
2302 display@14f07000 { <<
2303 compatible = "mediate <<
2304 reg = <0 0x14f07000 0 <<
2305 mediatek,gce-client-r <<
2306 clocks = <&vppsys1 CL <<
2307 }; <<
2308 <<
2309 dma-controller@14f08000 { <<
2310 compatible = "mediate <<
2311 reg = <0 0x14f08000 0 <<
2312 mediatek,gce-client-r <<
2313 mediatek,gce-events = <<
2314 <<
2315 clocks = <&vppsys1 CL <<
2316 iommus = <&iommu_vdo <<
2317 power-domains = <&spm <<
2318 #dma-cells = <1>; <<
2319 }; <<
2320 <<
2321 dma-controller@14f09000 { <<
2322 compatible = "mediate <<
2323 reg = <0 0x14f09000 0 <<
2324 mediatek,gce-client-r <<
2325 mediatek,gce-events = <<
2326 <<
2327 clocks = <&vppsys1 CL <<
2328 iommus = <&iommu_vdo <<
2329 power-domains = <&spm <<
2330 #dma-cells = <1>; <<
2331 }; <<
2332 <<
2333 dma-controller@14f0a000 { <<
2334 compatible = "mediate <<
2335 reg = <0 0x14f0a000 0 <<
2336 mediatek,gce-client-r <<
2337 mediatek,gce-events = <<
2338 <<
2339 clocks = <&vppsys1 CL <<
2340 iommus = <&iommu_vpp <<
2341 power-domains = <&spm <<
2342 #dma-cells = <1>; <<
2343 }; <<
2344 <<
2345 display@14f0b000 { <<
2346 compatible = "mediate <<
2347 reg = <0 0x14f0b000 0 <<
2348 mediatek,gce-client-r <<
2349 clocks = <&vppsys1 CL <<
2350 }; <<
2351 <<
2352 display@14f0c000 { <<
2353 compatible = "mediate <<
2354 reg = <0 0x14f0c000 0 <<
2355 mediatek,gce-client-r <<
2356 clocks = <&vppsys1 CL <<
2357 }; <<
2358 <<
2359 display@14f0d000 { <<
2360 compatible = "mediate <<
2361 reg = <0 0x14f0d000 0 <<
2362 mediatek,gce-client-r <<
2363 clocks = <&vppsys1 CL <<
2364 }; <<
2365 <<
2366 display@14f0e000 { <<
2367 compatible = "mediate <<
2368 reg = <0 0x14f0e000 0 <<
2369 mediatek,gce-client-r <<
2370 clocks = <&vppsys1 CL <<
2371 }; <<
2372 <<
2373 display@14f0f000 { <<
2374 compatible = "mediate <<
2375 reg = <0 0x14f0f000 0 <<
2376 mediatek,gce-client-r <<
2377 clocks = <&vppsys1 CL <<
2378 }; <<
2379 <<
2380 display@14f10000 { <<
2381 compatible = "mediate <<
2382 reg = <0 0x14f10000 0 <<
2383 mediatek,gce-client-r <<
2384 clocks = <&vppsys1 CL <<
2385 }; <<
2386 <<
2387 display@14f11000 { <<
2388 compatible = "mediate <<
2389 reg = <0 0x14f11000 0 <<
2390 interrupts = <GIC_SPI <<
2391 mediatek,gce-client-r <<
2392 clocks = <&vppsys1 CL <<
2393 power-domains = <&spm <<
2394 }; <<
2395 <<
2396 display@14f12000 { <<
2397 compatible = "mediate <<
2398 reg = <0 0x14f12000 0 <<
2399 interrupts = <GIC_SPI <<
2400 mediatek,gce-client-r <<
2401 clocks = <&vppsys1 CL <<
2402 power-domains = <&spm <<
2403 }; <<
2404 <<
2405 display@14f13000 { <<
2406 compatible = "mediate <<
2407 reg = <0 0x14f13000 0 <<
2408 interrupts = <GIC_SPI <<
2409 mediatek,gce-client-r <<
2410 clocks = <&vppsys1 CL <<
2411 power-domains = <&spm <<
2412 }; <<
2413 <<
2414 display@14f14000 { <<
2415 compatible = "mediate <<
2416 reg = <0 0x14f14000 0 <<
2417 mediatek,gce-client-r <<
2418 mediatek,gce-events = <<
2419 <<
2420 clocks = <&vppsys1 CL <<
2421 }; <<
2422 <<
2423 display@14f15000 { <<
2424 compatible = "mediate <<
2425 reg = <0 0x14f15000 0 <<
2426 mediatek,gce-client-r <<
2427 mediatek,gce-events = <<
2428 <<
2429 clocks = <&vppsys1 CL <<
2430 }; <<
2431 <<
2432 display@14f16000 { <<
2433 compatible = "mediate <<
2434 reg = <0 0x14f16000 0 <<
2435 mediatek,gce-client-r <<
2436 mediatek,gce-events = <<
2437 <<
2438 clocks = <&vppsys1 CL <<
2439 }; <<
2440 <<
2441 display@14f17000 { <<
2442 compatible = "mediate <<
2443 reg = <0 0x14f17000 0 <<
2444 mediatek,gce-client-r <<
2445 clocks = <&vppsys1 CL <<
2446 }; <<
2447 <<
2448 display@14f18000 { <<
2449 compatible = "mediate <<
2450 reg = <0 0x14f18000 0 <<
2451 mediatek,gce-client-r <<
2452 clocks = <&vppsys1 CL <<
2453 }; <<
2454 <<
2455 display@14f19000 { <<
2456 compatible = "mediate <<
2457 reg = <0 0x14f19000 0 <<
2458 mediatek,gce-client-r <<
2459 clocks = <&vppsys1 CL <<
2460 }; <<
2461 <<
2462 display@14f1a000 { <<
2463 compatible = "mediate <<
2464 reg = <0 0x14f1a000 0 <<
2465 mediatek,gce-client-r <<
2466 clocks = <&vppsys1 CL <<
2467 power-domains = <&spm <<
2468 }; <<
2469 <<
2470 display@14f1b000 { <<
2471 compatible = "mediate <<
2472 reg = <0 0x14f1b000 0 <<
2473 mediatek,gce-client-r <<
2474 clocks = <&vppsys1 CL <<
2475 power-domains = <&spm <<
2476 }; <<
2477 <<
2478 display@14f1c000 { <<
2479 compatible = "mediate <<
2480 reg = <0 0x14f1c000 0 <<
2481 interrupts = <GIC_SPI <<
2482 mediatek,gce-client-r <<
2483 clocks = <&vppsys1 CL <<
2484 power-domains = <&spm <<
2485 }; <<
2486 <<
2487 display@14f1d000 { <<
2488 compatible = "mediate <<
2489 reg = <0 0x14f1d000 0 <<
2490 mediatek,gce-client-r <<
2491 interrupts = <GIC_SPI <<
2492 clocks = <&vppsys1 CL <<
2493 power-domains = <&spm <<
2494 }; <<
2495 <<
2496 display@14f1e000 { <<
2497 compatible = "mediate <<
2498 reg = <0 0x14f1e000 0 <<
2499 interrupts = <GIC_SPI <<
2500 mediatek,gce-client-r <<
2501 clocks = <&vppsys1 CL <<
2502 power-domains = <&spm <<
2503 }; <<
2504 <<
2505 display@14f1f000 { <<
2506 compatible = "mediate <<
2507 reg = <0 0x14f1f000 0 <<
2508 interrupts = <GIC_SPI <<
2509 mediatek,gce-client-r <<
2510 clocks = <&vppsys1 CL <<
2511 power-domains = <&spm <<
2512 iommus = <&iommu_vdo <<
2513 }; <<
2514 <<
2515 display@14f20000 { <<
2516 compatible = "mediate <<
2517 reg = <0 0x14f20000 0 <<
2518 mediatek,gce-client-r <<
2519 clocks = <&vppsys1 CL <<
2520 power-domains = <&spm <<
2521 }; <<
2522 <<
2523 display@14f21000 { <<
2524 compatible = "mediate <<
2525 reg = <0 0x14f21000 0 <<
2526 mediatek,gce-client-r <<
2527 clocks = <&vppsys1 CL <<
2528 power-domains = <&spm <<
2529 }; <<
2530 <<
2531 display@14f22000 { <<
2532 compatible = "mediate <<
2533 reg = <0 0x14f22000 0 <<
2534 mediatek,gce-client-r <<
2535 clocks = <&vppsys1 CL <<
2536 power-domains = <&spm <<
2537 }; <<
2538 <<
2539 dma-controller@14f23000 { <<
2540 compatible = "mediate <<
2541 reg = <0 0x14f23000 0 <<
2542 mediatek,gce-client-r <<
2543 mediatek,gce-events = <<
2544 <<
2545 clocks = <&vppsys1 CL <<
2546 iommus = <&iommu_vdo <<
2547 power-domains = <&spm <<
2548 #dma-cells = <1>; <<
2549 }; <<
2550 <<
2551 dma-controller@14f24000 { <<
2552 compatible = "mediate <<
2553 reg = <0 0x14f24000 0 <<
2554 mediatek,gce-client-r <<
2555 mediatek,gce-events = <<
2556 <CMDQ <<
2557 clocks = <&vppsys1 CL <<
2558 iommus = <&iommu_vdo <<
2559 power-domains = <&spm <<
2560 #dma-cells = <1>; <<
2561 }; <<
2562 <<
2563 dma-controller@14f25000 { <<
2564 compatible = "mediate <<
2565 reg = <0 0x14f25000 0 <<
2566 mediatek,gce-client-r <<
2567 mediatek,gce-events = <<
2568 <CMDQ <<
2569 clocks = <&vppsys1 CL <<
2570 iommus = <&iommu_vpp <<
2571 power-domains = <&spm <<
2572 #dma-cells = <1>; <<
2573 }; <<
2574 <<
2575 imgsys: clock-controller@1500 1628 imgsys: clock-controller@15000000 {
2576 compatible = "mediate 1629 compatible = "mediatek,mt8195-imgsys";
2577 reg = <0 0x15000000 0 1630 reg = <0 0x15000000 0 0x1000>;
2578 #clock-cells = <1>; 1631 #clock-cells = <1>;
2579 }; 1632 };
2580 1633
2581 larb9: larb@15001000 { 1634 larb9: larb@15001000 {
2582 compatible = "mediate 1635 compatible = "mediatek,mt8195-smi-larb";
2583 reg = <0 0x15001000 0 1636 reg = <0 0x15001000 0 0x1000>;
2584 mediatek,larb-id = <9 1637 mediatek,larb-id = <9>;
2585 mediatek,smi = <&smi_ 1638 mediatek,smi = <&smi_sub_common_img1_3x1>;
2586 clocks = <&imgsys CLK 1639 clocks = <&imgsys CLK_IMG_LARB9>,
2587 <&imgsys CLK 1640 <&imgsys CLK_IMG_LARB9>,
2588 <&imgsys CLK 1641 <&imgsys CLK_IMG_GALS>;
2589 clock-names = "apb", 1642 clock-names = "apb", "smi", "gals";
2590 power-domains = <&spm 1643 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2591 }; 1644 };
2592 1645
2593 smi_sub_common_img0_3x1: smi@ 1646 smi_sub_common_img0_3x1: smi@15002000 {
2594 compatible = "mediate 1647 compatible = "mediatek,mt8195-smi-sub-common";
2595 reg = <0 0x15002000 0 1648 reg = <0 0x15002000 0 0x1000>;
2596 clocks = <&imgsys CLK 1649 clocks = <&imgsys CLK_IMG_IPE>,
2597 <&imgsys CLK 1650 <&imgsys CLK_IMG_IPE>,
2598 <&vppsys0 CL 1651 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2599 clock-names = "apb", 1652 clock-names = "apb", "smi", "gals0";
2600 mediatek,smi = <&smi_ 1653 mediatek,smi = <&smi_common_vpp>;
2601 power-domains = <&spm 1654 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2602 }; 1655 };
2603 1656
2604 smi_sub_common_img1_3x1: smi@ 1657 smi_sub_common_img1_3x1: smi@15003000 {
2605 compatible = "mediate 1658 compatible = "mediatek,mt8195-smi-sub-common";
2606 reg = <0 0x15003000 0 1659 reg = <0 0x15003000 0 0x1000>;
2607 clocks = <&imgsys CLK 1660 clocks = <&imgsys CLK_IMG_LARB9>,
2608 <&imgsys CLK 1661 <&imgsys CLK_IMG_LARB9>,
2609 <&imgsys CLK 1662 <&imgsys CLK_IMG_GALS>;
2610 clock-names = "apb", 1663 clock-names = "apb", "smi", "gals0";
2611 mediatek,smi = <&smi_ 1664 mediatek,smi = <&smi_common_vdo>;
2612 power-domains = <&spm 1665 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2613 }; 1666 };
2614 1667
2615 imgsys1_dip_top: clock-contro 1668 imgsys1_dip_top: clock-controller@15110000 {
2616 compatible = "mediate 1669 compatible = "mediatek,mt8195-imgsys1_dip_top";
2617 reg = <0 0x15110000 0 1670 reg = <0 0x15110000 0 0x1000>;
2618 #clock-cells = <1>; 1671 #clock-cells = <1>;
2619 }; 1672 };
2620 1673
2621 larb10: larb@15120000 { 1674 larb10: larb@15120000 {
2622 compatible = "mediate 1675 compatible = "mediatek,mt8195-smi-larb";
2623 reg = <0 0x15120000 0 1676 reg = <0 0x15120000 0 0x1000>;
2624 mediatek,larb-id = <1 1677 mediatek,larb-id = <10>;
2625 mediatek,smi = <&smi_ 1678 mediatek,smi = <&smi_sub_common_img1_3x1>;
2626 clocks = <&imgsys CLK 1679 clocks = <&imgsys CLK_IMG_DIP0>,
2627 <&imgsys1_dip_ 1680 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2628 clock-names = "apb", 1681 clock-names = "apb", "smi";
2629 power-domains = <&spm 1682 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2630 }; 1683 };
2631 1684
2632 imgsys1_dip_nr: clock-control 1685 imgsys1_dip_nr: clock-controller@15130000 {
2633 compatible = "mediate 1686 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2634 reg = <0 0x15130000 0 1687 reg = <0 0x15130000 0 0x1000>;
2635 #clock-cells = <1>; 1688 #clock-cells = <1>;
2636 }; 1689 };
2637 1690
2638 imgsys1_wpe: clock-controller 1691 imgsys1_wpe: clock-controller@15220000 {
2639 compatible = "mediate 1692 compatible = "mediatek,mt8195-imgsys1_wpe";
2640 reg = <0 0x15220000 0 1693 reg = <0 0x15220000 0 0x1000>;
2641 #clock-cells = <1>; 1694 #clock-cells = <1>;
2642 }; 1695 };
2643 1696
2644 larb11: larb@15230000 { 1697 larb11: larb@15230000 {
2645 compatible = "mediate 1698 compatible = "mediatek,mt8195-smi-larb";
2646 reg = <0 0x15230000 0 1699 reg = <0 0x15230000 0 0x1000>;
2647 mediatek,larb-id = <1 1700 mediatek,larb-id = <11>;
2648 mediatek,smi = <&smi_ 1701 mediatek,smi = <&smi_sub_common_img1_3x1>;
2649 clocks = <&imgsys CLK 1702 clocks = <&imgsys CLK_IMG_WPE0>,
2650 <&imgsys1_wpe 1703 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2651 clock-names = "apb", 1704 clock-names = "apb", "smi";
2652 power-domains = <&spm 1705 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2653 }; 1706 };
2654 1707
2655 ipesys: clock-controller@1533 1708 ipesys: clock-controller@15330000 {
2656 compatible = "mediate 1709 compatible = "mediatek,mt8195-ipesys";
2657 reg = <0 0x15330000 0 1710 reg = <0 0x15330000 0 0x1000>;
2658 #clock-cells = <1>; 1711 #clock-cells = <1>;
2659 }; 1712 };
2660 1713
2661 larb12: larb@15340000 { 1714 larb12: larb@15340000 {
2662 compatible = "mediate 1715 compatible = "mediatek,mt8195-smi-larb";
2663 reg = <0 0x15340000 0 1716 reg = <0 0x15340000 0 0x1000>;
2664 mediatek,larb-id = <1 1717 mediatek,larb-id = <12>;
2665 mediatek,smi = <&smi_ 1718 mediatek,smi = <&smi_sub_common_img0_3x1>;
2666 clocks = <&ipesys CLK 1719 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2667 <&ipesys CLK 1720 <&ipesys CLK_IPE_SMI_LARB12>;
2668 clock-names = "apb", 1721 clock-names = "apb", "smi";
2669 power-domains = <&spm 1722 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2670 }; 1723 };
2671 1724
2672 camsys: clock-controller@1600 1725 camsys: clock-controller@16000000 {
2673 compatible = "mediate 1726 compatible = "mediatek,mt8195-camsys";
2674 reg = <0 0x16000000 0 1727 reg = <0 0x16000000 0 0x1000>;
2675 #clock-cells = <1>; 1728 #clock-cells = <1>;
2676 }; 1729 };
2677 1730
2678 larb13: larb@16001000 { 1731 larb13: larb@16001000 {
2679 compatible = "mediate 1732 compatible = "mediatek,mt8195-smi-larb";
2680 reg = <0 0x16001000 0 1733 reg = <0 0x16001000 0 0x1000>;
2681 mediatek,larb-id = <1 1734 mediatek,larb-id = <13>;
2682 mediatek,smi = <&smi_ 1735 mediatek,smi = <&smi_sub_common_cam_4x1>;
2683 clocks = <&camsys CLK 1736 clocks = <&camsys CLK_CAM_LARB13>,
2684 <&camsys CLK_C 1737 <&camsys CLK_CAM_LARB13>,
2685 <&camsys CLK_C 1738 <&camsys CLK_CAM_CAM2MM0_GALS>;
2686 clock-names = "apb", 1739 clock-names = "apb", "smi", "gals";
2687 power-domains = <&spm 1740 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688 }; 1741 };
2689 1742
2690 larb14: larb@16002000 { 1743 larb14: larb@16002000 {
2691 compatible = "mediate 1744 compatible = "mediatek,mt8195-smi-larb";
2692 reg = <0 0x16002000 0 1745 reg = <0 0x16002000 0 0x1000>;
2693 mediatek,larb-id = <1 1746 mediatek,larb-id = <14>;
2694 mediatek,smi = <&smi_ 1747 mediatek,smi = <&smi_sub_common_cam_7x1>;
2695 clocks = <&camsys CLK 1748 clocks = <&camsys CLK_CAM_LARB14>,
2696 <&camsys CLK 1749 <&camsys CLK_CAM_LARB14>;
2697 clock-names = "apb", 1750 clock-names = "apb", "smi";
2698 power-domains = <&spm 1751 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2699 }; 1752 };
2700 1753
2701 smi_sub_common_cam_4x1: smi@1 1754 smi_sub_common_cam_4x1: smi@16004000 {
2702 compatible = "mediate 1755 compatible = "mediatek,mt8195-smi-sub-common";
2703 reg = <0 0x16004000 0 1756 reg = <0 0x16004000 0 0x1000>;
2704 clocks = <&camsys CLK 1757 clocks = <&camsys CLK_CAM_LARB13>,
2705 <&camsys CLK 1758 <&camsys CLK_CAM_LARB13>,
2706 <&camsys CLK 1759 <&camsys CLK_CAM_CAM2MM0_GALS>;
2707 clock-names = "apb", 1760 clock-names = "apb", "smi", "gals0";
2708 mediatek,smi = <&smi_ 1761 mediatek,smi = <&smi_common_vdo>;
2709 power-domains = <&spm 1762 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2710 }; 1763 };
2711 1764
2712 smi_sub_common_cam_7x1: smi@1 1765 smi_sub_common_cam_7x1: smi@16005000 {
2713 compatible = "mediate 1766 compatible = "mediatek,mt8195-smi-sub-common";
2714 reg = <0 0x16005000 0 1767 reg = <0 0x16005000 0 0x1000>;
2715 clocks = <&camsys CLK 1768 clocks = <&camsys CLK_CAM_LARB14>,
2716 <&camsys CLK 1769 <&camsys CLK_CAM_CAM2MM1_GALS>,
2717 <&vppsys0 CL 1770 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2718 clock-names = "apb", 1771 clock-names = "apb", "smi", "gals0";
2719 mediatek,smi = <&smi_ 1772 mediatek,smi = <&smi_common_vpp>;
2720 power-domains = <&spm 1773 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2721 }; 1774 };
2722 1775
2723 larb16: larb@16012000 { 1776 larb16: larb@16012000 {
2724 compatible = "mediate 1777 compatible = "mediatek,mt8195-smi-larb";
2725 reg = <0 0x16012000 0 1778 reg = <0 0x16012000 0 0x1000>;
2726 mediatek,larb-id = <1 1779 mediatek,larb-id = <16>;
2727 mediatek,smi = <&smi_ 1780 mediatek,smi = <&smi_sub_common_cam_7x1>;
2728 clocks = <&camsys_raw 1781 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2729 <&camsys_raw 1782 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2730 clock-names = "apb", 1783 clock-names = "apb", "smi";
2731 power-domains = <&spm 1784 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2732 }; 1785 };
2733 1786
2734 larb17: larb@16013000 { 1787 larb17: larb@16013000 {
2735 compatible = "mediate 1788 compatible = "mediatek,mt8195-smi-larb";
2736 reg = <0 0x16013000 0 1789 reg = <0 0x16013000 0 0x1000>;
2737 mediatek,larb-id = <1 1790 mediatek,larb-id = <17>;
2738 mediatek,smi = <&smi_ 1791 mediatek,smi = <&smi_sub_common_cam_4x1>;
2739 clocks = <&camsys_yuv 1792 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2740 <&camsys_yuv 1793 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2741 clock-names = "apb", 1794 clock-names = "apb", "smi";
2742 power-domains = <&spm 1795 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2743 }; 1796 };
2744 1797
2745 larb27: larb@16014000 { 1798 larb27: larb@16014000 {
2746 compatible = "mediate 1799 compatible = "mediatek,mt8195-smi-larb";
2747 reg = <0 0x16014000 0 1800 reg = <0 0x16014000 0 0x1000>;
2748 mediatek,larb-id = <2 1801 mediatek,larb-id = <27>;
2749 mediatek,smi = <&smi_ 1802 mediatek,smi = <&smi_sub_common_cam_7x1>;
2750 clocks = <&camsys_raw 1803 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2751 <&camsys_raw 1804 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2752 clock-names = "apb", 1805 clock-names = "apb", "smi";
2753 power-domains = <&spm 1806 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2754 }; 1807 };
2755 1808
2756 larb28: larb@16015000 { 1809 larb28: larb@16015000 {
2757 compatible = "mediate 1810 compatible = "mediatek,mt8195-smi-larb";
2758 reg = <0 0x16015000 0 1811 reg = <0 0x16015000 0 0x1000>;
2759 mediatek,larb-id = <2 1812 mediatek,larb-id = <28>;
2760 mediatek,smi = <&smi_ 1813 mediatek,smi = <&smi_sub_common_cam_4x1>;
2761 clocks = <&camsys_yuv 1814 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2762 <&camsys_yuv 1815 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2763 clock-names = "apb", 1816 clock-names = "apb", "smi";
2764 power-domains = <&spm 1817 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2765 }; 1818 };
2766 1819
2767 camsys_rawa: clock-controller 1820 camsys_rawa: clock-controller@1604f000 {
2768 compatible = "mediate 1821 compatible = "mediatek,mt8195-camsys_rawa";
2769 reg = <0 0x1604f000 0 1822 reg = <0 0x1604f000 0 0x1000>;
2770 #clock-cells = <1>; 1823 #clock-cells = <1>;
2771 }; 1824 };
2772 1825
2773 camsys_yuva: clock-controller 1826 camsys_yuva: clock-controller@1606f000 {
2774 compatible = "mediate 1827 compatible = "mediatek,mt8195-camsys_yuva";
2775 reg = <0 0x1606f000 0 1828 reg = <0 0x1606f000 0 0x1000>;
2776 #clock-cells = <1>; 1829 #clock-cells = <1>;
2777 }; 1830 };
2778 1831
2779 camsys_rawb: clock-controller 1832 camsys_rawb: clock-controller@1608f000 {
2780 compatible = "mediate 1833 compatible = "mediatek,mt8195-camsys_rawb";
2781 reg = <0 0x1608f000 0 1834 reg = <0 0x1608f000 0 0x1000>;
2782 #clock-cells = <1>; 1835 #clock-cells = <1>;
2783 }; 1836 };
2784 1837
2785 camsys_yuvb: clock-controller 1838 camsys_yuvb: clock-controller@160af000 {
2786 compatible = "mediate 1839 compatible = "mediatek,mt8195-camsys_yuvb";
2787 reg = <0 0x160af000 0 1840 reg = <0 0x160af000 0 0x1000>;
2788 #clock-cells = <1>; 1841 #clock-cells = <1>;
2789 }; 1842 };
2790 1843
2791 camsys_mraw: clock-controller 1844 camsys_mraw: clock-controller@16140000 {
2792 compatible = "mediate 1845 compatible = "mediatek,mt8195-camsys_mraw";
2793 reg = <0 0x16140000 0 1846 reg = <0 0x16140000 0 0x1000>;
2794 #clock-cells = <1>; 1847 #clock-cells = <1>;
2795 }; 1848 };
2796 1849
2797 larb25: larb@16141000 { 1850 larb25: larb@16141000 {
2798 compatible = "mediate 1851 compatible = "mediatek,mt8195-smi-larb";
2799 reg = <0 0x16141000 0 1852 reg = <0 0x16141000 0 0x1000>;
2800 mediatek,larb-id = <2 1853 mediatek,larb-id = <25>;
2801 mediatek,smi = <&smi_ 1854 mediatek,smi = <&smi_sub_common_cam_4x1>;
2802 clocks = <&camsys CLK 1855 clocks = <&camsys CLK_CAM_LARB13>,
2803 <&camsys_mra 1856 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2804 <&camsys CLK 1857 <&camsys CLK_CAM_CAM2MM0_GALS>;
2805 clock-names = "apb", 1858 clock-names = "apb", "smi", "gals";
2806 power-domains = <&spm 1859 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2807 }; 1860 };
2808 1861
2809 larb26: larb@16142000 { 1862 larb26: larb@16142000 {
2810 compatible = "mediate 1863 compatible = "mediatek,mt8195-smi-larb";
2811 reg = <0 0x16142000 0 1864 reg = <0 0x16142000 0 0x1000>;
2812 mediatek,larb-id = <2 1865 mediatek,larb-id = <26>;
2813 mediatek,smi = <&smi_ 1866 mediatek,smi = <&smi_sub_common_cam_7x1>;
2814 clocks = <&camsys_mra 1867 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2815 <&camsys_mra 1868 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2816 clock-names = "apb", 1869 clock-names = "apb", "smi";
2817 power-domains = <&spm 1870 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2818 1871
2819 }; 1872 };
2820 1873
2821 ccusys: clock-controller@1720 1874 ccusys: clock-controller@17200000 {
2822 compatible = "mediate 1875 compatible = "mediatek,mt8195-ccusys";
2823 reg = <0 0x17200000 0 1876 reg = <0 0x17200000 0 0x1000>;
2824 #clock-cells = <1>; 1877 #clock-cells = <1>;
2825 }; 1878 };
2826 1879
2827 larb18: larb@17201000 { 1880 larb18: larb@17201000 {
2828 compatible = "mediate 1881 compatible = "mediatek,mt8195-smi-larb";
2829 reg = <0 0x17201000 0 1882 reg = <0 0x17201000 0 0x1000>;
2830 mediatek,larb-id = <1 1883 mediatek,larb-id = <18>;
2831 mediatek,smi = <&smi_ 1884 mediatek,smi = <&smi_sub_common_cam_7x1>;
2832 clocks = <&ccusys CLK 1885 clocks = <&ccusys CLK_CCU_LARB18>,
2833 <&ccusys CLK 1886 <&ccusys CLK_CCU_LARB18>;
2834 clock-names = "apb", 1887 clock-names = "apb", "smi";
2835 power-domains = <&spm 1888 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2836 }; 1889 };
2837 1890
2838 video-codec@18000000 { <<
2839 compatible = "mediate <<
2840 mediatek,scp = <&scp> <<
2841 iommus = <&iommu_vdo <<
2842 #address-cells = <2>; <<
2843 #size-cells = <2>; <<
2844 reg = <0 0x18000000 0 <<
2845 <0 0x18004000 0 <<
2846 ranges = <0 0 0 0x180 <<
2847 <<
2848 video-codec@2000 { <<
2849 compatible = <<
2850 reg = <0 0x20 <<
2851 iommus = <&io <<
2852 <&io <<
2853 clocks = <&to <<
2854 <&vd <<
2855 <&vd <<
2856 <&to <<
2857 clock-names = <<
2858 assigned-cloc <<
2859 assigned-cloc <<
2860 power-domains <<
2861 }; <<
2862 <<
2863 video-codec@10000 { <<
2864 compatible = <<
2865 reg = <0 0x10 <<
2866 interrupts = <<
2867 iommus = <&io <<
2868 <&io <<
2869 <&io <<
2870 <&io <<
2871 <&io <<
2872 <&io <<
2873 clocks = <&to <<
2874 <&vd <<
2875 <&vd <<
2876 <&to <<
2877 clock-names = <<
2878 assigned-cloc <<
2879 assigned-cloc <<
2880 power-domains <<
2881 }; <<
2882 <<
2883 video-codec@25000 { <<
2884 compatible = <<
2885 reg = <0 0x25 <<
2886 interrupts = <<
2887 iommus = <&io <<
2888 <&io <<
2889 <&io <<
2890 <&io <<
2891 <&io <<
2892 <&io <<
2893 <&io <<
2894 <&io <<
2895 <&io <<
2896 <&io <<
2897 clocks = <&to <<
2898 <&vd <<
2899 <&vd <<
2900 <&to <<
2901 clock-names = <<
2902 assigned-cloc <<
2903 assigned-cloc <<
2904 power-domains <<
2905 }; <<
2906 }; <<
2907 <<
2908 larb24: larb@1800d000 { 1891 larb24: larb@1800d000 {
2909 compatible = "mediate 1892 compatible = "mediatek,mt8195-smi-larb";
2910 reg = <0 0x1800d000 0 1893 reg = <0 0x1800d000 0 0x1000>;
2911 mediatek,larb-id = <2 1894 mediatek,larb-id = <24>;
2912 mediatek,smi = <&smi_ 1895 mediatek,smi = <&smi_common_vdo>;
2913 clocks = <&vdecsys_so 1896 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2914 <&vdecsys_so 1897 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2915 clock-names = "apb", 1898 clock-names = "apb", "smi";
2916 power-domains = <&spm 1899 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2917 }; 1900 };
2918 1901
2919 larb23: larb@1800e000 { 1902 larb23: larb@1800e000 {
2920 compatible = "mediate 1903 compatible = "mediatek,mt8195-smi-larb";
2921 reg = <0 0x1800e000 0 1904 reg = <0 0x1800e000 0 0x1000>;
2922 mediatek,larb-id = <2 1905 mediatek,larb-id = <23>;
2923 mediatek,smi = <&smi_ 1906 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2924 clocks = <&vppsys0 CL 1907 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2925 <&vdecsys_so 1908 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2926 clock-names = "apb", 1909 clock-names = "apb", "smi";
2927 power-domains = <&spm 1910 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2928 }; 1911 };
2929 1912
2930 vdecsys_soc: clock-controller 1913 vdecsys_soc: clock-controller@1800f000 {
2931 compatible = "mediate 1914 compatible = "mediatek,mt8195-vdecsys_soc";
2932 reg = <0 0x1800f000 0 1915 reg = <0 0x1800f000 0 0x1000>;
2933 #clock-cells = <1>; 1916 #clock-cells = <1>;
2934 }; 1917 };
2935 1918
2936 larb21: larb@1802e000 { 1919 larb21: larb@1802e000 {
2937 compatible = "mediate 1920 compatible = "mediatek,mt8195-smi-larb";
2938 reg = <0 0x1802e000 0 1921 reg = <0 0x1802e000 0 0x1000>;
2939 mediatek,larb-id = <2 1922 mediatek,larb-id = <21>;
2940 mediatek,smi = <&smi_ 1923 mediatek,smi = <&smi_common_vdo>;
2941 clocks = <&vdecsys CL 1924 clocks = <&vdecsys CLK_VDEC_LARB1>,
2942 <&vdecsys CL 1925 <&vdecsys CLK_VDEC_LARB1>;
2943 clock-names = "apb", 1926 clock-names = "apb", "smi";
2944 power-domains = <&spm 1927 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2945 }; 1928 };
2946 1929
2947 vdecsys: clock-controller@180 1930 vdecsys: clock-controller@1802f000 {
2948 compatible = "mediate 1931 compatible = "mediatek,mt8195-vdecsys";
2949 reg = <0 0x1802f000 0 1932 reg = <0 0x1802f000 0 0x1000>;
2950 #clock-cells = <1>; 1933 #clock-cells = <1>;
2951 }; 1934 };
2952 1935
2953 larb22: larb@1803e000 { 1936 larb22: larb@1803e000 {
2954 compatible = "mediate 1937 compatible = "mediatek,mt8195-smi-larb";
2955 reg = <0 0x1803e000 0 1938 reg = <0 0x1803e000 0 0x1000>;
2956 mediatek,larb-id = <2 1939 mediatek,larb-id = <22>;
2957 mediatek,smi = <&smi_ 1940 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2958 clocks = <&vppsys0 CL 1941 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2959 <&vdecsys_co 1942 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2960 clock-names = "apb", 1943 clock-names = "apb", "smi";
2961 power-domains = <&spm 1944 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2962 }; 1945 };
2963 1946
2964 vdecsys_core1: clock-controll 1947 vdecsys_core1: clock-controller@1803f000 {
2965 compatible = "mediate 1948 compatible = "mediatek,mt8195-vdecsys_core1";
2966 reg = <0 0x1803f000 0 1949 reg = <0 0x1803f000 0 0x1000>;
2967 #clock-cells = <1>; 1950 #clock-cells = <1>;
2968 }; 1951 };
2969 1952
2970 apusys_pll: clock-controller@ 1953 apusys_pll: clock-controller@190f3000 {
2971 compatible = "mediate 1954 compatible = "mediatek,mt8195-apusys_pll";
2972 reg = <0 0x190f3000 0 1955 reg = <0 0x190f3000 0 0x1000>;
2973 #clock-cells = <1>; 1956 #clock-cells = <1>;
2974 }; 1957 };
2975 1958
2976 vencsys: clock-controller@1a0 1959 vencsys: clock-controller@1a000000 {
2977 compatible = "mediate 1960 compatible = "mediatek,mt8195-vencsys";
2978 reg = <0 0x1a000000 0 1961 reg = <0 0x1a000000 0 0x1000>;
2979 #clock-cells = <1>; 1962 #clock-cells = <1>;
2980 }; 1963 };
2981 1964
2982 larb19: larb@1a010000 { 1965 larb19: larb@1a010000 {
2983 compatible = "mediate 1966 compatible = "mediatek,mt8195-smi-larb";
2984 reg = <0 0x1a010000 0 1967 reg = <0 0x1a010000 0 0x1000>;
2985 mediatek,larb-id = <1 1968 mediatek,larb-id = <19>;
2986 mediatek,smi = <&smi_ 1969 mediatek,smi = <&smi_common_vdo>;
2987 clocks = <&vencsys CL 1970 clocks = <&vencsys CLK_VENC_VENC>,
2988 <&vencsys CL 1971 <&vencsys CLK_VENC_GALS>;
2989 clock-names = "apb", 1972 clock-names = "apb", "smi";
2990 power-domains = <&spm 1973 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2991 }; 1974 };
2992 1975
2993 venc: video-codec@1a020000 { <<
2994 compatible = "mediate <<
2995 reg = <0 0x1a020000 0 <<
2996 iommus = <&iommu_vdo <<
2997 <&iommu_vdo <<
2998 <&iommu_vdo <<
2999 <&iommu_vdo <<
3000 <&iommu_vdo <<
3001 <&iommu_vdo <<
3002 <&iommu_vdo <<
3003 <&iommu_vdo <<
3004 <&iommu_vdo <<
3005 interrupts = <GIC_SPI <<
3006 mediatek,scp = <&scp> <<
3007 clocks = <&vencsys CL <<
3008 clock-names = "venc_s <<
3009 assigned-clocks = <&t <<
3010 assigned-clock-parent <<
3011 power-domains = <&spm <<
3012 #address-cells = <2>; <<
3013 #size-cells = <2>; <<
3014 }; <<
3015 <<
3016 jpgdec-master { <<
3017 compatible = "mediate <<
3018 power-domains = <&spm <<
3019 iommus = <&iommu_vdo <<
3020 <&iommu_vdo <<
3021 <&iommu_vdo <<
3022 <&iommu_vdo <<
3023 <&iommu_vdo <<
3024 <&iommu_vdo <<
3025 #address-cells = <2>; <<
3026 #size-cells = <2>; <<
3027 ranges; <<
3028 <<
3029 jpgdec@1a040000 { <<
3030 compatible = <<
3031 reg = <0 0x1a <<
3032 iommus = <&io <<
3033 <&io <<
3034 <&io <<
3035 <&io <<
3036 <&io <<
3037 <&io <<
3038 interrupts = <<
3039 clocks = <&ve <<
3040 clock-names = <<
3041 power-domains <<
3042 }; <<
3043 <<
3044 jpgdec@1a050000 { <<
3045 compatible = <<
3046 reg = <0 0x1a <<
3047 iommus = <&io <<
3048 <&io <<
3049 <&io <<
3050 <&io <<
3051 <&io <<
3052 <&io <<
3053 interrupts = <<
3054 clocks = <&ve <<
3055 clock-names = <<
3056 power-domains <<
3057 }; <<
3058 <<
3059 jpgdec@1b040000 { <<
3060 compatible = <<
3061 reg = <0 0x1b <<
3062 iommus = <&io <<
3063 <&io <<
3064 <&io <<
3065 <&io <<
3066 <&io <<
3067 <&io <<
3068 interrupts = <<
3069 clocks = <&ve <<
3070 clock-names = <<
3071 power-domains <<
3072 }; <<
3073 }; <<
3074 <<
3075 vencsys_core1: clock-controll 1976 vencsys_core1: clock-controller@1b000000 {
3076 compatible = "mediate 1977 compatible = "mediatek,mt8195-vencsys_core1";
3077 reg = <0 0x1b000000 0 1978 reg = <0 0x1b000000 0 0x1000>;
3078 #clock-cells = <1>; 1979 #clock-cells = <1>;
3079 }; 1980 };
3080 1981
3081 vdosys0: syscon@1c01a000 { 1982 vdosys0: syscon@1c01a000 {
3082 compatible = "mediate 1983 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3083 reg = <0 0x1c01a000 0 1984 reg = <0 0x1c01a000 0 0x1000>;
3084 mboxes = <&gce0 0 CMD 1985 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3085 #clock-cells = <1>; 1986 #clock-cells = <1>;
3086 mediatek,gce-client-r 1987 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3087 }; 1988 };
3088 1989
3089 <<
3090 jpgenc-master { <<
3091 compatible = "mediate <<
3092 power-domains = <&spm <<
3093 iommus = <&iommu_vpp <<
3094 <&iom <<
3095 <&iom <<
3096 <&iom <<
3097 #address-cells = <2>; <<
3098 #size-cells = <2>; <<
3099 ranges; <<
3100 <<
3101 jpgenc@1a030000 { <<
3102 compatible = <<
3103 reg = <0 0x1a <<
3104 iommus = <&io <<
3105 <<
3106 <<
3107 <<
3108 interrupts = <<
3109 clocks = <&ve <<
3110 clock-names = <<
3111 power-domains <<
3112 }; <<
3113 <<
3114 jpgenc@1b030000 { <<
3115 compatible = <<
3116 reg = <0 0x1b <<
3117 iommus = <&io <<
3118 <<
3119 <<
3120 <<
3121 interrupts = <<
3122 clocks = <&ve <<
3123 clock-names = <<
3124 power-domains <<
3125 }; <<
3126 }; <<
3127 <<
3128 larb20: larb@1b010000 { 1990 larb20: larb@1b010000 {
3129 compatible = "mediate 1991 compatible = "mediatek,mt8195-smi-larb";
3130 reg = <0 0x1b010000 0 1992 reg = <0 0x1b010000 0 0x1000>;
3131 mediatek,larb-id = <2 1993 mediatek,larb-id = <20>;
3132 mediatek,smi = <&smi_ 1994 mediatek,smi = <&smi_common_vpp>;
3133 clocks = <&vencsys_co 1995 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
3134 <&vencsys_co 1996 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3135 <&vppsys0 CL 1997 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3136 clock-names = "apb", 1998 clock-names = "apb", "smi", "gals";
3137 power-domains = <&spm 1999 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3138 }; 2000 };
3139 2001
3140 ovl0: ovl@1c000000 { 2002 ovl0: ovl@1c000000 {
3141 compatible = "mediate 2003 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3142 reg = <0 0x1c000000 0 2004 reg = <0 0x1c000000 0 0x1000>;
3143 interrupts = <GIC_SPI 2005 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3144 power-domains = <&spm 2006 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3145 clocks = <&vdosys0 CL 2007 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3146 iommus = <&iommu_vdo 2008 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3147 mediatek,gce-client-r 2009 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3148 }; 2010 };
3149 2011
3150 rdma0: rdma@1c002000 { 2012 rdma0: rdma@1c002000 {
3151 compatible = "mediate 2013 compatible = "mediatek,mt8195-disp-rdma";
3152 reg = <0 0x1c002000 0 2014 reg = <0 0x1c002000 0 0x1000>;
3153 interrupts = <GIC_SPI 2015 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3154 power-domains = <&spm 2016 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3155 clocks = <&vdosys0 CL 2017 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3156 iommus = <&iommu_vdo 2018 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3157 mediatek,gce-client-r 2019 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3158 }; 2020 };
3159 2021
3160 color0: color@1c003000 { 2022 color0: color@1c003000 {
3161 compatible = "mediate 2023 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3162 reg = <0 0x1c003000 0 2024 reg = <0 0x1c003000 0 0x1000>;
3163 interrupts = <GIC_SPI 2025 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3164 power-domains = <&spm 2026 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3165 clocks = <&vdosys0 CL 2027 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3166 mediatek,gce-client-r 2028 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3167 }; 2029 };
3168 2030
3169 ccorr0: ccorr@1c004000 { 2031 ccorr0: ccorr@1c004000 {
3170 compatible = "mediate 2032 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3171 reg = <0 0x1c004000 0 2033 reg = <0 0x1c004000 0 0x1000>;
3172 interrupts = <GIC_SPI 2034 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3173 power-domains = <&spm 2035 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3174 clocks = <&vdosys0 CL 2036 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3175 mediatek,gce-client-r 2037 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3176 }; 2038 };
3177 2039
3178 aal0: aal@1c005000 { 2040 aal0: aal@1c005000 {
3179 compatible = "mediate 2041 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3180 reg = <0 0x1c005000 0 2042 reg = <0 0x1c005000 0 0x1000>;
3181 interrupts = <GIC_SPI 2043 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3182 power-domains = <&spm 2044 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3183 clocks = <&vdosys0 CL 2045 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3184 mediatek,gce-client-r 2046 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3185 }; 2047 };
3186 2048
3187 gamma0: gamma@1c006000 { 2049 gamma0: gamma@1c006000 {
3188 compatible = "mediate 2050 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3189 reg = <0 0x1c006000 0 2051 reg = <0 0x1c006000 0 0x1000>;
3190 interrupts = <GIC_SPI 2052 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3191 power-domains = <&spm 2053 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3192 clocks = <&vdosys0 CL 2054 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3193 mediatek,gce-client-r 2055 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3194 }; 2056 };
3195 2057
3196 dither0: dither@1c007000 { 2058 dither0: dither@1c007000 {
3197 compatible = "mediate 2059 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3198 reg = <0 0x1c007000 0 2060 reg = <0 0x1c007000 0 0x1000>;
3199 interrupts = <GIC_SPI 2061 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3200 power-domains = <&spm 2062 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3201 clocks = <&vdosys0 CL 2063 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3202 mediatek,gce-client-r 2064 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3203 }; 2065 };
3204 2066
3205 dsi0: dsi@1c008000 { <<
3206 compatible = "mediate <<
3207 reg = <0 0x1c008000 0 <<
3208 interrupts = <GIC_SPI <<
3209 power-domains = <&spm <<
3210 clocks = <&vdosys0 CL <<
3211 <&vdosys0 CL <<
3212 <&mipi_tx0>; <<
3213 clock-names = "engine <<
3214 phys = <&mipi_tx0>; <<
3215 phy-names = "dphy"; <<
3216 status = "disabled"; <<
3217 }; <<
3218 <<
3219 dsc0: dsc@1c009000 { 2067 dsc0: dsc@1c009000 {
3220 compatible = "mediate 2068 compatible = "mediatek,mt8195-disp-dsc";
3221 reg = <0 0x1c009000 0 2069 reg = <0 0x1c009000 0 0x1000>;
3222 interrupts = <GIC_SPI 2070 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3223 power-domains = <&spm 2071 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3224 clocks = <&vdosys0 CL 2072 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3225 mediatek,gce-client-r 2073 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3226 }; 2074 };
3227 2075
3228 dsi1: dsi@1c012000 { <<
3229 compatible = "mediate <<
3230 reg = <0 0x1c012000 0 <<
3231 interrupts = <GIC_SPI <<
3232 power-domains = <&spm <<
3233 clocks = <&vdosys0 CL <<
3234 <&vdosys0 CL <<
3235 <&mipi_tx1>; <<
3236 clock-names = "engine <<
3237 phys = <&mipi_tx1>; <<
3238 phy-names = "dphy"; <<
3239 status = "disabled"; <<
3240 }; <<
3241 <<
3242 merge0: merge@1c014000 { 2076 merge0: merge@1c014000 {
3243 compatible = "mediate 2077 compatible = "mediatek,mt8195-disp-merge";
3244 reg = <0 0x1c014000 0 2078 reg = <0 0x1c014000 0 0x1000>;
3245 interrupts = <GIC_SPI 2079 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3246 power-domains = <&spm 2080 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3247 clocks = <&vdosys0 CL 2081 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3248 mediatek,gce-client-r 2082 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3249 }; 2083 };
3250 2084
3251 dp_intf0: dp-intf@1c015000 { <<
3252 compatible = "mediate <<
3253 reg = <0 0x1c015000 0 <<
3254 interrupts = <GIC_SPI <<
3255 clocks = <&vdosys0 CL <<
3256 <&vdosys0 C <<
3257 <&apmixedsys <<
3258 clock-names = "pixel" <<
3259 status = "disabled"; <<
3260 }; <<
3261 <<
3262 mutex: mutex@1c016000 { 2085 mutex: mutex@1c016000 {
3263 compatible = "mediate 2086 compatible = "mediatek,mt8195-disp-mutex";
3264 reg = <0 0x1c016000 0 2087 reg = <0 0x1c016000 0 0x1000>;
3265 interrupts = <GIC_SPI 2088 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3266 power-domains = <&spm 2089 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3267 clocks = <&vdosys0 CL 2090 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3268 mediatek,gce-client-r 2091 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3269 mediatek,gce-events = 2092 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3270 }; 2093 };
3271 2094
3272 larb0: larb@1c018000 { 2095 larb0: larb@1c018000 {
3273 compatible = "mediate 2096 compatible = "mediatek,mt8195-smi-larb";
3274 reg = <0 0x1c018000 0 2097 reg = <0 0x1c018000 0 0x1000>;
3275 mediatek,larb-id = <0 2098 mediatek,larb-id = <0>;
3276 mediatek,smi = <&smi_ 2099 mediatek,smi = <&smi_common_vdo>;
3277 clocks = <&vdosys0 CL 2100 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3278 <&vdosys0 CL 2101 <&vdosys0 CLK_VDO0_SMI_LARB>,
3279 <&vppsys0 CL 2102 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3280 clock-names = "apb", 2103 clock-names = "apb", "smi", "gals";
3281 power-domains = <&spm 2104 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3282 }; 2105 };
3283 2106
3284 larb1: larb@1c019000 { 2107 larb1: larb@1c019000 {
3285 compatible = "mediate 2108 compatible = "mediatek,mt8195-smi-larb";
3286 reg = <0 0x1c019000 0 2109 reg = <0 0x1c019000 0 0x1000>;
3287 mediatek,larb-id = <1 2110 mediatek,larb-id = <1>;
3288 mediatek,smi = <&smi_ 2111 mediatek,smi = <&smi_common_vpp>;
3289 clocks = <&vdosys0 CL 2112 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3290 <&vppsys0 CL 2113 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3291 <&vppsys0 CL 2114 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3292 clock-names = "apb", 2115 clock-names = "apb", "smi", "gals";
3293 power-domains = <&spm 2116 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294 }; 2117 };
3295 2118
3296 vdosys1: syscon@1c100000 { 2119 vdosys1: syscon@1c100000 {
3297 compatible = "mediate 2120 compatible = "mediatek,mt8195-vdosys1", "syscon";
3298 reg = <0 0x1c100000 0 2121 reg = <0 0x1c100000 0 0x1000>;
3299 mboxes = <&gce0 1 CMD <<
3300 mediatek,gce-client-r <<
3301 #clock-cells = <1>; 2122 #clock-cells = <1>;
3302 #reset-cells = <1>; <<
3303 }; 2123 };
3304 2124
3305 smi_common_vdo: smi@1c01b000 2125 smi_common_vdo: smi@1c01b000 {
3306 compatible = "mediate 2126 compatible = "mediatek,mt8195-smi-common-vdo";
3307 reg = <0 0x1c01b000 0 2127 reg = <0 0x1c01b000 0 0x1000>;
3308 clocks = <&vdosys0 CL 2128 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3309 <&vdosys0 CL 2129 <&vdosys0 CLK_VDO0_SMI_EMI>,
3310 <&vdosys0 CL 2130 <&vdosys0 CLK_VDO0_SMI_RSI>,
3311 <&vdosys0 CL 2131 <&vdosys0 CLK_VDO0_SMI_GALS>;
3312 clock-names = "apb", 2132 clock-names = "apb", "smi", "gals0", "gals1";
3313 power-domains = <&spm 2133 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3314 2134
3315 }; 2135 };
3316 2136
3317 iommu_vdo: iommu@1c01f000 { 2137 iommu_vdo: iommu@1c01f000 {
3318 compatible = "mediate 2138 compatible = "mediatek,mt8195-iommu-vdo";
3319 reg = <0 0x1c01f000 0 2139 reg = <0 0x1c01f000 0 0x1000>;
3320 mediatek,larbs = <&la 2140 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3321 &la 2141 &larb10 &larb11 &larb13 &larb17
3322 &la 2142 &larb19 &larb21 &larb24 &larb25
3323 &la 2143 &larb28>;
3324 interrupts = <GIC_SPI 2144 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3325 #iommu-cells = <1>; 2145 #iommu-cells = <1>;
3326 clocks = <&vdosys0 CL 2146 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3327 clock-names = "bclk"; 2147 clock-names = "bclk";
3328 power-domains = <&spm 2148 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3329 }; 2149 };
3330 2150
3331 mutex1: mutex@1c101000 { <<
3332 compatible = "mediate <<
3333 reg = <0 0x1c101000 0 <<
3334 reg-names = "vdo1_mut <<
3335 interrupts = <GIC_SPI <<
3336 power-domains = <&spm <<
3337 clocks = <&vdosys1 CL <<
3338 clock-names = "vdo1_m <<
3339 mediatek,gce-client-r <<
3340 mediatek,gce-events = <<
3341 }; <<
3342 <<
3343 larb2: larb@1c102000 { 2151 larb2: larb@1c102000 {
3344 compatible = "mediate 2152 compatible = "mediatek,mt8195-smi-larb";
3345 reg = <0 0x1c102000 0 2153 reg = <0 0x1c102000 0 0x1000>;
3346 mediatek,larb-id = <2 2154 mediatek,larb-id = <2>;
3347 mediatek,smi = <&smi_ 2155 mediatek,smi = <&smi_common_vdo>;
3348 clocks = <&vdosys1 CL 2156 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CL 2157 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3350 <&vdosys1 CL 2158 <&vdosys1 CLK_VDO1_GALS>;
3351 clock-names = "apb", 2159 clock-names = "apb", "smi", "gals";
3352 power-domains = <&spm 2160 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3353 }; 2161 };
3354 2162
3355 larb3: larb@1c103000 { 2163 larb3: larb@1c103000 {
3356 compatible = "mediate 2164 compatible = "mediatek,mt8195-smi-larb";
3357 reg = <0 0x1c103000 0 2165 reg = <0 0x1c103000 0 0x1000>;
3358 mediatek,larb-id = <3 2166 mediatek,larb-id = <3>;
3359 mediatek,smi = <&smi_ 2167 mediatek,smi = <&smi_common_vpp>;
3360 clocks = <&vdosys1 CL 2168 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3361 <&vdosys1 CL 2169 <&vdosys1 CLK_VDO1_GALS>,
3362 <&vppsys0 CL 2170 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3363 clock-names = "apb", 2171 clock-names = "apb", "smi", "gals";
3364 power-domains = <&spm 2172 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3365 }; <<
3366 <<
3367 vdo1_rdma0: dma-controller@1c <<
3368 compatible = "mediate <<
3369 reg = <0 0x1c104000 0 <<
3370 interrupts = <GIC_SPI <<
3371 clocks = <&vdosys1 CL <<
3372 power-domains = <&spm <<
3373 iommus = <&iommu_vdo <<
3374 mediatek,gce-client-r <<
3375 #dma-cells = <1>; <<
3376 }; <<
3377 <<
3378 vdo1_rdma1: dma-controller@1c <<
3379 compatible = "mediate <<
3380 reg = <0 0x1c105000 0 <<
3381 interrupts = <GIC_SPI <<
3382 clocks = <&vdosys1 CL <<
3383 power-domains = <&spm <<
3384 iommus = <&iommu_vpp <<
3385 mediatek,gce-client-r <<
3386 #dma-cells = <1>; <<
3387 }; <<
3388 <<
3389 vdo1_rdma2: dma-controller@1c <<
3390 compatible = "mediate <<
3391 reg = <0 0x1c106000 0 <<
3392 interrupts = <GIC_SPI <<
3393 clocks = <&vdosys1 CL <<
3394 power-domains = <&spm <<
3395 iommus = <&iommu_vdo <<
3396 mediatek,gce-client-r <<
3397 #dma-cells = <1>; <<
3398 }; <<
3399 <<
3400 vdo1_rdma3: dma-controller@1c <<
3401 compatible = "mediate <<
3402 reg = <0 0x1c107000 0 <<
3403 interrupts = <GIC_SPI <<
3404 clocks = <&vdosys1 CL <<
3405 power-domains = <&spm <<
3406 iommus = <&iommu_vpp <<
3407 mediatek,gce-client-r <<
3408 #dma-cells = <1>; <<
3409 }; <<
3410 <<
3411 vdo1_rdma4: dma-controller@1c <<
3412 compatible = "mediate <<
3413 reg = <0 0x1c108000 0 <<
3414 interrupts = <GIC_SPI <<
3415 clocks = <&vdosys1 CL <<
3416 power-domains = <&spm <<
3417 iommus = <&iommu_vdo <<
3418 mediatek,gce-client-r <<
3419 #dma-cells = <1>; <<
3420 }; <<
3421 <<
3422 vdo1_rdma5: dma-controller@1c <<
3423 compatible = "mediate <<
3424 reg = <0 0x1c109000 0 <<
3425 interrupts = <GIC_SPI <<
3426 clocks = <&vdosys1 CL <<
3427 power-domains = <&spm <<
3428 iommus = <&iommu_vpp <<
3429 mediatek,gce-client-r <<
3430 #dma-cells = <1>; <<
3431 }; <<
3432 <<
3433 vdo1_rdma6: dma-controller@1c <<
3434 compatible = "mediate <<
3435 reg = <0 0x1c10a000 0 <<
3436 interrupts = <GIC_SPI <<
3437 clocks = <&vdosys1 CL <<
3438 power-domains = <&spm <<
3439 iommus = <&iommu_vdo <<
3440 mediatek,gce-client-r <<
3441 #dma-cells = <1>; <<
3442 }; <<
3443 <<
3444 vdo1_rdma7: dma-controller@1c <<
3445 compatible = "mediate <<
3446 reg = <0 0x1c10b000 0 <<
3447 interrupts = <GIC_SPI <<
3448 clocks = <&vdosys1 CL <<
3449 power-domains = <&spm <<
3450 iommus = <&iommu_vpp <<
3451 mediatek,gce-client-r <<
3452 #dma-cells = <1>; <<
3453 }; <<
3454 <<
3455 merge1: vpp-merge@1c10c000 { <<
3456 compatible = "mediate <<
3457 reg = <0 0x1c10c000 0 <<
3458 interrupts = <GIC_SPI <<
3459 clocks = <&vdosys1 CL <<
3460 <&vdosys1 CL <<
3461 clock-names = "merge" <<
3462 power-domains = <&spm <<
3463 mediatek,gce-client-r <<
3464 mediatek,merge-mute; <<
3465 resets = <&vdosys1 MT <<
3466 }; <<
3467 <<
3468 merge2: vpp-merge@1c10d000 { <<
3469 compatible = "mediate <<
3470 reg = <0 0x1c10d000 0 <<
3471 interrupts = <GIC_SPI <<
3472 clocks = <&vdosys1 CL <<
3473 <&vdosys1 CL <<
3474 clock-names = "merge" <<
3475 power-domains = <&spm <<
3476 mediatek,gce-client-r <<
3477 mediatek,merge-mute; <<
3478 resets = <&vdosys1 MT <<
3479 }; <<
3480 <<
3481 merge3: vpp-merge@1c10e000 { <<
3482 compatible = "mediate <<
3483 reg = <0 0x1c10e000 0 <<
3484 interrupts = <GIC_SPI <<
3485 clocks = <&vdosys1 CL <<
3486 <&vdosys1 CL <<
3487 clock-names = "merge" <<
3488 power-domains = <&spm <<
3489 mediatek,gce-client-r <<
3490 mediatek,merge-mute; <<
3491 resets = <&vdosys1 MT <<
3492 }; <<
3493 <<
3494 merge4: vpp-merge@1c10f000 { <<
3495 compatible = "mediate <<
3496 reg = <0 0x1c10f000 0 <<
3497 interrupts = <GIC_SPI <<
3498 clocks = <&vdosys1 CL <<
3499 <&vdosys1 CL <<
3500 clock-names = "merge" <<
3501 power-domains = <&spm <<
3502 mediatek,gce-client-r <<
3503 mediatek,merge-mute; <<
3504 resets = <&vdosys1 MT <<
3505 }; <<
3506 <<
3507 merge5: vpp-merge@1c110000 { <<
3508 compatible = "mediate <<
3509 reg = <0 0x1c110000 0 <<
3510 interrupts = <GIC_SPI <<
3511 clocks = <&vdosys1 CL <<
3512 <&vdosys1 CL <<
3513 clock-names = "merge" <<
3514 power-domains = <&spm <<
3515 mediatek,gce-client-r <<
3516 mediatek,merge-fifo-e <<
3517 resets = <&vdosys1 MT <<
3518 }; <<
3519 <<
3520 dp_intf1: dp-intf@1c113000 { <<
3521 compatible = "mediate <<
3522 reg = <0 0x1c113000 0 <<
3523 interrupts = <GIC_SPI <<
3524 power-domains = <&spm <<
3525 clocks = <&vdosys1 CL <<
3526 <&vdosys1 CL <<
3527 <&apmixedsys <<
3528 clock-names = "pixel" <<
3529 status = "disabled"; <<
3530 }; <<
3531 <<
3532 ethdr0: hdr-engine@1c114000 { <<
3533 compatible = "mediate <<
3534 reg = <0 0x1c114000 0 <<
3535 <0 0x1c115000 0 <<
3536 <0 0x1c117000 0 <<
3537 <0 0x1c119000 0 <<
3538 <0 0x1c11a000 0 <<
3539 <0 0x1c11b000 0 <<
3540 <0 0x1c11c000 0 <<
3541 reg-names = "mixer", <<
3542 "vdo_be", <<
3543 mediatek,gce-client-r <<
3544 <<
3545 <<
3546 <<
3547 <<
3548 <<
3549 <<
3550 clocks = <&vdosys1 CL <<
3551 <&vdosys1 CL <<
3552 <&vdosys1 CL <<
3553 <&vdosys1 CL <<
3554 <&vdosys1 CL <<
3555 <&vdosys1 CL <<
3556 <&vdosys1 CL <<
3557 <&vdosys1 CL <<
3558 <&vdosys1 CL <<
3559 <&vdosys1 CL <<
3560 <&vdosys1 CL <<
3561 <&vdosys1 CL <<
3562 <&topckgen C <<
3563 clock-names = "mixer" <<
3564 "vdo_be <<
3565 "gfx_fe <<
3566 "ethdr_ <<
3567 power-domains = <&spm <<
3568 iommus = <&iommu_vpp <<
3569 <&iommu_vpp <<
3570 interrupts = <GIC_SPI <<
3571 resets = <&vdosys1 MT <<
3572 <&vdosys1 MT <<
3573 <&vdosys1 MT <<
3574 <&vdosys1 MT <<
3575 <&vdosys1 MT <<
3576 reset-names = "vdo_fe <<
3577 "gfx_fe <<
3578 }; <<
3579 <<
3580 edp_tx: edp-tx@1c500000 { <<
3581 compatible = "mediate <<
3582 reg = <0 0x1c500000 0 <<
3583 nvmem-cells = <&dp_ca <<
3584 nvmem-cell-names = "d <<
3585 power-domains = <&spm <<
3586 interrupts = <GIC_SPI <<
3587 max-linkrate-mhz = <8 <<
3588 status = "disabled"; <<
3589 }; <<
3590 <<
3591 dp_tx: dp-tx@1c600000 { <<
3592 compatible = "mediate <<
3593 reg = <0 0x1c600000 0 <<
3594 nvmem-cells = <&dp_ca <<
3595 nvmem-cell-names = "d <<
3596 power-domains = <&spm <<
3597 interrupts = <GIC_SPI <<
3598 max-linkrate-mhz = <8 <<
3599 status = "disabled"; <<
3600 }; <<
3601 }; <<
3602 <<
3603 thermal_zones: thermal-zones { <<
3604 cpu0-thermal { <<
3605 polling-delay = <1000 <<
3606 polling-delay-passive <<
3607 thermal-sensors = <&l <<
3608 <<
3609 trips { <<
3610 cpu0_alert: t <<
3611 tempe <<
3612 hyste <<
3613 type <<
3614 }; <<
3615 <<
3616 cpu0_crit: tr <<
3617 tempe <<
3618 hyste <<
3619 type <<
3620 }; <<
3621 }; <<
3622 <<
3623 cooling-maps { <<
3624 map0 { <<
3625 trip <<
3626 cooli <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 <<
3634 cpu1-thermal { <<
3635 polling-delay = <1000 <<
3636 polling-delay-passive <<
3637 thermal-sensors = <&l <<
3638 <<
3639 trips { <<
3640 cpu1_alert: t <<
3641 tempe <<
3642 hyste <<
3643 type <<
3644 }; <<
3645 <<
3646 cpu1_crit: tr <<
3647 tempe <<
3648 hyste <<
3649 type <<
3650 }; <<
3651 }; <<
3652 <<
3653 cooling-maps { <<
3654 map0 { <<
3655 trip <<
3656 cooli <<
3657 <<
3658 <<
3659 <<
3660 }; <<
3661 }; <<
3662 }; <<
3663 <<
3664 cpu2-thermal { <<
3665 polling-delay = <1000 <<
3666 polling-delay-passive <<
3667 thermal-sensors = <&l <<
3668 <<
3669 trips { <<
3670 cpu2_alert: t <<
3671 tempe <<
3672 hyste <<
3673 type <<
3674 }; <<
3675 <<
3676 cpu2_crit: tr <<
3677 tempe <<
3678 hyste <<
3679 type <<
3680 }; <<
3681 }; <<
3682 <<
3683 cooling-maps { <<
3684 map0 { <<
3685 trip <<
3686 cooli <<
3687 <<
3688 <<
3689 <<
3690 }; <<
3691 }; <<
3692 }; <<
3693 <<
3694 cpu3-thermal { <<
3695 polling-delay = <1000 <<
3696 polling-delay-passive <<
3697 thermal-sensors = <&l <<
3698 <<
3699 trips { <<
3700 cpu3_alert: t <<
3701 tempe <<
3702 hyste <<
3703 type <<
3704 }; <<
3705 <<
3706 cpu3_crit: tr <<
3707 tempe <<
3708 hyste <<
3709 type <<
3710 }; <<
3711 }; <<
3712 <<
3713 cooling-maps { <<
3714 map0 { <<
3715 trip <<
3716 cooli <<
3717 <<
3718 <<
3719 <<
3720 }; <<
3721 }; <<
3722 }; <<
3723 <<
3724 cpu4-thermal { <<
3725 polling-delay = <1000 <<
3726 polling-delay-passive <<
3727 thermal-sensors = <&l <<
3728 <<
3729 trips { <<
3730 cpu4_alert: t <<
3731 tempe <<
3732 hyste <<
3733 type <<
3734 }; <<
3735 <<
3736 cpu4_crit: tr <<
3737 tempe <<
3738 hyste <<
3739 type <<
3740 }; <<
3741 }; <<
3742 <<
3743 cooling-maps { <<
3744 map0 { <<
3745 trip <<
3746 cooli <<
3747 <<
3748 <<
3749 <<
3750 }; <<
3751 }; <<
3752 }; <<
3753 <<
3754 cpu5-thermal { <<
3755 polling-delay = <1000 <<
3756 polling-delay-passive <<
3757 thermal-sensors = <&l <<
3758 <<
3759 trips { <<
3760 cpu5_alert: t <<
3761 tempe <<
3762 hyste <<
3763 type <<
3764 }; <<
3765 <<
3766 cpu5_crit: tr <<
3767 tempe <<
3768 hyste <<
3769 type <<
3770 }; <<
3771 }; <<
3772 <<
3773 cooling-maps { <<
3774 map0 { <<
3775 trip <<
3776 cooli <<
3777 <<
3778 <<
3779 <<
3780 }; <<
3781 }; <<
3782 }; <<
3783 <<
3784 cpu6-thermal { <<
3785 polling-delay = <1000 <<
3786 polling-delay-passive <<
3787 thermal-sensors = <&l <<
3788 <<
3789 trips { <<
3790 cpu6_alert: t <<
3791 tempe <<
3792 hyste <<
3793 type <<
3794 }; <<
3795 <<
3796 cpu6_crit: tr <<
3797 tempe <<
3798 hyste <<
3799 type <<
3800 }; <<
3801 }; <<
3802 <<
3803 cooling-maps { <<
3804 map0 { <<
3805 trip <<
3806 cooli <<
3807 <<
3808 <<
3809 <<
3810 }; <<
3811 }; <<
3812 }; <<
3813 <<
3814 cpu7-thermal { <<
3815 polling-delay = <1000 <<
3816 polling-delay-passive <<
3817 thermal-sensors = <&l <<
3818 <<
3819 trips { <<
3820 cpu7_alert: t <<
3821 tempe <<
3822 hyste <<
3823 type <<
3824 }; <<
3825 <<
3826 cpu7_crit: tr <<
3827 tempe <<
3828 hyste <<
3829 type <<
3830 }; <<
3831 }; <<
3832 <<
3833 cooling-maps { <<
3834 map0 { <<
3835 trip <<
3836 cooli <<
3837 <<
3838 <<
3839 <<
3840 }; <<
3841 }; <<
3842 }; <<
3843 <<
3844 vpu0-thermal { <<
3845 polling-delay = <1000 <<
3846 polling-delay-passive <<
3847 thermal-sensors = <&l <<
3848 <<
3849 trips { <<
3850 vpu0_alert: t <<
3851 tempe <<
3852 hyste <<
3853 type <<
3854 }; <<
3855 <<
3856 vpu0_crit: tr <<
3857 tempe <<
3858 hyste <<
3859 type <<
3860 }; <<
3861 }; <<
3862 }; <<
3863 <<
3864 vpu1-thermal { <<
3865 polling-delay = <1000 <<
3866 polling-delay-passive <<
3867 thermal-sensors = <&l <<
3868 <<
3869 trips { <<
3870 vpu1_alert: t <<
3871 tempe <<
3872 hyste <<
3873 type <<
3874 }; <<
3875 <<
3876 vpu1_crit: tr <<
3877 tempe <<
3878 hyste <<
3879 type <<
3880 }; <<
3881 }; <<
3882 }; <<
3883 <<
3884 gpu-thermal { <<
3885 polling-delay = <1000 <<
3886 polling-delay-passive <<
3887 thermal-sensors = <&l <<
3888 <<
3889 trips { <<
3890 gpu0_alert: t <<
3891 tempe <<
3892 hyste <<
3893 type <<
3894 }; <<
3895 <<
3896 gpu0_crit: tr <<
3897 tempe <<
3898 hyste <<
3899 type <<
3900 }; <<
3901 }; <<
3902 }; <<
3903 <<
3904 gpu1-thermal { <<
3905 polling-delay = <1000 <<
3906 polling-delay-passive <<
3907 thermal-sensors = <&l <<
3908 <<
3909 trips { <<
3910 gpu1_alert: t <<
3911 tempe <<
3912 hyste <<
3913 type <<
3914 }; <<
3915 <<
3916 gpu1_crit: tr <<
3917 tempe <<
3918 hyste <<
3919 type <<
3920 }; <<
3921 }; <<
3922 }; <<
3923 <<
3924 vdec-thermal { <<
3925 polling-delay = <1000 <<
3926 polling-delay-passive <<
3927 thermal-sensors = <&l <<
3928 <<
3929 trips { <<
3930 vdec_alert: t <<
3931 tempe <<
3932 hyste <<
3933 type <<
3934 }; <<
3935 <<
3936 vdec_crit: tr <<
3937 tempe <<
3938 hyste <<
3939 type <<
3940 }; <<
3941 }; <<
3942 }; <<
3943 <<
3944 img-thermal { <<
3945 polling-delay = <1000 <<
3946 polling-delay-passive <<
3947 thermal-sensors = <&l <<
3948 <<
3949 trips { <<
3950 img_alert: tr <<
3951 tempe <<
3952 hyste <<
3953 type <<
3954 }; <<
3955 <<
3956 img_crit: tri <<
3957 tempe <<
3958 hyste <<
3959 type <<
3960 }; <<
3961 }; <<
3962 }; <<
3963 <<
3964 infra-thermal { <<
3965 polling-delay = <1000 <<
3966 polling-delay-passive <<
3967 thermal-sensors = <&l <<
3968 <<
3969 trips { <<
3970 infra_alert: <<
3971 tempe <<
3972 hyste <<
3973 type <<
3974 }; <<
3975 <<
3976 infra_crit: t <<
3977 tempe <<
3978 hyste <<
3979 type <<
3980 }; <<
3981 }; <<
3982 }; <<
3983 <<
3984 cam0-thermal { <<
3985 polling-delay = <1000 <<
3986 polling-delay-passive <<
3987 thermal-sensors = <&l <<
3988 <<
3989 trips { <<
3990 cam0_alert: t <<
3991 tempe <<
3992 hyste <<
3993 type <<
3994 }; <<
3995 <<
3996 cam0_crit: tr <<
3997 tempe <<
3998 hyste <<
3999 type <<
4000 }; <<
4001 }; <<
4002 }; <<
4003 <<
4004 cam1-thermal { <<
4005 polling-delay = <1000 <<
4006 polling-delay-passive <<
4007 thermal-sensors = <&l <<
4008 <<
4009 trips { <<
4010 cam1_alert: t <<
4011 tempe <<
4012 hyste <<
4013 type <<
4014 }; <<
4015 <<
4016 cam1_crit: tr <<
4017 tempe <<
4018 hyste <<
4019 type <<
4020 }; <<
4021 }; <<
4022 }; 2173 };
4023 }; 2174 };
4024 }; 2175 };
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