1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 MediaTek Inc. 3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com> 4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h> 8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h> 9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-por 12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h> 15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h> 16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h> <<
18 #include <dt-bindings/thermal/mediatek,lvts-th <<
19 17
20 / { 18 / {
21 compatible = "mediatek,mt8195"; 19 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
23 #address-cells = <2>; 21 #address-cells = <2>;
24 #size-cells = <2>; 22 #size-cells = <2>;
25 23
26 aliases { 24 aliases {
27 dp-intf0 = &dp_intf0; <<
28 dp-intf1 = &dp_intf1; <<
29 gce0 = &gce0; 25 gce0 = &gce0;
30 gce1 = &gce1; 26 gce1 = &gce1;
31 ethdr0 = ðdr0; <<
32 mutex0 = &mutex; <<
33 mutex1 = &mutex1; <<
34 merge1 = &merge1; <<
35 merge2 = &merge2; <<
36 merge3 = &merge3; <<
37 merge4 = &merge4; <<
38 merge5 = &merge5; <<
39 vdo1-rdma0 = &vdo1_rdma0; <<
40 vdo1-rdma1 = &vdo1_rdma1; <<
41 vdo1-rdma2 = &vdo1_rdma2; <<
42 vdo1-rdma3 = &vdo1_rdma3; <<
43 vdo1-rdma4 = &vdo1_rdma4; <<
44 vdo1-rdma5 = &vdo1_rdma5; <<
45 vdo1-rdma6 = &vdo1_rdma6; <<
46 vdo1-rdma7 = &vdo1_rdma7; <<
47 }; 27 };
48 28
49 cpus { 29 cpus {
50 #address-cells = <1>; 30 #address-cells = <1>;
51 #size-cells = <0>; 31 #size-cells = <0>;
52 32
53 cpu0: cpu@0 { 33 cpu0: cpu@0 {
54 device_type = "cpu"; 34 device_type = "cpu";
55 compatible = "arm,cort 35 compatible = "arm,cortex-a55";
56 reg = <0x000>; 36 reg = <0x000>;
57 enable-method = "psci" 37 enable-method = "psci";
58 performance-domains = 38 performance-domains = <&performance 0>;
59 clock-frequency = <170 39 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = < 40 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cp 41 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768> 42 i-cache-size = <32768>;
63 i-cache-line-size = <6 43 i-cache-line-size = <64>;
64 i-cache-sets = <128>; 44 i-cache-sets = <128>;
65 d-cache-size = <32768> 45 d-cache-size = <32768>;
66 d-cache-line-size = <6 46 d-cache-line-size = <64>;
67 d-cache-sets = <128>; 47 d-cache-sets = <128>;
68 next-level-cache = <&l 48 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>; 49 #cooling-cells = <2>;
70 }; 50 };
71 51
72 cpu1: cpu@100 { 52 cpu1: cpu@100 {
73 device_type = "cpu"; 53 device_type = "cpu";
74 compatible = "arm,cort 54 compatible = "arm,cortex-a55";
75 reg = <0x100>; 55 reg = <0x100>;
76 enable-method = "psci" 56 enable-method = "psci";
77 performance-domains = 57 performance-domains = <&performance 0>;
78 clock-frequency = <170 58 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = < 59 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cp 60 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768> 61 i-cache-size = <32768>;
82 i-cache-line-size = <6 62 i-cache-line-size = <64>;
83 i-cache-sets = <128>; 63 i-cache-sets = <128>;
84 d-cache-size = <32768> 64 d-cache-size = <32768>;
85 d-cache-line-size = <6 65 d-cache-line-size = <64>;
86 d-cache-sets = <128>; 66 d-cache-sets = <128>;
87 next-level-cache = <&l 67 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>; 68 #cooling-cells = <2>;
89 }; 69 };
90 70
91 cpu2: cpu@200 { 71 cpu2: cpu@200 {
92 device_type = "cpu"; 72 device_type = "cpu";
93 compatible = "arm,cort 73 compatible = "arm,cortex-a55";
94 reg = <0x200>; 74 reg = <0x200>;
95 enable-method = "psci" 75 enable-method = "psci";
96 performance-domains = 76 performance-domains = <&performance 0>;
97 clock-frequency = <170 77 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cp 79 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768> 80 i-cache-size = <32768>;
101 i-cache-line-size = <6 81 i-cache-line-size = <64>;
102 i-cache-sets = <128>; 82 i-cache-sets = <128>;
103 d-cache-size = <32768> 83 d-cache-size = <32768>;
104 d-cache-line-size = <6 84 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 85 d-cache-sets = <128>;
106 next-level-cache = <&l 86 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>; 87 #cooling-cells = <2>;
108 }; 88 };
109 89
110 cpu3: cpu@300 { 90 cpu3: cpu@300 {
111 device_type = "cpu"; 91 device_type = "cpu";
112 compatible = "arm,cort 92 compatible = "arm,cortex-a55";
113 reg = <0x300>; 93 reg = <0x300>;
114 enable-method = "psci" 94 enable-method = "psci";
115 performance-domains = 95 performance-domains = <&performance 0>;
116 clock-frequency = <170 96 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cp 98 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768> 99 i-cache-size = <32768>;
120 i-cache-line-size = <6 100 i-cache-line-size = <64>;
121 i-cache-sets = <128>; 101 i-cache-sets = <128>;
122 d-cache-size = <32768> 102 d-cache-size = <32768>;
123 d-cache-line-size = <6 103 d-cache-line-size = <64>;
124 d-cache-sets = <128>; 104 d-cache-sets = <128>;
125 next-level-cache = <&l 105 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>; 106 #cooling-cells = <2>;
127 }; 107 };
128 108
129 cpu4: cpu@400 { 109 cpu4: cpu@400 {
130 device_type = "cpu"; 110 device_type = "cpu";
131 compatible = "arm,cort 111 compatible = "arm,cortex-a78";
132 reg = <0x400>; 112 reg = <0x400>;
133 enable-method = "psci" 113 enable-method = "psci";
134 performance-domains = 114 performance-domains = <&performance 1>;
135 clock-frequency = <217 115 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = < 116 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cp 117 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536> 118 i-cache-size = <65536>;
139 i-cache-line-size = <6 119 i-cache-line-size = <64>;
140 i-cache-sets = <256>; 120 i-cache-sets = <256>;
141 d-cache-size = <65536> 121 d-cache-size = <65536>;
142 d-cache-line-size = <6 122 d-cache-line-size = <64>;
143 d-cache-sets = <256>; 123 d-cache-sets = <256>;
144 next-level-cache = <&l 124 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>; 125 #cooling-cells = <2>;
146 }; 126 };
147 127
148 cpu5: cpu@500 { 128 cpu5: cpu@500 {
149 device_type = "cpu"; 129 device_type = "cpu";
150 compatible = "arm,cort 130 compatible = "arm,cortex-a78";
151 reg = <0x500>; 131 reg = <0x500>;
152 enable-method = "psci" 132 enable-method = "psci";
153 performance-domains = 133 performance-domains = <&performance 1>;
154 clock-frequency = <217 134 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = < 135 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cp 136 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536> 137 i-cache-size = <65536>;
158 i-cache-line-size = <6 138 i-cache-line-size = <64>;
159 i-cache-sets = <256>; 139 i-cache-sets = <256>;
160 d-cache-size = <65536> 140 d-cache-size = <65536>;
161 d-cache-line-size = <6 141 d-cache-line-size = <64>;
162 d-cache-sets = <256>; 142 d-cache-sets = <256>;
163 next-level-cache = <&l 143 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>; 144 #cooling-cells = <2>;
165 }; 145 };
166 146
167 cpu6: cpu@600 { 147 cpu6: cpu@600 {
168 device_type = "cpu"; 148 device_type = "cpu";
169 compatible = "arm,cort 149 compatible = "arm,cortex-a78";
170 reg = <0x600>; 150 reg = <0x600>;
171 enable-method = "psci" 151 enable-method = "psci";
172 performance-domains = 152 performance-domains = <&performance 1>;
173 clock-frequency = <217 153 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = < 154 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cp 155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536> 156 i-cache-size = <65536>;
177 i-cache-line-size = <6 157 i-cache-line-size = <64>;
178 i-cache-sets = <256>; 158 i-cache-sets = <256>;
179 d-cache-size = <65536> 159 d-cache-size = <65536>;
180 d-cache-line-size = <6 160 d-cache-line-size = <64>;
181 d-cache-sets = <256>; 161 d-cache-sets = <256>;
182 next-level-cache = <&l 162 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>; 163 #cooling-cells = <2>;
184 }; 164 };
185 165
186 cpu7: cpu@700 { 166 cpu7: cpu@700 {
187 device_type = "cpu"; 167 device_type = "cpu";
188 compatible = "arm,cort 168 compatible = "arm,cortex-a78";
189 reg = <0x700>; 169 reg = <0x700>;
190 enable-method = "psci" 170 enable-method = "psci";
191 performance-domains = 171 performance-domains = <&performance 1>;
192 clock-frequency = <217 172 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = < 173 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cp 174 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536> 175 i-cache-size = <65536>;
196 i-cache-line-size = <6 176 i-cache-line-size = <64>;
197 i-cache-sets = <256>; 177 i-cache-sets = <256>;
198 d-cache-size = <65536> 178 d-cache-size = <65536>;
199 d-cache-line-size = <6 179 d-cache-line-size = <64>;
200 d-cache-sets = <256>; 180 d-cache-sets = <256>;
201 next-level-cache = <&l 181 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>; 182 #cooling-cells = <2>;
203 }; 183 };
204 184
205 cpu-map { 185 cpu-map {
206 cluster0 { 186 cluster0 {
207 core0 { 187 core0 {
208 cpu = 188 cpu = <&cpu0>;
209 }; 189 };
210 190
211 core1 { 191 core1 {
212 cpu = 192 cpu = <&cpu1>;
213 }; 193 };
214 194
215 core2 { 195 core2 {
216 cpu = 196 cpu = <&cpu2>;
217 }; 197 };
218 198
219 core3 { 199 core3 {
220 cpu = 200 cpu = <&cpu3>;
221 }; 201 };
222 202
223 core4 { 203 core4 {
224 cpu = 204 cpu = <&cpu4>;
225 }; 205 };
226 206
227 core5 { 207 core5 {
228 cpu = 208 cpu = <&cpu5>;
229 }; 209 };
230 210
231 core6 { 211 core6 {
232 cpu = 212 cpu = <&cpu6>;
233 }; 213 };
234 214
235 core7 { 215 core7 {
236 cpu = 216 cpu = <&cpu7>;
237 }; 217 };
238 }; 218 };
239 }; 219 };
240 220
241 idle-states { 221 idle-states {
242 entry-method = "psci"; 222 entry-method = "psci";
243 223
244 cpu_ret_l: cpu-retenti 224 cpu_ret_l: cpu-retention-l {
245 compatible = " 225 compatible = "arm,idle-state";
246 arm,psci-suspe 226 arm,psci-suspend-param = <0x00010001>;
247 local-timer-st 227 local-timer-stop;
248 entry-latency- 228 entry-latency-us = <50>;
249 exit-latency-u 229 exit-latency-us = <95>;
250 min-residency- 230 min-residency-us = <580>;
251 }; 231 };
252 232
253 cpu_ret_b: cpu-retenti 233 cpu_ret_b: cpu-retention-b {
254 compatible = " 234 compatible = "arm,idle-state";
255 arm,psci-suspe 235 arm,psci-suspend-param = <0x00010001>;
256 local-timer-st 236 local-timer-stop;
257 entry-latency- 237 entry-latency-us = <45>;
258 exit-latency-u 238 exit-latency-us = <140>;
259 min-residency- 239 min-residency-us = <740>;
260 }; 240 };
261 241
262 cpu_off_l: cpu-off-l { 242 cpu_off_l: cpu-off-l {
263 compatible = " 243 compatible = "arm,idle-state";
264 arm,psci-suspe 244 arm,psci-suspend-param = <0x01010002>;
265 local-timer-st 245 local-timer-stop;
266 entry-latency- 246 entry-latency-us = <55>;
267 exit-latency-u 247 exit-latency-us = <155>;
268 min-residency- 248 min-residency-us = <840>;
269 }; 249 };
270 250
271 cpu_off_b: cpu-off-b { 251 cpu_off_b: cpu-off-b {
272 compatible = " 252 compatible = "arm,idle-state";
273 arm,psci-suspe 253 arm,psci-suspend-param = <0x01010002>;
274 local-timer-st 254 local-timer-stop;
275 entry-latency- 255 entry-latency-us = <50>;
276 exit-latency-u 256 exit-latency-us = <200>;
277 min-residency- 257 min-residency-us = <1000>;
278 }; 258 };
279 }; 259 };
280 260
281 l2_0: l2-cache0 { 261 l2_0: l2-cache0 {
282 compatible = "cache"; 262 compatible = "cache";
283 cache-level = <2>; 263 cache-level = <2>;
284 cache-size = <131072>; 264 cache-size = <131072>;
285 cache-line-size = <64> 265 cache-line-size = <64>;
286 cache-sets = <512>; 266 cache-sets = <512>;
287 next-level-cache = <&l 267 next-level-cache = <&l3_0>;
288 cache-unified; <<
289 }; 268 };
290 269
291 l2_1: l2-cache1 { 270 l2_1: l2-cache1 {
292 compatible = "cache"; 271 compatible = "cache";
293 cache-level = <2>; 272 cache-level = <2>;
294 cache-size = <262144>; 273 cache-size = <262144>;
295 cache-line-size = <64> 274 cache-line-size = <64>;
296 cache-sets = <512>; 275 cache-sets = <512>;
297 next-level-cache = <&l 276 next-level-cache = <&l3_0>;
298 cache-unified; <<
299 }; 277 };
300 278
301 l3_0: l3-cache { 279 l3_0: l3-cache {
302 compatible = "cache"; 280 compatible = "cache";
303 cache-level = <3>; 281 cache-level = <3>;
304 cache-size = <2097152> 282 cache-size = <2097152>;
305 cache-line-size = <64> 283 cache-line-size = <64>;
306 cache-sets = <2048>; 284 cache-sets = <2048>;
307 cache-unified; 285 cache-unified;
308 }; 286 };
309 }; 287 };
310 288
311 dsu-pmu { 289 dsu-pmu {
312 compatible = "arm,dsu-pmu"; 290 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_T 291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu 292 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu 293 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail"; <<
317 }; 294 };
318 295
319 dmic_codec: dmic-codec { 296 dmic_codec: dmic-codec {
320 compatible = "dmic-codec"; 297 compatible = "dmic-codec";
321 num-channels = <2>; 298 num-channels = <2>;
322 wakeup-delay-ms = <50>; 299 wakeup-delay-ms = <50>;
323 }; 300 };
324 301
325 sound: mt8195-sound { 302 sound: mt8195-sound {
326 mediatek,platform = <&afe>; 303 mediatek,platform = <&afe>;
327 status = "disabled"; 304 status = "disabled";
328 }; 305 };
329 306
330 clk13m: fixed-factor-clock-13m { 307 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clo 308 compatible = "fixed-factor-clock";
332 #clock-cells = <0>; 309 #clock-cells = <0>;
333 clocks = <&clk26m>; 310 clocks = <&clk26m>;
334 clock-div = <2>; 311 clock-div = <2>;
335 clock-mult = <1>; 312 clock-mult = <1>;
336 clock-output-names = "clk13m"; 313 clock-output-names = "clk13m";
337 }; 314 };
338 315
339 clk26m: oscillator-26m { 316 clk26m: oscillator-26m {
340 compatible = "fixed-clock"; 317 compatible = "fixed-clock";
341 #clock-cells = <0>; 318 #clock-cells = <0>;
342 clock-frequency = <26000000>; 319 clock-frequency = <26000000>;
343 clock-output-names = "clk26m"; 320 clock-output-names = "clk26m";
344 }; 321 };
345 322
346 clk32k: oscillator-32k { 323 clk32k: oscillator-32k {
347 compatible = "fixed-clock"; 324 compatible = "fixed-clock";
348 #clock-cells = <0>; 325 #clock-cells = <0>;
349 clock-frequency = <32768>; 326 clock-frequency = <32768>;
350 clock-output-names = "clk32k"; 327 clock-output-names = "clk32k";
351 }; 328 };
352 329
353 performance: performance-controller@11 330 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq 331 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, 332 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1 333 #performance-domain-cells = <1>;
357 }; 334 };
358 335
359 gpu_opp_table: opp-table-gpu { <<
360 compatible = "operating-points <<
361 opp-shared; <<
362 <<
363 opp-390000000 { <<
364 opp-hz = /bits/ 64 <39 <<
365 opp-microvolt = <62500 <<
366 }; <<
367 opp-410000000 { <<
368 opp-hz = /bits/ 64 <41 <<
369 opp-microvolt = <63125 <<
370 }; <<
371 opp-431000000 { <<
372 opp-hz = /bits/ 64 <43 <<
373 opp-microvolt = <63125 <<
374 }; <<
375 opp-473000000 { <<
376 opp-hz = /bits/ 64 <47 <<
377 opp-microvolt = <63750 <<
378 }; <<
379 opp-515000000 { <<
380 opp-hz = /bits/ 64 <51 <<
381 opp-microvolt = <63750 <<
382 }; <<
383 opp-556000000 { <<
384 opp-hz = /bits/ 64 <55 <<
385 opp-microvolt = <64375 <<
386 }; <<
387 opp-598000000 { <<
388 opp-hz = /bits/ 64 <59 <<
389 opp-microvolt = <65000 <<
390 }; <<
391 opp-640000000 { <<
392 opp-hz = /bits/ 64 <64 <<
393 opp-microvolt = <65000 <<
394 }; <<
395 opp-670000000 { <<
396 opp-hz = /bits/ 64 <67 <<
397 opp-microvolt = <66250 <<
398 }; <<
399 opp-700000000 { <<
400 opp-hz = /bits/ 64 <70 <<
401 opp-microvolt = <67500 <<
402 }; <<
403 opp-730000000 { <<
404 opp-hz = /bits/ 64 <73 <<
405 opp-microvolt = <68750 <<
406 }; <<
407 opp-760000000 { <<
408 opp-hz = /bits/ 64 <76 <<
409 opp-microvolt = <70000 <<
410 }; <<
411 opp-790000000 { <<
412 opp-hz = /bits/ 64 <79 <<
413 opp-microvolt = <71250 <<
414 }; <<
415 opp-820000000 { <<
416 opp-hz = /bits/ 64 <82 <<
417 opp-microvolt = <72500 <<
418 }; <<
419 opp-850000000 { <<
420 opp-hz = /bits/ 64 <85 <<
421 opp-microvolt = <73750 <<
422 }; <<
423 opp-880000000 { <<
424 opp-hz = /bits/ 64 <88 <<
425 opp-microvolt = <75000 <<
426 }; <<
427 }; <<
428 <<
429 pmu-a55 { 336 pmu-a55 {
430 compatible = "arm,cortex-a55-p 337 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>; 338 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TY 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 }; 340 };
434 341
435 pmu-a78 { 342 pmu-a78 {
436 compatible = "arm,cortex-a78-p 343 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>; 344 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TY 345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 }; 346 };
440 347
441 psci { 348 psci {
442 compatible = "arm,psci-1.0"; 349 compatible = "arm,psci-1.0";
443 method = "smc"; 350 method = "smc";
444 }; 351 };
445 352
446 timer: timer { 353 timer: timer {
447 compatible = "arm,armv8-timer" 354 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>; 355 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_T 356 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_T 357 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_T 358 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_T 359 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 }; 360 };
454 361
455 soc { 362 soc {
456 #address-cells = <2>; 363 #address-cells = <2>;
457 #size-cells = <2>; 364 #size-cells = <2>;
458 compatible = "simple-bus"; 365 compatible = "simple-bus";
459 ranges; 366 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 <<
461 367
462 gic: interrupt-controller@c000 368 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic- 369 compatible = "arm,gic-v3";
464 #interrupt-cells = <4> 370 #interrupt-cells = <4>;
465 #redistributor-regions 371 #redistributor-regions = <1>;
466 interrupt-parent = <&g 372 interrupt-parent = <&gic>;
467 interrupt-controller; 373 interrupt-controller;
468 reg = <0 0x0c000000 0 374 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 375 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 376 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471 377
472 ppi-partitions { 378 ppi-partitions {
473 ppi_cluster0: 379 ppi_cluster0: interrupt-partition-0 {
474 affini 380 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 }; 381 };
476 382
477 ppi_cluster1: 383 ppi_cluster1: interrupt-partition-1 {
478 affini 384 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 }; 385 };
480 }; 386 };
481 }; 387 };
482 388
483 topckgen: syscon@10000000 { 389 topckgen: syscon@10000000 {
484 compatible = "mediatek 390 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 391 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>; 392 #clock-cells = <1>;
487 }; 393 };
488 394
489 infracfg_ao: syscon@10001000 { 395 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek 396 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
491 reg = <0 0x10001000 0 397 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>; 398 #clock-cells = <1>;
493 #reset-cells = <1>; 399 #reset-cells = <1>;
494 }; 400 };
495 401
496 pericfg: syscon@10003000 { 402 pericfg: syscon@10003000 {
497 compatible = "mediatek 403 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 404 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>; 405 #clock-cells = <1>;
500 }; 406 };
501 407
502 pio: pinctrl@10005000 { 408 pio: pinctrl@10005000 {
503 compatible = "mediatek 409 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 410 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 411 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 412 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 413 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 414 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 415 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 416 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 417 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", 418 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br" 419 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl" 420 "iocfg_tl", "eint";
515 gpio-controller; 421 gpio-controller;
516 #gpio-cells = <2>; 422 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 423 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller; 424 interrupt-controller;
519 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2> 426 #interrupt-cells = <2>;
521 }; 427 };
522 428
523 scpsys: syscon@10006000 { 429 scpsys: syscon@10006000 {
524 compatible = "mediatek 430 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 431 reg = <0 0x10006000 0 0x1000>;
526 432
527 /* System Power Manage 433 /* System Power Manager */
528 spm: power-controller 434 spm: power-controller {
529 compatible = " 435 compatible = "mediatek,mt8195-power-controller";
530 #address-cells 436 #address-cells = <1>;
531 #size-cells = 437 #size-cells = <0>;
532 #power-domain- 438 #power-domain-cells = <1>;
533 439
534 /* power domai 440 /* power domain of the SoC */
535 mfg0: power-do 441 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = 442 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #addre 443 #address-cells = <1>;
538 #size- 444 #size-cells = <0>;
539 #power 445 #power-domain-cells = <1>;
540 446
541 mfg1: !! 447 power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 448 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 !! 449 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
544 !! 450 clock-names = "mfg";
545 <<
546 451 mediatek,infracfg = <&infracfg_ao>;
547 452 #address-cells = <1>;
548 453 #size-cells = <0>;
549 454 #power-domain-cells = <1>;
550 455
551 456 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 457 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 458 #power-domain-cells = <0>;
554 459 };
555 460
556 461 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 462 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 463 #power-domain-cells = <0>;
559 464 };
560 465
561 466 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 467 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 468 #power-domain-cells = <0>;
564 469 };
565 470
566 471 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 472 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 473 #power-domain-cells = <0>;
569 474 };
570 475
571 476 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 477 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 478 #power-domain-cells = <0>;
574 479 };
575 }; 480 };
576 }; 481 };
577 482
578 power-domain@M 483 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = 484 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks 485 clocks = <&topckgen CLK_TOP_VPP>,
581 486 <&topckgen CLK_TOP_CAM>,
582 487 <&topckgen CLK_TOP_CCU>,
583 488 <&topckgen CLK_TOP_IMG>,
584 489 <&topckgen CLK_TOP_VENC>,
585 490 <&topckgen CLK_TOP_VDEC>,
586 491 <&topckgen CLK_TOP_WPE_VPP>,
587 492 <&topckgen CLK_TOP_CFG_VPP0>,
588 493 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 494 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 495 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 496 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 497 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 498 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 499 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 500 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 501 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 502 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 503 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 504 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 505 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 506 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 507 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 508 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 509 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 510 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 511 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock- 512 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 513 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 514 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 515 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 516 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 517 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 518 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 519 "vppsys0-18";
615 mediat 520 mediatek,infracfg = <&infracfg_ao>;
616 #addre 521 #address-cells = <1>;
617 #size- 522 #size-cells = <0>;
618 #power 523 #power-domain-cells = <1>;
619 524
620 power- 525 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 526 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 527 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 528 clock-names = "vdec1-0";
624 529 mediatek,infracfg = <&infracfg_ao>;
625 530 #power-domain-cells = <0>;
626 }; 531 };
627 532
628 power- 533 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 534 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 <<
631 <<
632 535 mediatek,infracfg = <&infracfg_ao>;
633 536 #power-domain-cells = <0>;
634 }; 537 };
635 538
636 power- 539 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 540 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 541 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 542 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 543 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 544 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 545 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 546 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 547 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 548 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 549 "vdosys0-2", "vdosys0-3",
647 550 "vdosys0-4", "vdosys0-5";
648 551 mediatek,infracfg = <&infracfg_ao>;
649 552 #address-cells = <1>;
650 553 #size-cells = <0>;
651 554 #power-domain-cells = <1>;
652 555
653 556 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 557 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 558 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 559 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 560 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 561 clock-names = "vppsys1", "vppsys1-0",
659 562 "vppsys1-1";
660 563 mediatek,infracfg = <&infracfg_ao>;
661 564 #power-domain-cells = <0>;
662 565 };
663 566
664 567 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 568 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 569 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 570 <&wpesys CLK_WPE_SMI_LARB8>,
668 571 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 572 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 573 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 574 "wepsys-3";
672 575 mediatek,infracfg = <&infracfg_ao>;
673 576 #power-domain-cells = <0>;
674 577 };
675 578
676 579 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 580 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 581 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 582 clock-names = "vdec0-0";
680 583 mediatek,infracfg = <&infracfg_ao>;
681 584 #power-domain-cells = <0>;
682 585 };
683 586
684 587 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 588 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 589 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 590 clock-names = "vdec2-0";
688 591 mediatek,infracfg = <&infracfg_ao>;
689 592 #power-domain-cells = <0>;
690 593 };
691 594
692 595 power-domain@MT8195_POWER_DOMAIN_VENC {
693 596 reg = <MT8195_POWER_DOMAIN_VENC>;
694 <<
695 <<
696 597 mediatek,infracfg = <&infracfg_ao>;
697 598 #power-domain-cells = <0>;
698 599 };
699 600
700 601 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 602 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 603 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 604 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 605 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 606 <&vdosys1 CLK_VDO1_GALS>;
706 607 clock-names = "vdosys1", "vdosys1-0",
707 608 "vdosys1-1", "vdosys1-2";
708 609 mediatek,infracfg = <&infracfg_ao>;
709 610 #address-cells = <1>;
710 611 #size-cells = <0>;
711 612 #power-domain-cells = <1>;
712 613
713 614 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 615 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 616 mediatek,infracfg = <&infracfg_ao>;
716 617 #power-domain-cells = <0>;
717 618 };
718 619
719 620 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 621 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 622 mediatek,infracfg = <&infracfg_ao>;
722 623 #power-domain-cells = <0>;
723 624 };
724 625
725 626 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 627 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 628 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 629 clock-names = "hdmi_tx";
729 630 #power-domain-cells = <0>;
730 631 };
731 632 };
732 633
733 634 power-domain@MT8195_POWER_DOMAIN_IMG {
734 635 reg = <MT8195_POWER_DOMAIN_IMG>;
735 636 clocks = <&imgsys CLK_IMG_LARB9>,
736 637 <&imgsys CLK_IMG_GALS>;
737 638 clock-names = "img-0", "img-1";
738 639 mediatek,infracfg = <&infracfg_ao>;
739 640 #address-cells = <1>;
740 641 #size-cells = <0>;
741 642 #power-domain-cells = <1>;
742 643
743 644 power-domain@MT8195_POWER_DOMAIN_DIP {
744 645 reg = <MT8195_POWER_DOMAIN_DIP>;
745 646 #power-domain-cells = <0>;
746 647 };
747 648
748 649 power-domain@MT8195_POWER_DOMAIN_IPE {
749 650 reg = <MT8195_POWER_DOMAIN_IPE>;
750 651 clocks = <&topckgen CLK_TOP_IPE>,
751 652 <&imgsys CLK_IMG_IPE>,
752 653 <&ipesys CLK_IPE_SMI_LARB12>;
753 654 clock-names = "ipe", "ipe-0", "ipe-1";
754 655 mediatek,infracfg = <&infracfg_ao>;
755 656 #power-domain-cells = <0>;
756 657 };
757 658 };
758 659
759 660 power-domain@MT8195_POWER_DOMAIN_CAM {
760 661 reg = <MT8195_POWER_DOMAIN_CAM>;
761 662 clocks = <&camsys CLK_CAM_LARB13>,
762 663 <&camsys CLK_CAM_LARB14>,
763 664 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 665 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 666 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 667 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 668 "cam-4";
768 669 mediatek,infracfg = <&infracfg_ao>;
769 670 #address-cells = <1>;
770 671 #size-cells = <0>;
771 672 #power-domain-cells = <1>;
772 673
773 674 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 675 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 676 #power-domain-cells = <0>;
776 677 };
777 678
778 679 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 680 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 681 #power-domain-cells = <0>;
781 682 };
782 683
783 684 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 685 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 686 #power-domain-cells = <0>;
786 687 };
787 688 };
788 }; 689 };
789 }; 690 };
790 691
791 power-domain@M 692 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = 693 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediat 694 mediatek,infracfg = <&infracfg_ao>;
794 #power 695 #power-domain-cells = <0>;
795 }; 696 };
796 697
797 power-domain@M 698 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = 699 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediat 700 mediatek,infracfg = <&infracfg_ao>;
800 #power 701 #power-domain-cells = <0>;
801 }; 702 };
802 703
803 power-domain@M 704 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = 705 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power 706 #power-domain-cells = <0>;
806 }; 707 };
807 708
808 power-domain@M 709 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = 710 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power 711 #power-domain-cells = <0>;
811 }; 712 };
812 713
813 power-domain@M 714 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = 715 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks 716 clocks = <&topckgen CLK_TOP_SENINF>,
816 717 <&topckgen CLK_TOP_SENINF2>;
817 clock- 718 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power 719 #power-domain-cells = <0>;
819 }; 720 };
820 721
821 power-domain@M 722 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = 723 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks 724 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock- 725 clock-names = "ether";
825 #power 726 #power-domain-cells = <0>;
826 }; 727 };
827 728
828 power-domain@M 729 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = 730 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks 731 clocks = <&topckgen CLK_TOP_ADSP>,
831 732 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock- 733 clock-names = "adsp", "adsp1";
833 #addre 734 #address-cells = <1>;
834 #size- 735 #size-cells = <0>;
835 mediat 736 mediatek,infracfg = <&infracfg_ao>;
836 #power 737 #power-domain-cells = <1>;
837 738
838 power- 739 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 740 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 741 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 742 <&topckgen CLK_TOP_AUD_INTBUS>,
842 743 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 744 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 745 clock-names = "audio", "audio1", "audio2",
845 746 "audio3";
846 747 mediatek,infracfg = <&infracfg_ao>;
847 748 #power-domain-cells = <0>;
848 }; 749 };
849 }; 750 };
850 }; 751 };
851 }; 752 };
852 753
853 watchdog: watchdog@10007000 { 754 watchdog: watchdog@10007000 {
854 compatible = "mediatek 755 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrs 756 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 757 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>; 758 #reset-cells = <1>;
858 }; 759 };
859 760
860 apmixedsys: syscon@1000c000 { 761 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek 762 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 763 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>; 764 #clock-cells = <1>;
864 }; 765 };
865 766
866 systimer: timer@10017000 { 767 systimer: timer@10017000 {
867 compatible = "mediatek 768 compatible = "mediatek,mt8195-timer",
868 "mediatek 769 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 770 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 771 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>; 772 clocks = <&clk13m>;
872 }; 773 };
873 774
874 pwrap: pwrap@10024000 { 775 pwrap: pwrap@10024000 {
875 compatible = "mediatek 776 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 777 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap"; 778 reg-names = "pwrap";
878 interrupts = <GIC_SPI 779 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao 780 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao 781 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", " 782 clock-names = "spi", "wrap";
882 assigned-clocks = <&to 783 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents 784 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 }; 785 };
885 786
886 spmi: spmi@10027000 { 787 spmi: spmi@10027000 {
887 compatible = "mediatek 788 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 789 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 790 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "s 791 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao 792 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao 793 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CL 794 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sy 795 clock-names = "pmif_sys_ck",
895 "pmif_tm 796 "pmif_tmr_ck",
896 "spmimst 797 "spmimst_clk_mux";
897 assigned-clocks = <&to 798 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents 799 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 }; 800 };
900 801
901 iommu_infra: infra-iommu@10315 802 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek 803 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 804 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 805 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 806 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 807 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 808 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 809 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>; 810 #iommu-cells = <1>;
910 }; 811 };
911 812
912 gce0: mailbox@10320000 { 813 gce0: mailbox@10320000 {
913 compatible = "mediatek 814 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 815 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 816 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>; 817 #mbox-cells = <2>;
917 clocks = <&infracfg_ao 818 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 }; 819 };
919 820
920 gce1: mailbox@10330000 { 821 gce1: mailbox@10330000 {
921 compatible = "mediatek 822 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 823 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 824 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>; 825 #mbox-cells = <2>;
925 clocks = <&infracfg_ao 826 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 }; 827 };
927 828
928 scp: scp@10500000 { 829 scp: scp@10500000 {
929 compatible = "mediatek 830 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 831 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 832 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 833 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "c 834 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 835 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled"; 836 status = "disabled";
936 }; 837 };
937 838
938 scp_adsp: clock-controller@107 839 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek 840 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 841 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>; 842 #clock-cells = <1>;
942 }; 843 };
943 844
944 adsp: dsp@10803000 { 845 adsp: dsp@10803000 {
945 compatible = "mediatek 846 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 847 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 848 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sr 849 reg-names = "cfg", "sram";
949 clocks = <&topckgen CL 850 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>, 851 <&clk26m>,
951 <&topckgen CL 852 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CL 853 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CL 854 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CL 855 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_se 856 clock-names = "adsp_sel",
956 "clk26m_ck", 857 "clk26m_ck",
957 "audio_local_ 858 "audio_local_bus",
958 "mainpll_d7_d 859 "mainpll_d7_d2",
959 "scp_adsp_aud 860 "scp_adsp_audiodsp",
960 "audio_h"; 861 "audio_h";
961 power-domains = <&spm 862 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx 863 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbo 864 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled"; 865 status = "disabled";
965 }; 866 };
966 867
967 adsp_mailbox0: mailbox@1081600 868 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek 869 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>; 870 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 871 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 872 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 }; 873 };
973 874
974 adsp_mailbox1: mailbox@1081700 875 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek 876 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>; 877 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 878 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 879 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 }; 880 };
980 881
981 afe: mt8195-afe-pcm@10890000 { 882 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek 883 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 884 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <& 885 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm 886 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14 888 resets = <&watchdog 14>;
988 reset-names = "audiosy 889 reset-names = "audiosys";
989 clocks = <&clk26m>, 890 clocks = <&clk26m>,
990 <&apmixedsys C 891 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys C 892 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK 893 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK 894 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK 895 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK 896 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK 897 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK 898 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK 899 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK 900 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CL 901 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CL 902 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CL 903 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CL 904 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CL 905 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CL 906 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao 907 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CL 908 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m 909 clock-names = "clk26m",
1009 "apll1_ck", 910 "apll1_ck",
1010 "apll2_ck", 911 "apll2_ck",
1011 "apll12_div0" 912 "apll12_div0",
1012 "apll12_div1" 913 "apll12_div1",
1013 "apll12_div2" 914 "apll12_div2",
1014 "apll12_div3" 915 "apll12_div3",
1015 "apll12_div9" 916 "apll12_div9",
1016 "a1sys_hp_sel 917 "a1sys_hp_sel",
1017 "aud_intbus_s 918 "aud_intbus_sel",
1018 "audio_h_sel" 919 "audio_h_sel",
1019 "audio_local_ 920 "audio_local_bus_sel",
1020 "dptx_m_sel", 921 "dptx_m_sel",
1021 "i2so1_m_sel" 922 "i2so1_m_sel",
1022 "i2so2_m_sel" 923 "i2so2_m_sel",
1023 "i2si1_m_sel" 924 "i2si1_m_sel",
1024 "i2si2_m_sel" 925 "i2si2_m_sel",
1025 "infra_ao_aud 926 "infra_ao_audio_26m_b",
1026 "scp_adsp_aud 927 "scp_adsp_audiodsp";
1027 status = "disabled"; 928 status = "disabled";
1028 }; 929 };
1029 930
1030 uart0: serial@11001100 { 931 uart0: serial@11001100 {
1031 compatible = "mediate 932 compatible = "mediatek,mt8195-uart",
1032 "mediate 933 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 934 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 935 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, < 936 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", 937 clock-names = "baud", "bus";
1037 status = "disabled"; 938 status = "disabled";
1038 }; 939 };
1039 940
1040 uart1: serial@11001200 { 941 uart1: serial@11001200 {
1041 compatible = "mediate 942 compatible = "mediatek,mt8195-uart",
1042 "mediate 943 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 944 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 945 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, < 946 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", 947 clock-names = "baud", "bus";
1047 status = "disabled"; 948 status = "disabled";
1048 }; 949 };
1049 950
1050 uart2: serial@11001300 { 951 uart2: serial@11001300 {
1051 compatible = "mediate 952 compatible = "mediatek,mt8195-uart",
1052 "mediate 953 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 954 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 955 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, < 956 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", 957 clock-names = "baud", "bus";
1057 status = "disabled"; 958 status = "disabled";
1058 }; 959 };
1059 960
1060 uart3: serial@11001400 { 961 uart3: serial@11001400 {
1061 compatible = "mediate 962 compatible = "mediatek,mt8195-uart",
1062 "mediate 963 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 964 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 965 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, < 966 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", 967 clock-names = "baud", "bus";
1067 status = "disabled"; 968 status = "disabled";
1068 }; 969 };
1069 970
1070 uart4: serial@11001500 { 971 uart4: serial@11001500 {
1071 compatible = "mediate 972 compatible = "mediatek,mt8195-uart",
1072 "mediate 973 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 974 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 975 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, < 976 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", 977 clock-names = "baud", "bus";
1077 status = "disabled"; 978 status = "disabled";
1078 }; 979 };
1079 980
1080 uart5: serial@11001600 { 981 uart5: serial@11001600 {
1081 compatible = "mediate 982 compatible = "mediatek,mt8195-uart",
1082 "mediate 983 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 984 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 985 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, < 986 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", 987 clock-names = "baud", "bus";
1087 status = "disabled"; 988 status = "disabled";
1088 }; 989 };
1089 990
1090 auxadc: auxadc@11002000 { 991 auxadc: auxadc@11002000 {
1091 compatible = "mediate 992 compatible = "mediatek,mt8195-auxadc",
1092 "mediate 993 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 994 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_a 995 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main"; 996 clock-names = "main";
1096 #io-channel-cells = < 997 #io-channel-cells = <1>;
1097 status = "disabled"; 998 status = "disabled";
1098 }; 999 };
1099 1000
1100 pericfg_ao: syscon@11003000 { 1001 pericfg_ao: syscon@11003000 {
1101 compatible = "mediate 1002 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 1003 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>; 1004 #clock-cells = <1>;
1104 }; 1005 };
1105 1006
1106 spi0: spi@1100a000 { 1007 spi0: spi@1100a000 {
1107 compatible = "mediate 1008 compatible = "mediatek,mt8195-spi",
1108 "mediate 1009 "mediatek,mt6765-spi";
1109 #address-cells = <1>; 1010 #address-cells = <1>;
1110 #size-cells = <0>; 1011 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 1012 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 1013 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen C 1014 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen C 1015 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_a 1016 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent 1017 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled"; 1018 status = "disabled";
1118 }; 1019 };
1119 1020
1120 lvts_ap: thermal-sensor@1100b <<
1121 compatible = "mediate <<
1122 reg = <0 0x1100b000 0 <<
1123 interrupts = <GIC_SPI <<
1124 clocks = <&infracfg_a <<
1125 resets = <&infracfg_a <<
1126 nvmem-cells = <&lvts_ <<
1127 nvmem-cell-names = "l <<
1128 #thermal-sensor-cells <<
1129 }; <<
1130 <<
1131 svs: svs@1100bc00 { <<
1132 compatible = "mediate <<
1133 reg = <0 0x1100bc00 0 <<
1134 interrupts = <GIC_SPI <<
1135 clocks = <&infracfg_a <<
1136 clock-names = "main"; <<
1137 nvmem-cells = <&svs_c <<
1138 nvmem-cell-names = "s <<
1139 resets = <&infracfg_a <<
1140 reset-names = "svs_rs <<
1141 }; <<
1142 <<
1143 disp_pwm0: pwm@1100e000 { <<
1144 compatible = "mediate <<
1145 reg = <0 0x1100e000 0 <<
1146 interrupts = <GIC_SPI <<
1147 power-domains = <&spm <<
1148 #pwm-cells = <2>; <<
1149 clocks = <&topckgen C <<
1150 <&infracfg_a <<
1151 clock-names = "main", <<
1152 status = "disabled"; <<
1153 }; <<
1154 <<
1155 disp_pwm1: pwm@1100f000 { <<
1156 compatible = "mediate <<
1157 reg = <0 0x1100f000 0 <<
1158 interrupts = <GIC_SPI <<
1159 #pwm-cells = <2>; <<
1160 clocks = <&topckgen C <<
1161 <&infracfg_a <<
1162 clock-names = "main", <<
1163 status = "disabled"; <<
1164 }; <<
1165 <<
1166 spi1: spi@11010000 { 1021 spi1: spi@11010000 {
1167 compatible = "mediate 1022 compatible = "mediatek,mt8195-spi",
1168 "mediate 1023 "mediatek,mt6765-spi";
1169 #address-cells = <1>; 1024 #address-cells = <1>;
1170 #size-cells = <0>; 1025 #size-cells = <0>;
1171 reg = <0 0x11010000 0 1026 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 1027 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen C 1028 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen C 1029 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_a 1030 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent 1031 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled"; 1032 status = "disabled";
1178 }; 1033 };
1179 1034
1180 spi2: spi@11012000 { 1035 spi2: spi@11012000 {
1181 compatible = "mediate 1036 compatible = "mediatek,mt8195-spi",
1182 "mediate 1037 "mediatek,mt6765-spi";
1183 #address-cells = <1>; 1038 #address-cells = <1>;
1184 #size-cells = <0>; 1039 #size-cells = <0>;
1185 reg = <0 0x11012000 0 1040 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 1041 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen C 1042 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen C 1043 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_a 1044 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent 1045 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled"; 1046 status = "disabled";
1192 }; 1047 };
1193 1048
1194 spi3: spi@11013000 { 1049 spi3: spi@11013000 {
1195 compatible = "mediate 1050 compatible = "mediatek,mt8195-spi",
1196 "mediate 1051 "mediatek,mt6765-spi";
1197 #address-cells = <1>; 1052 #address-cells = <1>;
1198 #size-cells = <0>; 1053 #size-cells = <0>;
1199 reg = <0 0x11013000 0 1054 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 1055 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen C 1056 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen C 1057 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_a 1058 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent 1059 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled"; 1060 status = "disabled";
1206 }; 1061 };
1207 1062
1208 spi4: spi@11018000 { 1063 spi4: spi@11018000 {
1209 compatible = "mediate 1064 compatible = "mediatek,mt8195-spi",
1210 "mediate 1065 "mediatek,mt6765-spi";
1211 #address-cells = <1>; 1066 #address-cells = <1>;
1212 #size-cells = <0>; 1067 #size-cells = <0>;
1213 reg = <0 0x11018000 0 1068 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 1069 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen C 1070 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen C 1071 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_a 1072 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent 1073 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled"; 1074 status = "disabled";
1220 }; 1075 };
1221 1076
1222 spi5: spi@11019000 { 1077 spi5: spi@11019000 {
1223 compatible = "mediate 1078 compatible = "mediatek,mt8195-spi",
1224 "mediate 1079 "mediatek,mt6765-spi";
1225 #address-cells = <1>; 1080 #address-cells = <1>;
1226 #size-cells = <0>; 1081 #size-cells = <0>;
1227 reg = <0 0x11019000 0 1082 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 1083 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen C 1084 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen C 1085 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_a 1086 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent 1087 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled"; 1088 status = "disabled";
1234 }; 1089 };
1235 1090
1236 spis0: spi@1101d000 { 1091 spis0: spi@1101d000 {
1237 compatible = "mediate 1092 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 1093 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 1094 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_a 1095 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi"; 1096 clock-names = "spi";
1242 assigned-clocks = <&t 1097 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parent 1098 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled"; 1099 status = "disabled";
1245 }; 1100 };
1246 1101
1247 spis1: spi@1101e000 { 1102 spis1: spi@1101e000 {
1248 compatible = "mediate 1103 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 1104 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 1105 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_a 1106 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi"; 1107 clock-names = "spi";
1253 assigned-clocks = <&t 1108 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parent 1109 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled"; 1110 status = "disabled";
1256 }; 1111 };
1257 1112
1258 eth: ethernet@11021000 { 1113 eth: ethernet@11021000 {
1259 compatible = "mediate 1114 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260 reg = <0 0x11021000 0 1115 reg = <0 0x11021000 0 0x4000>;
1261 interrupts = <GIC_SPI 1116 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262 interrupt-names = "ma 1117 interrupt-names = "macirq";
1263 clock-names = "axi", 1118 clock-names = "axi",
1264 "apb", 1119 "apb",
1265 "mac_ma 1120 "mac_main",
1266 "ptp_re 1121 "ptp_ref",
1267 "rmii_i 1122 "rmii_internal",
1268 "mac_cg 1123 "mac_cg";
1269 clocks = <&pericfg_ao 1124 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270 <&pericfg_ao 1125 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271 <&topckgen C 1126 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen C 1127 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen C 1128 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274 <&pericfg_ao 1129 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275 assigned-clocks = <&t 1130 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&t 1131 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&t 1132 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parent 1133 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 1134 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 1135 <&topckgen CLK_TOP_ETHPLL_D10>;
1281 power-domains = <&spm 1136 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282 mediatek,pericfg = <& 1137 mediatek,pericfg = <&infracfg_ao>;
1283 snps,axi-config = <&s 1138 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = 1139 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = 1140 snps,mtl-tx-config = <&mtl_tx_setup>;
1286 snps,txpbl = <16>; 1141 snps,txpbl = <16>;
1287 snps,rxpbl = <16>; 1142 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>; 1143 snps,clk-csr = <0>;
1289 status = "disabled"; 1144 status = "disabled";
1290 1145
1291 mdio { 1146 mdio {
1292 compatible = 1147 compatible = "snps,dwmac-mdio";
1293 #address-cell 1148 #address-cells = <1>;
1294 #size-cells = 1149 #size-cells = <0>;
1295 }; 1150 };
1296 1151
1297 stmmac_axi_setup: stm 1152 stmmac_axi_setup: stmmac-axi-config {
1298 snps,wr_osr_l 1153 snps,wr_osr_lmt = <0x7>;
1299 snps,rd_osr_l 1154 snps,rd_osr_lmt = <0x7>;
1300 snps,blen = < 1155 snps,blen = <0 0 0 0 16 8 4>;
1301 }; 1156 };
1302 1157
1303 mtl_rx_setup: rx-queu 1158 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queue 1159 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched 1160 snps,rx-sched-sp;
1306 queue0 { 1161 queue0 {
1307 snps, 1162 snps,dcb-algorithm;
1308 snps, 1163 snps,map-to-dma-channel = <0x0>;
1309 }; 1164 };
1310 queue1 { 1165 queue1 {
1311 snps, 1166 snps,dcb-algorithm;
1312 snps, 1167 snps,map-to-dma-channel = <0x0>;
1313 }; 1168 };
1314 queue2 { 1169 queue2 {
1315 snps, 1170 snps,dcb-algorithm;
1316 snps, 1171 snps,map-to-dma-channel = <0x0>;
1317 }; 1172 };
1318 queue3 { 1173 queue3 {
1319 snps, 1174 snps,dcb-algorithm;
1320 snps, 1175 snps,map-to-dma-channel = <0x0>;
1321 }; 1176 };
1322 }; 1177 };
1323 1178
1324 mtl_tx_setup: tx-queu 1179 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queue 1180 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched 1181 snps,tx-sched-wrr;
1327 queue0 { 1182 queue0 {
1328 snps, 1183 snps,weight = <0x10>;
1329 snps, 1184 snps,dcb-algorithm;
1330 snps, 1185 snps,priority = <0x0>;
1331 }; 1186 };
1332 queue1 { 1187 queue1 {
1333 snps, 1188 snps,weight = <0x11>;
1334 snps, 1189 snps,dcb-algorithm;
1335 snps, 1190 snps,priority = <0x1>;
1336 }; 1191 };
1337 queue2 { 1192 queue2 {
1338 snps, 1193 snps,weight = <0x12>;
1339 snps, 1194 snps,dcb-algorithm;
1340 snps, 1195 snps,priority = <0x2>;
1341 }; 1196 };
1342 queue3 { 1197 queue3 {
1343 snps, 1198 snps,weight = <0x13>;
1344 snps, 1199 snps,dcb-algorithm;
1345 snps, 1200 snps,priority = <0x3>;
1346 }; 1201 };
1347 }; 1202 };
1348 }; 1203 };
1349 1204
1350 ssusb0: usb@11201000 { !! 1205 xhci0: usb@11200000 {
1351 compatible = "mediate !! 1206 compatible = "mediatek,mt8195-xhci",
1352 reg = <0 0x11201000 0 !! 1207 "mediatek,mtk-xhci";
>> 1208 reg = <0 0x11200000 0 0x1000>,
>> 1209 <0 0x11203e00 0 0x0100>;
1353 reg-names = "mac", "i 1210 reg-names = "mac", "ippc";
1354 ranges = <0 0 0 0x112 !! 1211 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1355 #address-cells = <2>; !! 1212 phys = <&u2port0 PHY_TYPE_USB2>,
1356 #size-cells = <2>; !! 1213 <&u3port0 PHY_TYPE_USB3>;
1357 interrupts = <GIC_SPI !! 1214 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
>> 1215 <&topckgen CLK_TOP_SSUSB_XHCI>;
>> 1216 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
>> 1217 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1358 clocks = <&infracfg_a 1218 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen C 1219 <&topckgen CLK_TOP_SSUSB_REF>,
>> 1220 <&apmixedsys CLK_APMIXED_USB1PLL>,
>> 1221 <&clk26m>,
1360 <&infracfg_a 1222 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1361 clock-names = "sys_ck !! 1223 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1362 phys = <&u2port0 PHY_ !! 1224 "xhci_ck";
1363 wakeup-source; <<
1364 mediatek,syscon-wakeu 1225 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
>> 1226 wakeup-source;
1365 status = "disabled"; 1227 status = "disabled";
1366 <<
1367 xhci0: usb@0 { <<
1368 compatible = <<
1369 reg = <0 0 0 <<
1370 reg-names = " <<
1371 interrupts = <<
1372 assigned-cloc <<
1373 <<
1374 assigned-cloc <<
1375 <<
1376 clocks = <&in <<
1377 <&to <<
1378 <&ap <<
1379 <&cl <<
1380 <&in <<
1381 clock-names = <<
1382 status = "dis <<
1383 }; <<
1384 }; 1228 };
1385 1229
1386 mmc0: mmc@11230000 { 1230 mmc0: mmc@11230000 {
1387 compatible = "mediate 1231 compatible = "mediatek,mt8195-mmc",
1388 "mediate 1232 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 1233 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 1234 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 1235 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen C 1236 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_a 1237 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_a 1238 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source 1239 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled"; 1240 status = "disabled";
1397 }; 1241 };
1398 1242
1399 mmc1: mmc@11240000 { 1243 mmc1: mmc@11240000 {
1400 compatible = "mediate 1244 compatible = "mediatek,mt8195-mmc",
1401 "mediate 1245 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 1246 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 1247 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen C 1249 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_a 1250 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_a 1251 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source 1252 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&t 1253 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parent 1254 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled"; 1255 status = "disabled";
1412 }; 1256 };
1413 1257
1414 mmc2: mmc@11250000 { 1258 mmc2: mmc@11250000 {
1415 compatible = "mediate 1259 compatible = "mediatek,mt8195-mmc",
1416 "mediate 1260 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 1261 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 1262 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 1263 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen C 1264 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_a 1265 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_a 1266 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source 1267 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&t 1268 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parent 1269 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled"; 1270 status = "disabled";
1427 }; 1271 };
1428 1272
1429 lvts_mcu: thermal-sensor@1127 <<
1430 compatible = "mediate <<
1431 reg = <0 0x11278000 0 <<
1432 interrupts = <GIC_SPI <<
1433 clocks = <&infracfg_a <<
1434 resets = <&infracfg_a <<
1435 nvmem-cells = <&lvts_ <<
1436 nvmem-cell-names = "l <<
1437 #thermal-sensor-cells <<
1438 }; <<
1439 <<
1440 xhci1: usb@11290000 { 1273 xhci1: usb@11290000 {
1441 compatible = "mediate 1274 compatible = "mediatek,mt8195-xhci",
1442 "mediate 1275 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 1276 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 1277 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "i 1278 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 1279 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_ !! 1280 phys = <&u2port1 PHY_TYPE_USB2>;
1448 assigned-clocks = <&t 1281 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&t 1282 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parent 1283 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 1284 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao 1285 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen C 1286 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys 1287 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>, 1288 <&clk26m>,
1456 <&pericfg_ao 1289 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck 1290 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_c 1291 "xhci_ck";
1459 mediatek,syscon-wakeu 1292 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source; 1293 wakeup-source;
1461 status = "disabled"; 1294 status = "disabled";
1462 }; 1295 };
1463 1296
1464 ssusb2: usb@112a1000 { !! 1297 xhci2: usb@112a0000 {
1465 compatible = "mediate !! 1298 compatible = "mediatek,mt8195-xhci",
1466 reg = <0 0x112a1000 0 !! 1299 "mediatek,mtk-xhci";
>> 1300 reg = <0 0x112a0000 0 0x1000>,
>> 1301 <0 0x112a3e00 0 0x0100>;
1467 reg-names = "mac", "i 1302 reg-names = "mac", "ippc";
1468 ranges = <0 0 0 0x112 !! 1303 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1469 #address-cells = <2>; !! 1304 phys = <&u2port2 PHY_TYPE_USB2>;
1470 #size-cells = <2>; !! 1305 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1471 interrupts = <GIC_SPI !! 1306 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1472 assigned-clocks = <&t !! 1307 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1473 assigned-clock-parent !! 1308 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1474 clocks = <&pericfg_ao 1309 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen C 1310 <&topckgen CLK_TOP_SSUSB_P2_REF>,
>> 1311 <&clk26m>,
>> 1312 <&clk26m>,
1476 <&pericfg_ao 1313 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1477 clock-names = "sys_ck !! 1314 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1478 phys = <&u2port2 PHY_ !! 1315 "xhci_ck";
1479 wakeup-source; <<
1480 mediatek,syscon-wakeu 1316 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
>> 1317 wakeup-source;
1481 status = "disabled"; 1318 status = "disabled";
1482 <<
1483 xhci2: usb@0 { <<
1484 compatible = <<
1485 reg = <0 0 0 <<
1486 reg-names = " <<
1487 interrupts = <<
1488 assigned-cloc <<
1489 assigned-cloc <<
1490 clocks = <&pe <<
1491 clock-names = <<
1492 status = "dis <<
1493 }; <<
1494 }; 1319 };
1495 1320
1496 ssusb3: usb@112b1000 { !! 1321 xhci3: usb@112b0000 {
1497 compatible = "mediate !! 1322 compatible = "mediatek,mt8195-xhci",
1498 reg = <0 0x112b1000 0 !! 1323 "mediatek,mtk-xhci";
>> 1324 reg = <0 0x112b0000 0 0x1000>,
>> 1325 <0 0x112b3e00 0 0x0100>;
1499 reg-names = "mac", "i 1326 reg-names = "mac", "ippc";
1500 ranges = <0 0 0 0x112 !! 1327 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1501 #address-cells = <2>; !! 1328 phys = <&u2port3 PHY_TYPE_USB2>;
1502 #size-cells = <2>; !! 1329 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1503 interrupts = <GIC_SPI !! 1330 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1504 assigned-clocks = <&t !! 1331 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1505 assigned-clock-parent !! 1332 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clocks = <&pericfg_ao 1333 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen C 1334 <&topckgen CLK_TOP_SSUSB_P3_REF>,
>> 1335 <&clk26m>,
>> 1336 <&clk26m>,
1508 <&pericfg_ao 1337 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1509 clock-names = "sys_ck !! 1338 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1510 phys = <&u2port3 PHY_ !! 1339 "xhci_ck";
1511 wakeup-source; <<
1512 mediatek,syscon-wakeu 1340 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
>> 1341 wakeup-source;
1513 status = "disabled"; 1342 status = "disabled";
1514 <<
1515 xhci3: usb@0 { <<
1516 compatible = <<
1517 reg = <0 0 0 <<
1518 reg-names = " <<
1519 interrupts = <<
1520 assigned-cloc <<
1521 assigned-cloc <<
1522 clocks = <&pe <<
1523 clock-names = <<
1524 status = "dis <<
1525 }; <<
1526 }; 1343 };
1527 1344
1528 pcie0: pcie@112f0000 { 1345 pcie0: pcie@112f0000 {
1529 compatible = "mediate 1346 compatible = "mediatek,mt8195-pcie",
1530 "mediate 1347 "mediatek,mt8192-pcie";
1531 device_type = "pci"; 1348 device_type = "pci";
1532 #address-cells = <3>; 1349 #address-cells = <3>;
1533 #size-cells = <2>; 1350 #size-cells = <2>;
1534 reg = <0 0x112f0000 0 1351 reg = <0 0x112f0000 0 0x4000>;
1535 reg-names = "pcie-mac 1352 reg-names = "pcie-mac";
1536 interrupts = <GIC_SPI 1353 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1537 bus-range = <0x00 0xf 1354 bus-range = <0x00 0xff>;
1538 ranges = <0x81000000 1355 ranges = <0x81000000 0 0x20000000
1539 0x0 0x20000 1356 0x0 0x20000000 0 0x200000>,
1540 <0x82000000 1357 <0x82000000 0 0x20200000
1541 0x0 0x20200 1358 0x0 0x20200000 0 0x3e00000>;
1542 1359
1543 iommu-map = <0 &iommu 1360 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0 1361 iommu-map-mask = <0x0>;
1545 1362
1546 clocks = <&infracfg_a 1363 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 <&infracfg_a 1364 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 <&infracfg_a 1365 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 <&infracfg_a 1366 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 <&infracfg_a 1367 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1551 <&pericfg_ao 1368 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1552 clock-names = "pl_250 1369 clock-names = "pl_250m", "tl_26m", "tl_96m",
1553 "tl_32k 1370 "tl_32k", "peri_26m", "peri_mem";
1554 assigned-clocks = <&t 1371 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parent 1372 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1556 1373
1557 phys = <&pciephy>; 1374 phys = <&pciephy>;
1558 phy-names = "pcie-phy 1375 phy-names = "pcie-phy";
1559 1376
1560 power-domains = <&spm 1377 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1561 1378
1562 resets = <&infracfg_a 1379 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1563 reset-names = "mac"; 1380 reset-names = "mac";
1564 1381
1565 #interrupt-cells = <1 1382 #interrupt-cells = <1>;
1566 interrupt-map-mask = 1383 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 1384 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 1385 <0 0 0 2 &pcie_intc0 1>,
1569 <0 0 1386 <0 0 0 3 &pcie_intc0 2>,
1570 <0 0 1387 <0 0 0 4 &pcie_intc0 3>;
1571 status = "disabled"; 1388 status = "disabled";
1572 1389
1573 pcie_intc0: interrupt 1390 pcie_intc0: interrupt-controller {
1574 interrupt-con 1391 interrupt-controller;
1575 #address-cell 1392 #address-cells = <0>;
1576 #interrupt-ce 1393 #interrupt-cells = <1>;
1577 }; 1394 };
1578 }; 1395 };
1579 1396
1580 pcie1: pcie@112f8000 { 1397 pcie1: pcie@112f8000 {
1581 compatible = "mediate 1398 compatible = "mediatek,mt8195-pcie",
1582 "mediate 1399 "mediatek,mt8192-pcie";
1583 device_type = "pci"; 1400 device_type = "pci";
1584 #address-cells = <3>; 1401 #address-cells = <3>;
1585 #size-cells = <2>; 1402 #size-cells = <2>;
1586 reg = <0 0x112f8000 0 1403 reg = <0 0x112f8000 0 0x4000>;
1587 reg-names = "pcie-mac 1404 reg-names = "pcie-mac";
1588 interrupts = <GIC_SPI 1405 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1589 bus-range = <0x00 0xf 1406 bus-range = <0x00 0xff>;
1590 ranges = <0x81000000 1407 ranges = <0x81000000 0 0x24000000
1591 0x0 0x24000 1408 0x0 0x24000000 0 0x200000>,
1592 <0x82000000 1409 <0x82000000 0 0x24200000
1593 0x0 0x24200 1410 0x0 0x24200000 0 0x3e00000>;
1594 1411
1595 iommu-map = <0 &iommu 1412 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0 1413 iommu-map-mask = <0x0>;
1597 1414
1598 clocks = <&infracfg_a 1415 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1599 <&clk26m>, 1416 <&clk26m>,
1600 <&infracfg_a 1417 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1601 <&clk26m>, 1418 <&clk26m>,
1602 <&infracfg_a 1419 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1603 /* Designer 1420 /* Designer has connect pcie1 with peri_mem_p0 clock */
1604 <&pericfg_ao 1421 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1605 clock-names = "pl_250 1422 clock-names = "pl_250m", "tl_26m", "tl_96m",
1606 "tl_32k 1423 "tl_32k", "peri_26m", "peri_mem";
1607 assigned-clocks = <&t 1424 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parent 1425 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1609 1426
1610 phys = <&u3port1 PHY_ 1427 phys = <&u3port1 PHY_TYPE_PCIE>;
1611 phy-names = "pcie-phy 1428 phy-names = "pcie-phy";
1612 power-domains = <&spm 1429 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1613 1430
1614 resets = <&infracfg_a 1431 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1615 reset-names = "mac"; 1432 reset-names = "mac";
1616 1433
1617 #interrupt-cells = <1 1434 #interrupt-cells = <1>;
1618 interrupt-map-mask = 1435 interrupt-map-mask = <0 0 0 7>;
1619 interrupt-map = <0 0 1436 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1620 <0 0 1437 <0 0 0 2 &pcie_intc1 1>,
1621 <0 0 1438 <0 0 0 3 &pcie_intc1 2>,
1622 <0 0 1439 <0 0 0 4 &pcie_intc1 3>;
1623 status = "disabled"; 1440 status = "disabled";
1624 1441
1625 pcie_intc1: interrupt 1442 pcie_intc1: interrupt-controller {
1626 interrupt-con 1443 interrupt-controller;
1627 #address-cell 1444 #address-cells = <0>;
1628 #interrupt-ce 1445 #interrupt-cells = <1>;
1629 }; 1446 };
1630 }; 1447 };
1631 1448
1632 nor_flash: spi@1132c000 { 1449 nor_flash: spi@1132c000 {
1633 compatible = "mediate 1450 compatible = "mediatek,mt8195-nor",
1634 "mediate 1451 "mediatek,mt8173-nor";
1635 reg = <0 0x1132c000 0 1452 reg = <0 0x1132c000 0 0x1000>;
1636 interrupts = <GIC_SPI 1453 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1637 clocks = <&topckgen C 1454 clocks = <&topckgen CLK_TOP_SPINOR>,
1638 <&pericfg_ao 1455 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1639 <&pericfg_ao 1456 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1640 clock-names = "spi", 1457 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>; 1458 #address-cells = <1>;
1642 #size-cells = <0>; 1459 #size-cells = <0>;
1643 status = "disabled"; 1460 status = "disabled";
1644 }; 1461 };
1645 1462
1646 efuse: efuse@11c10000 { 1463 efuse: efuse@11c10000 {
1647 compatible = "mediate 1464 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1648 reg = <0 0x11c10000 0 1465 reg = <0 0x11c10000 0 0x1000>;
1649 #address-cells = <1>; 1466 #address-cells = <1>;
1650 #size-cells = <1>; 1467 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx 1468 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 reg = <0x184 1469 reg = <0x184 0x1>;
1653 bits = <0 5>; 1470 bits = <0 5>;
1654 }; 1471 };
1655 u3_rx_imp_p0: usb3-rx 1472 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 reg = <0x184 1473 reg = <0x184 0x2>;
1657 bits = <5 5>; 1474 bits = <5 5>;
1658 }; 1475 };
1659 u3_intr_p0: usb3-intr 1476 u3_intr_p0: usb3-intr@185 {
1660 reg = <0x185 1477 reg = <0x185 0x1>;
1661 bits = <2 6>; 1478 bits = <2 6>;
1662 }; 1479 };
1663 comb_tx_imp_p1: usb3- 1480 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 reg = <0x186 1481 reg = <0x186 0x1>;
1665 bits = <0 5>; 1482 bits = <0 5>;
1666 }; 1483 };
1667 comb_rx_imp_p1: usb3- 1484 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 reg = <0x186 1485 reg = <0x186 0x2>;
1669 bits = <5 5>; 1486 bits = <5 5>;
1670 }; 1487 };
1671 comb_intr_p1: usb3-in 1488 comb_intr_p1: usb3-intr@187 {
1672 reg = <0x187 1489 reg = <0x187 0x1>;
1673 bits = <2 6>; 1490 bits = <2 6>;
1674 }; 1491 };
1675 u2_intr_p0: usb2-intr 1492 u2_intr_p0: usb2-intr-p0@188,1 {
1676 reg = <0x188 1493 reg = <0x188 0x1>;
1677 bits = <0 5>; 1494 bits = <0 5>;
1678 }; 1495 };
1679 u2_intr_p1: usb2-intr 1496 u2_intr_p1: usb2-intr-p1@188,2 {
1680 reg = <0x188 1497 reg = <0x188 0x2>;
1681 bits = <5 5>; 1498 bits = <5 5>;
1682 }; 1499 };
1683 u2_intr_p2: usb2-intr 1500 u2_intr_p2: usb2-intr-p2@189,1 {
1684 reg = <0x189 1501 reg = <0x189 0x1>;
1685 bits = <2 5>; 1502 bits = <2 5>;
1686 }; 1503 };
1687 u2_intr_p3: usb2-intr 1504 u2_intr_p3: usb2-intr-p3@189,2 {
1688 reg = <0x189 1505 reg = <0x189 0x2>;
1689 bits = <7 5>; 1506 bits = <7 5>;
1690 }; 1507 };
1691 pciephy_rx_ln1: pciep 1508 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1692 reg = <0x190 1509 reg = <0x190 0x1>;
1693 bits = <0 4>; 1510 bits = <0 4>;
1694 }; 1511 };
1695 pciephy_tx_ln1_nmos: 1512 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1696 reg = <0x190 1513 reg = <0x190 0x1>;
1697 bits = <4 4>; 1514 bits = <4 4>;
1698 }; 1515 };
1699 pciephy_tx_ln1_pmos: 1516 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1700 reg = <0x191 1517 reg = <0x191 0x1>;
1701 bits = <0 4>; 1518 bits = <0 4>;
1702 }; 1519 };
1703 pciephy_rx_ln0: pciep 1520 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1704 reg = <0x191 1521 reg = <0x191 0x1>;
1705 bits = <4 4>; 1522 bits = <4 4>;
1706 }; 1523 };
1707 pciephy_tx_ln0_nmos: 1524 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1708 reg = <0x192 1525 reg = <0x192 0x1>;
1709 bits = <0 4>; 1526 bits = <0 4>;
1710 }; 1527 };
1711 pciephy_tx_ln0_pmos: 1528 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1712 reg = <0x192 1529 reg = <0x192 0x1>;
1713 bits = <4 4>; 1530 bits = <4 4>;
1714 }; 1531 };
1715 pciephy_glb_intr: pci 1532 pciephy_glb_intr: pciephy-glb-intr@193 {
1716 reg = <0x193 1533 reg = <0x193 0x1>;
1717 bits = <0 4>; 1534 bits = <0 4>;
1718 }; 1535 };
1719 dp_calibration: dp-da 1536 dp_calibration: dp-data@1ac {
1720 reg = <0x1ac 1537 reg = <0x1ac 0x10>;
1721 }; 1538 };
1722 lvts_efuse_data1: lvt 1539 lvts_efuse_data1: lvts1-calib@1bc {
1723 reg = <0x1bc 1540 reg = <0x1bc 0x14>;
1724 }; 1541 };
1725 lvts_efuse_data2: lvt 1542 lvts_efuse_data2: lvts2-calib@1d0 {
1726 reg = <0x1d0 1543 reg = <0x1d0 0x38>;
1727 }; 1544 };
1728 svs_calib_data: svs-c <<
1729 reg = <0x580 <<
1730 }; <<
1731 socinfo-data1@7a0 { <<
1732 reg = <0x7a0 <<
1733 }; <<
1734 }; 1545 };
1735 1546
1736 u3phy2: t-phy@11c40000 { 1547 u3phy2: t-phy@11c40000 {
1737 compatible = "mediate 1548 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>; 1549 #address-cells = <1>;
1739 #size-cells = <1>; 1550 #size-cells = <1>;
1740 ranges = <0 0 0x11c40 1551 ranges = <0 0 0x11c40000 0x700>;
1741 status = "disabled"; 1552 status = "disabled";
1742 1553
1743 u2port2: usb-phy@0 { 1554 u2port2: usb-phy@0 {
1744 reg = <0x0 0x 1555 reg = <0x0 0x700>;
1745 clocks = <&to 1556 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1746 clock-names = 1557 clock-names = "ref";
1747 #phy-cells = 1558 #phy-cells = <1>;
1748 }; 1559 };
1749 }; 1560 };
1750 1561
1751 u3phy3: t-phy@11c50000 { 1562 u3phy3: t-phy@11c50000 {
1752 compatible = "mediate 1563 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>; 1564 #address-cells = <1>;
1754 #size-cells = <1>; 1565 #size-cells = <1>;
1755 ranges = <0 0 0x11c50 1566 ranges = <0 0 0x11c50000 0x700>;
1756 status = "disabled"; 1567 status = "disabled";
1757 1568
1758 u2port3: usb-phy@0 { 1569 u2port3: usb-phy@0 {
1759 reg = <0x0 0x 1570 reg = <0x0 0x700>;
1760 clocks = <&to 1571 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1761 clock-names = 1572 clock-names = "ref";
1762 #phy-cells = 1573 #phy-cells = <1>;
1763 }; 1574 };
1764 }; 1575 };
1765 1576
1766 mipi_tx0: dsi-phy@11c80000 { <<
1767 compatible = "mediate <<
1768 reg = <0 0x11c80000 0 <<
1769 clocks = <&clk26m>; <<
1770 clock-output-names = <<
1771 #clock-cells = <0>; <<
1772 #phy-cells = <0>; <<
1773 status = "disabled"; <<
1774 }; <<
1775 <<
1776 mipi_tx1: dsi-phy@11c90000 { <<
1777 compatible = "mediate <<
1778 reg = <0 0x11c90000 0 <<
1779 clocks = <&clk26m>; <<
1780 clock-output-names = <<
1781 #clock-cells = <0>; <<
1782 #phy-cells = <0>; <<
1783 status = "disabled"; <<
1784 }; <<
1785 <<
1786 i2c5: i2c@11d00000 { 1577 i2c5: i2c@11d00000 {
1787 compatible = "mediate 1578 compatible = "mediatek,mt8195-i2c",
1788 "mediate 1579 "mediatek,mt8192-i2c";
1789 reg = <0 0x11d00000 0 1580 reg = <0 0x11d00000 0 0x1000>,
1790 <0 0x10220580 0 1581 <0 0x10220580 0 0x80>;
1791 interrupts = <GIC_SPI 1582 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1792 clock-div = <1>; 1583 clock-div = <1>;
1793 clocks = <&imp_iic_wr 1584 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1794 <&infracfg_a 1585 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795 clock-names = "main", 1586 clock-names = "main", "dma";
1796 #address-cells = <1>; 1587 #address-cells = <1>;
1797 #size-cells = <0>; 1588 #size-cells = <0>;
1798 status = "disabled"; 1589 status = "disabled";
1799 }; 1590 };
1800 1591
1801 i2c6: i2c@11d01000 { 1592 i2c6: i2c@11d01000 {
1802 compatible = "mediate 1593 compatible = "mediatek,mt8195-i2c",
1803 "mediate 1594 "mediatek,mt8192-i2c";
1804 reg = <0 0x11d01000 0 1595 reg = <0 0x11d01000 0 0x1000>,
1805 <0 0x10220600 0 1596 <0 0x10220600 0 0x80>;
1806 interrupts = <GIC_SPI 1597 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1807 clock-div = <1>; 1598 clock-div = <1>;
1808 clocks = <&imp_iic_wr 1599 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1809 <&infracfg_a 1600 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1810 clock-names = "main", 1601 clock-names = "main", "dma";
1811 #address-cells = <1>; 1602 #address-cells = <1>;
1812 #size-cells = <0>; 1603 #size-cells = <0>;
1813 status = "disabled"; 1604 status = "disabled";
1814 }; 1605 };
1815 1606
1816 i2c7: i2c@11d02000 { 1607 i2c7: i2c@11d02000 {
1817 compatible = "mediate 1608 compatible = "mediatek,mt8195-i2c",
1818 "mediate 1609 "mediatek,mt8192-i2c";
1819 reg = <0 0x11d02000 0 1610 reg = <0 0x11d02000 0 0x1000>,
1820 <0 0x10220680 0 1611 <0 0x10220680 0 0x80>;
1821 interrupts = <GIC_SPI 1612 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1822 clock-div = <1>; 1613 clock-div = <1>;
1823 clocks = <&imp_iic_wr 1614 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1824 <&infracfg_a 1615 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1825 clock-names = "main", 1616 clock-names = "main", "dma";
1826 #address-cells = <1>; 1617 #address-cells = <1>;
1827 #size-cells = <0>; 1618 #size-cells = <0>;
1828 status = "disabled"; 1619 status = "disabled";
1829 }; 1620 };
1830 1621
1831 imp_iic_wrap_s: clock-control 1622 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediate 1623 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1833 reg = <0 0x11d03000 0 1624 reg = <0 0x11d03000 0 0x1000>;
1834 #clock-cells = <1>; 1625 #clock-cells = <1>;
1835 }; 1626 };
1836 1627
1837 i2c0: i2c@11e00000 { 1628 i2c0: i2c@11e00000 {
1838 compatible = "mediate 1629 compatible = "mediatek,mt8195-i2c",
1839 "mediate 1630 "mediatek,mt8192-i2c";
1840 reg = <0 0x11e00000 0 1631 reg = <0 0x11e00000 0 0x1000>,
1841 <0 0x10220080 0 1632 <0 0x10220080 0 0x80>;
1842 interrupts = <GIC_SPI 1633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1843 clock-div = <1>; 1634 clock-div = <1>;
1844 clocks = <&imp_iic_wr 1635 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1845 <&infracfg_a 1636 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846 clock-names = "main", 1637 clock-names = "main", "dma";
1847 #address-cells = <1>; 1638 #address-cells = <1>;
1848 #size-cells = <0>; 1639 #size-cells = <0>;
1849 status = "disabled"; 1640 status = "disabled";
1850 }; 1641 };
1851 1642
1852 i2c1: i2c@11e01000 { 1643 i2c1: i2c@11e01000 {
1853 compatible = "mediate 1644 compatible = "mediatek,mt8195-i2c",
1854 "mediate 1645 "mediatek,mt8192-i2c";
1855 reg = <0 0x11e01000 0 1646 reg = <0 0x11e01000 0 0x1000>,
1856 <0 0x10220200 0 1647 <0 0x10220200 0 0x80>;
1857 interrupts = <GIC_SPI 1648 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clock-div = <1>; 1649 clock-div = <1>;
1859 clocks = <&imp_iic_wr 1650 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1860 <&infracfg_a 1651 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861 clock-names = "main", 1652 clock-names = "main", "dma";
1862 #address-cells = <1>; 1653 #address-cells = <1>;
1863 #size-cells = <0>; 1654 #size-cells = <0>;
1864 status = "disabled"; 1655 status = "disabled";
1865 }; 1656 };
1866 1657
1867 i2c2: i2c@11e02000 { 1658 i2c2: i2c@11e02000 {
1868 compatible = "mediate 1659 compatible = "mediatek,mt8195-i2c",
1869 "mediate 1660 "mediatek,mt8192-i2c";
1870 reg = <0 0x11e02000 0 1661 reg = <0 0x11e02000 0 0x1000>,
1871 <0 0x10220380 0 1662 <0 0x10220380 0 0x80>;
1872 interrupts = <GIC_SPI 1663 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1873 clock-div = <1>; 1664 clock-div = <1>;
1874 clocks = <&imp_iic_wr 1665 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1875 <&infracfg_a 1666 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876 clock-names = "main", 1667 clock-names = "main", "dma";
1877 #address-cells = <1>; 1668 #address-cells = <1>;
1878 #size-cells = <0>; 1669 #size-cells = <0>;
1879 status = "disabled"; 1670 status = "disabled";
1880 }; 1671 };
1881 1672
1882 i2c3: i2c@11e03000 { 1673 i2c3: i2c@11e03000 {
1883 compatible = "mediate 1674 compatible = "mediatek,mt8195-i2c",
1884 "mediate 1675 "mediatek,mt8192-i2c";
1885 reg = <0 0x11e03000 0 1676 reg = <0 0x11e03000 0 0x1000>,
1886 <0 0x10220480 0 1677 <0 0x10220480 0 0x80>;
1887 interrupts = <GIC_SPI 1678 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clock-div = <1>; 1679 clock-div = <1>;
1889 clocks = <&imp_iic_wr 1680 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1890 <&infracfg_a 1681 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1891 clock-names = "main", 1682 clock-names = "main", "dma";
1892 #address-cells = <1>; 1683 #address-cells = <1>;
1893 #size-cells = <0>; 1684 #size-cells = <0>;
1894 status = "disabled"; 1685 status = "disabled";
1895 }; 1686 };
1896 1687
1897 i2c4: i2c@11e04000 { 1688 i2c4: i2c@11e04000 {
1898 compatible = "mediate 1689 compatible = "mediatek,mt8195-i2c",
1899 "mediate 1690 "mediatek,mt8192-i2c";
1900 reg = <0 0x11e04000 0 1691 reg = <0 0x11e04000 0 0x1000>,
1901 <0 0x10220500 0 1692 <0 0x10220500 0 0x80>;
1902 interrupts = <GIC_SPI 1693 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1903 clock-div = <1>; 1694 clock-div = <1>;
1904 clocks = <&imp_iic_wr 1695 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1905 <&infracfg_a 1696 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1906 clock-names = "main", 1697 clock-names = "main", "dma";
1907 #address-cells = <1>; 1698 #address-cells = <1>;
1908 #size-cells = <0>; 1699 #size-cells = <0>;
1909 status = "disabled"; 1700 status = "disabled";
1910 }; 1701 };
1911 1702
1912 imp_iic_wrap_w: clock-control 1703 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediate 1704 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1914 reg = <0 0x11e05000 0 1705 reg = <0 0x11e05000 0 0x1000>;
1915 #clock-cells = <1>; 1706 #clock-cells = <1>;
1916 }; 1707 };
1917 1708
1918 u3phy1: t-phy@11e30000 { 1709 u3phy1: t-phy@11e30000 {
1919 compatible = "mediate 1710 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>; 1711 #address-cells = <1>;
1921 #size-cells = <1>; 1712 #size-cells = <1>;
1922 ranges = <0 0 0x11e30 1713 ranges = <0 0 0x11e30000 0xe00>;
1923 power-domains = <&spm 1714 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1924 status = "disabled"; 1715 status = "disabled";
1925 1716
1926 u2port1: usb-phy@0 { 1717 u2port1: usb-phy@0 {
1927 reg = <0x0 0x 1718 reg = <0x0 0x700>;
1928 clocks = <&to 1719 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1929 <&cl 1720 <&clk26m>;
1930 clock-names = 1721 clock-names = "ref", "da_ref";
1931 #phy-cells = 1722 #phy-cells = <1>;
1932 }; 1723 };
1933 1724
1934 u3port1: usb-phy@700 1725 u3port1: usb-phy@700 {
1935 reg = <0x700 1726 reg = <0x700 0x700>;
1936 clocks = <&ap 1727 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1937 <&to 1728 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1938 clock-names = 1729 clock-names = "ref", "da_ref";
1939 nvmem-cells = 1730 nvmem-cells = <&comb_intr_p1>,
1940 1731 <&comb_rx_imp_p1>,
1941 1732 <&comb_tx_imp_p1>;
1942 nvmem-cell-na 1733 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = 1734 #phy-cells = <1>;
1944 }; 1735 };
1945 }; 1736 };
1946 1737
1947 u3phy0: t-phy@11e40000 { 1738 u3phy0: t-phy@11e40000 {
1948 compatible = "mediate 1739 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>; 1740 #address-cells = <1>;
1950 #size-cells = <1>; 1741 #size-cells = <1>;
1951 ranges = <0 0 0x11e40 1742 ranges = <0 0 0x11e40000 0xe00>;
1952 status = "disabled"; 1743 status = "disabled";
1953 1744
1954 u2port0: usb-phy@0 { 1745 u2port0: usb-phy@0 {
1955 reg = <0x0 0x 1746 reg = <0x0 0x700>;
1956 clocks = <&to 1747 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1957 <&cl 1748 <&clk26m>;
1958 clock-names = 1749 clock-names = "ref", "da_ref";
1959 #phy-cells = 1750 #phy-cells = <1>;
1960 }; 1751 };
1961 1752
1962 u3port0: usb-phy@700 1753 u3port0: usb-phy@700 {
1963 reg = <0x700 1754 reg = <0x700 0x700>;
1964 clocks = <&ap 1755 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1965 <&to 1756 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1966 clock-names = 1757 clock-names = "ref", "da_ref";
1967 nvmem-cells = 1758 nvmem-cells = <&u3_intr_p0>,
1968 1759 <&u3_rx_imp_p0>,
1969 1760 <&u3_tx_imp_p0>;
1970 nvmem-cell-na 1761 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = 1762 #phy-cells = <1>;
1972 }; 1763 };
1973 }; 1764 };
1974 1765
1975 pciephy: phy@11e80000 { 1766 pciephy: phy@11e80000 {
1976 compatible = "mediate 1767 compatible = "mediatek,mt8195-pcie-phy";
1977 reg = <0 0x11e80000 0 1768 reg = <0 0x11e80000 0 0x10000>;
1978 reg-names = "sif"; 1769 reg-names = "sif";
1979 nvmem-cells = <&pciep 1770 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1980 <&pciep 1771 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1981 <&pciep 1772 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1982 <&pciep 1773 <&pciephy_rx_ln1>;
1983 nvmem-cell-names = "g 1774 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1984 "t 1775 "tx_ln0_nmos", "rx_ln0",
1985 "t 1776 "tx_ln1_pmos", "tx_ln1_nmos",
1986 "r 1777 "rx_ln1";
1987 power-domains = <&spm 1778 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1988 #phy-cells = <0>; 1779 #phy-cells = <0>;
1989 status = "disabled"; 1780 status = "disabled";
1990 }; 1781 };
1991 1782
1992 ufsphy: ufs-phy@11fa0000 { 1783 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediate 1784 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1994 reg = <0 0x11fa0000 0 1785 reg = <0 0x11fa0000 0 0xc000>;
1995 clocks = <&clk26m>, < 1786 clocks = <&clk26m>, <&clk26m>;
1996 clock-names = "unipro 1787 clock-names = "unipro", "mp";
1997 #phy-cells = <0>; 1788 #phy-cells = <0>;
1998 status = "disabled"; 1789 status = "disabled";
1999 }; 1790 };
2000 1791
2001 gpu: gpu@13000000 { <<
2002 compatible = "mediate <<
2003 "arm,mal <<
2004 reg = <0 0x13000000 0 <<
2005 <<
2006 clocks = <&mfgcfg CLK <<
2007 interrupts = <GIC_SPI <<
2008 <GIC_SPI <<
2009 <GIC_SPI <<
2010 interrupt-names = "jo <<
2011 operating-points-v2 = <<
2012 power-domains = <&spm <<
2013 <&spm <<
2014 <&spm <<
2015 <&spm <<
2016 <&spm <<
2017 power-domain-names = <<
2018 status = "disabled"; <<
2019 }; <<
2020 <<
2021 mfgcfg: clock-controller@13fb 1792 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediate 1793 compatible = "mediatek,mt8195-mfgcfg";
2023 reg = <0 0x13fbf000 0 1794 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>; 1795 #clock-cells = <1>;
2025 }; 1796 };
2026 1797
2027 vppsys0: syscon@14000000 { !! 1798 vppsys0: clock-controller@14000000 {
2028 compatible = "mediate !! 1799 compatible = "mediatek,mt8195-vppsys0";
2029 reg = <0 0x14000000 0 1800 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>; 1801 #clock-cells = <1>;
2031 mediatek,gce-client-r <<
2032 }; <<
2033 <<
2034 dma-controller@14001000 { <<
2035 compatible = "mediate <<
2036 reg = <0 0x14001000 0 <<
2037 mediatek,gce-client-r <<
2038 mediatek,gce-events = <<
2039 <<
2040 mediatek,scp = <&scp> <<
2041 power-domains = <&spm <<
2042 iommus = <&iommu_vpp <<
2043 clocks = <&vppsys0 CL <<
2044 mboxes = <&gce1 12 CM <<
2045 <&gce1 13 CM <<
2046 <&gce1 14 CM <<
2047 <&gce1 21 CM <<
2048 <&gce1 22 CM <<
2049 #dma-cells = <1>; <<
2050 }; <<
2051 <<
2052 display@14002000 { <<
2053 compatible = "mediate <<
2054 reg = <0 0x14002000 0 <<
2055 mediatek,gce-client-r <<
2056 clocks = <&vppsys0 CL <<
2057 }; <<
2058 <<
2059 display@14003000 { <<
2060 compatible = "mediate <<
2061 reg = <0 0x14003000 0 <<
2062 mediatek,gce-client-r <<
2063 clocks = <&vppsys0 CL <<
2064 }; <<
2065 <<
2066 display@14004000 { <<
2067 compatible = "mediate <<
2068 reg = <0 0x14004000 0 <<
2069 mediatek,gce-client-r <<
2070 clocks = <&vppsys0 CL <<
2071 }; <<
2072 <<
2073 display@14005000 { <<
2074 compatible = "mediate <<
2075 reg = <0 0x14005000 0 <<
2076 interrupts = <GIC_SPI <<
2077 mediatek,gce-client-r <<
2078 clocks = <&vppsys0 CL <<
2079 power-domains = <&spm <<
2080 }; <<
2081 <<
2082 display@14006000 { <<
2083 compatible = "mediate <<
2084 reg = <0 0x14006000 0 <<
2085 mediatek,gce-client-r <<
2086 mediatek,gce-events = <<
2087 <<
2088 clocks = <&vppsys0 CL <<
2089 }; <<
2090 <<
2091 display@14007000 { <<
2092 compatible = "mediate <<
2093 reg = <0 0x14007000 0 <<
2094 mediatek,gce-client-r <<
2095 clocks = <&vppsys0 CL <<
2096 }; <<
2097 <<
2098 display@14008000 { <<
2099 compatible = "mediate <<
2100 reg = <0 0x14008000 0 <<
2101 interrupts = <GIC_SPI <<
2102 mediatek,gce-client-r <<
2103 clocks = <&vppsys0 CL <<
2104 power-domains = <&spm <<
2105 }; <<
2106 <<
2107 display@14009000 { <<
2108 compatible = "mediate <<
2109 reg = <0 0x14009000 0 <<
2110 interrupts = <GIC_SPI <<
2111 mediatek,gce-client-r <<
2112 clocks = <&vppsys0 CL <<
2113 power-domains = <&spm <<
2114 iommus = <&iommu_vpp <<
2115 }; <<
2116 <<
2117 display@1400a000 { <<
2118 compatible = "mediate <<
2119 reg = <0 0x1400a000 0 <<
2120 mediatek,gce-client-r <<
2121 clocks = <&vppsys0 CL <<
2122 power-domains = <&spm <<
2123 }; <<
2124 <<
2125 display@1400b000 { <<
2126 compatible = "mediate <<
2127 reg = <0 0x1400b000 0 <<
2128 mediatek,gce-client-r <<
2129 clocks = <&vppsys0 CL <<
2130 }; <<
2131 <<
2132 dma-controller@1400c000 { <<
2133 compatible = "mediate <<
2134 reg = <0 0x1400c000 0 <<
2135 mediatek,gce-client-r <<
2136 mediatek,gce-events = <<
2137 <<
2138 clocks = <&vppsys0 CL <<
2139 iommus = <&iommu_vpp <<
2140 power-domains = <&spm <<
2141 #dma-cells = <1>; <<
2142 }; <<
2143 <<
2144 mutex@1400f000 { <<
2145 compatible = "mediate <<
2146 reg = <0 0x1400f000 0 <<
2147 interrupts = <GIC_SPI <<
2148 mediatek,gce-client-r <<
2149 clocks = <&vppsys0 CL <<
2150 power-domains = <&spm <<
2151 }; 1802 };
2152 1803
2153 smi_sub_common_vpp0_vpp1_2x1: 1804 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2154 compatible = "mediate 1805 compatible = "mediatek,mt8195-smi-sub-common";
2155 reg = <0 0x14010000 0 1806 reg = <0 0x14010000 0 0x1000>;
2156 clocks = <&vppsys0 CL 1807 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_ 1808 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2158 <&vppsys0 CLK_ 1809 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2159 clock-names = "apb", 1810 clock-names = "apb", "smi", "gals0";
2160 mediatek,smi = <&smi_ 1811 mediatek,smi = <&smi_common_vpp>;
2161 power-domains = <&spm 1812 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2162 }; 1813 };
2163 1814
2164 smi_sub_common_vdec_vpp0_2x1: 1815 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2165 compatible = "mediate 1816 compatible = "mediatek,mt8195-smi-sub-common";
2166 reg = <0 0x14011000 0 1817 reg = <0 0x14011000 0 0x1000>;
2167 clocks = <&vppsys0 CL 1818 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CL 1819 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2169 <&vppsys0 CL 1820 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2170 clock-names = "apb", 1821 clock-names = "apb", "smi", "gals0";
2171 mediatek,smi = <&smi_ 1822 mediatek,smi = <&smi_common_vpp>;
2172 power-domains = <&spm 1823 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2173 }; 1824 };
2174 1825
2175 smi_common_vpp: smi@14012000 1826 smi_common_vpp: smi@14012000 {
2176 compatible = "mediate 1827 compatible = "mediatek,mt8195-smi-common-vpp";
2177 reg = <0 0x14012000 0 1828 reg = <0 0x14012000 0 0x1000>;
2178 clocks = <&vppsys0 CL 1829 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_ 1830 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2180 <&vppsys0 CLK_ 1831 <&vppsys0 CLK_VPP0_SMI_RSI>,
2181 <&vppsys0 CLK_ 1832 <&vppsys0 CLK_VPP0_SMI_RSI>;
2182 clock-names = "apb", 1833 clock-names = "apb", "smi", "gals0", "gals1";
2183 power-domains = <&spm 1834 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2184 }; 1835 };
2185 1836
2186 larb4: larb@14013000 { 1837 larb4: larb@14013000 {
2187 compatible = "mediate 1838 compatible = "mediatek,mt8195-smi-larb";
2188 reg = <0 0x14013000 0 1839 reg = <0 0x14013000 0 0x1000>;
2189 mediatek,larb-id = <4 1840 mediatek,larb-id = <4>;
2190 mediatek,smi = <&smi_ 1841 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2191 clocks = <&vppsys0 CL 1842 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2192 <&vppsys0 CLK_ 1843 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2193 clock-names = "apb", 1844 clock-names = "apb", "smi";
2194 power-domains = <&spm 1845 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2195 }; 1846 };
2196 1847
2197 iommu_vpp: iommu@14018000 { 1848 iommu_vpp: iommu@14018000 {
2198 compatible = "mediate 1849 compatible = "mediatek,mt8195-iommu-vpp";
2199 reg = <0 0x14018000 0 1850 reg = <0 0x14018000 0 0x1000>;
2200 mediatek,larbs = <&la 1851 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2201 &la 1852 &larb12 &larb14 &larb16 &larb18
2202 &la 1853 &larb20 &larb22 &larb23 &larb26
2203 &la 1854 &larb27>;
2204 interrupts = <GIC_SPI 1855 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2205 clocks = <&vppsys0 CL 1856 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2206 clock-names = "bclk"; 1857 clock-names = "bclk";
2207 #iommu-cells = <1>; 1858 #iommu-cells = <1>;
2208 power-domains = <&spm 1859 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2209 }; 1860 };
2210 1861
2211 wpesys: clock-controller@14e0 1862 wpesys: clock-controller@14e00000 {
2212 compatible = "mediate 1863 compatible = "mediatek,mt8195-wpesys";
2213 reg = <0 0x14e00000 0 1864 reg = <0 0x14e00000 0 0x1000>;
2214 #clock-cells = <1>; 1865 #clock-cells = <1>;
2215 }; 1866 };
2216 1867
2217 wpesys_vpp0: clock-controller 1868 wpesys_vpp0: clock-controller@14e02000 {
2218 compatible = "mediate 1869 compatible = "mediatek,mt8195-wpesys_vpp0";
2219 reg = <0 0x14e02000 0 1870 reg = <0 0x14e02000 0 0x1000>;
2220 #clock-cells = <1>; 1871 #clock-cells = <1>;
2221 }; 1872 };
2222 1873
2223 wpesys_vpp1: clock-controller 1874 wpesys_vpp1: clock-controller@14e03000 {
2224 compatible = "mediate 1875 compatible = "mediatek,mt8195-wpesys_vpp1";
2225 reg = <0 0x14e03000 0 1876 reg = <0 0x14e03000 0 0x1000>;
2226 #clock-cells = <1>; 1877 #clock-cells = <1>;
2227 }; 1878 };
2228 1879
2229 larb7: larb@14e04000 { 1880 larb7: larb@14e04000 {
2230 compatible = "mediate 1881 compatible = "mediatek,mt8195-smi-larb";
2231 reg = <0 0x14e04000 0 1882 reg = <0 0x14e04000 0 0x1000>;
2232 mediatek,larb-id = <7 1883 mediatek,larb-id = <7>;
2233 mediatek,smi = <&smi_ 1884 mediatek,smi = <&smi_common_vdo>;
2234 clocks = <&wpesys CLK 1885 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2235 <&wpesys CLK 1886 <&wpesys CLK_WPE_SMI_LARB7>;
2236 clock-names = "apb", 1887 clock-names = "apb", "smi";
2237 power-domains = <&spm 1888 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2238 }; 1889 };
2239 1890
2240 larb8: larb@14e05000 { 1891 larb8: larb@14e05000 {
2241 compatible = "mediate 1892 compatible = "mediatek,mt8195-smi-larb";
2242 reg = <0 0x14e05000 0 1893 reg = <0 0x14e05000 0 0x1000>;
2243 mediatek,larb-id = <8 1894 mediatek,larb-id = <8>;
2244 mediatek,smi = <&smi_ 1895 mediatek,smi = <&smi_common_vpp>;
2245 clocks = <&wpesys CLK 1896 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2246 <&wpesys CLK_W 1897 <&wpesys CLK_WPE_SMI_LARB8>,
2247 <&vppsys0 CLK_ 1898 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2248 clock-names = "apb", 1899 clock-names = "apb", "smi", "gals";
2249 power-domains = <&spm 1900 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2250 }; 1901 };
2251 1902
2252 vppsys1: syscon@14f00000 { !! 1903 vppsys1: clock-controller@14f00000 {
2253 compatible = "mediate !! 1904 compatible = "mediatek,mt8195-vppsys1";
2254 reg = <0 0x14f00000 0 1905 reg = <0 0x14f00000 0 0x1000>;
2255 #clock-cells = <1>; 1906 #clock-cells = <1>;
2256 mediatek,gce-client-r <<
2257 }; <<
2258 <<
2259 mutex@14f01000 { <<
2260 compatible = "mediate <<
2261 reg = <0 0x14f01000 0 <<
2262 interrupts = <GIC_SPI <<
2263 mediatek,gce-client-r <<
2264 clocks = <&vppsys1 CL <<
2265 power-domains = <&spm <<
2266 }; 1907 };
2267 1908
2268 larb5: larb@14f02000 { 1909 larb5: larb@14f02000 {
2269 compatible = "mediate 1910 compatible = "mediatek,mt8195-smi-larb";
2270 reg = <0 0x14f02000 0 1911 reg = <0 0x14f02000 0 0x1000>;
2271 mediatek,larb-id = <5 1912 mediatek,larb-id = <5>;
2272 mediatek,smi = <&smi_ 1913 mediatek,smi = <&smi_common_vdo>;
2273 clocks = <&vppsys1 CL 1914 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2274 <&vppsys1 CLK_ 1915 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2275 <&vppsys0 CLK_ 1916 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2276 clock-names = "apb", 1917 clock-names = "apb", "smi", "gals";
2277 power-domains = <&spm 1918 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2278 }; 1919 };
2279 1920
2280 larb6: larb@14f03000 { 1921 larb6: larb@14f03000 {
2281 compatible = "mediate 1922 compatible = "mediatek,mt8195-smi-larb";
2282 reg = <0 0x14f03000 0 1923 reg = <0 0x14f03000 0 0x1000>;
2283 mediatek,larb-id = <6 1924 mediatek,larb-id = <6>;
2284 mediatek,smi = <&smi_ 1925 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2285 clocks = <&vppsys1 CL 1926 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2286 <&vppsys1 CLK_ 1927 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2287 <&vppsys0 CLK_ 1928 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2288 clock-names = "apb", 1929 clock-names = "apb", "smi", "gals";
2289 power-domains = <&spm 1930 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2290 }; 1931 };
2291 1932
2292 display@14f06000 { <<
2293 compatible = "mediate <<
2294 reg = <0 0x14f06000 0 <<
2295 mediatek,gce-client-r <<
2296 clocks = <&vppsys1 CL <<
2297 <&vppsys1 CL <<
2298 <&vppsys1 CL <<
2299 power-domains = <&spm <<
2300 }; <<
2301 <<
2302 display@14f07000 { <<
2303 compatible = "mediate <<
2304 reg = <0 0x14f07000 0 <<
2305 mediatek,gce-client-r <<
2306 clocks = <&vppsys1 CL <<
2307 }; <<
2308 <<
2309 dma-controller@14f08000 { <<
2310 compatible = "mediate <<
2311 reg = <0 0x14f08000 0 <<
2312 mediatek,gce-client-r <<
2313 mediatek,gce-events = <<
2314 <<
2315 clocks = <&vppsys1 CL <<
2316 iommus = <&iommu_vdo <<
2317 power-domains = <&spm <<
2318 #dma-cells = <1>; <<
2319 }; <<
2320 <<
2321 dma-controller@14f09000 { <<
2322 compatible = "mediate <<
2323 reg = <0 0x14f09000 0 <<
2324 mediatek,gce-client-r <<
2325 mediatek,gce-events = <<
2326 <<
2327 clocks = <&vppsys1 CL <<
2328 iommus = <&iommu_vdo <<
2329 power-domains = <&spm <<
2330 #dma-cells = <1>; <<
2331 }; <<
2332 <<
2333 dma-controller@14f0a000 { <<
2334 compatible = "mediate <<
2335 reg = <0 0x14f0a000 0 <<
2336 mediatek,gce-client-r <<
2337 mediatek,gce-events = <<
2338 <<
2339 clocks = <&vppsys1 CL <<
2340 iommus = <&iommu_vpp <<
2341 power-domains = <&spm <<
2342 #dma-cells = <1>; <<
2343 }; <<
2344 <<
2345 display@14f0b000 { <<
2346 compatible = "mediate <<
2347 reg = <0 0x14f0b000 0 <<
2348 mediatek,gce-client-r <<
2349 clocks = <&vppsys1 CL <<
2350 }; <<
2351 <<
2352 display@14f0c000 { <<
2353 compatible = "mediate <<
2354 reg = <0 0x14f0c000 0 <<
2355 mediatek,gce-client-r <<
2356 clocks = <&vppsys1 CL <<
2357 }; <<
2358 <<
2359 display@14f0d000 { <<
2360 compatible = "mediate <<
2361 reg = <0 0x14f0d000 0 <<
2362 mediatek,gce-client-r <<
2363 clocks = <&vppsys1 CL <<
2364 }; <<
2365 <<
2366 display@14f0e000 { <<
2367 compatible = "mediate <<
2368 reg = <0 0x14f0e000 0 <<
2369 mediatek,gce-client-r <<
2370 clocks = <&vppsys1 CL <<
2371 }; <<
2372 <<
2373 display@14f0f000 { <<
2374 compatible = "mediate <<
2375 reg = <0 0x14f0f000 0 <<
2376 mediatek,gce-client-r <<
2377 clocks = <&vppsys1 CL <<
2378 }; <<
2379 <<
2380 display@14f10000 { <<
2381 compatible = "mediate <<
2382 reg = <0 0x14f10000 0 <<
2383 mediatek,gce-client-r <<
2384 clocks = <&vppsys1 CL <<
2385 }; <<
2386 <<
2387 display@14f11000 { <<
2388 compatible = "mediate <<
2389 reg = <0 0x14f11000 0 <<
2390 interrupts = <GIC_SPI <<
2391 mediatek,gce-client-r <<
2392 clocks = <&vppsys1 CL <<
2393 power-domains = <&spm <<
2394 }; <<
2395 <<
2396 display@14f12000 { <<
2397 compatible = "mediate <<
2398 reg = <0 0x14f12000 0 <<
2399 interrupts = <GIC_SPI <<
2400 mediatek,gce-client-r <<
2401 clocks = <&vppsys1 CL <<
2402 power-domains = <&spm <<
2403 }; <<
2404 <<
2405 display@14f13000 { <<
2406 compatible = "mediate <<
2407 reg = <0 0x14f13000 0 <<
2408 interrupts = <GIC_SPI <<
2409 mediatek,gce-client-r <<
2410 clocks = <&vppsys1 CL <<
2411 power-domains = <&spm <<
2412 }; <<
2413 <<
2414 display@14f14000 { <<
2415 compatible = "mediate <<
2416 reg = <0 0x14f14000 0 <<
2417 mediatek,gce-client-r <<
2418 mediatek,gce-events = <<
2419 <<
2420 clocks = <&vppsys1 CL <<
2421 }; <<
2422 <<
2423 display@14f15000 { <<
2424 compatible = "mediate <<
2425 reg = <0 0x14f15000 0 <<
2426 mediatek,gce-client-r <<
2427 mediatek,gce-events = <<
2428 <<
2429 clocks = <&vppsys1 CL <<
2430 }; <<
2431 <<
2432 display@14f16000 { <<
2433 compatible = "mediate <<
2434 reg = <0 0x14f16000 0 <<
2435 mediatek,gce-client-r <<
2436 mediatek,gce-events = <<
2437 <<
2438 clocks = <&vppsys1 CL <<
2439 }; <<
2440 <<
2441 display@14f17000 { <<
2442 compatible = "mediate <<
2443 reg = <0 0x14f17000 0 <<
2444 mediatek,gce-client-r <<
2445 clocks = <&vppsys1 CL <<
2446 }; <<
2447 <<
2448 display@14f18000 { <<
2449 compatible = "mediate <<
2450 reg = <0 0x14f18000 0 <<
2451 mediatek,gce-client-r <<
2452 clocks = <&vppsys1 CL <<
2453 }; <<
2454 <<
2455 display@14f19000 { <<
2456 compatible = "mediate <<
2457 reg = <0 0x14f19000 0 <<
2458 mediatek,gce-client-r <<
2459 clocks = <&vppsys1 CL <<
2460 }; <<
2461 <<
2462 display@14f1a000 { <<
2463 compatible = "mediate <<
2464 reg = <0 0x14f1a000 0 <<
2465 mediatek,gce-client-r <<
2466 clocks = <&vppsys1 CL <<
2467 power-domains = <&spm <<
2468 }; <<
2469 <<
2470 display@14f1b000 { <<
2471 compatible = "mediate <<
2472 reg = <0 0x14f1b000 0 <<
2473 mediatek,gce-client-r <<
2474 clocks = <&vppsys1 CL <<
2475 power-domains = <&spm <<
2476 }; <<
2477 <<
2478 display@14f1c000 { <<
2479 compatible = "mediate <<
2480 reg = <0 0x14f1c000 0 <<
2481 interrupts = <GIC_SPI <<
2482 mediatek,gce-client-r <<
2483 clocks = <&vppsys1 CL <<
2484 power-domains = <&spm <<
2485 }; <<
2486 <<
2487 display@14f1d000 { <<
2488 compatible = "mediate <<
2489 reg = <0 0x14f1d000 0 <<
2490 mediatek,gce-client-r <<
2491 interrupts = <GIC_SPI <<
2492 clocks = <&vppsys1 CL <<
2493 power-domains = <&spm <<
2494 }; <<
2495 <<
2496 display@14f1e000 { <<
2497 compatible = "mediate <<
2498 reg = <0 0x14f1e000 0 <<
2499 interrupts = <GIC_SPI <<
2500 mediatek,gce-client-r <<
2501 clocks = <&vppsys1 CL <<
2502 power-domains = <&spm <<
2503 }; <<
2504 <<
2505 display@14f1f000 { <<
2506 compatible = "mediate <<
2507 reg = <0 0x14f1f000 0 <<
2508 interrupts = <GIC_SPI <<
2509 mediatek,gce-client-r <<
2510 clocks = <&vppsys1 CL <<
2511 power-domains = <&spm <<
2512 iommus = <&iommu_vdo <<
2513 }; <<
2514 <<
2515 display@14f20000 { <<
2516 compatible = "mediate <<
2517 reg = <0 0x14f20000 0 <<
2518 mediatek,gce-client-r <<
2519 clocks = <&vppsys1 CL <<
2520 power-domains = <&spm <<
2521 }; <<
2522 <<
2523 display@14f21000 { <<
2524 compatible = "mediate <<
2525 reg = <0 0x14f21000 0 <<
2526 mediatek,gce-client-r <<
2527 clocks = <&vppsys1 CL <<
2528 power-domains = <&spm <<
2529 }; <<
2530 <<
2531 display@14f22000 { <<
2532 compatible = "mediate <<
2533 reg = <0 0x14f22000 0 <<
2534 mediatek,gce-client-r <<
2535 clocks = <&vppsys1 CL <<
2536 power-domains = <&spm <<
2537 }; <<
2538 <<
2539 dma-controller@14f23000 { <<
2540 compatible = "mediate <<
2541 reg = <0 0x14f23000 0 <<
2542 mediatek,gce-client-r <<
2543 mediatek,gce-events = <<
2544 <<
2545 clocks = <&vppsys1 CL <<
2546 iommus = <&iommu_vdo <<
2547 power-domains = <&spm <<
2548 #dma-cells = <1>; <<
2549 }; <<
2550 <<
2551 dma-controller@14f24000 { <<
2552 compatible = "mediate <<
2553 reg = <0 0x14f24000 0 <<
2554 mediatek,gce-client-r <<
2555 mediatek,gce-events = <<
2556 <CMDQ <<
2557 clocks = <&vppsys1 CL <<
2558 iommus = <&iommu_vdo <<
2559 power-domains = <&spm <<
2560 #dma-cells = <1>; <<
2561 }; <<
2562 <<
2563 dma-controller@14f25000 { <<
2564 compatible = "mediate <<
2565 reg = <0 0x14f25000 0 <<
2566 mediatek,gce-client-r <<
2567 mediatek,gce-events = <<
2568 <CMDQ <<
2569 clocks = <&vppsys1 CL <<
2570 iommus = <&iommu_vpp <<
2571 power-domains = <&spm <<
2572 #dma-cells = <1>; <<
2573 }; <<
2574 <<
2575 imgsys: clock-controller@1500 1933 imgsys: clock-controller@15000000 {
2576 compatible = "mediate 1934 compatible = "mediatek,mt8195-imgsys";
2577 reg = <0 0x15000000 0 1935 reg = <0 0x15000000 0 0x1000>;
2578 #clock-cells = <1>; 1936 #clock-cells = <1>;
2579 }; 1937 };
2580 1938
2581 larb9: larb@15001000 { 1939 larb9: larb@15001000 {
2582 compatible = "mediate 1940 compatible = "mediatek,mt8195-smi-larb";
2583 reg = <0 0x15001000 0 1941 reg = <0 0x15001000 0 0x1000>;
2584 mediatek,larb-id = <9 1942 mediatek,larb-id = <9>;
2585 mediatek,smi = <&smi_ 1943 mediatek,smi = <&smi_sub_common_img1_3x1>;
2586 clocks = <&imgsys CLK 1944 clocks = <&imgsys CLK_IMG_LARB9>,
2587 <&imgsys CLK 1945 <&imgsys CLK_IMG_LARB9>,
2588 <&imgsys CLK 1946 <&imgsys CLK_IMG_GALS>;
2589 clock-names = "apb", 1947 clock-names = "apb", "smi", "gals";
2590 power-domains = <&spm 1948 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2591 }; 1949 };
2592 1950
2593 smi_sub_common_img0_3x1: smi@ 1951 smi_sub_common_img0_3x1: smi@15002000 {
2594 compatible = "mediate 1952 compatible = "mediatek,mt8195-smi-sub-common";
2595 reg = <0 0x15002000 0 1953 reg = <0 0x15002000 0 0x1000>;
2596 clocks = <&imgsys CLK 1954 clocks = <&imgsys CLK_IMG_IPE>,
2597 <&imgsys CLK 1955 <&imgsys CLK_IMG_IPE>,
2598 <&vppsys0 CL 1956 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2599 clock-names = "apb", 1957 clock-names = "apb", "smi", "gals0";
2600 mediatek,smi = <&smi_ 1958 mediatek,smi = <&smi_common_vpp>;
2601 power-domains = <&spm 1959 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2602 }; 1960 };
2603 1961
2604 smi_sub_common_img1_3x1: smi@ 1962 smi_sub_common_img1_3x1: smi@15003000 {
2605 compatible = "mediate 1963 compatible = "mediatek,mt8195-smi-sub-common";
2606 reg = <0 0x15003000 0 1964 reg = <0 0x15003000 0 0x1000>;
2607 clocks = <&imgsys CLK 1965 clocks = <&imgsys CLK_IMG_LARB9>,
2608 <&imgsys CLK 1966 <&imgsys CLK_IMG_LARB9>,
2609 <&imgsys CLK 1967 <&imgsys CLK_IMG_GALS>;
2610 clock-names = "apb", 1968 clock-names = "apb", "smi", "gals0";
2611 mediatek,smi = <&smi_ 1969 mediatek,smi = <&smi_common_vdo>;
2612 power-domains = <&spm 1970 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2613 }; 1971 };
2614 1972
2615 imgsys1_dip_top: clock-contro 1973 imgsys1_dip_top: clock-controller@15110000 {
2616 compatible = "mediate 1974 compatible = "mediatek,mt8195-imgsys1_dip_top";
2617 reg = <0 0x15110000 0 1975 reg = <0 0x15110000 0 0x1000>;
2618 #clock-cells = <1>; 1976 #clock-cells = <1>;
2619 }; 1977 };
2620 1978
2621 larb10: larb@15120000 { 1979 larb10: larb@15120000 {
2622 compatible = "mediate 1980 compatible = "mediatek,mt8195-smi-larb";
2623 reg = <0 0x15120000 0 1981 reg = <0 0x15120000 0 0x1000>;
2624 mediatek,larb-id = <1 1982 mediatek,larb-id = <10>;
2625 mediatek,smi = <&smi_ 1983 mediatek,smi = <&smi_sub_common_img1_3x1>;
2626 clocks = <&imgsys CLK 1984 clocks = <&imgsys CLK_IMG_DIP0>,
2627 <&imgsys1_dip_ 1985 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2628 clock-names = "apb", 1986 clock-names = "apb", "smi";
2629 power-domains = <&spm 1987 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2630 }; 1988 };
2631 1989
2632 imgsys1_dip_nr: clock-control 1990 imgsys1_dip_nr: clock-controller@15130000 {
2633 compatible = "mediate 1991 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2634 reg = <0 0x15130000 0 1992 reg = <0 0x15130000 0 0x1000>;
2635 #clock-cells = <1>; 1993 #clock-cells = <1>;
2636 }; 1994 };
2637 1995
2638 imgsys1_wpe: clock-controller 1996 imgsys1_wpe: clock-controller@15220000 {
2639 compatible = "mediate 1997 compatible = "mediatek,mt8195-imgsys1_wpe";
2640 reg = <0 0x15220000 0 1998 reg = <0 0x15220000 0 0x1000>;
2641 #clock-cells = <1>; 1999 #clock-cells = <1>;
2642 }; 2000 };
2643 2001
2644 larb11: larb@15230000 { 2002 larb11: larb@15230000 {
2645 compatible = "mediate 2003 compatible = "mediatek,mt8195-smi-larb";
2646 reg = <0 0x15230000 0 2004 reg = <0 0x15230000 0 0x1000>;
2647 mediatek,larb-id = <1 2005 mediatek,larb-id = <11>;
2648 mediatek,smi = <&smi_ 2006 mediatek,smi = <&smi_sub_common_img1_3x1>;
2649 clocks = <&imgsys CLK 2007 clocks = <&imgsys CLK_IMG_WPE0>,
2650 <&imgsys1_wpe 2008 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2651 clock-names = "apb", 2009 clock-names = "apb", "smi";
2652 power-domains = <&spm 2010 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2653 }; 2011 };
2654 2012
2655 ipesys: clock-controller@1533 2013 ipesys: clock-controller@15330000 {
2656 compatible = "mediate 2014 compatible = "mediatek,mt8195-ipesys";
2657 reg = <0 0x15330000 0 2015 reg = <0 0x15330000 0 0x1000>;
2658 #clock-cells = <1>; 2016 #clock-cells = <1>;
2659 }; 2017 };
2660 2018
2661 larb12: larb@15340000 { 2019 larb12: larb@15340000 {
2662 compatible = "mediate 2020 compatible = "mediatek,mt8195-smi-larb";
2663 reg = <0 0x15340000 0 2021 reg = <0 0x15340000 0 0x1000>;
2664 mediatek,larb-id = <1 2022 mediatek,larb-id = <12>;
2665 mediatek,smi = <&smi_ 2023 mediatek,smi = <&smi_sub_common_img0_3x1>;
2666 clocks = <&ipesys CLK 2024 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2667 <&ipesys CLK 2025 <&ipesys CLK_IPE_SMI_LARB12>;
2668 clock-names = "apb", 2026 clock-names = "apb", "smi";
2669 power-domains = <&spm 2027 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2670 }; 2028 };
2671 2029
2672 camsys: clock-controller@1600 2030 camsys: clock-controller@16000000 {
2673 compatible = "mediate 2031 compatible = "mediatek,mt8195-camsys";
2674 reg = <0 0x16000000 0 2032 reg = <0 0x16000000 0 0x1000>;
2675 #clock-cells = <1>; 2033 #clock-cells = <1>;
2676 }; 2034 };
2677 2035
2678 larb13: larb@16001000 { 2036 larb13: larb@16001000 {
2679 compatible = "mediate 2037 compatible = "mediatek,mt8195-smi-larb";
2680 reg = <0 0x16001000 0 2038 reg = <0 0x16001000 0 0x1000>;
2681 mediatek,larb-id = <1 2039 mediatek,larb-id = <13>;
2682 mediatek,smi = <&smi_ 2040 mediatek,smi = <&smi_sub_common_cam_4x1>;
2683 clocks = <&camsys CLK 2041 clocks = <&camsys CLK_CAM_LARB13>,
2684 <&camsys CLK_C 2042 <&camsys CLK_CAM_LARB13>,
2685 <&camsys CLK_C 2043 <&camsys CLK_CAM_CAM2MM0_GALS>;
2686 clock-names = "apb", 2044 clock-names = "apb", "smi", "gals";
2687 power-domains = <&spm 2045 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688 }; 2046 };
2689 2047
2690 larb14: larb@16002000 { 2048 larb14: larb@16002000 {
2691 compatible = "mediate 2049 compatible = "mediatek,mt8195-smi-larb";
2692 reg = <0 0x16002000 0 2050 reg = <0 0x16002000 0 0x1000>;
2693 mediatek,larb-id = <1 2051 mediatek,larb-id = <14>;
2694 mediatek,smi = <&smi_ 2052 mediatek,smi = <&smi_sub_common_cam_7x1>;
2695 clocks = <&camsys CLK 2053 clocks = <&camsys CLK_CAM_LARB14>,
2696 <&camsys CLK 2054 <&camsys CLK_CAM_LARB14>;
2697 clock-names = "apb", 2055 clock-names = "apb", "smi";
2698 power-domains = <&spm 2056 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2699 }; 2057 };
2700 2058
2701 smi_sub_common_cam_4x1: smi@1 2059 smi_sub_common_cam_4x1: smi@16004000 {
2702 compatible = "mediate 2060 compatible = "mediatek,mt8195-smi-sub-common";
2703 reg = <0 0x16004000 0 2061 reg = <0 0x16004000 0 0x1000>;
2704 clocks = <&camsys CLK 2062 clocks = <&camsys CLK_CAM_LARB13>,
2705 <&camsys CLK 2063 <&camsys CLK_CAM_LARB13>,
2706 <&camsys CLK 2064 <&camsys CLK_CAM_CAM2MM0_GALS>;
2707 clock-names = "apb", 2065 clock-names = "apb", "smi", "gals0";
2708 mediatek,smi = <&smi_ 2066 mediatek,smi = <&smi_common_vdo>;
2709 power-domains = <&spm 2067 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2710 }; 2068 };
2711 2069
2712 smi_sub_common_cam_7x1: smi@1 2070 smi_sub_common_cam_7x1: smi@16005000 {
2713 compatible = "mediate 2071 compatible = "mediatek,mt8195-smi-sub-common";
2714 reg = <0 0x16005000 0 2072 reg = <0 0x16005000 0 0x1000>;
2715 clocks = <&camsys CLK 2073 clocks = <&camsys CLK_CAM_LARB14>,
2716 <&camsys CLK 2074 <&camsys CLK_CAM_CAM2MM1_GALS>,
2717 <&vppsys0 CL 2075 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2718 clock-names = "apb", 2076 clock-names = "apb", "smi", "gals0";
2719 mediatek,smi = <&smi_ 2077 mediatek,smi = <&smi_common_vpp>;
2720 power-domains = <&spm 2078 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2721 }; 2079 };
2722 2080
2723 larb16: larb@16012000 { 2081 larb16: larb@16012000 {
2724 compatible = "mediate 2082 compatible = "mediatek,mt8195-smi-larb";
2725 reg = <0 0x16012000 0 2083 reg = <0 0x16012000 0 0x1000>;
2726 mediatek,larb-id = <1 2084 mediatek,larb-id = <16>;
2727 mediatek,smi = <&smi_ 2085 mediatek,smi = <&smi_sub_common_cam_7x1>;
2728 clocks = <&camsys_raw 2086 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2729 <&camsys_raw 2087 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2730 clock-names = "apb", 2088 clock-names = "apb", "smi";
2731 power-domains = <&spm 2089 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2732 }; 2090 };
2733 2091
2734 larb17: larb@16013000 { 2092 larb17: larb@16013000 {
2735 compatible = "mediate 2093 compatible = "mediatek,mt8195-smi-larb";
2736 reg = <0 0x16013000 0 2094 reg = <0 0x16013000 0 0x1000>;
2737 mediatek,larb-id = <1 2095 mediatek,larb-id = <17>;
2738 mediatek,smi = <&smi_ 2096 mediatek,smi = <&smi_sub_common_cam_4x1>;
2739 clocks = <&camsys_yuv 2097 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2740 <&camsys_yuv 2098 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2741 clock-names = "apb", 2099 clock-names = "apb", "smi";
2742 power-domains = <&spm 2100 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2743 }; 2101 };
2744 2102
2745 larb27: larb@16014000 { 2103 larb27: larb@16014000 {
2746 compatible = "mediate 2104 compatible = "mediatek,mt8195-smi-larb";
2747 reg = <0 0x16014000 0 2105 reg = <0 0x16014000 0 0x1000>;
2748 mediatek,larb-id = <2 2106 mediatek,larb-id = <27>;
2749 mediatek,smi = <&smi_ 2107 mediatek,smi = <&smi_sub_common_cam_7x1>;
2750 clocks = <&camsys_raw 2108 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2751 <&camsys_raw 2109 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2752 clock-names = "apb", 2110 clock-names = "apb", "smi";
2753 power-domains = <&spm 2111 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2754 }; 2112 };
2755 2113
2756 larb28: larb@16015000 { 2114 larb28: larb@16015000 {
2757 compatible = "mediate 2115 compatible = "mediatek,mt8195-smi-larb";
2758 reg = <0 0x16015000 0 2116 reg = <0 0x16015000 0 0x1000>;
2759 mediatek,larb-id = <2 2117 mediatek,larb-id = <28>;
2760 mediatek,smi = <&smi_ 2118 mediatek,smi = <&smi_sub_common_cam_4x1>;
2761 clocks = <&camsys_yuv 2119 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2762 <&camsys_yuv 2120 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2763 clock-names = "apb", 2121 clock-names = "apb", "smi";
2764 power-domains = <&spm 2122 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2765 }; 2123 };
2766 2124
2767 camsys_rawa: clock-controller 2125 camsys_rawa: clock-controller@1604f000 {
2768 compatible = "mediate 2126 compatible = "mediatek,mt8195-camsys_rawa";
2769 reg = <0 0x1604f000 0 2127 reg = <0 0x1604f000 0 0x1000>;
2770 #clock-cells = <1>; 2128 #clock-cells = <1>;
2771 }; 2129 };
2772 2130
2773 camsys_yuva: clock-controller 2131 camsys_yuva: clock-controller@1606f000 {
2774 compatible = "mediate 2132 compatible = "mediatek,mt8195-camsys_yuva";
2775 reg = <0 0x1606f000 0 2133 reg = <0 0x1606f000 0 0x1000>;
2776 #clock-cells = <1>; 2134 #clock-cells = <1>;
2777 }; 2135 };
2778 2136
2779 camsys_rawb: clock-controller 2137 camsys_rawb: clock-controller@1608f000 {
2780 compatible = "mediate 2138 compatible = "mediatek,mt8195-camsys_rawb";
2781 reg = <0 0x1608f000 0 2139 reg = <0 0x1608f000 0 0x1000>;
2782 #clock-cells = <1>; 2140 #clock-cells = <1>;
2783 }; 2141 };
2784 2142
2785 camsys_yuvb: clock-controller 2143 camsys_yuvb: clock-controller@160af000 {
2786 compatible = "mediate 2144 compatible = "mediatek,mt8195-camsys_yuvb";
2787 reg = <0 0x160af000 0 2145 reg = <0 0x160af000 0 0x1000>;
2788 #clock-cells = <1>; 2146 #clock-cells = <1>;
2789 }; 2147 };
2790 2148
2791 camsys_mraw: clock-controller 2149 camsys_mraw: clock-controller@16140000 {
2792 compatible = "mediate 2150 compatible = "mediatek,mt8195-camsys_mraw";
2793 reg = <0 0x16140000 0 2151 reg = <0 0x16140000 0 0x1000>;
2794 #clock-cells = <1>; 2152 #clock-cells = <1>;
2795 }; 2153 };
2796 2154
2797 larb25: larb@16141000 { 2155 larb25: larb@16141000 {
2798 compatible = "mediate 2156 compatible = "mediatek,mt8195-smi-larb";
2799 reg = <0 0x16141000 0 2157 reg = <0 0x16141000 0 0x1000>;
2800 mediatek,larb-id = <2 2158 mediatek,larb-id = <25>;
2801 mediatek,smi = <&smi_ 2159 mediatek,smi = <&smi_sub_common_cam_4x1>;
2802 clocks = <&camsys CLK 2160 clocks = <&camsys CLK_CAM_LARB13>,
2803 <&camsys_mra 2161 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2804 <&camsys CLK 2162 <&camsys CLK_CAM_CAM2MM0_GALS>;
2805 clock-names = "apb", 2163 clock-names = "apb", "smi", "gals";
2806 power-domains = <&spm 2164 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2807 }; 2165 };
2808 2166
2809 larb26: larb@16142000 { 2167 larb26: larb@16142000 {
2810 compatible = "mediate 2168 compatible = "mediatek,mt8195-smi-larb";
2811 reg = <0 0x16142000 0 2169 reg = <0 0x16142000 0 0x1000>;
2812 mediatek,larb-id = <2 2170 mediatek,larb-id = <26>;
2813 mediatek,smi = <&smi_ 2171 mediatek,smi = <&smi_sub_common_cam_7x1>;
2814 clocks = <&camsys_mra 2172 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2815 <&camsys_mra 2173 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2816 clock-names = "apb", 2174 clock-names = "apb", "smi";
2817 power-domains = <&spm 2175 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2818 2176
2819 }; 2177 };
2820 2178
2821 ccusys: clock-controller@1720 2179 ccusys: clock-controller@17200000 {
2822 compatible = "mediate 2180 compatible = "mediatek,mt8195-ccusys";
2823 reg = <0 0x17200000 0 2181 reg = <0 0x17200000 0 0x1000>;
2824 #clock-cells = <1>; 2182 #clock-cells = <1>;
2825 }; 2183 };
2826 2184
2827 larb18: larb@17201000 { 2185 larb18: larb@17201000 {
2828 compatible = "mediate 2186 compatible = "mediatek,mt8195-smi-larb";
2829 reg = <0 0x17201000 0 2187 reg = <0 0x17201000 0 0x1000>;
2830 mediatek,larb-id = <1 2188 mediatek,larb-id = <18>;
2831 mediatek,smi = <&smi_ 2189 mediatek,smi = <&smi_sub_common_cam_7x1>;
2832 clocks = <&ccusys CLK 2190 clocks = <&ccusys CLK_CCU_LARB18>,
2833 <&ccusys CLK 2191 <&ccusys CLK_CCU_LARB18>;
2834 clock-names = "apb", 2192 clock-names = "apb", "smi";
2835 power-domains = <&spm 2193 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2836 }; 2194 };
2837 2195
2838 video-codec@18000000 { <<
2839 compatible = "mediate <<
2840 mediatek,scp = <&scp> <<
2841 iommus = <&iommu_vdo <<
2842 #address-cells = <2>; <<
2843 #size-cells = <2>; <<
2844 reg = <0 0x18000000 0 <<
2845 <0 0x18004000 0 <<
2846 ranges = <0 0 0 0x180 <<
2847 <<
2848 video-codec@2000 { <<
2849 compatible = <<
2850 reg = <0 0x20 <<
2851 iommus = <&io <<
2852 <&io <<
2853 clocks = <&to <<
2854 <&vd <<
2855 <&vd <<
2856 <&to <<
2857 clock-names = <<
2858 assigned-cloc <<
2859 assigned-cloc <<
2860 power-domains <<
2861 }; <<
2862 <<
2863 video-codec@10000 { <<
2864 compatible = <<
2865 reg = <0 0x10 <<
2866 interrupts = <<
2867 iommus = <&io <<
2868 <&io <<
2869 <&io <<
2870 <&io <<
2871 <&io <<
2872 <&io <<
2873 clocks = <&to <<
2874 <&vd <<
2875 <&vd <<
2876 <&to <<
2877 clock-names = <<
2878 assigned-cloc <<
2879 assigned-cloc <<
2880 power-domains <<
2881 }; <<
2882 <<
2883 video-codec@25000 { <<
2884 compatible = <<
2885 reg = <0 0x25 <<
2886 interrupts = <<
2887 iommus = <&io <<
2888 <&io <<
2889 <&io <<
2890 <&io <<
2891 <&io <<
2892 <&io <<
2893 <&io <<
2894 <&io <<
2895 <&io <<
2896 <&io <<
2897 clocks = <&to <<
2898 <&vd <<
2899 <&vd <<
2900 <&to <<
2901 clock-names = <<
2902 assigned-cloc <<
2903 assigned-cloc <<
2904 power-domains <<
2905 }; <<
2906 }; <<
2907 <<
2908 larb24: larb@1800d000 { 2196 larb24: larb@1800d000 {
2909 compatible = "mediate 2197 compatible = "mediatek,mt8195-smi-larb";
2910 reg = <0 0x1800d000 0 2198 reg = <0 0x1800d000 0 0x1000>;
2911 mediatek,larb-id = <2 2199 mediatek,larb-id = <24>;
2912 mediatek,smi = <&smi_ 2200 mediatek,smi = <&smi_common_vdo>;
2913 clocks = <&vdecsys_so 2201 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2914 <&vdecsys_so 2202 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2915 clock-names = "apb", 2203 clock-names = "apb", "smi";
2916 power-domains = <&spm 2204 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2917 }; 2205 };
2918 2206
2919 larb23: larb@1800e000 { 2207 larb23: larb@1800e000 {
2920 compatible = "mediate 2208 compatible = "mediatek,mt8195-smi-larb";
2921 reg = <0 0x1800e000 0 2209 reg = <0 0x1800e000 0 0x1000>;
2922 mediatek,larb-id = <2 2210 mediatek,larb-id = <23>;
2923 mediatek,smi = <&smi_ 2211 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2924 clocks = <&vppsys0 CL 2212 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2925 <&vdecsys_so 2213 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2926 clock-names = "apb", 2214 clock-names = "apb", "smi";
2927 power-domains = <&spm 2215 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2928 }; 2216 };
2929 2217
2930 vdecsys_soc: clock-controller 2218 vdecsys_soc: clock-controller@1800f000 {
2931 compatible = "mediate 2219 compatible = "mediatek,mt8195-vdecsys_soc";
2932 reg = <0 0x1800f000 0 2220 reg = <0 0x1800f000 0 0x1000>;
2933 #clock-cells = <1>; 2221 #clock-cells = <1>;
2934 }; 2222 };
2935 2223
2936 larb21: larb@1802e000 { 2224 larb21: larb@1802e000 {
2937 compatible = "mediate 2225 compatible = "mediatek,mt8195-smi-larb";
2938 reg = <0 0x1802e000 0 2226 reg = <0 0x1802e000 0 0x1000>;
2939 mediatek,larb-id = <2 2227 mediatek,larb-id = <21>;
2940 mediatek,smi = <&smi_ 2228 mediatek,smi = <&smi_common_vdo>;
2941 clocks = <&vdecsys CL 2229 clocks = <&vdecsys CLK_VDEC_LARB1>,
2942 <&vdecsys CL 2230 <&vdecsys CLK_VDEC_LARB1>;
2943 clock-names = "apb", 2231 clock-names = "apb", "smi";
2944 power-domains = <&spm 2232 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2945 }; 2233 };
2946 2234
2947 vdecsys: clock-controller@180 2235 vdecsys: clock-controller@1802f000 {
2948 compatible = "mediate 2236 compatible = "mediatek,mt8195-vdecsys";
2949 reg = <0 0x1802f000 0 2237 reg = <0 0x1802f000 0 0x1000>;
2950 #clock-cells = <1>; 2238 #clock-cells = <1>;
2951 }; 2239 };
2952 2240
2953 larb22: larb@1803e000 { 2241 larb22: larb@1803e000 {
2954 compatible = "mediate 2242 compatible = "mediatek,mt8195-smi-larb";
2955 reg = <0 0x1803e000 0 2243 reg = <0 0x1803e000 0 0x1000>;
2956 mediatek,larb-id = <2 2244 mediatek,larb-id = <22>;
2957 mediatek,smi = <&smi_ 2245 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2958 clocks = <&vppsys0 CL 2246 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2959 <&vdecsys_co 2247 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2960 clock-names = "apb", 2248 clock-names = "apb", "smi";
2961 power-domains = <&spm 2249 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2962 }; 2250 };
2963 2251
2964 vdecsys_core1: clock-controll 2252 vdecsys_core1: clock-controller@1803f000 {
2965 compatible = "mediate 2253 compatible = "mediatek,mt8195-vdecsys_core1";
2966 reg = <0 0x1803f000 0 2254 reg = <0 0x1803f000 0 0x1000>;
2967 #clock-cells = <1>; 2255 #clock-cells = <1>;
2968 }; 2256 };
2969 2257
2970 apusys_pll: clock-controller@ 2258 apusys_pll: clock-controller@190f3000 {
2971 compatible = "mediate 2259 compatible = "mediatek,mt8195-apusys_pll";
2972 reg = <0 0x190f3000 0 2260 reg = <0 0x190f3000 0 0x1000>;
2973 #clock-cells = <1>; 2261 #clock-cells = <1>;
2974 }; 2262 };
2975 2263
2976 vencsys: clock-controller@1a0 2264 vencsys: clock-controller@1a000000 {
2977 compatible = "mediate 2265 compatible = "mediatek,mt8195-vencsys";
2978 reg = <0 0x1a000000 0 2266 reg = <0 0x1a000000 0 0x1000>;
2979 #clock-cells = <1>; 2267 #clock-cells = <1>;
2980 }; 2268 };
2981 2269
2982 larb19: larb@1a010000 { 2270 larb19: larb@1a010000 {
2983 compatible = "mediate 2271 compatible = "mediatek,mt8195-smi-larb";
2984 reg = <0 0x1a010000 0 2272 reg = <0 0x1a010000 0 0x1000>;
2985 mediatek,larb-id = <1 2273 mediatek,larb-id = <19>;
2986 mediatek,smi = <&smi_ 2274 mediatek,smi = <&smi_common_vdo>;
2987 clocks = <&vencsys CL 2275 clocks = <&vencsys CLK_VENC_VENC>,
2988 <&vencsys CL 2276 <&vencsys CLK_VENC_GALS>;
2989 clock-names = "apb", 2277 clock-names = "apb", "smi";
2990 power-domains = <&spm 2278 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2991 }; 2279 };
2992 2280
2993 venc: video-codec@1a020000 { 2281 venc: video-codec@1a020000 {
2994 compatible = "mediate 2282 compatible = "mediatek,mt8195-vcodec-enc";
2995 reg = <0 0x1a020000 0 2283 reg = <0 0x1a020000 0 0x10000>;
2996 iommus = <&iommu_vdo 2284 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2997 <&iommu_vdo 2285 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2998 <&iommu_vdo 2286 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2999 <&iommu_vdo 2287 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
3000 <&iommu_vdo 2288 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
3001 <&iommu_vdo 2289 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
3002 <&iommu_vdo 2290 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
3003 <&iommu_vdo 2291 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
3004 <&iommu_vdo 2292 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
3005 interrupts = <GIC_SPI 2293 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
3006 mediatek,scp = <&scp> 2294 mediatek,scp = <&scp>;
3007 clocks = <&vencsys CL 2295 clocks = <&vencsys CLK_VENC_VENC>;
3008 clock-names = "venc_s 2296 clock-names = "venc_sel";
3009 assigned-clocks = <&t 2297 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3010 assigned-clock-parent 2298 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3011 power-domains = <&spm 2299 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3012 #address-cells = <2>; 2300 #address-cells = <2>;
3013 #size-cells = <2>; 2301 #size-cells = <2>;
>> 2302 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
3014 }; 2303 };
3015 2304
3016 jpgdec-master { 2305 jpgdec-master {
3017 compatible = "mediate 2306 compatible = "mediatek,mt8195-jpgdec";
3018 power-domains = <&spm 2307 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3019 iommus = <&iommu_vdo 2308 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3020 <&iommu_vdo 2309 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3021 <&iommu_vdo 2310 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3022 <&iommu_vdo 2311 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3023 <&iommu_vdo 2312 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3024 <&iommu_vdo 2313 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
>> 2314 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
3025 #address-cells = <2>; 2315 #address-cells = <2>;
3026 #size-cells = <2>; 2316 #size-cells = <2>;
3027 ranges; 2317 ranges;
3028 2318
3029 jpgdec@1a040000 { 2319 jpgdec@1a040000 {
3030 compatible = 2320 compatible = "mediatek,mt8195-jpgdec-hw";
3031 reg = <0 0x1a 2321 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3032 iommus = <&io 2322 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3033 <&io 2323 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3034 <&io 2324 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3035 <&io 2325 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3036 <&io 2326 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3037 <&io 2327 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3038 interrupts = 2328 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3039 clocks = <&ve 2329 clocks = <&vencsys CLK_VENC_JPGDEC>;
3040 clock-names = 2330 clock-names = "jpgdec";
3041 power-domains 2331 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3042 }; 2332 };
3043 2333
3044 jpgdec@1a050000 { 2334 jpgdec@1a050000 {
3045 compatible = 2335 compatible = "mediatek,mt8195-jpgdec-hw";
3046 reg = <0 0x1a 2336 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3047 iommus = <&io 2337 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3048 <&io 2338 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3049 <&io 2339 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3050 <&io 2340 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3051 <&io 2341 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3052 <&io 2342 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3053 interrupts = 2343 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3054 clocks = <&ve 2344 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3055 clock-names = 2345 clock-names = "jpgdec";
3056 power-domains 2346 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3057 }; 2347 };
3058 2348
3059 jpgdec@1b040000 { 2349 jpgdec@1b040000 {
3060 compatible = 2350 compatible = "mediatek,mt8195-jpgdec-hw";
3061 reg = <0 0x1b 2351 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3062 iommus = <&io 2352 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3063 <&io 2353 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3064 <&io 2354 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3065 <&io 2355 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3066 <&io 2356 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3067 <&io 2357 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3068 interrupts = 2358 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3069 clocks = <&ve 2359 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3070 clock-names = 2360 clock-names = "jpgdec";
3071 power-domains 2361 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3072 }; 2362 };
3073 }; 2363 };
3074 2364
3075 vencsys_core1: clock-controll 2365 vencsys_core1: clock-controller@1b000000 {
3076 compatible = "mediate 2366 compatible = "mediatek,mt8195-vencsys_core1";
3077 reg = <0 0x1b000000 0 2367 reg = <0 0x1b000000 0 0x1000>;
3078 #clock-cells = <1>; 2368 #clock-cells = <1>;
3079 }; 2369 };
3080 2370
3081 vdosys0: syscon@1c01a000 { 2371 vdosys0: syscon@1c01a000 {
3082 compatible = "mediate 2372 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3083 reg = <0 0x1c01a000 0 2373 reg = <0 0x1c01a000 0 0x1000>;
3084 mboxes = <&gce0 0 CMD 2374 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3085 #clock-cells = <1>; 2375 #clock-cells = <1>;
3086 mediatek,gce-client-r <<
3087 }; 2376 };
3088 2377
3089 2378
3090 jpgenc-master { 2379 jpgenc-master {
3091 compatible = "mediate 2380 compatible = "mediatek,mt8195-jpgenc";
3092 power-domains = <&spm 2381 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3093 iommus = <&iommu_vpp 2382 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3094 <&iom 2383 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3095 <&iom 2384 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3096 <&iom 2385 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
>> 2386 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
3097 #address-cells = <2>; 2387 #address-cells = <2>;
3098 #size-cells = <2>; 2388 #size-cells = <2>;
3099 ranges; 2389 ranges;
3100 2390
3101 jpgenc@1a030000 { 2391 jpgenc@1a030000 {
3102 compatible = 2392 compatible = "mediatek,mt8195-jpgenc-hw";
3103 reg = <0 0x1a 2393 reg = <0 0x1a030000 0 0x10000>;
3104 iommus = <&io 2394 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3105 2395 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3106 2396 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3107 2397 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3108 interrupts = 2398 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3109 clocks = <&ve 2399 clocks = <&vencsys CLK_VENC_JPGENC>;
3110 clock-names = 2400 clock-names = "jpgenc";
3111 power-domains 2401 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3112 }; 2402 };
3113 2403
3114 jpgenc@1b030000 { 2404 jpgenc@1b030000 {
3115 compatible = 2405 compatible = "mediatek,mt8195-jpgenc-hw";
3116 reg = <0 0x1b 2406 reg = <0 0x1b030000 0 0x10000>;
3117 iommus = <&io 2407 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3118 2408 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3119 2409 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3120 2410 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3121 interrupts = 2411 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3122 clocks = <&ve 2412 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3123 clock-names = 2413 clock-names = "jpgenc";
3124 power-domains 2414 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3125 }; 2415 };
3126 }; 2416 };
3127 2417
3128 larb20: larb@1b010000 { 2418 larb20: larb@1b010000 {
3129 compatible = "mediate 2419 compatible = "mediatek,mt8195-smi-larb";
3130 reg = <0 0x1b010000 0 2420 reg = <0 0x1b010000 0 0x1000>;
3131 mediatek,larb-id = <2 2421 mediatek,larb-id = <20>;
3132 mediatek,smi = <&smi_ 2422 mediatek,smi = <&smi_common_vpp>;
3133 clocks = <&vencsys_co !! 2423 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
3134 <&vencsys_co 2424 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3135 <&vppsys0 CL 2425 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3136 clock-names = "apb", 2426 clock-names = "apb", "smi", "gals";
3137 power-domains = <&spm 2427 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3138 }; 2428 };
3139 2429
3140 ovl0: ovl@1c000000 { 2430 ovl0: ovl@1c000000 {
3141 compatible = "mediate 2431 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3142 reg = <0 0x1c000000 0 2432 reg = <0 0x1c000000 0 0x1000>;
3143 interrupts = <GIC_SPI 2433 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3144 power-domains = <&spm 2434 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3145 clocks = <&vdosys0 CL 2435 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3146 iommus = <&iommu_vdo 2436 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3147 mediatek,gce-client-r 2437 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3148 }; 2438 };
3149 2439
3150 rdma0: rdma@1c002000 { 2440 rdma0: rdma@1c002000 {
3151 compatible = "mediate 2441 compatible = "mediatek,mt8195-disp-rdma";
3152 reg = <0 0x1c002000 0 2442 reg = <0 0x1c002000 0 0x1000>;
3153 interrupts = <GIC_SPI 2443 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3154 power-domains = <&spm 2444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3155 clocks = <&vdosys0 CL 2445 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3156 iommus = <&iommu_vdo 2446 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3157 mediatek,gce-client-r 2447 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3158 }; 2448 };
3159 2449
3160 color0: color@1c003000 { 2450 color0: color@1c003000 {
3161 compatible = "mediate 2451 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3162 reg = <0 0x1c003000 0 2452 reg = <0 0x1c003000 0 0x1000>;
3163 interrupts = <GIC_SPI 2453 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3164 power-domains = <&spm 2454 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3165 clocks = <&vdosys0 CL 2455 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3166 mediatek,gce-client-r 2456 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3167 }; 2457 };
3168 2458
3169 ccorr0: ccorr@1c004000 { 2459 ccorr0: ccorr@1c004000 {
3170 compatible = "mediate 2460 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3171 reg = <0 0x1c004000 0 2461 reg = <0 0x1c004000 0 0x1000>;
3172 interrupts = <GIC_SPI 2462 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3173 power-domains = <&spm 2463 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3174 clocks = <&vdosys0 CL 2464 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3175 mediatek,gce-client-r 2465 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3176 }; 2466 };
3177 2467
3178 aal0: aal@1c005000 { 2468 aal0: aal@1c005000 {
3179 compatible = "mediate 2469 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3180 reg = <0 0x1c005000 0 2470 reg = <0 0x1c005000 0 0x1000>;
3181 interrupts = <GIC_SPI 2471 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3182 power-domains = <&spm 2472 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3183 clocks = <&vdosys0 CL 2473 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3184 mediatek,gce-client-r 2474 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3185 }; 2475 };
3186 2476
3187 gamma0: gamma@1c006000 { 2477 gamma0: gamma@1c006000 {
3188 compatible = "mediate 2478 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3189 reg = <0 0x1c006000 0 2479 reg = <0 0x1c006000 0 0x1000>;
3190 interrupts = <GIC_SPI 2480 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3191 power-domains = <&spm 2481 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3192 clocks = <&vdosys0 CL 2482 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3193 mediatek,gce-client-r 2483 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3194 }; 2484 };
3195 2485
3196 dither0: dither@1c007000 { 2486 dither0: dither@1c007000 {
3197 compatible = "mediate 2487 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3198 reg = <0 0x1c007000 0 2488 reg = <0 0x1c007000 0 0x1000>;
3199 interrupts = <GIC_SPI 2489 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3200 power-domains = <&spm 2490 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3201 clocks = <&vdosys0 CL 2491 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3202 mediatek,gce-client-r 2492 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3203 }; 2493 };
3204 2494
3205 dsi0: dsi@1c008000 { <<
3206 compatible = "mediate <<
3207 reg = <0 0x1c008000 0 <<
3208 interrupts = <GIC_SPI <<
3209 power-domains = <&spm <<
3210 clocks = <&vdosys0 CL <<
3211 <&vdosys0 CL <<
3212 <&mipi_tx0>; <<
3213 clock-names = "engine <<
3214 phys = <&mipi_tx0>; <<
3215 phy-names = "dphy"; <<
3216 status = "disabled"; <<
3217 }; <<
3218 <<
3219 dsc0: dsc@1c009000 { 2495 dsc0: dsc@1c009000 {
3220 compatible = "mediate 2496 compatible = "mediatek,mt8195-disp-dsc";
3221 reg = <0 0x1c009000 0 2497 reg = <0 0x1c009000 0 0x1000>;
3222 interrupts = <GIC_SPI 2498 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3223 power-domains = <&spm 2499 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3224 clocks = <&vdosys0 CL 2500 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3225 mediatek,gce-client-r 2501 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3226 }; 2502 };
3227 2503
3228 dsi1: dsi@1c012000 { <<
3229 compatible = "mediate <<
3230 reg = <0 0x1c012000 0 <<
3231 interrupts = <GIC_SPI <<
3232 power-domains = <&spm <<
3233 clocks = <&vdosys0 CL <<
3234 <&vdosys0 CL <<
3235 <&mipi_tx1>; <<
3236 clock-names = "engine <<
3237 phys = <&mipi_tx1>; <<
3238 phy-names = "dphy"; <<
3239 status = "disabled"; <<
3240 }; <<
3241 <<
3242 merge0: merge@1c014000 { 2504 merge0: merge@1c014000 {
3243 compatible = "mediate 2505 compatible = "mediatek,mt8195-disp-merge";
3244 reg = <0 0x1c014000 0 2506 reg = <0 0x1c014000 0 0x1000>;
3245 interrupts = <GIC_SPI 2507 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3246 power-domains = <&spm 2508 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3247 clocks = <&vdosys0 CL 2509 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3248 mediatek,gce-client-r 2510 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3249 }; 2511 };
3250 2512
3251 dp_intf0: dp-intf@1c015000 { 2513 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediate 2514 compatible = "mediatek,mt8195-dp-intf";
3253 reg = <0 0x1c015000 0 2515 reg = <0 0x1c015000 0 0x1000>;
3254 interrupts = <GIC_SPI 2516 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3255 clocks = <&vdosys0 CL !! 2517 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
3256 <&vdosys0 C !! 2518 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3257 <&apmixedsys 2519 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3258 clock-names = "pixel" !! 2520 clock-names = "engine", "pixel", "pll";
3259 status = "disabled"; 2521 status = "disabled";
3260 }; 2522 };
3261 2523
3262 mutex: mutex@1c016000 { 2524 mutex: mutex@1c016000 {
3263 compatible = "mediate 2525 compatible = "mediatek,mt8195-disp-mutex";
3264 reg = <0 0x1c016000 0 2526 reg = <0 0x1c016000 0 0x1000>;
3265 interrupts = <GIC_SPI 2527 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3266 power-domains = <&spm 2528 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3267 clocks = <&vdosys0 CL 2529 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3268 mediatek,gce-client-r <<
3269 mediatek,gce-events = 2530 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3270 }; 2531 };
3271 2532
3272 larb0: larb@1c018000 { 2533 larb0: larb@1c018000 {
3273 compatible = "mediate 2534 compatible = "mediatek,mt8195-smi-larb";
3274 reg = <0 0x1c018000 0 2535 reg = <0 0x1c018000 0 0x1000>;
3275 mediatek,larb-id = <0 2536 mediatek,larb-id = <0>;
3276 mediatek,smi = <&smi_ 2537 mediatek,smi = <&smi_common_vdo>;
3277 clocks = <&vdosys0 CL 2538 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3278 <&vdosys0 CL 2539 <&vdosys0 CLK_VDO0_SMI_LARB>,
3279 <&vppsys0 CL 2540 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3280 clock-names = "apb", 2541 clock-names = "apb", "smi", "gals";
3281 power-domains = <&spm 2542 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3282 }; 2543 };
3283 2544
3284 larb1: larb@1c019000 { 2545 larb1: larb@1c019000 {
3285 compatible = "mediate 2546 compatible = "mediatek,mt8195-smi-larb";
3286 reg = <0 0x1c019000 0 2547 reg = <0 0x1c019000 0 0x1000>;
3287 mediatek,larb-id = <1 2548 mediatek,larb-id = <1>;
3288 mediatek,smi = <&smi_ 2549 mediatek,smi = <&smi_common_vpp>;
3289 clocks = <&vdosys0 CL 2550 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3290 <&vppsys0 CL 2551 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3291 <&vppsys0 CL 2552 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3292 clock-names = "apb", 2553 clock-names = "apb", "smi", "gals";
3293 power-domains = <&spm 2554 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294 }; 2555 };
3295 2556
3296 vdosys1: syscon@1c100000 { 2557 vdosys1: syscon@1c100000 {
3297 compatible = "mediate 2558 compatible = "mediatek,mt8195-vdosys1", "syscon";
3298 reg = <0 0x1c100000 0 2559 reg = <0 0x1c100000 0 0x1000>;
3299 mboxes = <&gce0 1 CMD <<
3300 mediatek,gce-client-r <<
3301 #clock-cells = <1>; 2560 #clock-cells = <1>;
3302 #reset-cells = <1>; <<
3303 }; 2561 };
3304 2562
3305 smi_common_vdo: smi@1c01b000 2563 smi_common_vdo: smi@1c01b000 {
3306 compatible = "mediate 2564 compatible = "mediatek,mt8195-smi-common-vdo";
3307 reg = <0 0x1c01b000 0 2565 reg = <0 0x1c01b000 0 0x1000>;
3308 clocks = <&vdosys0 CL 2566 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3309 <&vdosys0 CL 2567 <&vdosys0 CLK_VDO0_SMI_EMI>,
3310 <&vdosys0 CL 2568 <&vdosys0 CLK_VDO0_SMI_RSI>,
3311 <&vdosys0 CL 2569 <&vdosys0 CLK_VDO0_SMI_GALS>;
3312 clock-names = "apb", 2570 clock-names = "apb", "smi", "gals0", "gals1";
3313 power-domains = <&spm 2571 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3314 2572
3315 }; 2573 };
3316 2574
3317 iommu_vdo: iommu@1c01f000 { 2575 iommu_vdo: iommu@1c01f000 {
3318 compatible = "mediate 2576 compatible = "mediatek,mt8195-iommu-vdo";
3319 reg = <0 0x1c01f000 0 2577 reg = <0 0x1c01f000 0 0x1000>;
3320 mediatek,larbs = <&la 2578 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3321 &la 2579 &larb10 &larb11 &larb13 &larb17
3322 &la 2580 &larb19 &larb21 &larb24 &larb25
3323 &la 2581 &larb28>;
3324 interrupts = <GIC_SPI 2582 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3325 #iommu-cells = <1>; 2583 #iommu-cells = <1>;
3326 clocks = <&vdosys0 CL 2584 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3327 clock-names = "bclk"; 2585 clock-names = "bclk";
3328 power-domains = <&spm 2586 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3329 }; 2587 };
3330 2588
3331 mutex1: mutex@1c101000 { <<
3332 compatible = "mediate <<
3333 reg = <0 0x1c101000 0 <<
3334 reg-names = "vdo1_mut <<
3335 interrupts = <GIC_SPI <<
3336 power-domains = <&spm <<
3337 clocks = <&vdosys1 CL <<
3338 clock-names = "vdo1_m <<
3339 mediatek,gce-client-r <<
3340 mediatek,gce-events = <<
3341 }; <<
3342 <<
3343 larb2: larb@1c102000 { 2589 larb2: larb@1c102000 {
3344 compatible = "mediate 2590 compatible = "mediatek,mt8195-smi-larb";
3345 reg = <0 0x1c102000 0 2591 reg = <0 0x1c102000 0 0x1000>;
3346 mediatek,larb-id = <2 2592 mediatek,larb-id = <2>;
3347 mediatek,smi = <&smi_ 2593 mediatek,smi = <&smi_common_vdo>;
3348 clocks = <&vdosys1 CL 2594 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CL 2595 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3350 <&vdosys1 CL 2596 <&vdosys1 CLK_VDO1_GALS>;
3351 clock-names = "apb", 2597 clock-names = "apb", "smi", "gals";
3352 power-domains = <&spm 2598 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3353 }; 2599 };
3354 2600
3355 larb3: larb@1c103000 { 2601 larb3: larb@1c103000 {
3356 compatible = "mediate 2602 compatible = "mediatek,mt8195-smi-larb";
3357 reg = <0 0x1c103000 0 2603 reg = <0 0x1c103000 0 0x1000>;
3358 mediatek,larb-id = <3 2604 mediatek,larb-id = <3>;
3359 mediatek,smi = <&smi_ 2605 mediatek,smi = <&smi_common_vpp>;
3360 clocks = <&vdosys1 CL 2606 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3361 <&vdosys1 CL 2607 <&vdosys1 CLK_VDO1_GALS>,
3362 <&vppsys0 CL 2608 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3363 clock-names = "apb", 2609 clock-names = "apb", "smi", "gals";
3364 power-domains = <&spm 2610 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3365 }; 2611 };
3366 2612
3367 vdo1_rdma0: dma-controller@1c <<
3368 compatible = "mediate <<
3369 reg = <0 0x1c104000 0 <<
3370 interrupts = <GIC_SPI <<
3371 clocks = <&vdosys1 CL <<
3372 power-domains = <&spm <<
3373 iommus = <&iommu_vdo <<
3374 mediatek,gce-client-r <<
3375 #dma-cells = <1>; <<
3376 }; <<
3377 <<
3378 vdo1_rdma1: dma-controller@1c <<
3379 compatible = "mediate <<
3380 reg = <0 0x1c105000 0 <<
3381 interrupts = <GIC_SPI <<
3382 clocks = <&vdosys1 CL <<
3383 power-domains = <&spm <<
3384 iommus = <&iommu_vpp <<
3385 mediatek,gce-client-r <<
3386 #dma-cells = <1>; <<
3387 }; <<
3388 <<
3389 vdo1_rdma2: dma-controller@1c <<
3390 compatible = "mediate <<
3391 reg = <0 0x1c106000 0 <<
3392 interrupts = <GIC_SPI <<
3393 clocks = <&vdosys1 CL <<
3394 power-domains = <&spm <<
3395 iommus = <&iommu_vdo <<
3396 mediatek,gce-client-r <<
3397 #dma-cells = <1>; <<
3398 }; <<
3399 <<
3400 vdo1_rdma3: dma-controller@1c <<
3401 compatible = "mediate <<
3402 reg = <0 0x1c107000 0 <<
3403 interrupts = <GIC_SPI <<
3404 clocks = <&vdosys1 CL <<
3405 power-domains = <&spm <<
3406 iommus = <&iommu_vpp <<
3407 mediatek,gce-client-r <<
3408 #dma-cells = <1>; <<
3409 }; <<
3410 <<
3411 vdo1_rdma4: dma-controller@1c <<
3412 compatible = "mediate <<
3413 reg = <0 0x1c108000 0 <<
3414 interrupts = <GIC_SPI <<
3415 clocks = <&vdosys1 CL <<
3416 power-domains = <&spm <<
3417 iommus = <&iommu_vdo <<
3418 mediatek,gce-client-r <<
3419 #dma-cells = <1>; <<
3420 }; <<
3421 <<
3422 vdo1_rdma5: dma-controller@1c <<
3423 compatible = "mediate <<
3424 reg = <0 0x1c109000 0 <<
3425 interrupts = <GIC_SPI <<
3426 clocks = <&vdosys1 CL <<
3427 power-domains = <&spm <<
3428 iommus = <&iommu_vpp <<
3429 mediatek,gce-client-r <<
3430 #dma-cells = <1>; <<
3431 }; <<
3432 <<
3433 vdo1_rdma6: dma-controller@1c <<
3434 compatible = "mediate <<
3435 reg = <0 0x1c10a000 0 <<
3436 interrupts = <GIC_SPI <<
3437 clocks = <&vdosys1 CL <<
3438 power-domains = <&spm <<
3439 iommus = <&iommu_vdo <<
3440 mediatek,gce-client-r <<
3441 #dma-cells = <1>; <<
3442 }; <<
3443 <<
3444 vdo1_rdma7: dma-controller@1c <<
3445 compatible = "mediate <<
3446 reg = <0 0x1c10b000 0 <<
3447 interrupts = <GIC_SPI <<
3448 clocks = <&vdosys1 CL <<
3449 power-domains = <&spm <<
3450 iommus = <&iommu_vpp <<
3451 mediatek,gce-client-r <<
3452 #dma-cells = <1>; <<
3453 }; <<
3454 <<
3455 merge1: vpp-merge@1c10c000 { <<
3456 compatible = "mediate <<
3457 reg = <0 0x1c10c000 0 <<
3458 interrupts = <GIC_SPI <<
3459 clocks = <&vdosys1 CL <<
3460 <&vdosys1 CL <<
3461 clock-names = "merge" <<
3462 power-domains = <&spm <<
3463 mediatek,gce-client-r <<
3464 mediatek,merge-mute; <<
3465 resets = <&vdosys1 MT <<
3466 }; <<
3467 <<
3468 merge2: vpp-merge@1c10d000 { <<
3469 compatible = "mediate <<
3470 reg = <0 0x1c10d000 0 <<
3471 interrupts = <GIC_SPI <<
3472 clocks = <&vdosys1 CL <<
3473 <&vdosys1 CL <<
3474 clock-names = "merge" <<
3475 power-domains = <&spm <<
3476 mediatek,gce-client-r <<
3477 mediatek,merge-mute; <<
3478 resets = <&vdosys1 MT <<
3479 }; <<
3480 <<
3481 merge3: vpp-merge@1c10e000 { <<
3482 compatible = "mediate <<
3483 reg = <0 0x1c10e000 0 <<
3484 interrupts = <GIC_SPI <<
3485 clocks = <&vdosys1 CL <<
3486 <&vdosys1 CL <<
3487 clock-names = "merge" <<
3488 power-domains = <&spm <<
3489 mediatek,gce-client-r <<
3490 mediatek,merge-mute; <<
3491 resets = <&vdosys1 MT <<
3492 }; <<
3493 <<
3494 merge4: vpp-merge@1c10f000 { <<
3495 compatible = "mediate <<
3496 reg = <0 0x1c10f000 0 <<
3497 interrupts = <GIC_SPI <<
3498 clocks = <&vdosys1 CL <<
3499 <&vdosys1 CL <<
3500 clock-names = "merge" <<
3501 power-domains = <&spm <<
3502 mediatek,gce-client-r <<
3503 mediatek,merge-mute; <<
3504 resets = <&vdosys1 MT <<
3505 }; <<
3506 <<
3507 merge5: vpp-merge@1c110000 { <<
3508 compatible = "mediate <<
3509 reg = <0 0x1c110000 0 <<
3510 interrupts = <GIC_SPI <<
3511 clocks = <&vdosys1 CL <<
3512 <&vdosys1 CL <<
3513 clock-names = "merge" <<
3514 power-domains = <&spm <<
3515 mediatek,gce-client-r <<
3516 mediatek,merge-fifo-e <<
3517 resets = <&vdosys1 MT <<
3518 }; <<
3519 <<
3520 dp_intf1: dp-intf@1c113000 { 2613 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediate 2614 compatible = "mediatek,mt8195-dp-intf";
3522 reg = <0 0x1c113000 0 2615 reg = <0 0x1c113000 0 0x1000>;
3523 interrupts = <GIC_SPI 2616 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3524 power-domains = <&spm 2617 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3525 clocks = <&vdosys1 CL !! 2618 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3526 <&vdosys1 CL !! 2619 <&vdosys1 CLK_VDO1_DPINTF>,
3527 <&apmixedsys 2620 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3528 clock-names = "pixel" !! 2621 clock-names = "engine", "pixel", "pll";
3529 status = "disabled"; 2622 status = "disabled";
3530 }; 2623 };
3531 2624
3532 ethdr0: hdr-engine@1c114000 { <<
3533 compatible = "mediate <<
3534 reg = <0 0x1c114000 0 <<
3535 <0 0x1c115000 0 <<
3536 <0 0x1c117000 0 <<
3537 <0 0x1c119000 0 <<
3538 <0 0x1c11a000 0 <<
3539 <0 0x1c11b000 0 <<
3540 <0 0x1c11c000 0 <<
3541 reg-names = "mixer", <<
3542 "vdo_be", <<
3543 mediatek,gce-client-r <<
3544 <<
3545 <<
3546 <<
3547 <<
3548 <<
3549 <<
3550 clocks = <&vdosys1 CL <<
3551 <&vdosys1 CL <<
3552 <&vdosys1 CL <<
3553 <&vdosys1 CL <<
3554 <&vdosys1 CL <<
3555 <&vdosys1 CL <<
3556 <&vdosys1 CL <<
3557 <&vdosys1 CL <<
3558 <&vdosys1 CL <<
3559 <&vdosys1 CL <<
3560 <&vdosys1 CL <<
3561 <&vdosys1 CL <<
3562 <&topckgen C <<
3563 clock-names = "mixer" <<
3564 "vdo_be <<
3565 "gfx_fe <<
3566 "ethdr_ <<
3567 power-domains = <&spm <<
3568 iommus = <&iommu_vpp <<
3569 <&iommu_vpp <<
3570 interrupts = <GIC_SPI <<
3571 resets = <&vdosys1 MT <<
3572 <&vdosys1 MT <<
3573 <&vdosys1 MT <<
3574 <&vdosys1 MT <<
3575 <&vdosys1 MT <<
3576 reset-names = "vdo_fe <<
3577 "gfx_fe <<
3578 }; <<
3579 <<
3580 edp_tx: edp-tx@1c500000 { 2625 edp_tx: edp-tx@1c500000 {
3581 compatible = "mediate 2626 compatible = "mediatek,mt8195-edp-tx";
3582 reg = <0 0x1c500000 0 2627 reg = <0 0x1c500000 0 0x8000>;
3583 nvmem-cells = <&dp_ca 2628 nvmem-cells = <&dp_calibration>;
3584 nvmem-cell-names = "d 2629 nvmem-cell-names = "dp_calibration_data";
3585 power-domains = <&spm 2630 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3586 interrupts = <GIC_SPI 2631 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3587 max-linkrate-mhz = <8 2632 max-linkrate-mhz = <8100>;
3588 status = "disabled"; 2633 status = "disabled";
3589 }; 2634 };
3590 2635
3591 dp_tx: dp-tx@1c600000 { 2636 dp_tx: dp-tx@1c600000 {
3592 compatible = "mediate 2637 compatible = "mediatek,mt8195-dp-tx";
3593 reg = <0 0x1c600000 0 2638 reg = <0 0x1c600000 0 0x8000>;
3594 nvmem-cells = <&dp_ca 2639 nvmem-cells = <&dp_calibration>;
3595 nvmem-cell-names = "d 2640 nvmem-cell-names = "dp_calibration_data";
3596 power-domains = <&spm 2641 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3597 interrupts = <GIC_SPI 2642 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3598 max-linkrate-mhz = <8 2643 max-linkrate-mhz = <8100>;
3599 status = "disabled"; 2644 status = "disabled";
3600 }; <<
3601 }; <<
3602 <<
3603 thermal_zones: thermal-zones { <<
3604 cpu0-thermal { <<
3605 polling-delay = <1000 <<
3606 polling-delay-passive <<
3607 thermal-sensors = <&l <<
3608 <<
3609 trips { <<
3610 cpu0_alert: t <<
3611 tempe <<
3612 hyste <<
3613 type <<
3614 }; <<
3615 <<
3616 cpu0_crit: tr <<
3617 tempe <<
3618 hyste <<
3619 type <<
3620 }; <<
3621 }; <<
3622 <<
3623 cooling-maps { <<
3624 map0 { <<
3625 trip <<
3626 cooli <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 <<
3634 cpu1-thermal { <<
3635 polling-delay = <1000 <<
3636 polling-delay-passive <<
3637 thermal-sensors = <&l <<
3638 <<
3639 trips { <<
3640 cpu1_alert: t <<
3641 tempe <<
3642 hyste <<
3643 type <<
3644 }; <<
3645 <<
3646 cpu1_crit: tr <<
3647 tempe <<
3648 hyste <<
3649 type <<
3650 }; <<
3651 }; <<
3652 <<
3653 cooling-maps { <<
3654 map0 { <<
3655 trip <<
3656 cooli <<
3657 <<
3658 <<
3659 <<
3660 }; <<
3661 }; <<
3662 }; <<
3663 <<
3664 cpu2-thermal { <<
3665 polling-delay = <1000 <<
3666 polling-delay-passive <<
3667 thermal-sensors = <&l <<
3668 <<
3669 trips { <<
3670 cpu2_alert: t <<
3671 tempe <<
3672 hyste <<
3673 type <<
3674 }; <<
3675 <<
3676 cpu2_crit: tr <<
3677 tempe <<
3678 hyste <<
3679 type <<
3680 }; <<
3681 }; <<
3682 <<
3683 cooling-maps { <<
3684 map0 { <<
3685 trip <<
3686 cooli <<
3687 <<
3688 <<
3689 <<
3690 }; <<
3691 }; <<
3692 }; <<
3693 <<
3694 cpu3-thermal { <<
3695 polling-delay = <1000 <<
3696 polling-delay-passive <<
3697 thermal-sensors = <&l <<
3698 <<
3699 trips { <<
3700 cpu3_alert: t <<
3701 tempe <<
3702 hyste <<
3703 type <<
3704 }; <<
3705 <<
3706 cpu3_crit: tr <<
3707 tempe <<
3708 hyste <<
3709 type <<
3710 }; <<
3711 }; <<
3712 <<
3713 cooling-maps { <<
3714 map0 { <<
3715 trip <<
3716 cooli <<
3717 <<
3718 <<
3719 <<
3720 }; <<
3721 }; <<
3722 }; <<
3723 <<
3724 cpu4-thermal { <<
3725 polling-delay = <1000 <<
3726 polling-delay-passive <<
3727 thermal-sensors = <&l <<
3728 <<
3729 trips { <<
3730 cpu4_alert: t <<
3731 tempe <<
3732 hyste <<
3733 type <<
3734 }; <<
3735 <<
3736 cpu4_crit: tr <<
3737 tempe <<
3738 hyste <<
3739 type <<
3740 }; <<
3741 }; <<
3742 <<
3743 cooling-maps { <<
3744 map0 { <<
3745 trip <<
3746 cooli <<
3747 <<
3748 <<
3749 <<
3750 }; <<
3751 }; <<
3752 }; <<
3753 <<
3754 cpu5-thermal { <<
3755 polling-delay = <1000 <<
3756 polling-delay-passive <<
3757 thermal-sensors = <&l <<
3758 <<
3759 trips { <<
3760 cpu5_alert: t <<
3761 tempe <<
3762 hyste <<
3763 type <<
3764 }; <<
3765 <<
3766 cpu5_crit: tr <<
3767 tempe <<
3768 hyste <<
3769 type <<
3770 }; <<
3771 }; <<
3772 <<
3773 cooling-maps { <<
3774 map0 { <<
3775 trip <<
3776 cooli <<
3777 <<
3778 <<
3779 <<
3780 }; <<
3781 }; <<
3782 }; <<
3783 <<
3784 cpu6-thermal { <<
3785 polling-delay = <1000 <<
3786 polling-delay-passive <<
3787 thermal-sensors = <&l <<
3788 <<
3789 trips { <<
3790 cpu6_alert: t <<
3791 tempe <<
3792 hyste <<
3793 type <<
3794 }; <<
3795 <<
3796 cpu6_crit: tr <<
3797 tempe <<
3798 hyste <<
3799 type <<
3800 }; <<
3801 }; <<
3802 <<
3803 cooling-maps { <<
3804 map0 { <<
3805 trip <<
3806 cooli <<
3807 <<
3808 <<
3809 <<
3810 }; <<
3811 }; <<
3812 }; <<
3813 <<
3814 cpu7-thermal { <<
3815 polling-delay = <1000 <<
3816 polling-delay-passive <<
3817 thermal-sensors = <&l <<
3818 <<
3819 trips { <<
3820 cpu7_alert: t <<
3821 tempe <<
3822 hyste <<
3823 type <<
3824 }; <<
3825 <<
3826 cpu7_crit: tr <<
3827 tempe <<
3828 hyste <<
3829 type <<
3830 }; <<
3831 }; <<
3832 <<
3833 cooling-maps { <<
3834 map0 { <<
3835 trip <<
3836 cooli <<
3837 <<
3838 <<
3839 <<
3840 }; <<
3841 }; <<
3842 }; <<
3843 <<
3844 vpu0-thermal { <<
3845 polling-delay = <1000 <<
3846 polling-delay-passive <<
3847 thermal-sensors = <&l <<
3848 <<
3849 trips { <<
3850 vpu0_alert: t <<
3851 tempe <<
3852 hyste <<
3853 type <<
3854 }; <<
3855 <<
3856 vpu0_crit: tr <<
3857 tempe <<
3858 hyste <<
3859 type <<
3860 }; <<
3861 }; <<
3862 }; <<
3863 <<
3864 vpu1-thermal { <<
3865 polling-delay = <1000 <<
3866 polling-delay-passive <<
3867 thermal-sensors = <&l <<
3868 <<
3869 trips { <<
3870 vpu1_alert: t <<
3871 tempe <<
3872 hyste <<
3873 type <<
3874 }; <<
3875 <<
3876 vpu1_crit: tr <<
3877 tempe <<
3878 hyste <<
3879 type <<
3880 }; <<
3881 }; <<
3882 }; <<
3883 <<
3884 gpu-thermal { <<
3885 polling-delay = <1000 <<
3886 polling-delay-passive <<
3887 thermal-sensors = <&l <<
3888 <<
3889 trips { <<
3890 gpu0_alert: t <<
3891 tempe <<
3892 hyste <<
3893 type <<
3894 }; <<
3895 <<
3896 gpu0_crit: tr <<
3897 tempe <<
3898 hyste <<
3899 type <<
3900 }; <<
3901 }; <<
3902 }; <<
3903 <<
3904 gpu1-thermal { <<
3905 polling-delay = <1000 <<
3906 polling-delay-passive <<
3907 thermal-sensors = <&l <<
3908 <<
3909 trips { <<
3910 gpu1_alert: t <<
3911 tempe <<
3912 hyste <<
3913 type <<
3914 }; <<
3915 <<
3916 gpu1_crit: tr <<
3917 tempe <<
3918 hyste <<
3919 type <<
3920 }; <<
3921 }; <<
3922 }; <<
3923 <<
3924 vdec-thermal { <<
3925 polling-delay = <1000 <<
3926 polling-delay-passive <<
3927 thermal-sensors = <&l <<
3928 <<
3929 trips { <<
3930 vdec_alert: t <<
3931 tempe <<
3932 hyste <<
3933 type <<
3934 }; <<
3935 <<
3936 vdec_crit: tr <<
3937 tempe <<
3938 hyste <<
3939 type <<
3940 }; <<
3941 }; <<
3942 }; <<
3943 <<
3944 img-thermal { <<
3945 polling-delay = <1000 <<
3946 polling-delay-passive <<
3947 thermal-sensors = <&l <<
3948 <<
3949 trips { <<
3950 img_alert: tr <<
3951 tempe <<
3952 hyste <<
3953 type <<
3954 }; <<
3955 <<
3956 img_crit: tri <<
3957 tempe <<
3958 hyste <<
3959 type <<
3960 }; <<
3961 }; <<
3962 }; <<
3963 <<
3964 infra-thermal { <<
3965 polling-delay = <1000 <<
3966 polling-delay-passive <<
3967 thermal-sensors = <&l <<
3968 <<
3969 trips { <<
3970 infra_alert: <<
3971 tempe <<
3972 hyste <<
3973 type <<
3974 }; <<
3975 <<
3976 infra_crit: t <<
3977 tempe <<
3978 hyste <<
3979 type <<
3980 }; <<
3981 }; <<
3982 }; <<
3983 <<
3984 cam0-thermal { <<
3985 polling-delay = <1000 <<
3986 polling-delay-passive <<
3987 thermal-sensors = <&l <<
3988 <<
3989 trips { <<
3990 cam0_alert: t <<
3991 tempe <<
3992 hyste <<
3993 type <<
3994 }; <<
3995 <<
3996 cam0_crit: tr <<
3997 tempe <<
3998 hyste <<
3999 type <<
4000 }; <<
4001 }; <<
4002 }; <<
4003 <<
4004 cam1-thermal { <<
4005 polling-delay = <1000 <<
4006 polling-delay-passive <<
4007 thermal-sensors = <&l <<
4008 <<
4009 trips { <<
4010 cam1_alert: t <<
4011 tempe <<
4012 hyste <<
4013 type <<
4014 }; <<
4015 <<
4016 cam1_crit: tr <<
4017 tempe <<
4018 hyste <<
4019 type <<
4020 }; <<
4021 }; <<
4022 }; 2645 };
4023 }; 2646 };
4024 }; 2647 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.