1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 MediaTek Inc. 3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com> 4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h> 8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h> 9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-por 12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h> 15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h> 16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h> 17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-th 18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
19 19
20 / { 20 / {
21 compatible = "mediatek,mt8195"; 21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>; 22 interrupt-parent = <&gic>;
23 #address-cells = <2>; 23 #address-cells = <2>;
24 #size-cells = <2>; 24 #size-cells = <2>;
25 25
26 aliases { 26 aliases {
27 dp-intf0 = &dp_intf0; <<
28 dp-intf1 = &dp_intf1; <<
29 gce0 = &gce0; 27 gce0 = &gce0;
30 gce1 = &gce1; 28 gce1 = &gce1;
31 ethdr0 = ðdr0; 29 ethdr0 = ðdr0;
32 mutex0 = &mutex; 30 mutex0 = &mutex;
33 mutex1 = &mutex1; 31 mutex1 = &mutex1;
34 merge1 = &merge1; 32 merge1 = &merge1;
35 merge2 = &merge2; 33 merge2 = &merge2;
36 merge3 = &merge3; 34 merge3 = &merge3;
37 merge4 = &merge4; 35 merge4 = &merge4;
38 merge5 = &merge5; 36 merge5 = &merge5;
39 vdo1-rdma0 = &vdo1_rdma0; 37 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1; 38 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2; 39 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3; 40 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4; 41 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5; 42 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6; 43 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7; 44 vdo1-rdma7 = &vdo1_rdma7;
47 }; 45 };
48 46
49 cpus { 47 cpus {
50 #address-cells = <1>; 48 #address-cells = <1>;
51 #size-cells = <0>; 49 #size-cells = <0>;
52 50
53 cpu0: cpu@0 { 51 cpu0: cpu@0 {
54 device_type = "cpu"; 52 device_type = "cpu";
55 compatible = "arm,cort 53 compatible = "arm,cortex-a55";
56 reg = <0x000>; 54 reg = <0x000>;
57 enable-method = "psci" 55 enable-method = "psci";
58 performance-domains = 56 performance-domains = <&performance 0>;
59 clock-frequency = <170 57 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = < 58 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cp 59 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768> 60 i-cache-size = <32768>;
63 i-cache-line-size = <6 61 i-cache-line-size = <64>;
64 i-cache-sets = <128>; 62 i-cache-sets = <128>;
65 d-cache-size = <32768> 63 d-cache-size = <32768>;
66 d-cache-line-size = <6 64 d-cache-line-size = <64>;
67 d-cache-sets = <128>; 65 d-cache-sets = <128>;
68 next-level-cache = <&l 66 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>; 67 #cooling-cells = <2>;
70 }; 68 };
71 69
72 cpu1: cpu@100 { 70 cpu1: cpu@100 {
73 device_type = "cpu"; 71 device_type = "cpu";
74 compatible = "arm,cort 72 compatible = "arm,cortex-a55";
75 reg = <0x100>; 73 reg = <0x100>;
76 enable-method = "psci" 74 enable-method = "psci";
77 performance-domains = 75 performance-domains = <&performance 0>;
78 clock-frequency = <170 76 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = < 77 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cp 78 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768> 79 i-cache-size = <32768>;
82 i-cache-line-size = <6 80 i-cache-line-size = <64>;
83 i-cache-sets = <128>; 81 i-cache-sets = <128>;
84 d-cache-size = <32768> 82 d-cache-size = <32768>;
85 d-cache-line-size = <6 83 d-cache-line-size = <64>;
86 d-cache-sets = <128>; 84 d-cache-sets = <128>;
87 next-level-cache = <&l 85 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>; 86 #cooling-cells = <2>;
89 }; 87 };
90 88
91 cpu2: cpu@200 { 89 cpu2: cpu@200 {
92 device_type = "cpu"; 90 device_type = "cpu";
93 compatible = "arm,cort 91 compatible = "arm,cortex-a55";
94 reg = <0x200>; 92 reg = <0x200>;
95 enable-method = "psci" 93 enable-method = "psci";
96 performance-domains = 94 performance-domains = <&performance 0>;
97 clock-frequency = <170 95 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = < 96 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cp 97 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768> 98 i-cache-size = <32768>;
101 i-cache-line-size = <6 99 i-cache-line-size = <64>;
102 i-cache-sets = <128>; 100 i-cache-sets = <128>;
103 d-cache-size = <32768> 101 d-cache-size = <32768>;
104 d-cache-line-size = <6 102 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 103 d-cache-sets = <128>;
106 next-level-cache = <&l 104 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>; 105 #cooling-cells = <2>;
108 }; 106 };
109 107
110 cpu3: cpu@300 { 108 cpu3: cpu@300 {
111 device_type = "cpu"; 109 device_type = "cpu";
112 compatible = "arm,cort 110 compatible = "arm,cortex-a55";
113 reg = <0x300>; 111 reg = <0x300>;
114 enable-method = "psci" 112 enable-method = "psci";
115 performance-domains = 113 performance-domains = <&performance 0>;
116 clock-frequency = <170 114 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = < 115 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cp 116 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768> 117 i-cache-size = <32768>;
120 i-cache-line-size = <6 118 i-cache-line-size = <64>;
121 i-cache-sets = <128>; 119 i-cache-sets = <128>;
122 d-cache-size = <32768> 120 d-cache-size = <32768>;
123 d-cache-line-size = <6 121 d-cache-line-size = <64>;
124 d-cache-sets = <128>; 122 d-cache-sets = <128>;
125 next-level-cache = <&l 123 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>; 124 #cooling-cells = <2>;
127 }; 125 };
128 126
129 cpu4: cpu@400 { 127 cpu4: cpu@400 {
130 device_type = "cpu"; 128 device_type = "cpu";
131 compatible = "arm,cort 129 compatible = "arm,cortex-a78";
132 reg = <0x400>; 130 reg = <0x400>;
133 enable-method = "psci" 131 enable-method = "psci";
134 performance-domains = 132 performance-domains = <&performance 1>;
135 clock-frequency = <217 133 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = < 134 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cp 135 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536> 136 i-cache-size = <65536>;
139 i-cache-line-size = <6 137 i-cache-line-size = <64>;
140 i-cache-sets = <256>; 138 i-cache-sets = <256>;
141 d-cache-size = <65536> 139 d-cache-size = <65536>;
142 d-cache-line-size = <6 140 d-cache-line-size = <64>;
143 d-cache-sets = <256>; 141 d-cache-sets = <256>;
144 next-level-cache = <&l 142 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>; 143 #cooling-cells = <2>;
146 }; 144 };
147 145
148 cpu5: cpu@500 { 146 cpu5: cpu@500 {
149 device_type = "cpu"; 147 device_type = "cpu";
150 compatible = "arm,cort 148 compatible = "arm,cortex-a78";
151 reg = <0x500>; 149 reg = <0x500>;
152 enable-method = "psci" 150 enable-method = "psci";
153 performance-domains = 151 performance-domains = <&performance 1>;
154 clock-frequency = <217 152 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = < 153 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cp 154 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536> 155 i-cache-size = <65536>;
158 i-cache-line-size = <6 156 i-cache-line-size = <64>;
159 i-cache-sets = <256>; 157 i-cache-sets = <256>;
160 d-cache-size = <65536> 158 d-cache-size = <65536>;
161 d-cache-line-size = <6 159 d-cache-line-size = <64>;
162 d-cache-sets = <256>; 160 d-cache-sets = <256>;
163 next-level-cache = <&l 161 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>; 162 #cooling-cells = <2>;
165 }; 163 };
166 164
167 cpu6: cpu@600 { 165 cpu6: cpu@600 {
168 device_type = "cpu"; 166 device_type = "cpu";
169 compatible = "arm,cort 167 compatible = "arm,cortex-a78";
170 reg = <0x600>; 168 reg = <0x600>;
171 enable-method = "psci" 169 enable-method = "psci";
172 performance-domains = 170 performance-domains = <&performance 1>;
173 clock-frequency = <217 171 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = < 172 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cp 173 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536> 174 i-cache-size = <65536>;
177 i-cache-line-size = <6 175 i-cache-line-size = <64>;
178 i-cache-sets = <256>; 176 i-cache-sets = <256>;
179 d-cache-size = <65536> 177 d-cache-size = <65536>;
180 d-cache-line-size = <6 178 d-cache-line-size = <64>;
181 d-cache-sets = <256>; 179 d-cache-sets = <256>;
182 next-level-cache = <&l 180 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>; 181 #cooling-cells = <2>;
184 }; 182 };
185 183
186 cpu7: cpu@700 { 184 cpu7: cpu@700 {
187 device_type = "cpu"; 185 device_type = "cpu";
188 compatible = "arm,cort 186 compatible = "arm,cortex-a78";
189 reg = <0x700>; 187 reg = <0x700>;
190 enable-method = "psci" 188 enable-method = "psci";
191 performance-domains = 189 performance-domains = <&performance 1>;
192 clock-frequency = <217 190 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = < 191 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cp 192 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536> 193 i-cache-size = <65536>;
196 i-cache-line-size = <6 194 i-cache-line-size = <64>;
197 i-cache-sets = <256>; 195 i-cache-sets = <256>;
198 d-cache-size = <65536> 196 d-cache-size = <65536>;
199 d-cache-line-size = <6 197 d-cache-line-size = <64>;
200 d-cache-sets = <256>; 198 d-cache-sets = <256>;
201 next-level-cache = <&l 199 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>; 200 #cooling-cells = <2>;
203 }; 201 };
204 202
205 cpu-map { 203 cpu-map {
206 cluster0 { 204 cluster0 {
207 core0 { 205 core0 {
208 cpu = 206 cpu = <&cpu0>;
209 }; 207 };
210 208
211 core1 { 209 core1 {
212 cpu = 210 cpu = <&cpu1>;
213 }; 211 };
214 212
215 core2 { 213 core2 {
216 cpu = 214 cpu = <&cpu2>;
217 }; 215 };
218 216
219 core3 { 217 core3 {
220 cpu = 218 cpu = <&cpu3>;
221 }; 219 };
222 220
223 core4 { 221 core4 {
224 cpu = 222 cpu = <&cpu4>;
225 }; 223 };
226 224
227 core5 { 225 core5 {
228 cpu = 226 cpu = <&cpu5>;
229 }; 227 };
230 228
231 core6 { 229 core6 {
232 cpu = 230 cpu = <&cpu6>;
233 }; 231 };
234 232
235 core7 { 233 core7 {
236 cpu = 234 cpu = <&cpu7>;
237 }; 235 };
238 }; 236 };
239 }; 237 };
240 238
241 idle-states { 239 idle-states {
242 entry-method = "psci"; 240 entry-method = "psci";
243 241
244 cpu_ret_l: cpu-retenti 242 cpu_ret_l: cpu-retention-l {
245 compatible = " 243 compatible = "arm,idle-state";
246 arm,psci-suspe 244 arm,psci-suspend-param = <0x00010001>;
247 local-timer-st 245 local-timer-stop;
248 entry-latency- 246 entry-latency-us = <50>;
249 exit-latency-u 247 exit-latency-us = <95>;
250 min-residency- 248 min-residency-us = <580>;
251 }; 249 };
252 250
253 cpu_ret_b: cpu-retenti 251 cpu_ret_b: cpu-retention-b {
254 compatible = " 252 compatible = "arm,idle-state";
255 arm,psci-suspe 253 arm,psci-suspend-param = <0x00010001>;
256 local-timer-st 254 local-timer-stop;
257 entry-latency- 255 entry-latency-us = <45>;
258 exit-latency-u 256 exit-latency-us = <140>;
259 min-residency- 257 min-residency-us = <740>;
260 }; 258 };
261 259
262 cpu_off_l: cpu-off-l { 260 cpu_off_l: cpu-off-l {
263 compatible = " 261 compatible = "arm,idle-state";
264 arm,psci-suspe 262 arm,psci-suspend-param = <0x01010002>;
265 local-timer-st 263 local-timer-stop;
266 entry-latency- 264 entry-latency-us = <55>;
267 exit-latency-u 265 exit-latency-us = <155>;
268 min-residency- 266 min-residency-us = <840>;
269 }; 267 };
270 268
271 cpu_off_b: cpu-off-b { 269 cpu_off_b: cpu-off-b {
272 compatible = " 270 compatible = "arm,idle-state";
273 arm,psci-suspe 271 arm,psci-suspend-param = <0x01010002>;
274 local-timer-st 272 local-timer-stop;
275 entry-latency- 273 entry-latency-us = <50>;
276 exit-latency-u 274 exit-latency-us = <200>;
277 min-residency- 275 min-residency-us = <1000>;
278 }; 276 };
279 }; 277 };
280 278
281 l2_0: l2-cache0 { 279 l2_0: l2-cache0 {
282 compatible = "cache"; 280 compatible = "cache";
283 cache-level = <2>; 281 cache-level = <2>;
284 cache-size = <131072>; 282 cache-size = <131072>;
285 cache-line-size = <64> 283 cache-line-size = <64>;
286 cache-sets = <512>; 284 cache-sets = <512>;
287 next-level-cache = <&l 285 next-level-cache = <&l3_0>;
288 cache-unified; <<
289 }; 286 };
290 287
291 l2_1: l2-cache1 { 288 l2_1: l2-cache1 {
292 compatible = "cache"; 289 compatible = "cache";
293 cache-level = <2>; 290 cache-level = <2>;
294 cache-size = <262144>; 291 cache-size = <262144>;
295 cache-line-size = <64> 292 cache-line-size = <64>;
296 cache-sets = <512>; 293 cache-sets = <512>;
297 next-level-cache = <&l 294 next-level-cache = <&l3_0>;
298 cache-unified; <<
299 }; 295 };
300 296
301 l3_0: l3-cache { 297 l3_0: l3-cache {
302 compatible = "cache"; 298 compatible = "cache";
303 cache-level = <3>; 299 cache-level = <3>;
304 cache-size = <2097152> 300 cache-size = <2097152>;
305 cache-line-size = <64> 301 cache-line-size = <64>;
306 cache-sets = <2048>; 302 cache-sets = <2048>;
307 cache-unified; 303 cache-unified;
308 }; 304 };
309 }; 305 };
310 306
311 dsu-pmu { 307 dsu-pmu {
312 compatible = "arm,dsu-pmu"; 308 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_T 309 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu 310 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu 311 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail"; <<
317 }; 312 };
318 313
319 dmic_codec: dmic-codec { 314 dmic_codec: dmic-codec {
320 compatible = "dmic-codec"; 315 compatible = "dmic-codec";
321 num-channels = <2>; 316 num-channels = <2>;
322 wakeup-delay-ms = <50>; 317 wakeup-delay-ms = <50>;
323 }; 318 };
324 319
325 sound: mt8195-sound { 320 sound: mt8195-sound {
326 mediatek,platform = <&afe>; 321 mediatek,platform = <&afe>;
327 status = "disabled"; 322 status = "disabled";
328 }; 323 };
329 324
330 clk13m: fixed-factor-clock-13m { 325 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clo 326 compatible = "fixed-factor-clock";
332 #clock-cells = <0>; 327 #clock-cells = <0>;
333 clocks = <&clk26m>; 328 clocks = <&clk26m>;
334 clock-div = <2>; 329 clock-div = <2>;
335 clock-mult = <1>; 330 clock-mult = <1>;
336 clock-output-names = "clk13m"; 331 clock-output-names = "clk13m";
337 }; 332 };
338 333
339 clk26m: oscillator-26m { 334 clk26m: oscillator-26m {
340 compatible = "fixed-clock"; 335 compatible = "fixed-clock";
341 #clock-cells = <0>; 336 #clock-cells = <0>;
342 clock-frequency = <26000000>; 337 clock-frequency = <26000000>;
343 clock-output-names = "clk26m"; 338 clock-output-names = "clk26m";
344 }; 339 };
345 340
346 clk32k: oscillator-32k { 341 clk32k: oscillator-32k {
347 compatible = "fixed-clock"; 342 compatible = "fixed-clock";
348 #clock-cells = <0>; 343 #clock-cells = <0>;
349 clock-frequency = <32768>; 344 clock-frequency = <32768>;
350 clock-output-names = "clk32k"; 345 clock-output-names = "clk32k";
351 }; 346 };
352 347
353 performance: performance-controller@11 348 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq 349 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, 350 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1 351 #performance-domain-cells = <1>;
357 }; 352 };
358 353
359 gpu_opp_table: opp-table-gpu { 354 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points 355 compatible = "operating-points-v2";
361 opp-shared; 356 opp-shared;
362 357
363 opp-390000000 { 358 opp-390000000 {
364 opp-hz = /bits/ 64 <39 359 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <62500 360 opp-microvolt = <625000>;
366 }; 361 };
367 opp-410000000 { 362 opp-410000000 {
368 opp-hz = /bits/ 64 <41 363 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <63125 364 opp-microvolt = <631250>;
370 }; 365 };
371 opp-431000000 { 366 opp-431000000 {
372 opp-hz = /bits/ 64 <43 367 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <63125 368 opp-microvolt = <631250>;
374 }; 369 };
375 opp-473000000 { 370 opp-473000000 {
376 opp-hz = /bits/ 64 <47 371 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <63750 372 opp-microvolt = <637500>;
378 }; 373 };
379 opp-515000000 { 374 opp-515000000 {
380 opp-hz = /bits/ 64 <51 375 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <63750 376 opp-microvolt = <637500>;
382 }; 377 };
383 opp-556000000 { 378 opp-556000000 {
384 opp-hz = /bits/ 64 <55 379 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <64375 380 opp-microvolt = <643750>;
386 }; 381 };
387 opp-598000000 { 382 opp-598000000 {
388 opp-hz = /bits/ 64 <59 383 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <65000 384 opp-microvolt = <650000>;
390 }; 385 };
391 opp-640000000 { 386 opp-640000000 {
392 opp-hz = /bits/ 64 <64 387 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <65000 388 opp-microvolt = <650000>;
394 }; 389 };
395 opp-670000000 { 390 opp-670000000 {
396 opp-hz = /bits/ 64 <67 391 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <66250 392 opp-microvolt = <662500>;
398 }; 393 };
399 opp-700000000 { 394 opp-700000000 {
400 opp-hz = /bits/ 64 <70 395 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <67500 396 opp-microvolt = <675000>;
402 }; 397 };
403 opp-730000000 { 398 opp-730000000 {
404 opp-hz = /bits/ 64 <73 399 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <68750 400 opp-microvolt = <687500>;
406 }; 401 };
407 opp-760000000 { 402 opp-760000000 {
408 opp-hz = /bits/ 64 <76 403 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <70000 404 opp-microvolt = <700000>;
410 }; 405 };
411 opp-790000000 { 406 opp-790000000 {
412 opp-hz = /bits/ 64 <79 407 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <71250 408 opp-microvolt = <712500>;
414 }; 409 };
415 opp-820000000 { 410 opp-820000000 {
416 opp-hz = /bits/ 64 <82 411 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <72500 412 opp-microvolt = <725000>;
418 }; 413 };
419 opp-850000000 { 414 opp-850000000 {
420 opp-hz = /bits/ 64 <85 415 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <73750 416 opp-microvolt = <737500>;
422 }; 417 };
423 opp-880000000 { 418 opp-880000000 {
424 opp-hz = /bits/ 64 <88 419 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <75000 420 opp-microvolt = <750000>;
426 }; 421 };
427 }; 422 };
428 423
429 pmu-a55 { 424 pmu-a55 {
430 compatible = "arm,cortex-a55-p 425 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>; 426 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TY 427 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 }; 428 };
434 429
435 pmu-a78 { 430 pmu-a78 {
436 compatible = "arm,cortex-a78-p 431 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>; 432 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TY 433 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 }; 434 };
440 435
441 psci { 436 psci {
442 compatible = "arm,psci-1.0"; 437 compatible = "arm,psci-1.0";
443 method = "smc"; 438 method = "smc";
444 }; 439 };
445 440
446 timer: timer { 441 timer: timer {
447 compatible = "arm,armv8-timer" 442 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>; 443 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_T 444 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_T 445 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_T 446 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_T 447 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 }; 448 };
454 449
455 soc { 450 soc {
456 #address-cells = <2>; 451 #address-cells = <2>;
457 #size-cells = <2>; 452 #size-cells = <2>;
458 compatible = "simple-bus"; 453 compatible = "simple-bus";
459 ranges; 454 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 455 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
461 456
462 gic: interrupt-controller@c000 457 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic- 458 compatible = "arm,gic-v3";
464 #interrupt-cells = <4> 459 #interrupt-cells = <4>;
465 #redistributor-regions 460 #redistributor-regions = <1>;
466 interrupt-parent = <&g 461 interrupt-parent = <&gic>;
467 interrupt-controller; 462 interrupt-controller;
468 reg = <0 0x0c000000 0 463 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 464 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 465 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471 466
472 ppi-partitions { 467 ppi-partitions {
473 ppi_cluster0: 468 ppi_cluster0: interrupt-partition-0 {
474 affini 469 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 }; 470 };
476 471
477 ppi_cluster1: 472 ppi_cluster1: interrupt-partition-1 {
478 affini 473 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 }; 474 };
480 }; 475 };
481 }; 476 };
482 477
483 topckgen: syscon@10000000 { 478 topckgen: syscon@10000000 {
484 compatible = "mediatek 479 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 480 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>; 481 #clock-cells = <1>;
487 }; 482 };
488 483
489 infracfg_ao: syscon@10001000 { 484 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek 485 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
491 reg = <0 0x10001000 0 486 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>; 487 #clock-cells = <1>;
493 #reset-cells = <1>; 488 #reset-cells = <1>;
494 }; 489 };
495 490
496 pericfg: syscon@10003000 { 491 pericfg: syscon@10003000 {
497 compatible = "mediatek 492 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 493 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>; 494 #clock-cells = <1>;
500 }; 495 };
501 496
502 pio: pinctrl@10005000 { 497 pio: pinctrl@10005000 {
503 compatible = "mediatek 498 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 499 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 500 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 501 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 502 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 503 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 504 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 505 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 506 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", 507 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br" 508 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl" 509 "iocfg_tl", "eint";
515 gpio-controller; 510 gpio-controller;
516 #gpio-cells = <2>; 511 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 512 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller; 513 interrupt-controller;
519 interrupts = <GIC_SPI 514 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2> 515 #interrupt-cells = <2>;
521 }; 516 };
522 517
523 scpsys: syscon@10006000 { 518 scpsys: syscon@10006000 {
524 compatible = "mediatek 519 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 520 reg = <0 0x10006000 0 0x1000>;
526 521
527 /* System Power Manage 522 /* System Power Manager */
528 spm: power-controller 523 spm: power-controller {
529 compatible = " 524 compatible = "mediatek,mt8195-power-controller";
530 #address-cells 525 #address-cells = <1>;
531 #size-cells = 526 #size-cells = <0>;
532 #power-domain- 527 #power-domain-cells = <1>;
533 528
534 /* power domai 529 /* power domain of the SoC */
535 mfg0: power-do 530 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = 531 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #addre 532 #address-cells = <1>;
538 #size- 533 #size-cells = <0>;
539 #power 534 #power-domain-cells = <1>;
540 535
541 mfg1: !! 536 power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 537 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 538 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 539 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 540 clock-names = "mfg", "alt";
546 541 mediatek,infracfg = <&infracfg_ao>;
547 542 #address-cells = <1>;
548 543 #size-cells = <0>;
549 544 #power-domain-cells = <1>;
550 545
551 546 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 547 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 548 #power-domain-cells = <0>;
554 549 };
555 550
556 551 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 552 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 553 #power-domain-cells = <0>;
559 554 };
560 555
561 556 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 557 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 558 #power-domain-cells = <0>;
564 559 };
565 560
566 561 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 562 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 563 #power-domain-cells = <0>;
569 564 };
570 565
571 566 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 567 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 568 #power-domain-cells = <0>;
574 569 };
575 }; 570 };
576 }; 571 };
577 572
578 power-domain@M 573 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = 574 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks 575 clocks = <&topckgen CLK_TOP_VPP>,
581 576 <&topckgen CLK_TOP_CAM>,
582 577 <&topckgen CLK_TOP_CCU>,
583 578 <&topckgen CLK_TOP_IMG>,
584 579 <&topckgen CLK_TOP_VENC>,
585 580 <&topckgen CLK_TOP_VDEC>,
586 581 <&topckgen CLK_TOP_WPE_VPP>,
587 582 <&topckgen CLK_TOP_CFG_VPP0>,
588 583 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 584 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 585 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 586 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 587 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 588 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 589 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 590 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 591 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 592 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 593 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 594 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 595 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 596 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 597 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 598 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 599 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 600 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 601 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock- 602 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 603 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 604 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 605 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 606 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 607 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 608 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 609 "vppsys0-18";
615 mediat 610 mediatek,infracfg = <&infracfg_ao>;
616 #addre 611 #address-cells = <1>;
617 #size- 612 #size-cells = <0>;
618 #power 613 #power-domain-cells = <1>;
619 614
620 power- 615 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 616 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 617 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 618 clock-names = "vdec1-0";
624 619 mediatek,infracfg = <&infracfg_ao>;
625 620 #power-domain-cells = <0>;
626 }; 621 };
627 622
628 power- 623 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 624 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 <<
631 <<
632 625 mediatek,infracfg = <&infracfg_ao>;
633 626 #power-domain-cells = <0>;
634 }; 627 };
635 628
636 power- 629 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 630 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 631 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 632 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 633 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 634 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 635 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 636 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 637 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 638 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 639 "vdosys0-2", "vdosys0-3",
647 640 "vdosys0-4", "vdosys0-5";
648 641 mediatek,infracfg = <&infracfg_ao>;
649 642 #address-cells = <1>;
650 643 #size-cells = <0>;
651 644 #power-domain-cells = <1>;
652 645
653 646 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 647 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 648 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 649 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 650 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 651 clock-names = "vppsys1", "vppsys1-0",
659 652 "vppsys1-1";
660 653 mediatek,infracfg = <&infracfg_ao>;
661 654 #power-domain-cells = <0>;
662 655 };
663 656
664 657 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 658 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 659 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 660 <&wpesys CLK_WPE_SMI_LARB8>,
668 661 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 662 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 663 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 664 "wepsys-3";
672 665 mediatek,infracfg = <&infracfg_ao>;
673 666 #power-domain-cells = <0>;
674 667 };
675 668
676 669 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 670 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 671 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 672 clock-names = "vdec0-0";
680 673 mediatek,infracfg = <&infracfg_ao>;
681 674 #power-domain-cells = <0>;
682 675 };
683 676
684 677 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 678 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 679 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 680 clock-names = "vdec2-0";
688 681 mediatek,infracfg = <&infracfg_ao>;
689 682 #power-domain-cells = <0>;
690 683 };
691 684
692 685 power-domain@MT8195_POWER_DOMAIN_VENC {
693 686 reg = <MT8195_POWER_DOMAIN_VENC>;
694 <<
695 <<
696 687 mediatek,infracfg = <&infracfg_ao>;
697 688 #power-domain-cells = <0>;
698 689 };
699 690
700 691 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 692 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 693 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 694 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 695 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 696 <&vdosys1 CLK_VDO1_GALS>;
706 697 clock-names = "vdosys1", "vdosys1-0",
707 698 "vdosys1-1", "vdosys1-2";
708 699 mediatek,infracfg = <&infracfg_ao>;
709 700 #address-cells = <1>;
710 701 #size-cells = <0>;
711 702 #power-domain-cells = <1>;
712 703
713 704 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 705 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 706 mediatek,infracfg = <&infracfg_ao>;
716 707 #power-domain-cells = <0>;
717 708 };
718 709
719 710 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 711 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 712 mediatek,infracfg = <&infracfg_ao>;
722 713 #power-domain-cells = <0>;
723 714 };
724 715
725 716 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 717 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 718 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 719 clock-names = "hdmi_tx";
729 720 #power-domain-cells = <0>;
730 721 };
731 722 };
732 723
733 724 power-domain@MT8195_POWER_DOMAIN_IMG {
734 725 reg = <MT8195_POWER_DOMAIN_IMG>;
735 726 clocks = <&imgsys CLK_IMG_LARB9>,
736 727 <&imgsys CLK_IMG_GALS>;
737 728 clock-names = "img-0", "img-1";
738 729 mediatek,infracfg = <&infracfg_ao>;
739 730 #address-cells = <1>;
740 731 #size-cells = <0>;
741 732 #power-domain-cells = <1>;
742 733
743 734 power-domain@MT8195_POWER_DOMAIN_DIP {
744 735 reg = <MT8195_POWER_DOMAIN_DIP>;
745 736 #power-domain-cells = <0>;
746 737 };
747 738
748 739 power-domain@MT8195_POWER_DOMAIN_IPE {
749 740 reg = <MT8195_POWER_DOMAIN_IPE>;
750 741 clocks = <&topckgen CLK_TOP_IPE>,
751 742 <&imgsys CLK_IMG_IPE>,
752 743 <&ipesys CLK_IPE_SMI_LARB12>;
753 744 clock-names = "ipe", "ipe-0", "ipe-1";
754 745 mediatek,infracfg = <&infracfg_ao>;
755 746 #power-domain-cells = <0>;
756 747 };
757 748 };
758 749
759 750 power-domain@MT8195_POWER_DOMAIN_CAM {
760 751 reg = <MT8195_POWER_DOMAIN_CAM>;
761 752 clocks = <&camsys CLK_CAM_LARB13>,
762 753 <&camsys CLK_CAM_LARB14>,
763 754 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 755 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 756 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 757 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 758 "cam-4";
768 759 mediatek,infracfg = <&infracfg_ao>;
769 760 #address-cells = <1>;
770 761 #size-cells = <0>;
771 762 #power-domain-cells = <1>;
772 763
773 764 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 765 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 766 #power-domain-cells = <0>;
776 767 };
777 768
778 769 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 770 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 771 #power-domain-cells = <0>;
781 772 };
782 773
783 774 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 775 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 776 #power-domain-cells = <0>;
786 777 };
787 778 };
788 }; 779 };
789 }; 780 };
790 781
791 power-domain@M 782 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = 783 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediat 784 mediatek,infracfg = <&infracfg_ao>;
794 #power 785 #power-domain-cells = <0>;
795 }; 786 };
796 787
797 power-domain@M 788 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = 789 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediat 790 mediatek,infracfg = <&infracfg_ao>;
800 #power 791 #power-domain-cells = <0>;
801 }; 792 };
802 793
803 power-domain@M 794 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = 795 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power 796 #power-domain-cells = <0>;
806 }; 797 };
807 798
808 power-domain@M 799 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = 800 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power 801 #power-domain-cells = <0>;
811 }; 802 };
812 803
813 power-domain@M 804 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = 805 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks 806 clocks = <&topckgen CLK_TOP_SENINF>,
816 807 <&topckgen CLK_TOP_SENINF2>;
817 clock- 808 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power 809 #power-domain-cells = <0>;
819 }; 810 };
820 811
821 power-domain@M 812 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = 813 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks 814 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock- 815 clock-names = "ether";
825 #power 816 #power-domain-cells = <0>;
826 }; 817 };
827 818
828 power-domain@M 819 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = 820 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks 821 clocks = <&topckgen CLK_TOP_ADSP>,
831 822 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock- 823 clock-names = "adsp", "adsp1";
833 #addre 824 #address-cells = <1>;
834 #size- 825 #size-cells = <0>;
835 mediat 826 mediatek,infracfg = <&infracfg_ao>;
836 #power 827 #power-domain-cells = <1>;
837 828
838 power- 829 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 830 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 831 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 832 <&topckgen CLK_TOP_AUD_INTBUS>,
842 833 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 834 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 835 clock-names = "audio", "audio1", "audio2",
845 836 "audio3";
846 837 mediatek,infracfg = <&infracfg_ao>;
847 838 #power-domain-cells = <0>;
848 }; 839 };
849 }; 840 };
850 }; 841 };
851 }; 842 };
852 843
853 watchdog: watchdog@10007000 { 844 watchdog: watchdog@10007000 {
854 compatible = "mediatek 845 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrs 846 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 847 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>; 848 #reset-cells = <1>;
858 }; 849 };
859 850
860 apmixedsys: syscon@1000c000 { 851 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek 852 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 853 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>; 854 #clock-cells = <1>;
864 }; 855 };
865 856
866 systimer: timer@10017000 { 857 systimer: timer@10017000 {
867 compatible = "mediatek 858 compatible = "mediatek,mt8195-timer",
868 "mediatek 859 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 860 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 861 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>; 862 clocks = <&clk13m>;
872 }; 863 };
873 864
874 pwrap: pwrap@10024000 { 865 pwrap: pwrap@10024000 {
875 compatible = "mediatek 866 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 867 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap"; 868 reg-names = "pwrap";
878 interrupts = <GIC_SPI 869 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao 870 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao 871 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", " 872 clock-names = "spi", "wrap";
882 assigned-clocks = <&to 873 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents 874 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 }; 875 };
885 876
886 spmi: spmi@10027000 { 877 spmi: spmi@10027000 {
887 compatible = "mediatek 878 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 879 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 880 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "s 881 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao 882 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao 883 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CL 884 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sy 885 clock-names = "pmif_sys_ck",
895 "pmif_tm 886 "pmif_tmr_ck",
896 "spmimst 887 "spmimst_clk_mux";
897 assigned-clocks = <&to 888 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents 889 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 }; 890 };
900 891
901 iommu_infra: infra-iommu@10315 892 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek 893 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 894 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 895 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 896 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 897 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 898 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 899 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>; 900 #iommu-cells = <1>;
910 }; 901 };
911 902
912 gce0: mailbox@10320000 { 903 gce0: mailbox@10320000 {
913 compatible = "mediatek 904 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 905 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 906 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>; 907 #mbox-cells = <2>;
917 clocks = <&infracfg_ao 908 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 }; 909 };
919 910
920 gce1: mailbox@10330000 { 911 gce1: mailbox@10330000 {
921 compatible = "mediatek 912 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 913 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 914 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>; 915 #mbox-cells = <2>;
925 clocks = <&infracfg_ao 916 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 }; 917 };
927 918
928 scp: scp@10500000 { 919 scp: scp@10500000 {
929 compatible = "mediatek 920 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 921 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 922 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 923 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "c 924 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled"; 926 status = "disabled";
936 }; 927 };
937 928
938 scp_adsp: clock-controller@107 929 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek 930 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 931 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>; 932 #clock-cells = <1>;
942 }; 933 };
943 934
944 adsp: dsp@10803000 { 935 adsp: dsp@10803000 {
945 compatible = "mediatek 936 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 937 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 938 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sr 939 reg-names = "cfg", "sram";
949 clocks = <&topckgen CL 940 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>, 941 <&clk26m>,
951 <&topckgen CL 942 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CL 943 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CL 944 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CL 945 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_se 946 clock-names = "adsp_sel",
956 "clk26m_ck", 947 "clk26m_ck",
957 "audio_local_ 948 "audio_local_bus",
958 "mainpll_d7_d 949 "mainpll_d7_d2",
959 "scp_adsp_aud 950 "scp_adsp_audiodsp",
960 "audio_h"; 951 "audio_h";
961 power-domains = <&spm 952 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx 953 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbo 954 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled"; 955 status = "disabled";
965 }; 956 };
966 957
967 adsp_mailbox0: mailbox@1081600 958 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek 959 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>; 960 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 961 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 }; 963 };
973 964
974 adsp_mailbox1: mailbox@1081700 965 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek 966 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>; 967 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 968 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 969 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 }; 970 };
980 971
981 afe: mt8195-afe-pcm@10890000 { 972 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek 973 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 974 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <& 975 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm 976 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 977 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14 978 resets = <&watchdog 14>;
988 reset-names = "audiosy 979 reset-names = "audiosys";
989 clocks = <&clk26m>, 980 clocks = <&clk26m>,
990 <&apmixedsys C 981 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys C 982 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK 983 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK 984 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK 985 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK 986 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK 987 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK 988 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK 989 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK 990 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CL 991 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CL 992 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CL 993 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CL 994 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CL 995 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CL 996 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao 997 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CL 998 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m 999 clock-names = "clk26m",
1009 "apll1_ck", 1000 "apll1_ck",
1010 "apll2_ck", 1001 "apll2_ck",
1011 "apll12_div0" 1002 "apll12_div0",
1012 "apll12_div1" 1003 "apll12_div1",
1013 "apll12_div2" 1004 "apll12_div2",
1014 "apll12_div3" 1005 "apll12_div3",
1015 "apll12_div9" 1006 "apll12_div9",
1016 "a1sys_hp_sel 1007 "a1sys_hp_sel",
1017 "aud_intbus_s 1008 "aud_intbus_sel",
1018 "audio_h_sel" 1009 "audio_h_sel",
1019 "audio_local_ 1010 "audio_local_bus_sel",
1020 "dptx_m_sel", 1011 "dptx_m_sel",
1021 "i2so1_m_sel" 1012 "i2so1_m_sel",
1022 "i2so2_m_sel" 1013 "i2so2_m_sel",
1023 "i2si1_m_sel" 1014 "i2si1_m_sel",
1024 "i2si2_m_sel" 1015 "i2si2_m_sel",
1025 "infra_ao_aud 1016 "infra_ao_audio_26m_b",
1026 "scp_adsp_aud 1017 "scp_adsp_audiodsp";
1027 status = "disabled"; 1018 status = "disabled";
1028 }; 1019 };
1029 1020
1030 uart0: serial@11001100 { 1021 uart0: serial@11001100 {
1031 compatible = "mediate 1022 compatible = "mediatek,mt8195-uart",
1032 "mediate 1023 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 1024 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 1025 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, < 1026 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", 1027 clock-names = "baud", "bus";
1037 status = "disabled"; 1028 status = "disabled";
1038 }; 1029 };
1039 1030
1040 uart1: serial@11001200 { 1031 uart1: serial@11001200 {
1041 compatible = "mediate 1032 compatible = "mediatek,mt8195-uart",
1042 "mediate 1033 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 1034 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 1035 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, < 1036 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", 1037 clock-names = "baud", "bus";
1047 status = "disabled"; 1038 status = "disabled";
1048 }; 1039 };
1049 1040
1050 uart2: serial@11001300 { 1041 uart2: serial@11001300 {
1051 compatible = "mediate 1042 compatible = "mediatek,mt8195-uart",
1052 "mediate 1043 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 1044 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 1045 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, < 1046 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", 1047 clock-names = "baud", "bus";
1057 status = "disabled"; 1048 status = "disabled";
1058 }; 1049 };
1059 1050
1060 uart3: serial@11001400 { 1051 uart3: serial@11001400 {
1061 compatible = "mediate 1052 compatible = "mediatek,mt8195-uart",
1062 "mediate 1053 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 1054 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 1055 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, < 1056 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", 1057 clock-names = "baud", "bus";
1067 status = "disabled"; 1058 status = "disabled";
1068 }; 1059 };
1069 1060
1070 uart4: serial@11001500 { 1061 uart4: serial@11001500 {
1071 compatible = "mediate 1062 compatible = "mediatek,mt8195-uart",
1072 "mediate 1063 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 1064 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 1065 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, < 1066 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", 1067 clock-names = "baud", "bus";
1077 status = "disabled"; 1068 status = "disabled";
1078 }; 1069 };
1079 1070
1080 uart5: serial@11001600 { 1071 uart5: serial@11001600 {
1081 compatible = "mediate 1072 compatible = "mediatek,mt8195-uart",
1082 "mediate 1073 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 1074 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 1075 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, < 1076 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", 1077 clock-names = "baud", "bus";
1087 status = "disabled"; 1078 status = "disabled";
1088 }; 1079 };
1089 1080
1090 auxadc: auxadc@11002000 { 1081 auxadc: auxadc@11002000 {
1091 compatible = "mediate 1082 compatible = "mediatek,mt8195-auxadc",
1092 "mediate 1083 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 1084 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_a 1085 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main"; 1086 clock-names = "main";
1096 #io-channel-cells = < 1087 #io-channel-cells = <1>;
1097 status = "disabled"; 1088 status = "disabled";
1098 }; 1089 };
1099 1090
1100 pericfg_ao: syscon@11003000 { 1091 pericfg_ao: syscon@11003000 {
1101 compatible = "mediate 1092 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 1093 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>; 1094 #clock-cells = <1>;
1104 }; 1095 };
1105 1096
1106 spi0: spi@1100a000 { 1097 spi0: spi@1100a000 {
1107 compatible = "mediate 1098 compatible = "mediatek,mt8195-spi",
1108 "mediate 1099 "mediatek,mt6765-spi";
1109 #address-cells = <1>; 1100 #address-cells = <1>;
1110 #size-cells = <0>; 1101 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 1102 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 1103 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen C 1104 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen C 1105 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_a 1106 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent 1107 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled"; 1108 status = "disabled";
1118 }; 1109 };
1119 1110
1120 lvts_ap: thermal-sensor@1100b 1111 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediate 1112 compatible = "mediatek,mt8195-lvts-ap";
1122 reg = <0 0x1100b000 0 !! 1113 reg = <0 0x1100b000 0 0x1000>;
1123 interrupts = <GIC_SPI 1114 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1124 clocks = <&infracfg_a 1115 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125 resets = <&infracfg_a 1116 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1126 nvmem-cells = <&lvts_ 1117 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "l 1118 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells 1119 #thermal-sensor-cells = <1>;
1129 }; 1120 };
1130 1121
1131 svs: svs@1100bc00 { <<
1132 compatible = "mediate <<
1133 reg = <0 0x1100bc00 0 <<
1134 interrupts = <GIC_SPI <<
1135 clocks = <&infracfg_a <<
1136 clock-names = "main"; <<
1137 nvmem-cells = <&svs_c <<
1138 nvmem-cell-names = "s <<
1139 resets = <&infracfg_a <<
1140 reset-names = "svs_rs <<
1141 }; <<
1142 <<
1143 disp_pwm0: pwm@1100e000 { 1122 disp_pwm0: pwm@1100e000 {
1144 compatible = "mediate 1123 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1145 reg = <0 0x1100e000 0 1124 reg = <0 0x1100e000 0 0x1000>;
1146 interrupts = <GIC_SPI 1125 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1147 power-domains = <&spm 1126 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>; 1127 #pwm-cells = <2>;
1149 clocks = <&topckgen C 1128 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1150 <&infracfg_a 1129 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1151 clock-names = "main", 1130 clock-names = "main", "mm";
1152 status = "disabled"; 1131 status = "disabled";
1153 }; 1132 };
1154 1133
1155 disp_pwm1: pwm@1100f000 { 1134 disp_pwm1: pwm@1100f000 {
1156 compatible = "mediate 1135 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1157 reg = <0 0x1100f000 0 1136 reg = <0 0x1100f000 0 0x1000>;
1158 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1159 #pwm-cells = <2>; 1138 #pwm-cells = <2>;
1160 clocks = <&topckgen C 1139 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1161 <&infracfg_a 1140 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1162 clock-names = "main", 1141 clock-names = "main", "mm";
1163 status = "disabled"; 1142 status = "disabled";
1164 }; 1143 };
1165 1144
1166 spi1: spi@11010000 { 1145 spi1: spi@11010000 {
1167 compatible = "mediate 1146 compatible = "mediatek,mt8195-spi",
1168 "mediate 1147 "mediatek,mt6765-spi";
1169 #address-cells = <1>; 1148 #address-cells = <1>;
1170 #size-cells = <0>; 1149 #size-cells = <0>;
1171 reg = <0 0x11010000 0 1150 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 1151 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen C 1152 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen C 1153 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_a 1154 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent 1155 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled"; 1156 status = "disabled";
1178 }; 1157 };
1179 1158
1180 spi2: spi@11012000 { 1159 spi2: spi@11012000 {
1181 compatible = "mediate 1160 compatible = "mediatek,mt8195-spi",
1182 "mediate 1161 "mediatek,mt6765-spi";
1183 #address-cells = <1>; 1162 #address-cells = <1>;
1184 #size-cells = <0>; 1163 #size-cells = <0>;
1185 reg = <0 0x11012000 0 1164 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 1165 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen C 1166 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen C 1167 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_a 1168 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent 1169 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled"; 1170 status = "disabled";
1192 }; 1171 };
1193 1172
1194 spi3: spi@11013000 { 1173 spi3: spi@11013000 {
1195 compatible = "mediate 1174 compatible = "mediatek,mt8195-spi",
1196 "mediate 1175 "mediatek,mt6765-spi";
1197 #address-cells = <1>; 1176 #address-cells = <1>;
1198 #size-cells = <0>; 1177 #size-cells = <0>;
1199 reg = <0 0x11013000 0 1178 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 1179 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen C 1180 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen C 1181 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_a 1182 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent 1183 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled"; 1184 status = "disabled";
1206 }; 1185 };
1207 1186
1208 spi4: spi@11018000 { 1187 spi4: spi@11018000 {
1209 compatible = "mediate 1188 compatible = "mediatek,mt8195-spi",
1210 "mediate 1189 "mediatek,mt6765-spi";
1211 #address-cells = <1>; 1190 #address-cells = <1>;
1212 #size-cells = <0>; 1191 #size-cells = <0>;
1213 reg = <0 0x11018000 0 1192 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 1193 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen C 1194 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen C 1195 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_a 1196 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent 1197 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled"; 1198 status = "disabled";
1220 }; 1199 };
1221 1200
1222 spi5: spi@11019000 { 1201 spi5: spi@11019000 {
1223 compatible = "mediate 1202 compatible = "mediatek,mt8195-spi",
1224 "mediate 1203 "mediatek,mt6765-spi";
1225 #address-cells = <1>; 1204 #address-cells = <1>;
1226 #size-cells = <0>; 1205 #size-cells = <0>;
1227 reg = <0 0x11019000 0 1206 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 1207 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen C 1208 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen C 1209 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_a 1210 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent 1211 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled"; 1212 status = "disabled";
1234 }; 1213 };
1235 1214
1236 spis0: spi@1101d000 { 1215 spis0: spi@1101d000 {
1237 compatible = "mediate 1216 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 1217 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 1218 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_a 1219 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi"; 1220 clock-names = "spi";
1242 assigned-clocks = <&t 1221 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parent 1222 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled"; 1223 status = "disabled";
1245 }; 1224 };
1246 1225
1247 spis1: spi@1101e000 { 1226 spis1: spi@1101e000 {
1248 compatible = "mediate 1227 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 1228 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 1229 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_a 1230 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi"; 1231 clock-names = "spi";
1253 assigned-clocks = <&t 1232 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parent 1233 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled"; 1234 status = "disabled";
1256 }; 1235 };
1257 1236
1258 eth: ethernet@11021000 { 1237 eth: ethernet@11021000 {
1259 compatible = "mediate 1238 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260 reg = <0 0x11021000 0 1239 reg = <0 0x11021000 0 0x4000>;
1261 interrupts = <GIC_SPI 1240 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262 interrupt-names = "ma 1241 interrupt-names = "macirq";
1263 clock-names = "axi", 1242 clock-names = "axi",
1264 "apb", 1243 "apb",
1265 "mac_ma 1244 "mac_main",
1266 "ptp_re 1245 "ptp_ref",
1267 "rmii_i 1246 "rmii_internal",
1268 "mac_cg 1247 "mac_cg";
1269 clocks = <&pericfg_ao 1248 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270 <&pericfg_ao 1249 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271 <&topckgen C 1250 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen C 1251 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen C 1252 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274 <&pericfg_ao 1253 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275 assigned-clocks = <&t 1254 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&t 1255 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&t 1256 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parent 1257 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 1258 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 1259 <&topckgen CLK_TOP_ETHPLL_D10>;
1281 power-domains = <&spm 1260 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282 mediatek,pericfg = <& 1261 mediatek,pericfg = <&infracfg_ao>;
1283 snps,axi-config = <&s 1262 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = 1263 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = 1264 snps,mtl-tx-config = <&mtl_tx_setup>;
1286 snps,txpbl = <16>; 1265 snps,txpbl = <16>;
1287 snps,rxpbl = <16>; 1266 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>; 1267 snps,clk-csr = <0>;
1289 status = "disabled"; 1268 status = "disabled";
1290 1269
1291 mdio { 1270 mdio {
1292 compatible = 1271 compatible = "snps,dwmac-mdio";
1293 #address-cell 1272 #address-cells = <1>;
1294 #size-cells = 1273 #size-cells = <0>;
1295 }; 1274 };
1296 1275
1297 stmmac_axi_setup: stm 1276 stmmac_axi_setup: stmmac-axi-config {
1298 snps,wr_osr_l 1277 snps,wr_osr_lmt = <0x7>;
1299 snps,rd_osr_l 1278 snps,rd_osr_lmt = <0x7>;
1300 snps,blen = < 1279 snps,blen = <0 0 0 0 16 8 4>;
1301 }; 1280 };
1302 1281
1303 mtl_rx_setup: rx-queu 1282 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queue 1283 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched 1284 snps,rx-sched-sp;
1306 queue0 { 1285 queue0 {
1307 snps, 1286 snps,dcb-algorithm;
1308 snps, 1287 snps,map-to-dma-channel = <0x0>;
1309 }; 1288 };
1310 queue1 { 1289 queue1 {
1311 snps, 1290 snps,dcb-algorithm;
1312 snps, 1291 snps,map-to-dma-channel = <0x0>;
1313 }; 1292 };
1314 queue2 { 1293 queue2 {
1315 snps, 1294 snps,dcb-algorithm;
1316 snps, 1295 snps,map-to-dma-channel = <0x0>;
1317 }; 1296 };
1318 queue3 { 1297 queue3 {
1319 snps, 1298 snps,dcb-algorithm;
1320 snps, 1299 snps,map-to-dma-channel = <0x0>;
1321 }; 1300 };
1322 }; 1301 };
1323 1302
1324 mtl_tx_setup: tx-queu 1303 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queue 1304 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched 1305 snps,tx-sched-wrr;
1327 queue0 { 1306 queue0 {
1328 snps, 1307 snps,weight = <0x10>;
1329 snps, 1308 snps,dcb-algorithm;
1330 snps, 1309 snps,priority = <0x0>;
1331 }; 1310 };
1332 queue1 { 1311 queue1 {
1333 snps, 1312 snps,weight = <0x11>;
1334 snps, 1313 snps,dcb-algorithm;
1335 snps, 1314 snps,priority = <0x1>;
1336 }; 1315 };
1337 queue2 { 1316 queue2 {
1338 snps, 1317 snps,weight = <0x12>;
1339 snps, 1318 snps,dcb-algorithm;
1340 snps, 1319 snps,priority = <0x2>;
1341 }; 1320 };
1342 queue3 { 1321 queue3 {
1343 snps, 1322 snps,weight = <0x13>;
1344 snps, 1323 snps,dcb-algorithm;
1345 snps, 1324 snps,priority = <0x3>;
1346 }; 1325 };
1347 }; 1326 };
1348 }; 1327 };
1349 1328
1350 ssusb0: usb@11201000 { !! 1329 xhci0: usb@11200000 {
1351 compatible = "mediate !! 1330 compatible = "mediatek,mt8195-xhci",
1352 reg = <0 0x11201000 0 !! 1331 "mediatek,mtk-xhci";
>> 1332 reg = <0 0x11200000 0 0x1000>,
>> 1333 <0 0x11203e00 0 0x0100>;
1353 reg-names = "mac", "i 1334 reg-names = "mac", "ippc";
1354 ranges = <0 0 0 0x112 !! 1335 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1355 #address-cells = <2>; !! 1336 phys = <&u2port0 PHY_TYPE_USB2>,
1356 #size-cells = <2>; !! 1337 <&u3port0 PHY_TYPE_USB3>;
1357 interrupts = <GIC_SPI !! 1338 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
>> 1339 <&topckgen CLK_TOP_SSUSB_XHCI>;
>> 1340 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
>> 1341 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1358 clocks = <&infracfg_a 1342 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen C 1343 <&topckgen CLK_TOP_SSUSB_REF>,
>> 1344 <&apmixedsys CLK_APMIXED_USB1PLL>,
>> 1345 <&clk26m>,
1360 <&infracfg_a 1346 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1361 clock-names = "sys_ck !! 1347 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1362 phys = <&u2port0 PHY_ !! 1348 "xhci_ck";
1363 wakeup-source; <<
1364 mediatek,syscon-wakeu 1349 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
>> 1350 wakeup-source;
1365 status = "disabled"; 1351 status = "disabled";
1366 <<
1367 xhci0: usb@0 { <<
1368 compatible = <<
1369 reg = <0 0 0 <<
1370 reg-names = " <<
1371 interrupts = <<
1372 assigned-cloc <<
1373 <<
1374 assigned-cloc <<
1375 <<
1376 clocks = <&in <<
1377 <&to <<
1378 <&ap <<
1379 <&cl <<
1380 <&in <<
1381 clock-names = <<
1382 status = "dis <<
1383 }; <<
1384 }; 1352 };
1385 1353
1386 mmc0: mmc@11230000 { 1354 mmc0: mmc@11230000 {
1387 compatible = "mediate 1355 compatible = "mediatek,mt8195-mmc",
1388 "mediate 1356 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 1357 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 1358 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 1359 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen C 1360 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_a 1361 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_a 1362 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source 1363 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled"; 1364 status = "disabled";
1397 }; 1365 };
1398 1366
1399 mmc1: mmc@11240000 { 1367 mmc1: mmc@11240000 {
1400 compatible = "mediate 1368 compatible = "mediatek,mt8195-mmc",
1401 "mediate 1369 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 1370 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 1371 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 1372 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen C 1373 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_a 1374 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_a 1375 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source 1376 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&t 1377 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parent 1378 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled"; 1379 status = "disabled";
1412 }; 1380 };
1413 1381
1414 mmc2: mmc@11250000 { 1382 mmc2: mmc@11250000 {
1415 compatible = "mediate 1383 compatible = "mediatek,mt8195-mmc",
1416 "mediate 1384 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 1385 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 1386 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 1387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen C 1388 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_a 1389 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_a 1390 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source 1391 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&t 1392 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parent 1393 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled"; 1394 status = "disabled";
1427 }; 1395 };
1428 1396
1429 lvts_mcu: thermal-sensor@1127 1397 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediate 1398 compatible = "mediatek,mt8195-lvts-mcu";
1431 reg = <0 0x11278000 0 1399 reg = <0 0x11278000 0 0x1000>;
1432 interrupts = <GIC_SPI 1400 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1433 clocks = <&infracfg_a 1401 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1434 resets = <&infracfg_a 1402 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1435 nvmem-cells = <&lvts_ 1403 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "l 1404 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells 1405 #thermal-sensor-cells = <1>;
1438 }; 1406 };
1439 1407
1440 xhci1: usb@11290000 { 1408 xhci1: usb@11290000 {
1441 compatible = "mediate 1409 compatible = "mediatek,mt8195-xhci",
1442 "mediate 1410 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 1411 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 1412 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "i 1413 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 1414 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_ !! 1415 phys = <&u2port1 PHY_TYPE_USB2>;
1448 assigned-clocks = <&t 1416 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&t 1417 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parent 1418 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 1419 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao 1420 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen C 1421 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys 1422 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>, 1423 <&clk26m>,
1456 <&pericfg_ao 1424 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck 1425 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_c 1426 "xhci_ck";
1459 mediatek,syscon-wakeu 1427 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source; 1428 wakeup-source;
1461 status = "disabled"; 1429 status = "disabled";
1462 }; 1430 };
1463 1431
1464 ssusb2: usb@112a1000 { !! 1432 xhci2: usb@112a0000 {
1465 compatible = "mediate !! 1433 compatible = "mediatek,mt8195-xhci",
1466 reg = <0 0x112a1000 0 !! 1434 "mediatek,mtk-xhci";
>> 1435 reg = <0 0x112a0000 0 0x1000>,
>> 1436 <0 0x112a3e00 0 0x0100>;
1467 reg-names = "mac", "i 1437 reg-names = "mac", "ippc";
1468 ranges = <0 0 0 0x112 !! 1438 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1469 #address-cells = <2>; !! 1439 phys = <&u2port2 PHY_TYPE_USB2>;
1470 #size-cells = <2>; !! 1440 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1471 interrupts = <GIC_SPI !! 1441 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1472 assigned-clocks = <&t !! 1442 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1473 assigned-clock-parent !! 1443 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1474 clocks = <&pericfg_ao 1444 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen C 1445 <&topckgen CLK_TOP_SSUSB_P2_REF>,
>> 1446 <&clk26m>,
>> 1447 <&clk26m>,
1476 <&pericfg_ao 1448 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1477 clock-names = "sys_ck !! 1449 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1478 phys = <&u2port2 PHY_ !! 1450 "xhci_ck";
1479 wakeup-source; <<
1480 mediatek,syscon-wakeu 1451 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
>> 1452 wakeup-source;
1481 status = "disabled"; 1453 status = "disabled";
1482 <<
1483 xhci2: usb@0 { <<
1484 compatible = <<
1485 reg = <0 0 0 <<
1486 reg-names = " <<
1487 interrupts = <<
1488 assigned-cloc <<
1489 assigned-cloc <<
1490 clocks = <&pe <<
1491 clock-names = <<
1492 status = "dis <<
1493 }; <<
1494 }; 1454 };
1495 1455
1496 ssusb3: usb@112b1000 { !! 1456 xhci3: usb@112b0000 {
1497 compatible = "mediate !! 1457 compatible = "mediatek,mt8195-xhci",
1498 reg = <0 0x112b1000 0 !! 1458 "mediatek,mtk-xhci";
>> 1459 reg = <0 0x112b0000 0 0x1000>,
>> 1460 <0 0x112b3e00 0 0x0100>;
1499 reg-names = "mac", "i 1461 reg-names = "mac", "ippc";
1500 ranges = <0 0 0 0x112 !! 1462 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1501 #address-cells = <2>; !! 1463 phys = <&u2port3 PHY_TYPE_USB2>;
1502 #size-cells = <2>; !! 1464 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1503 interrupts = <GIC_SPI !! 1465 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1504 assigned-clocks = <&t !! 1466 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1505 assigned-clock-parent !! 1467 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clocks = <&pericfg_ao 1468 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen C 1469 <&topckgen CLK_TOP_SSUSB_P3_REF>,
>> 1470 <&clk26m>,
>> 1471 <&clk26m>,
1508 <&pericfg_ao 1472 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1509 clock-names = "sys_ck !! 1473 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1510 phys = <&u2port3 PHY_ !! 1474 "xhci_ck";
1511 wakeup-source; <<
1512 mediatek,syscon-wakeu 1475 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
>> 1476 wakeup-source;
1513 status = "disabled"; 1477 status = "disabled";
1514 <<
1515 xhci3: usb@0 { <<
1516 compatible = <<
1517 reg = <0 0 0 <<
1518 reg-names = " <<
1519 interrupts = <<
1520 assigned-cloc <<
1521 assigned-cloc <<
1522 clocks = <&pe <<
1523 clock-names = <<
1524 status = "dis <<
1525 }; <<
1526 }; 1478 };
1527 1479
1528 pcie0: pcie@112f0000 { 1480 pcie0: pcie@112f0000 {
1529 compatible = "mediate 1481 compatible = "mediatek,mt8195-pcie",
1530 "mediate 1482 "mediatek,mt8192-pcie";
1531 device_type = "pci"; 1483 device_type = "pci";
1532 #address-cells = <3>; 1484 #address-cells = <3>;
1533 #size-cells = <2>; 1485 #size-cells = <2>;
1534 reg = <0 0x112f0000 0 1486 reg = <0 0x112f0000 0 0x4000>;
1535 reg-names = "pcie-mac 1487 reg-names = "pcie-mac";
1536 interrupts = <GIC_SPI 1488 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1537 bus-range = <0x00 0xf 1489 bus-range = <0x00 0xff>;
1538 ranges = <0x81000000 1490 ranges = <0x81000000 0 0x20000000
1539 0x0 0x20000 1491 0x0 0x20000000 0 0x200000>,
1540 <0x82000000 1492 <0x82000000 0 0x20200000
1541 0x0 0x20200 1493 0x0 0x20200000 0 0x3e00000>;
1542 1494
1543 iommu-map = <0 &iommu 1495 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0 1496 iommu-map-mask = <0x0>;
1545 1497
1546 clocks = <&infracfg_a 1498 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 <&infracfg_a 1499 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 <&infracfg_a 1500 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 <&infracfg_a 1501 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 <&infracfg_a 1502 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1551 <&pericfg_ao 1503 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1552 clock-names = "pl_250 1504 clock-names = "pl_250m", "tl_26m", "tl_96m",
1553 "tl_32k 1505 "tl_32k", "peri_26m", "peri_mem";
1554 assigned-clocks = <&t 1506 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parent 1507 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1556 1508
1557 phys = <&pciephy>; 1509 phys = <&pciephy>;
1558 phy-names = "pcie-phy 1510 phy-names = "pcie-phy";
1559 1511
1560 power-domains = <&spm 1512 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1561 1513
1562 resets = <&infracfg_a 1514 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1563 reset-names = "mac"; 1515 reset-names = "mac";
1564 1516
1565 #interrupt-cells = <1 1517 #interrupt-cells = <1>;
1566 interrupt-map-mask = 1518 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 1519 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 1520 <0 0 0 2 &pcie_intc0 1>,
1569 <0 0 1521 <0 0 0 3 &pcie_intc0 2>,
1570 <0 0 1522 <0 0 0 4 &pcie_intc0 3>;
1571 status = "disabled"; 1523 status = "disabled";
1572 1524
1573 pcie_intc0: interrupt 1525 pcie_intc0: interrupt-controller {
1574 interrupt-con 1526 interrupt-controller;
1575 #address-cell 1527 #address-cells = <0>;
1576 #interrupt-ce 1528 #interrupt-cells = <1>;
1577 }; 1529 };
1578 }; 1530 };
1579 1531
1580 pcie1: pcie@112f8000 { 1532 pcie1: pcie@112f8000 {
1581 compatible = "mediate 1533 compatible = "mediatek,mt8195-pcie",
1582 "mediate 1534 "mediatek,mt8192-pcie";
1583 device_type = "pci"; 1535 device_type = "pci";
1584 #address-cells = <3>; 1536 #address-cells = <3>;
1585 #size-cells = <2>; 1537 #size-cells = <2>;
1586 reg = <0 0x112f8000 0 1538 reg = <0 0x112f8000 0 0x4000>;
1587 reg-names = "pcie-mac 1539 reg-names = "pcie-mac";
1588 interrupts = <GIC_SPI 1540 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1589 bus-range = <0x00 0xf 1541 bus-range = <0x00 0xff>;
1590 ranges = <0x81000000 1542 ranges = <0x81000000 0 0x24000000
1591 0x0 0x24000 1543 0x0 0x24000000 0 0x200000>,
1592 <0x82000000 1544 <0x82000000 0 0x24200000
1593 0x0 0x24200 1545 0x0 0x24200000 0 0x3e00000>;
1594 1546
1595 iommu-map = <0 &iommu 1547 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0 1548 iommu-map-mask = <0x0>;
1597 1549
1598 clocks = <&infracfg_a 1550 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1599 <&clk26m>, 1551 <&clk26m>,
1600 <&infracfg_a 1552 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1601 <&clk26m>, 1553 <&clk26m>,
1602 <&infracfg_a 1554 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1603 /* Designer 1555 /* Designer has connect pcie1 with peri_mem_p0 clock */
1604 <&pericfg_ao 1556 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1605 clock-names = "pl_250 1557 clock-names = "pl_250m", "tl_26m", "tl_96m",
1606 "tl_32k 1558 "tl_32k", "peri_26m", "peri_mem";
1607 assigned-clocks = <&t 1559 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parent 1560 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1609 1561
1610 phys = <&u3port1 PHY_ 1562 phys = <&u3port1 PHY_TYPE_PCIE>;
1611 phy-names = "pcie-phy 1563 phy-names = "pcie-phy";
1612 power-domains = <&spm 1564 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1613 1565
1614 resets = <&infracfg_a 1566 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1615 reset-names = "mac"; 1567 reset-names = "mac";
1616 1568
1617 #interrupt-cells = <1 1569 #interrupt-cells = <1>;
1618 interrupt-map-mask = 1570 interrupt-map-mask = <0 0 0 7>;
1619 interrupt-map = <0 0 1571 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1620 <0 0 1572 <0 0 0 2 &pcie_intc1 1>,
1621 <0 0 1573 <0 0 0 3 &pcie_intc1 2>,
1622 <0 0 1574 <0 0 0 4 &pcie_intc1 3>;
1623 status = "disabled"; 1575 status = "disabled";
1624 1576
1625 pcie_intc1: interrupt 1577 pcie_intc1: interrupt-controller {
1626 interrupt-con 1578 interrupt-controller;
1627 #address-cell 1579 #address-cells = <0>;
1628 #interrupt-ce 1580 #interrupt-cells = <1>;
1629 }; 1581 };
1630 }; 1582 };
1631 1583
1632 nor_flash: spi@1132c000 { 1584 nor_flash: spi@1132c000 {
1633 compatible = "mediate 1585 compatible = "mediatek,mt8195-nor",
1634 "mediate 1586 "mediatek,mt8173-nor";
1635 reg = <0 0x1132c000 0 1587 reg = <0 0x1132c000 0 0x1000>;
1636 interrupts = <GIC_SPI 1588 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1637 clocks = <&topckgen C 1589 clocks = <&topckgen CLK_TOP_SPINOR>,
1638 <&pericfg_ao 1590 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1639 <&pericfg_ao 1591 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1640 clock-names = "spi", 1592 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>; 1593 #address-cells = <1>;
1642 #size-cells = <0>; 1594 #size-cells = <0>;
1643 status = "disabled"; 1595 status = "disabled";
1644 }; 1596 };
1645 1597
1646 efuse: efuse@11c10000 { 1598 efuse: efuse@11c10000 {
1647 compatible = "mediate 1599 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1648 reg = <0 0x11c10000 0 1600 reg = <0 0x11c10000 0 0x1000>;
1649 #address-cells = <1>; 1601 #address-cells = <1>;
1650 #size-cells = <1>; 1602 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx 1603 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 reg = <0x184 1604 reg = <0x184 0x1>;
1653 bits = <0 5>; 1605 bits = <0 5>;
1654 }; 1606 };
1655 u3_rx_imp_p0: usb3-rx 1607 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 reg = <0x184 1608 reg = <0x184 0x2>;
1657 bits = <5 5>; 1609 bits = <5 5>;
1658 }; 1610 };
1659 u3_intr_p0: usb3-intr 1611 u3_intr_p0: usb3-intr@185 {
1660 reg = <0x185 1612 reg = <0x185 0x1>;
1661 bits = <2 6>; 1613 bits = <2 6>;
1662 }; 1614 };
1663 comb_tx_imp_p1: usb3- 1615 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 reg = <0x186 1616 reg = <0x186 0x1>;
1665 bits = <0 5>; 1617 bits = <0 5>;
1666 }; 1618 };
1667 comb_rx_imp_p1: usb3- 1619 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 reg = <0x186 1620 reg = <0x186 0x2>;
1669 bits = <5 5>; 1621 bits = <5 5>;
1670 }; 1622 };
1671 comb_intr_p1: usb3-in 1623 comb_intr_p1: usb3-intr@187 {
1672 reg = <0x187 1624 reg = <0x187 0x1>;
1673 bits = <2 6>; 1625 bits = <2 6>;
1674 }; 1626 };
1675 u2_intr_p0: usb2-intr 1627 u2_intr_p0: usb2-intr-p0@188,1 {
1676 reg = <0x188 1628 reg = <0x188 0x1>;
1677 bits = <0 5>; 1629 bits = <0 5>;
1678 }; 1630 };
1679 u2_intr_p1: usb2-intr 1631 u2_intr_p1: usb2-intr-p1@188,2 {
1680 reg = <0x188 1632 reg = <0x188 0x2>;
1681 bits = <5 5>; 1633 bits = <5 5>;
1682 }; 1634 };
1683 u2_intr_p2: usb2-intr 1635 u2_intr_p2: usb2-intr-p2@189,1 {
1684 reg = <0x189 1636 reg = <0x189 0x1>;
1685 bits = <2 5>; 1637 bits = <2 5>;
1686 }; 1638 };
1687 u2_intr_p3: usb2-intr 1639 u2_intr_p3: usb2-intr-p3@189,2 {
1688 reg = <0x189 1640 reg = <0x189 0x2>;
1689 bits = <7 5>; 1641 bits = <7 5>;
1690 }; 1642 };
1691 pciephy_rx_ln1: pciep 1643 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1692 reg = <0x190 1644 reg = <0x190 0x1>;
1693 bits = <0 4>; 1645 bits = <0 4>;
1694 }; 1646 };
1695 pciephy_tx_ln1_nmos: 1647 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1696 reg = <0x190 1648 reg = <0x190 0x1>;
1697 bits = <4 4>; 1649 bits = <4 4>;
1698 }; 1650 };
1699 pciephy_tx_ln1_pmos: 1651 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1700 reg = <0x191 1652 reg = <0x191 0x1>;
1701 bits = <0 4>; 1653 bits = <0 4>;
1702 }; 1654 };
1703 pciephy_rx_ln0: pciep 1655 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1704 reg = <0x191 1656 reg = <0x191 0x1>;
1705 bits = <4 4>; 1657 bits = <4 4>;
1706 }; 1658 };
1707 pciephy_tx_ln0_nmos: 1659 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1708 reg = <0x192 1660 reg = <0x192 0x1>;
1709 bits = <0 4>; 1661 bits = <0 4>;
1710 }; 1662 };
1711 pciephy_tx_ln0_pmos: 1663 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1712 reg = <0x192 1664 reg = <0x192 0x1>;
1713 bits = <4 4>; 1665 bits = <4 4>;
1714 }; 1666 };
1715 pciephy_glb_intr: pci 1667 pciephy_glb_intr: pciephy-glb-intr@193 {
1716 reg = <0x193 1668 reg = <0x193 0x1>;
1717 bits = <0 4>; 1669 bits = <0 4>;
1718 }; 1670 };
1719 dp_calibration: dp-da 1671 dp_calibration: dp-data@1ac {
1720 reg = <0x1ac 1672 reg = <0x1ac 0x10>;
1721 }; 1673 };
1722 lvts_efuse_data1: lvt 1674 lvts_efuse_data1: lvts1-calib@1bc {
1723 reg = <0x1bc 1675 reg = <0x1bc 0x14>;
1724 }; 1676 };
1725 lvts_efuse_data2: lvt 1677 lvts_efuse_data2: lvts2-calib@1d0 {
1726 reg = <0x1d0 1678 reg = <0x1d0 0x38>;
1727 }; 1679 };
1728 svs_calib_data: svs-c <<
1729 reg = <0x580 <<
1730 }; <<
1731 socinfo-data1@7a0 { <<
1732 reg = <0x7a0 <<
1733 }; <<
1734 }; 1680 };
1735 1681
1736 u3phy2: t-phy@11c40000 { 1682 u3phy2: t-phy@11c40000 {
1737 compatible = "mediate 1683 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>; 1684 #address-cells = <1>;
1739 #size-cells = <1>; 1685 #size-cells = <1>;
1740 ranges = <0 0 0x11c40 1686 ranges = <0 0 0x11c40000 0x700>;
1741 status = "disabled"; 1687 status = "disabled";
1742 1688
1743 u2port2: usb-phy@0 { 1689 u2port2: usb-phy@0 {
1744 reg = <0x0 0x 1690 reg = <0x0 0x700>;
1745 clocks = <&to 1691 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1746 clock-names = 1692 clock-names = "ref";
1747 #phy-cells = 1693 #phy-cells = <1>;
1748 }; 1694 };
1749 }; 1695 };
1750 1696
1751 u3phy3: t-phy@11c50000 { 1697 u3phy3: t-phy@11c50000 {
1752 compatible = "mediate 1698 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>; 1699 #address-cells = <1>;
1754 #size-cells = <1>; 1700 #size-cells = <1>;
1755 ranges = <0 0 0x11c50 1701 ranges = <0 0 0x11c50000 0x700>;
1756 status = "disabled"; 1702 status = "disabled";
1757 1703
1758 u2port3: usb-phy@0 { 1704 u2port3: usb-phy@0 {
1759 reg = <0x0 0x 1705 reg = <0x0 0x700>;
1760 clocks = <&to 1706 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1761 clock-names = 1707 clock-names = "ref";
1762 #phy-cells = 1708 #phy-cells = <1>;
1763 }; 1709 };
1764 }; 1710 };
1765 1711
1766 mipi_tx0: dsi-phy@11c80000 { <<
1767 compatible = "mediate <<
1768 reg = <0 0x11c80000 0 <<
1769 clocks = <&clk26m>; <<
1770 clock-output-names = <<
1771 #clock-cells = <0>; <<
1772 #phy-cells = <0>; <<
1773 status = "disabled"; <<
1774 }; <<
1775 <<
1776 mipi_tx1: dsi-phy@11c90000 { <<
1777 compatible = "mediate <<
1778 reg = <0 0x11c90000 0 <<
1779 clocks = <&clk26m>; <<
1780 clock-output-names = <<
1781 #clock-cells = <0>; <<
1782 #phy-cells = <0>; <<
1783 status = "disabled"; <<
1784 }; <<
1785 <<
1786 i2c5: i2c@11d00000 { 1712 i2c5: i2c@11d00000 {
1787 compatible = "mediate 1713 compatible = "mediatek,mt8195-i2c",
1788 "mediate 1714 "mediatek,mt8192-i2c";
1789 reg = <0 0x11d00000 0 1715 reg = <0 0x11d00000 0 0x1000>,
1790 <0 0x10220580 0 1716 <0 0x10220580 0 0x80>;
1791 interrupts = <GIC_SPI 1717 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1792 clock-div = <1>; 1718 clock-div = <1>;
1793 clocks = <&imp_iic_wr 1719 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1794 <&infracfg_a 1720 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795 clock-names = "main", 1721 clock-names = "main", "dma";
1796 #address-cells = <1>; 1722 #address-cells = <1>;
1797 #size-cells = <0>; 1723 #size-cells = <0>;
1798 status = "disabled"; 1724 status = "disabled";
1799 }; 1725 };
1800 1726
1801 i2c6: i2c@11d01000 { 1727 i2c6: i2c@11d01000 {
1802 compatible = "mediate 1728 compatible = "mediatek,mt8195-i2c",
1803 "mediate 1729 "mediatek,mt8192-i2c";
1804 reg = <0 0x11d01000 0 1730 reg = <0 0x11d01000 0 0x1000>,
1805 <0 0x10220600 0 1731 <0 0x10220600 0 0x80>;
1806 interrupts = <GIC_SPI 1732 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1807 clock-div = <1>; 1733 clock-div = <1>;
1808 clocks = <&imp_iic_wr 1734 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1809 <&infracfg_a 1735 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1810 clock-names = "main", 1736 clock-names = "main", "dma";
1811 #address-cells = <1>; 1737 #address-cells = <1>;
1812 #size-cells = <0>; 1738 #size-cells = <0>;
1813 status = "disabled"; 1739 status = "disabled";
1814 }; 1740 };
1815 1741
1816 i2c7: i2c@11d02000 { 1742 i2c7: i2c@11d02000 {
1817 compatible = "mediate 1743 compatible = "mediatek,mt8195-i2c",
1818 "mediate 1744 "mediatek,mt8192-i2c";
1819 reg = <0 0x11d02000 0 1745 reg = <0 0x11d02000 0 0x1000>,
1820 <0 0x10220680 0 1746 <0 0x10220680 0 0x80>;
1821 interrupts = <GIC_SPI 1747 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1822 clock-div = <1>; 1748 clock-div = <1>;
1823 clocks = <&imp_iic_wr 1749 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1824 <&infracfg_a 1750 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1825 clock-names = "main", 1751 clock-names = "main", "dma";
1826 #address-cells = <1>; 1752 #address-cells = <1>;
1827 #size-cells = <0>; 1753 #size-cells = <0>;
1828 status = "disabled"; 1754 status = "disabled";
1829 }; 1755 };
1830 1756
1831 imp_iic_wrap_s: clock-control 1757 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediate 1758 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1833 reg = <0 0x11d03000 0 1759 reg = <0 0x11d03000 0 0x1000>;
1834 #clock-cells = <1>; 1760 #clock-cells = <1>;
1835 }; 1761 };
1836 1762
1837 i2c0: i2c@11e00000 { 1763 i2c0: i2c@11e00000 {
1838 compatible = "mediate 1764 compatible = "mediatek,mt8195-i2c",
1839 "mediate 1765 "mediatek,mt8192-i2c";
1840 reg = <0 0x11e00000 0 1766 reg = <0 0x11e00000 0 0x1000>,
1841 <0 0x10220080 0 1767 <0 0x10220080 0 0x80>;
1842 interrupts = <GIC_SPI 1768 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1843 clock-div = <1>; 1769 clock-div = <1>;
1844 clocks = <&imp_iic_wr 1770 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1845 <&infracfg_a 1771 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846 clock-names = "main", 1772 clock-names = "main", "dma";
1847 #address-cells = <1>; 1773 #address-cells = <1>;
1848 #size-cells = <0>; 1774 #size-cells = <0>;
1849 status = "disabled"; 1775 status = "disabled";
1850 }; 1776 };
1851 1777
1852 i2c1: i2c@11e01000 { 1778 i2c1: i2c@11e01000 {
1853 compatible = "mediate 1779 compatible = "mediatek,mt8195-i2c",
1854 "mediate 1780 "mediatek,mt8192-i2c";
1855 reg = <0 0x11e01000 0 1781 reg = <0 0x11e01000 0 0x1000>,
1856 <0 0x10220200 0 1782 <0 0x10220200 0 0x80>;
1857 interrupts = <GIC_SPI 1783 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clock-div = <1>; 1784 clock-div = <1>;
1859 clocks = <&imp_iic_wr 1785 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1860 <&infracfg_a 1786 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861 clock-names = "main", 1787 clock-names = "main", "dma";
1862 #address-cells = <1>; 1788 #address-cells = <1>;
1863 #size-cells = <0>; 1789 #size-cells = <0>;
1864 status = "disabled"; 1790 status = "disabled";
1865 }; 1791 };
1866 1792
1867 i2c2: i2c@11e02000 { 1793 i2c2: i2c@11e02000 {
1868 compatible = "mediate 1794 compatible = "mediatek,mt8195-i2c",
1869 "mediate 1795 "mediatek,mt8192-i2c";
1870 reg = <0 0x11e02000 0 1796 reg = <0 0x11e02000 0 0x1000>,
1871 <0 0x10220380 0 1797 <0 0x10220380 0 0x80>;
1872 interrupts = <GIC_SPI 1798 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1873 clock-div = <1>; 1799 clock-div = <1>;
1874 clocks = <&imp_iic_wr 1800 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1875 <&infracfg_a 1801 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876 clock-names = "main", 1802 clock-names = "main", "dma";
1877 #address-cells = <1>; 1803 #address-cells = <1>;
1878 #size-cells = <0>; 1804 #size-cells = <0>;
1879 status = "disabled"; 1805 status = "disabled";
1880 }; 1806 };
1881 1807
1882 i2c3: i2c@11e03000 { 1808 i2c3: i2c@11e03000 {
1883 compatible = "mediate 1809 compatible = "mediatek,mt8195-i2c",
1884 "mediate 1810 "mediatek,mt8192-i2c";
1885 reg = <0 0x11e03000 0 1811 reg = <0 0x11e03000 0 0x1000>,
1886 <0 0x10220480 0 1812 <0 0x10220480 0 0x80>;
1887 interrupts = <GIC_SPI 1813 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clock-div = <1>; 1814 clock-div = <1>;
1889 clocks = <&imp_iic_wr 1815 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1890 <&infracfg_a 1816 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1891 clock-names = "main", 1817 clock-names = "main", "dma";
1892 #address-cells = <1>; 1818 #address-cells = <1>;
1893 #size-cells = <0>; 1819 #size-cells = <0>;
1894 status = "disabled"; 1820 status = "disabled";
1895 }; 1821 };
1896 1822
1897 i2c4: i2c@11e04000 { 1823 i2c4: i2c@11e04000 {
1898 compatible = "mediate 1824 compatible = "mediatek,mt8195-i2c",
1899 "mediate 1825 "mediatek,mt8192-i2c";
1900 reg = <0 0x11e04000 0 1826 reg = <0 0x11e04000 0 0x1000>,
1901 <0 0x10220500 0 1827 <0 0x10220500 0 0x80>;
1902 interrupts = <GIC_SPI 1828 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1903 clock-div = <1>; 1829 clock-div = <1>;
1904 clocks = <&imp_iic_wr 1830 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1905 <&infracfg_a 1831 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1906 clock-names = "main", 1832 clock-names = "main", "dma";
1907 #address-cells = <1>; 1833 #address-cells = <1>;
1908 #size-cells = <0>; 1834 #size-cells = <0>;
1909 status = "disabled"; 1835 status = "disabled";
1910 }; 1836 };
1911 1837
1912 imp_iic_wrap_w: clock-control 1838 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediate 1839 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1914 reg = <0 0x11e05000 0 1840 reg = <0 0x11e05000 0 0x1000>;
1915 #clock-cells = <1>; 1841 #clock-cells = <1>;
1916 }; 1842 };
1917 1843
1918 u3phy1: t-phy@11e30000 { 1844 u3phy1: t-phy@11e30000 {
1919 compatible = "mediate 1845 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>; 1846 #address-cells = <1>;
1921 #size-cells = <1>; 1847 #size-cells = <1>;
1922 ranges = <0 0 0x11e30 1848 ranges = <0 0 0x11e30000 0xe00>;
1923 power-domains = <&spm 1849 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1924 status = "disabled"; 1850 status = "disabled";
1925 1851
1926 u2port1: usb-phy@0 { 1852 u2port1: usb-phy@0 {
1927 reg = <0x0 0x 1853 reg = <0x0 0x700>;
1928 clocks = <&to 1854 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1929 <&cl 1855 <&clk26m>;
1930 clock-names = 1856 clock-names = "ref", "da_ref";
1931 #phy-cells = 1857 #phy-cells = <1>;
1932 }; 1858 };
1933 1859
1934 u3port1: usb-phy@700 1860 u3port1: usb-phy@700 {
1935 reg = <0x700 1861 reg = <0x700 0x700>;
1936 clocks = <&ap 1862 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1937 <&to 1863 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1938 clock-names = 1864 clock-names = "ref", "da_ref";
1939 nvmem-cells = 1865 nvmem-cells = <&comb_intr_p1>,
1940 1866 <&comb_rx_imp_p1>,
1941 1867 <&comb_tx_imp_p1>;
1942 nvmem-cell-na 1868 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = 1869 #phy-cells = <1>;
1944 }; 1870 };
1945 }; 1871 };
1946 1872
1947 u3phy0: t-phy@11e40000 { 1873 u3phy0: t-phy@11e40000 {
1948 compatible = "mediate 1874 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>; 1875 #address-cells = <1>;
1950 #size-cells = <1>; 1876 #size-cells = <1>;
1951 ranges = <0 0 0x11e40 1877 ranges = <0 0 0x11e40000 0xe00>;
1952 status = "disabled"; 1878 status = "disabled";
1953 1879
1954 u2port0: usb-phy@0 { 1880 u2port0: usb-phy@0 {
1955 reg = <0x0 0x 1881 reg = <0x0 0x700>;
1956 clocks = <&to 1882 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1957 <&cl 1883 <&clk26m>;
1958 clock-names = 1884 clock-names = "ref", "da_ref";
1959 #phy-cells = 1885 #phy-cells = <1>;
1960 }; 1886 };
1961 1887
1962 u3port0: usb-phy@700 1888 u3port0: usb-phy@700 {
1963 reg = <0x700 1889 reg = <0x700 0x700>;
1964 clocks = <&ap 1890 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1965 <&to 1891 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1966 clock-names = 1892 clock-names = "ref", "da_ref";
1967 nvmem-cells = 1893 nvmem-cells = <&u3_intr_p0>,
1968 1894 <&u3_rx_imp_p0>,
1969 1895 <&u3_tx_imp_p0>;
1970 nvmem-cell-na 1896 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = 1897 #phy-cells = <1>;
1972 }; 1898 };
1973 }; 1899 };
1974 1900
1975 pciephy: phy@11e80000 { 1901 pciephy: phy@11e80000 {
1976 compatible = "mediate 1902 compatible = "mediatek,mt8195-pcie-phy";
1977 reg = <0 0x11e80000 0 1903 reg = <0 0x11e80000 0 0x10000>;
1978 reg-names = "sif"; 1904 reg-names = "sif";
1979 nvmem-cells = <&pciep 1905 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1980 <&pciep 1906 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1981 <&pciep 1907 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1982 <&pciep 1908 <&pciephy_rx_ln1>;
1983 nvmem-cell-names = "g 1909 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1984 "t 1910 "tx_ln0_nmos", "rx_ln0",
1985 "t 1911 "tx_ln1_pmos", "tx_ln1_nmos",
1986 "r 1912 "rx_ln1";
1987 power-domains = <&spm 1913 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1988 #phy-cells = <0>; 1914 #phy-cells = <0>;
1989 status = "disabled"; 1915 status = "disabled";
1990 }; 1916 };
1991 1917
1992 ufsphy: ufs-phy@11fa0000 { 1918 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediate 1919 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1994 reg = <0 0x11fa0000 0 1920 reg = <0 0x11fa0000 0 0xc000>;
1995 clocks = <&clk26m>, < 1921 clocks = <&clk26m>, <&clk26m>;
1996 clock-names = "unipro 1922 clock-names = "unipro", "mp";
1997 #phy-cells = <0>; 1923 #phy-cells = <0>;
1998 status = "disabled"; 1924 status = "disabled";
1999 }; 1925 };
2000 1926
2001 gpu: gpu@13000000 { 1927 gpu: gpu@13000000 {
2002 compatible = "mediate 1928 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2003 "arm,mal 1929 "arm,mali-valhall-jm";
2004 reg = <0 0x13000000 0 1930 reg = <0 0x13000000 0 0x4000>;
2005 1931
2006 clocks = <&mfgcfg CLK 1932 clocks = <&mfgcfg CLK_MFG_BG3D>;
2007 interrupts = <GIC_SPI 1933 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
2008 <GIC_SPI 1934 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
2009 <GIC_SPI 1935 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
2010 interrupt-names = "jo 1936 interrupt-names = "job", "mmu", "gpu";
2011 operating-points-v2 = 1937 operating-points-v2 = <&gpu_opp_table>;
2012 power-domains = <&spm 1938 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2013 <&spm 1939 <&spm MT8195_POWER_DOMAIN_MFG3>,
2014 <&spm 1940 <&spm MT8195_POWER_DOMAIN_MFG4>,
2015 <&spm 1941 <&spm MT8195_POWER_DOMAIN_MFG5>,
2016 <&spm 1942 <&spm MT8195_POWER_DOMAIN_MFG6>;
2017 power-domain-names = 1943 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2018 status = "disabled"; 1944 status = "disabled";
2019 }; 1945 };
2020 1946
2021 mfgcfg: clock-controller@13fb 1947 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediate 1948 compatible = "mediatek,mt8195-mfgcfg";
2023 reg = <0 0x13fbf000 0 1949 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>; 1950 #clock-cells = <1>;
2025 }; 1951 };
2026 1952
2027 vppsys0: syscon@14000000 { 1953 vppsys0: syscon@14000000 {
2028 compatible = "mediate 1954 compatible = "mediatek,mt8195-vppsys0", "syscon";
2029 reg = <0 0x14000000 0 1955 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>; 1956 #clock-cells = <1>;
2031 mediatek,gce-client-r <<
2032 }; <<
2033 <<
2034 dma-controller@14001000 { <<
2035 compatible = "mediate <<
2036 reg = <0 0x14001000 0 <<
2037 mediatek,gce-client-r <<
2038 mediatek,gce-events = <<
2039 <<
2040 mediatek,scp = <&scp> <<
2041 power-domains = <&spm <<
2042 iommus = <&iommu_vpp <<
2043 clocks = <&vppsys0 CL <<
2044 mboxes = <&gce1 12 CM <<
2045 <&gce1 13 CM <<
2046 <&gce1 14 CM <<
2047 <&gce1 21 CM <<
2048 <&gce1 22 CM <<
2049 #dma-cells = <1>; <<
2050 }; <<
2051 <<
2052 display@14002000 { <<
2053 compatible = "mediate <<
2054 reg = <0 0x14002000 0 <<
2055 mediatek,gce-client-r <<
2056 clocks = <&vppsys0 CL <<
2057 }; <<
2058 <<
2059 display@14003000 { <<
2060 compatible = "mediate <<
2061 reg = <0 0x14003000 0 <<
2062 mediatek,gce-client-r <<
2063 clocks = <&vppsys0 CL <<
2064 }; <<
2065 <<
2066 display@14004000 { <<
2067 compatible = "mediate <<
2068 reg = <0 0x14004000 0 <<
2069 mediatek,gce-client-r <<
2070 clocks = <&vppsys0 CL <<
2071 }; <<
2072 <<
2073 display@14005000 { <<
2074 compatible = "mediate <<
2075 reg = <0 0x14005000 0 <<
2076 interrupts = <GIC_SPI <<
2077 mediatek,gce-client-r <<
2078 clocks = <&vppsys0 CL <<
2079 power-domains = <&spm <<
2080 }; <<
2081 <<
2082 display@14006000 { <<
2083 compatible = "mediate <<
2084 reg = <0 0x14006000 0 <<
2085 mediatek,gce-client-r <<
2086 mediatek,gce-events = <<
2087 <<
2088 clocks = <&vppsys0 CL <<
2089 }; <<
2090 <<
2091 display@14007000 { <<
2092 compatible = "mediate <<
2093 reg = <0 0x14007000 0 <<
2094 mediatek,gce-client-r <<
2095 clocks = <&vppsys0 CL <<
2096 }; <<
2097 <<
2098 display@14008000 { <<
2099 compatible = "mediate <<
2100 reg = <0 0x14008000 0 <<
2101 interrupts = <GIC_SPI <<
2102 mediatek,gce-client-r <<
2103 clocks = <&vppsys0 CL <<
2104 power-domains = <&spm <<
2105 }; <<
2106 <<
2107 display@14009000 { <<
2108 compatible = "mediate <<
2109 reg = <0 0x14009000 0 <<
2110 interrupts = <GIC_SPI <<
2111 mediatek,gce-client-r <<
2112 clocks = <&vppsys0 CL <<
2113 power-domains = <&spm <<
2114 iommus = <&iommu_vpp <<
2115 }; <<
2116 <<
2117 display@1400a000 { <<
2118 compatible = "mediate <<
2119 reg = <0 0x1400a000 0 <<
2120 mediatek,gce-client-r <<
2121 clocks = <&vppsys0 CL <<
2122 power-domains = <&spm <<
2123 }; <<
2124 <<
2125 display@1400b000 { <<
2126 compatible = "mediate <<
2127 reg = <0 0x1400b000 0 <<
2128 mediatek,gce-client-r <<
2129 clocks = <&vppsys0 CL <<
2130 }; <<
2131 <<
2132 dma-controller@1400c000 { <<
2133 compatible = "mediate <<
2134 reg = <0 0x1400c000 0 <<
2135 mediatek,gce-client-r <<
2136 mediatek,gce-events = <<
2137 <<
2138 clocks = <&vppsys0 CL <<
2139 iommus = <&iommu_vpp <<
2140 power-domains = <&spm <<
2141 #dma-cells = <1>; <<
2142 }; 1957 };
2143 1958
2144 mutex@1400f000 { 1959 mutex@1400f000 {
2145 compatible = "mediate 1960 compatible = "mediatek,mt8195-vpp-mutex";
2146 reg = <0 0x1400f000 0 1961 reg = <0 0x1400f000 0 0x1000>;
2147 interrupts = <GIC_SPI 1962 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
2148 mediatek,gce-client-r 1963 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2149 clocks = <&vppsys0 CL 1964 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2150 power-domains = <&spm 1965 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2151 }; 1966 };
2152 1967
2153 smi_sub_common_vpp0_vpp1_2x1: 1968 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2154 compatible = "mediate 1969 compatible = "mediatek,mt8195-smi-sub-common";
2155 reg = <0 0x14010000 0 1970 reg = <0 0x14010000 0 0x1000>;
2156 clocks = <&vppsys0 CL 1971 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_ 1972 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2158 <&vppsys0 CLK_ 1973 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2159 clock-names = "apb", 1974 clock-names = "apb", "smi", "gals0";
2160 mediatek,smi = <&smi_ 1975 mediatek,smi = <&smi_common_vpp>;
2161 power-domains = <&spm 1976 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2162 }; 1977 };
2163 1978
2164 smi_sub_common_vdec_vpp0_2x1: 1979 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2165 compatible = "mediate 1980 compatible = "mediatek,mt8195-smi-sub-common";
2166 reg = <0 0x14011000 0 1981 reg = <0 0x14011000 0 0x1000>;
2167 clocks = <&vppsys0 CL 1982 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CL 1983 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2169 <&vppsys0 CL 1984 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2170 clock-names = "apb", 1985 clock-names = "apb", "smi", "gals0";
2171 mediatek,smi = <&smi_ 1986 mediatek,smi = <&smi_common_vpp>;
2172 power-domains = <&spm 1987 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2173 }; 1988 };
2174 1989
2175 smi_common_vpp: smi@14012000 1990 smi_common_vpp: smi@14012000 {
2176 compatible = "mediate 1991 compatible = "mediatek,mt8195-smi-common-vpp";
2177 reg = <0 0x14012000 0 1992 reg = <0 0x14012000 0 0x1000>;
2178 clocks = <&vppsys0 CL 1993 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_ 1994 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2180 <&vppsys0 CLK_ 1995 <&vppsys0 CLK_VPP0_SMI_RSI>,
2181 <&vppsys0 CLK_ 1996 <&vppsys0 CLK_VPP0_SMI_RSI>;
2182 clock-names = "apb", 1997 clock-names = "apb", "smi", "gals0", "gals1";
2183 power-domains = <&spm 1998 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2184 }; 1999 };
2185 2000
2186 larb4: larb@14013000 { 2001 larb4: larb@14013000 {
2187 compatible = "mediate 2002 compatible = "mediatek,mt8195-smi-larb";
2188 reg = <0 0x14013000 0 2003 reg = <0 0x14013000 0 0x1000>;
2189 mediatek,larb-id = <4 2004 mediatek,larb-id = <4>;
2190 mediatek,smi = <&smi_ 2005 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2191 clocks = <&vppsys0 CL 2006 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2192 <&vppsys0 CLK_ 2007 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2193 clock-names = "apb", 2008 clock-names = "apb", "smi";
2194 power-domains = <&spm 2009 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2195 }; 2010 };
2196 2011
2197 iommu_vpp: iommu@14018000 { 2012 iommu_vpp: iommu@14018000 {
2198 compatible = "mediate 2013 compatible = "mediatek,mt8195-iommu-vpp";
2199 reg = <0 0x14018000 0 2014 reg = <0 0x14018000 0 0x1000>;
2200 mediatek,larbs = <&la 2015 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2201 &la 2016 &larb12 &larb14 &larb16 &larb18
2202 &la 2017 &larb20 &larb22 &larb23 &larb26
2203 &la 2018 &larb27>;
2204 interrupts = <GIC_SPI 2019 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2205 clocks = <&vppsys0 CL 2020 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2206 clock-names = "bclk"; 2021 clock-names = "bclk";
2207 #iommu-cells = <1>; 2022 #iommu-cells = <1>;
2208 power-domains = <&spm 2023 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2209 }; 2024 };
2210 2025
2211 wpesys: clock-controller@14e0 2026 wpesys: clock-controller@14e00000 {
2212 compatible = "mediate 2027 compatible = "mediatek,mt8195-wpesys";
2213 reg = <0 0x14e00000 0 2028 reg = <0 0x14e00000 0 0x1000>;
2214 #clock-cells = <1>; 2029 #clock-cells = <1>;
2215 }; 2030 };
2216 2031
2217 wpesys_vpp0: clock-controller 2032 wpesys_vpp0: clock-controller@14e02000 {
2218 compatible = "mediate 2033 compatible = "mediatek,mt8195-wpesys_vpp0";
2219 reg = <0 0x14e02000 0 2034 reg = <0 0x14e02000 0 0x1000>;
2220 #clock-cells = <1>; 2035 #clock-cells = <1>;
2221 }; 2036 };
2222 2037
2223 wpesys_vpp1: clock-controller 2038 wpesys_vpp1: clock-controller@14e03000 {
2224 compatible = "mediate 2039 compatible = "mediatek,mt8195-wpesys_vpp1";
2225 reg = <0 0x14e03000 0 2040 reg = <0 0x14e03000 0 0x1000>;
2226 #clock-cells = <1>; 2041 #clock-cells = <1>;
2227 }; 2042 };
2228 2043
2229 larb7: larb@14e04000 { 2044 larb7: larb@14e04000 {
2230 compatible = "mediate 2045 compatible = "mediatek,mt8195-smi-larb";
2231 reg = <0 0x14e04000 0 2046 reg = <0 0x14e04000 0 0x1000>;
2232 mediatek,larb-id = <7 2047 mediatek,larb-id = <7>;
2233 mediatek,smi = <&smi_ 2048 mediatek,smi = <&smi_common_vdo>;
2234 clocks = <&wpesys CLK 2049 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2235 <&wpesys CLK 2050 <&wpesys CLK_WPE_SMI_LARB7>;
2236 clock-names = "apb", 2051 clock-names = "apb", "smi";
2237 power-domains = <&spm 2052 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2238 }; 2053 };
2239 2054
2240 larb8: larb@14e05000 { 2055 larb8: larb@14e05000 {
2241 compatible = "mediate 2056 compatible = "mediatek,mt8195-smi-larb";
2242 reg = <0 0x14e05000 0 2057 reg = <0 0x14e05000 0 0x1000>;
2243 mediatek,larb-id = <8 2058 mediatek,larb-id = <8>;
2244 mediatek,smi = <&smi_ 2059 mediatek,smi = <&smi_common_vpp>;
2245 clocks = <&wpesys CLK 2060 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2246 <&wpesys CLK_W 2061 <&wpesys CLK_WPE_SMI_LARB8>,
2247 <&vppsys0 CLK_ 2062 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2248 clock-names = "apb", 2063 clock-names = "apb", "smi", "gals";
2249 power-domains = <&spm 2064 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2250 }; 2065 };
2251 2066
2252 vppsys1: syscon@14f00000 { 2067 vppsys1: syscon@14f00000 {
2253 compatible = "mediate 2068 compatible = "mediatek,mt8195-vppsys1", "syscon";
2254 reg = <0 0x14f00000 0 2069 reg = <0 0x14f00000 0 0x1000>;
2255 #clock-cells = <1>; 2070 #clock-cells = <1>;
2256 mediatek,gce-client-r <<
2257 }; 2071 };
2258 2072
2259 mutex@14f01000 { 2073 mutex@14f01000 {
2260 compatible = "mediate 2074 compatible = "mediatek,mt8195-vpp-mutex";
2261 reg = <0 0x14f01000 0 2075 reg = <0 0x14f01000 0 0x1000>;
2262 interrupts = <GIC_SPI 2076 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2263 mediatek,gce-client-r 2077 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2264 clocks = <&vppsys1 CL 2078 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2265 power-domains = <&spm 2079 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2266 }; 2080 };
2267 2081
2268 larb5: larb@14f02000 { 2082 larb5: larb@14f02000 {
2269 compatible = "mediate 2083 compatible = "mediatek,mt8195-smi-larb";
2270 reg = <0 0x14f02000 0 2084 reg = <0 0x14f02000 0 0x1000>;
2271 mediatek,larb-id = <5 2085 mediatek,larb-id = <5>;
2272 mediatek,smi = <&smi_ 2086 mediatek,smi = <&smi_common_vdo>;
2273 clocks = <&vppsys1 CL 2087 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2274 <&vppsys1 CLK_ 2088 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2275 <&vppsys0 CLK_ 2089 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2276 clock-names = "apb", 2090 clock-names = "apb", "smi", "gals";
2277 power-domains = <&spm 2091 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2278 }; 2092 };
2279 2093
2280 larb6: larb@14f03000 { 2094 larb6: larb@14f03000 {
2281 compatible = "mediate 2095 compatible = "mediatek,mt8195-smi-larb";
2282 reg = <0 0x14f03000 0 2096 reg = <0 0x14f03000 0 0x1000>;
2283 mediatek,larb-id = <6 2097 mediatek,larb-id = <6>;
2284 mediatek,smi = <&smi_ 2098 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2285 clocks = <&vppsys1 CL 2099 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2286 <&vppsys1 CLK_ 2100 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2287 <&vppsys0 CLK_ 2101 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2288 clock-names = "apb", 2102 clock-names = "apb", "smi", "gals";
2289 power-domains = <&spm 2103 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2290 }; 2104 };
2291 2105
2292 display@14f06000 { <<
2293 compatible = "mediate <<
2294 reg = <0 0x14f06000 0 <<
2295 mediatek,gce-client-r <<
2296 clocks = <&vppsys1 CL <<
2297 <&vppsys1 CL <<
2298 <&vppsys1 CL <<
2299 power-domains = <&spm <<
2300 }; <<
2301 <<
2302 display@14f07000 { <<
2303 compatible = "mediate <<
2304 reg = <0 0x14f07000 0 <<
2305 mediatek,gce-client-r <<
2306 clocks = <&vppsys1 CL <<
2307 }; <<
2308 <<
2309 dma-controller@14f08000 { <<
2310 compatible = "mediate <<
2311 reg = <0 0x14f08000 0 <<
2312 mediatek,gce-client-r <<
2313 mediatek,gce-events = <<
2314 <<
2315 clocks = <&vppsys1 CL <<
2316 iommus = <&iommu_vdo <<
2317 power-domains = <&spm <<
2318 #dma-cells = <1>; <<
2319 }; <<
2320 <<
2321 dma-controller@14f09000 { <<
2322 compatible = "mediate <<
2323 reg = <0 0x14f09000 0 <<
2324 mediatek,gce-client-r <<
2325 mediatek,gce-events = <<
2326 <<
2327 clocks = <&vppsys1 CL <<
2328 iommus = <&iommu_vdo <<
2329 power-domains = <&spm <<
2330 #dma-cells = <1>; <<
2331 }; <<
2332 <<
2333 dma-controller@14f0a000 { <<
2334 compatible = "mediate <<
2335 reg = <0 0x14f0a000 0 <<
2336 mediatek,gce-client-r <<
2337 mediatek,gce-events = <<
2338 <<
2339 clocks = <&vppsys1 CL <<
2340 iommus = <&iommu_vpp <<
2341 power-domains = <&spm <<
2342 #dma-cells = <1>; <<
2343 }; <<
2344 <<
2345 display@14f0b000 { <<
2346 compatible = "mediate <<
2347 reg = <0 0x14f0b000 0 <<
2348 mediatek,gce-client-r <<
2349 clocks = <&vppsys1 CL <<
2350 }; <<
2351 <<
2352 display@14f0c000 { <<
2353 compatible = "mediate <<
2354 reg = <0 0x14f0c000 0 <<
2355 mediatek,gce-client-r <<
2356 clocks = <&vppsys1 CL <<
2357 }; <<
2358 <<
2359 display@14f0d000 { <<
2360 compatible = "mediate <<
2361 reg = <0 0x14f0d000 0 <<
2362 mediatek,gce-client-r <<
2363 clocks = <&vppsys1 CL <<
2364 }; <<
2365 <<
2366 display@14f0e000 { <<
2367 compatible = "mediate <<
2368 reg = <0 0x14f0e000 0 <<
2369 mediatek,gce-client-r <<
2370 clocks = <&vppsys1 CL <<
2371 }; <<
2372 <<
2373 display@14f0f000 { <<
2374 compatible = "mediate <<
2375 reg = <0 0x14f0f000 0 <<
2376 mediatek,gce-client-r <<
2377 clocks = <&vppsys1 CL <<
2378 }; <<
2379 <<
2380 display@14f10000 { <<
2381 compatible = "mediate <<
2382 reg = <0 0x14f10000 0 <<
2383 mediatek,gce-client-r <<
2384 clocks = <&vppsys1 CL <<
2385 }; <<
2386 <<
2387 display@14f11000 { <<
2388 compatible = "mediate <<
2389 reg = <0 0x14f11000 0 <<
2390 interrupts = <GIC_SPI <<
2391 mediatek,gce-client-r <<
2392 clocks = <&vppsys1 CL <<
2393 power-domains = <&spm <<
2394 }; <<
2395 <<
2396 display@14f12000 { <<
2397 compatible = "mediate <<
2398 reg = <0 0x14f12000 0 <<
2399 interrupts = <GIC_SPI <<
2400 mediatek,gce-client-r <<
2401 clocks = <&vppsys1 CL <<
2402 power-domains = <&spm <<
2403 }; <<
2404 <<
2405 display@14f13000 { <<
2406 compatible = "mediate <<
2407 reg = <0 0x14f13000 0 <<
2408 interrupts = <GIC_SPI <<
2409 mediatek,gce-client-r <<
2410 clocks = <&vppsys1 CL <<
2411 power-domains = <&spm <<
2412 }; <<
2413 <<
2414 display@14f14000 { <<
2415 compatible = "mediate <<
2416 reg = <0 0x14f14000 0 <<
2417 mediatek,gce-client-r <<
2418 mediatek,gce-events = <<
2419 <<
2420 clocks = <&vppsys1 CL <<
2421 }; <<
2422 <<
2423 display@14f15000 { <<
2424 compatible = "mediate <<
2425 reg = <0 0x14f15000 0 <<
2426 mediatek,gce-client-r <<
2427 mediatek,gce-events = <<
2428 <<
2429 clocks = <&vppsys1 CL <<
2430 }; <<
2431 <<
2432 display@14f16000 { <<
2433 compatible = "mediate <<
2434 reg = <0 0x14f16000 0 <<
2435 mediatek,gce-client-r <<
2436 mediatek,gce-events = <<
2437 <<
2438 clocks = <&vppsys1 CL <<
2439 }; <<
2440 <<
2441 display@14f17000 { <<
2442 compatible = "mediate <<
2443 reg = <0 0x14f17000 0 <<
2444 mediatek,gce-client-r <<
2445 clocks = <&vppsys1 CL <<
2446 }; <<
2447 <<
2448 display@14f18000 { <<
2449 compatible = "mediate <<
2450 reg = <0 0x14f18000 0 <<
2451 mediatek,gce-client-r <<
2452 clocks = <&vppsys1 CL <<
2453 }; <<
2454 <<
2455 display@14f19000 { <<
2456 compatible = "mediate <<
2457 reg = <0 0x14f19000 0 <<
2458 mediatek,gce-client-r <<
2459 clocks = <&vppsys1 CL <<
2460 }; <<
2461 <<
2462 display@14f1a000 { <<
2463 compatible = "mediate <<
2464 reg = <0 0x14f1a000 0 <<
2465 mediatek,gce-client-r <<
2466 clocks = <&vppsys1 CL <<
2467 power-domains = <&spm <<
2468 }; <<
2469 <<
2470 display@14f1b000 { <<
2471 compatible = "mediate <<
2472 reg = <0 0x14f1b000 0 <<
2473 mediatek,gce-client-r <<
2474 clocks = <&vppsys1 CL <<
2475 power-domains = <&spm <<
2476 }; <<
2477 <<
2478 display@14f1c000 { <<
2479 compatible = "mediate <<
2480 reg = <0 0x14f1c000 0 <<
2481 interrupts = <GIC_SPI <<
2482 mediatek,gce-client-r <<
2483 clocks = <&vppsys1 CL <<
2484 power-domains = <&spm <<
2485 }; <<
2486 <<
2487 display@14f1d000 { <<
2488 compatible = "mediate <<
2489 reg = <0 0x14f1d000 0 <<
2490 mediatek,gce-client-r <<
2491 interrupts = <GIC_SPI <<
2492 clocks = <&vppsys1 CL <<
2493 power-domains = <&spm <<
2494 }; <<
2495 <<
2496 display@14f1e000 { <<
2497 compatible = "mediate <<
2498 reg = <0 0x14f1e000 0 <<
2499 interrupts = <GIC_SPI <<
2500 mediatek,gce-client-r <<
2501 clocks = <&vppsys1 CL <<
2502 power-domains = <&spm <<
2503 }; <<
2504 <<
2505 display@14f1f000 { <<
2506 compatible = "mediate <<
2507 reg = <0 0x14f1f000 0 <<
2508 interrupts = <GIC_SPI <<
2509 mediatek,gce-client-r <<
2510 clocks = <&vppsys1 CL <<
2511 power-domains = <&spm <<
2512 iommus = <&iommu_vdo <<
2513 }; <<
2514 <<
2515 display@14f20000 { <<
2516 compatible = "mediate <<
2517 reg = <0 0x14f20000 0 <<
2518 mediatek,gce-client-r <<
2519 clocks = <&vppsys1 CL <<
2520 power-domains = <&spm <<
2521 }; <<
2522 <<
2523 display@14f21000 { <<
2524 compatible = "mediate <<
2525 reg = <0 0x14f21000 0 <<
2526 mediatek,gce-client-r <<
2527 clocks = <&vppsys1 CL <<
2528 power-domains = <&spm <<
2529 }; <<
2530 <<
2531 display@14f22000 { <<
2532 compatible = "mediate <<
2533 reg = <0 0x14f22000 0 <<
2534 mediatek,gce-client-r <<
2535 clocks = <&vppsys1 CL <<
2536 power-domains = <&spm <<
2537 }; <<
2538 <<
2539 dma-controller@14f23000 { <<
2540 compatible = "mediate <<
2541 reg = <0 0x14f23000 0 <<
2542 mediatek,gce-client-r <<
2543 mediatek,gce-events = <<
2544 <<
2545 clocks = <&vppsys1 CL <<
2546 iommus = <&iommu_vdo <<
2547 power-domains = <&spm <<
2548 #dma-cells = <1>; <<
2549 }; <<
2550 <<
2551 dma-controller@14f24000 { <<
2552 compatible = "mediate <<
2553 reg = <0 0x14f24000 0 <<
2554 mediatek,gce-client-r <<
2555 mediatek,gce-events = <<
2556 <CMDQ <<
2557 clocks = <&vppsys1 CL <<
2558 iommus = <&iommu_vdo <<
2559 power-domains = <&spm <<
2560 #dma-cells = <1>; <<
2561 }; <<
2562 <<
2563 dma-controller@14f25000 { <<
2564 compatible = "mediate <<
2565 reg = <0 0x14f25000 0 <<
2566 mediatek,gce-client-r <<
2567 mediatek,gce-events = <<
2568 <CMDQ <<
2569 clocks = <&vppsys1 CL <<
2570 iommus = <&iommu_vpp <<
2571 power-domains = <&spm <<
2572 #dma-cells = <1>; <<
2573 }; <<
2574 <<
2575 imgsys: clock-controller@1500 2106 imgsys: clock-controller@15000000 {
2576 compatible = "mediate 2107 compatible = "mediatek,mt8195-imgsys";
2577 reg = <0 0x15000000 0 2108 reg = <0 0x15000000 0 0x1000>;
2578 #clock-cells = <1>; 2109 #clock-cells = <1>;
2579 }; 2110 };
2580 2111
2581 larb9: larb@15001000 { 2112 larb9: larb@15001000 {
2582 compatible = "mediate 2113 compatible = "mediatek,mt8195-smi-larb";
2583 reg = <0 0x15001000 0 2114 reg = <0 0x15001000 0 0x1000>;
2584 mediatek,larb-id = <9 2115 mediatek,larb-id = <9>;
2585 mediatek,smi = <&smi_ 2116 mediatek,smi = <&smi_sub_common_img1_3x1>;
2586 clocks = <&imgsys CLK 2117 clocks = <&imgsys CLK_IMG_LARB9>,
2587 <&imgsys CLK 2118 <&imgsys CLK_IMG_LARB9>,
2588 <&imgsys CLK 2119 <&imgsys CLK_IMG_GALS>;
2589 clock-names = "apb", 2120 clock-names = "apb", "smi", "gals";
2590 power-domains = <&spm 2121 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2591 }; 2122 };
2592 2123
2593 smi_sub_common_img0_3x1: smi@ 2124 smi_sub_common_img0_3x1: smi@15002000 {
2594 compatible = "mediate 2125 compatible = "mediatek,mt8195-smi-sub-common";
2595 reg = <0 0x15002000 0 2126 reg = <0 0x15002000 0 0x1000>;
2596 clocks = <&imgsys CLK 2127 clocks = <&imgsys CLK_IMG_IPE>,
2597 <&imgsys CLK 2128 <&imgsys CLK_IMG_IPE>,
2598 <&vppsys0 CL 2129 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2599 clock-names = "apb", 2130 clock-names = "apb", "smi", "gals0";
2600 mediatek,smi = <&smi_ 2131 mediatek,smi = <&smi_common_vpp>;
2601 power-domains = <&spm 2132 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2602 }; 2133 };
2603 2134
2604 smi_sub_common_img1_3x1: smi@ 2135 smi_sub_common_img1_3x1: smi@15003000 {
2605 compatible = "mediate 2136 compatible = "mediatek,mt8195-smi-sub-common";
2606 reg = <0 0x15003000 0 2137 reg = <0 0x15003000 0 0x1000>;
2607 clocks = <&imgsys CLK 2138 clocks = <&imgsys CLK_IMG_LARB9>,
2608 <&imgsys CLK 2139 <&imgsys CLK_IMG_LARB9>,
2609 <&imgsys CLK 2140 <&imgsys CLK_IMG_GALS>;
2610 clock-names = "apb", 2141 clock-names = "apb", "smi", "gals0";
2611 mediatek,smi = <&smi_ 2142 mediatek,smi = <&smi_common_vdo>;
2612 power-domains = <&spm 2143 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2613 }; 2144 };
2614 2145
2615 imgsys1_dip_top: clock-contro 2146 imgsys1_dip_top: clock-controller@15110000 {
2616 compatible = "mediate 2147 compatible = "mediatek,mt8195-imgsys1_dip_top";
2617 reg = <0 0x15110000 0 2148 reg = <0 0x15110000 0 0x1000>;
2618 #clock-cells = <1>; 2149 #clock-cells = <1>;
2619 }; 2150 };
2620 2151
2621 larb10: larb@15120000 { 2152 larb10: larb@15120000 {
2622 compatible = "mediate 2153 compatible = "mediatek,mt8195-smi-larb";
2623 reg = <0 0x15120000 0 2154 reg = <0 0x15120000 0 0x1000>;
2624 mediatek,larb-id = <1 2155 mediatek,larb-id = <10>;
2625 mediatek,smi = <&smi_ 2156 mediatek,smi = <&smi_sub_common_img1_3x1>;
2626 clocks = <&imgsys CLK 2157 clocks = <&imgsys CLK_IMG_DIP0>,
2627 <&imgsys1_dip_ 2158 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2628 clock-names = "apb", 2159 clock-names = "apb", "smi";
2629 power-domains = <&spm 2160 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2630 }; 2161 };
2631 2162
2632 imgsys1_dip_nr: clock-control 2163 imgsys1_dip_nr: clock-controller@15130000 {
2633 compatible = "mediate 2164 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2634 reg = <0 0x15130000 0 2165 reg = <0 0x15130000 0 0x1000>;
2635 #clock-cells = <1>; 2166 #clock-cells = <1>;
2636 }; 2167 };
2637 2168
2638 imgsys1_wpe: clock-controller 2169 imgsys1_wpe: clock-controller@15220000 {
2639 compatible = "mediate 2170 compatible = "mediatek,mt8195-imgsys1_wpe";
2640 reg = <0 0x15220000 0 2171 reg = <0 0x15220000 0 0x1000>;
2641 #clock-cells = <1>; 2172 #clock-cells = <1>;
2642 }; 2173 };
2643 2174
2644 larb11: larb@15230000 { 2175 larb11: larb@15230000 {
2645 compatible = "mediate 2176 compatible = "mediatek,mt8195-smi-larb";
2646 reg = <0 0x15230000 0 2177 reg = <0 0x15230000 0 0x1000>;
2647 mediatek,larb-id = <1 2178 mediatek,larb-id = <11>;
2648 mediatek,smi = <&smi_ 2179 mediatek,smi = <&smi_sub_common_img1_3x1>;
2649 clocks = <&imgsys CLK 2180 clocks = <&imgsys CLK_IMG_WPE0>,
2650 <&imgsys1_wpe 2181 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2651 clock-names = "apb", 2182 clock-names = "apb", "smi";
2652 power-domains = <&spm 2183 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2653 }; 2184 };
2654 2185
2655 ipesys: clock-controller@1533 2186 ipesys: clock-controller@15330000 {
2656 compatible = "mediate 2187 compatible = "mediatek,mt8195-ipesys";
2657 reg = <0 0x15330000 0 2188 reg = <0 0x15330000 0 0x1000>;
2658 #clock-cells = <1>; 2189 #clock-cells = <1>;
2659 }; 2190 };
2660 2191
2661 larb12: larb@15340000 { 2192 larb12: larb@15340000 {
2662 compatible = "mediate 2193 compatible = "mediatek,mt8195-smi-larb";
2663 reg = <0 0x15340000 0 2194 reg = <0 0x15340000 0 0x1000>;
2664 mediatek,larb-id = <1 2195 mediatek,larb-id = <12>;
2665 mediatek,smi = <&smi_ 2196 mediatek,smi = <&smi_sub_common_img0_3x1>;
2666 clocks = <&ipesys CLK 2197 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2667 <&ipesys CLK 2198 <&ipesys CLK_IPE_SMI_LARB12>;
2668 clock-names = "apb", 2199 clock-names = "apb", "smi";
2669 power-domains = <&spm 2200 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2670 }; 2201 };
2671 2202
2672 camsys: clock-controller@1600 2203 camsys: clock-controller@16000000 {
2673 compatible = "mediate 2204 compatible = "mediatek,mt8195-camsys";
2674 reg = <0 0x16000000 0 2205 reg = <0 0x16000000 0 0x1000>;
2675 #clock-cells = <1>; 2206 #clock-cells = <1>;
2676 }; 2207 };
2677 2208
2678 larb13: larb@16001000 { 2209 larb13: larb@16001000 {
2679 compatible = "mediate 2210 compatible = "mediatek,mt8195-smi-larb";
2680 reg = <0 0x16001000 0 2211 reg = <0 0x16001000 0 0x1000>;
2681 mediatek,larb-id = <1 2212 mediatek,larb-id = <13>;
2682 mediatek,smi = <&smi_ 2213 mediatek,smi = <&smi_sub_common_cam_4x1>;
2683 clocks = <&camsys CLK 2214 clocks = <&camsys CLK_CAM_LARB13>,
2684 <&camsys CLK_C 2215 <&camsys CLK_CAM_LARB13>,
2685 <&camsys CLK_C 2216 <&camsys CLK_CAM_CAM2MM0_GALS>;
2686 clock-names = "apb", 2217 clock-names = "apb", "smi", "gals";
2687 power-domains = <&spm 2218 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688 }; 2219 };
2689 2220
2690 larb14: larb@16002000 { 2221 larb14: larb@16002000 {
2691 compatible = "mediate 2222 compatible = "mediatek,mt8195-smi-larb";
2692 reg = <0 0x16002000 0 2223 reg = <0 0x16002000 0 0x1000>;
2693 mediatek,larb-id = <1 2224 mediatek,larb-id = <14>;
2694 mediatek,smi = <&smi_ 2225 mediatek,smi = <&smi_sub_common_cam_7x1>;
2695 clocks = <&camsys CLK 2226 clocks = <&camsys CLK_CAM_LARB14>,
2696 <&camsys CLK 2227 <&camsys CLK_CAM_LARB14>;
2697 clock-names = "apb", 2228 clock-names = "apb", "smi";
2698 power-domains = <&spm 2229 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2699 }; 2230 };
2700 2231
2701 smi_sub_common_cam_4x1: smi@1 2232 smi_sub_common_cam_4x1: smi@16004000 {
2702 compatible = "mediate 2233 compatible = "mediatek,mt8195-smi-sub-common";
2703 reg = <0 0x16004000 0 2234 reg = <0 0x16004000 0 0x1000>;
2704 clocks = <&camsys CLK 2235 clocks = <&camsys CLK_CAM_LARB13>,
2705 <&camsys CLK 2236 <&camsys CLK_CAM_LARB13>,
2706 <&camsys CLK 2237 <&camsys CLK_CAM_CAM2MM0_GALS>;
2707 clock-names = "apb", 2238 clock-names = "apb", "smi", "gals0";
2708 mediatek,smi = <&smi_ 2239 mediatek,smi = <&smi_common_vdo>;
2709 power-domains = <&spm 2240 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2710 }; 2241 };
2711 2242
2712 smi_sub_common_cam_7x1: smi@1 2243 smi_sub_common_cam_7x1: smi@16005000 {
2713 compatible = "mediate 2244 compatible = "mediatek,mt8195-smi-sub-common";
2714 reg = <0 0x16005000 0 2245 reg = <0 0x16005000 0 0x1000>;
2715 clocks = <&camsys CLK 2246 clocks = <&camsys CLK_CAM_LARB14>,
2716 <&camsys CLK 2247 <&camsys CLK_CAM_CAM2MM1_GALS>,
2717 <&vppsys0 CL 2248 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2718 clock-names = "apb", 2249 clock-names = "apb", "smi", "gals0";
2719 mediatek,smi = <&smi_ 2250 mediatek,smi = <&smi_common_vpp>;
2720 power-domains = <&spm 2251 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2721 }; 2252 };
2722 2253
2723 larb16: larb@16012000 { 2254 larb16: larb@16012000 {
2724 compatible = "mediate 2255 compatible = "mediatek,mt8195-smi-larb";
2725 reg = <0 0x16012000 0 2256 reg = <0 0x16012000 0 0x1000>;
2726 mediatek,larb-id = <1 2257 mediatek,larb-id = <16>;
2727 mediatek,smi = <&smi_ 2258 mediatek,smi = <&smi_sub_common_cam_7x1>;
2728 clocks = <&camsys_raw 2259 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2729 <&camsys_raw 2260 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2730 clock-names = "apb", 2261 clock-names = "apb", "smi";
2731 power-domains = <&spm 2262 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2732 }; 2263 };
2733 2264
2734 larb17: larb@16013000 { 2265 larb17: larb@16013000 {
2735 compatible = "mediate 2266 compatible = "mediatek,mt8195-smi-larb";
2736 reg = <0 0x16013000 0 2267 reg = <0 0x16013000 0 0x1000>;
2737 mediatek,larb-id = <1 2268 mediatek,larb-id = <17>;
2738 mediatek,smi = <&smi_ 2269 mediatek,smi = <&smi_sub_common_cam_4x1>;
2739 clocks = <&camsys_yuv 2270 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2740 <&camsys_yuv 2271 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2741 clock-names = "apb", 2272 clock-names = "apb", "smi";
2742 power-domains = <&spm 2273 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2743 }; 2274 };
2744 2275
2745 larb27: larb@16014000 { 2276 larb27: larb@16014000 {
2746 compatible = "mediate 2277 compatible = "mediatek,mt8195-smi-larb";
2747 reg = <0 0x16014000 0 2278 reg = <0 0x16014000 0 0x1000>;
2748 mediatek,larb-id = <2 2279 mediatek,larb-id = <27>;
2749 mediatek,smi = <&smi_ 2280 mediatek,smi = <&smi_sub_common_cam_7x1>;
2750 clocks = <&camsys_raw 2281 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2751 <&camsys_raw 2282 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2752 clock-names = "apb", 2283 clock-names = "apb", "smi";
2753 power-domains = <&spm 2284 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2754 }; 2285 };
2755 2286
2756 larb28: larb@16015000 { 2287 larb28: larb@16015000 {
2757 compatible = "mediate 2288 compatible = "mediatek,mt8195-smi-larb";
2758 reg = <0 0x16015000 0 2289 reg = <0 0x16015000 0 0x1000>;
2759 mediatek,larb-id = <2 2290 mediatek,larb-id = <28>;
2760 mediatek,smi = <&smi_ 2291 mediatek,smi = <&smi_sub_common_cam_4x1>;
2761 clocks = <&camsys_yuv 2292 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2762 <&camsys_yuv 2293 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2763 clock-names = "apb", 2294 clock-names = "apb", "smi";
2764 power-domains = <&spm 2295 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2765 }; 2296 };
2766 2297
2767 camsys_rawa: clock-controller 2298 camsys_rawa: clock-controller@1604f000 {
2768 compatible = "mediate 2299 compatible = "mediatek,mt8195-camsys_rawa";
2769 reg = <0 0x1604f000 0 2300 reg = <0 0x1604f000 0 0x1000>;
2770 #clock-cells = <1>; 2301 #clock-cells = <1>;
2771 }; 2302 };
2772 2303
2773 camsys_yuva: clock-controller 2304 camsys_yuva: clock-controller@1606f000 {
2774 compatible = "mediate 2305 compatible = "mediatek,mt8195-camsys_yuva";
2775 reg = <0 0x1606f000 0 2306 reg = <0 0x1606f000 0 0x1000>;
2776 #clock-cells = <1>; 2307 #clock-cells = <1>;
2777 }; 2308 };
2778 2309
2779 camsys_rawb: clock-controller 2310 camsys_rawb: clock-controller@1608f000 {
2780 compatible = "mediate 2311 compatible = "mediatek,mt8195-camsys_rawb";
2781 reg = <0 0x1608f000 0 2312 reg = <0 0x1608f000 0 0x1000>;
2782 #clock-cells = <1>; 2313 #clock-cells = <1>;
2783 }; 2314 };
2784 2315
2785 camsys_yuvb: clock-controller 2316 camsys_yuvb: clock-controller@160af000 {
2786 compatible = "mediate 2317 compatible = "mediatek,mt8195-camsys_yuvb";
2787 reg = <0 0x160af000 0 2318 reg = <0 0x160af000 0 0x1000>;
2788 #clock-cells = <1>; 2319 #clock-cells = <1>;
2789 }; 2320 };
2790 2321
2791 camsys_mraw: clock-controller 2322 camsys_mraw: clock-controller@16140000 {
2792 compatible = "mediate 2323 compatible = "mediatek,mt8195-camsys_mraw";
2793 reg = <0 0x16140000 0 2324 reg = <0 0x16140000 0 0x1000>;
2794 #clock-cells = <1>; 2325 #clock-cells = <1>;
2795 }; 2326 };
2796 2327
2797 larb25: larb@16141000 { 2328 larb25: larb@16141000 {
2798 compatible = "mediate 2329 compatible = "mediatek,mt8195-smi-larb";
2799 reg = <0 0x16141000 0 2330 reg = <0 0x16141000 0 0x1000>;
2800 mediatek,larb-id = <2 2331 mediatek,larb-id = <25>;
2801 mediatek,smi = <&smi_ 2332 mediatek,smi = <&smi_sub_common_cam_4x1>;
2802 clocks = <&camsys CLK 2333 clocks = <&camsys CLK_CAM_LARB13>,
2803 <&camsys_mra 2334 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2804 <&camsys CLK 2335 <&camsys CLK_CAM_CAM2MM0_GALS>;
2805 clock-names = "apb", 2336 clock-names = "apb", "smi", "gals";
2806 power-domains = <&spm 2337 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2807 }; 2338 };
2808 2339
2809 larb26: larb@16142000 { 2340 larb26: larb@16142000 {
2810 compatible = "mediate 2341 compatible = "mediatek,mt8195-smi-larb";
2811 reg = <0 0x16142000 0 2342 reg = <0 0x16142000 0 0x1000>;
2812 mediatek,larb-id = <2 2343 mediatek,larb-id = <26>;
2813 mediatek,smi = <&smi_ 2344 mediatek,smi = <&smi_sub_common_cam_7x1>;
2814 clocks = <&camsys_mra 2345 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2815 <&camsys_mra 2346 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2816 clock-names = "apb", 2347 clock-names = "apb", "smi";
2817 power-domains = <&spm 2348 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2818 2349
2819 }; 2350 };
2820 2351
2821 ccusys: clock-controller@1720 2352 ccusys: clock-controller@17200000 {
2822 compatible = "mediate 2353 compatible = "mediatek,mt8195-ccusys";
2823 reg = <0 0x17200000 0 2354 reg = <0 0x17200000 0 0x1000>;
2824 #clock-cells = <1>; 2355 #clock-cells = <1>;
2825 }; 2356 };
2826 2357
2827 larb18: larb@17201000 { 2358 larb18: larb@17201000 {
2828 compatible = "mediate 2359 compatible = "mediatek,mt8195-smi-larb";
2829 reg = <0 0x17201000 0 2360 reg = <0 0x17201000 0 0x1000>;
2830 mediatek,larb-id = <1 2361 mediatek,larb-id = <18>;
2831 mediatek,smi = <&smi_ 2362 mediatek,smi = <&smi_sub_common_cam_7x1>;
2832 clocks = <&ccusys CLK 2363 clocks = <&ccusys CLK_CCU_LARB18>,
2833 <&ccusys CLK 2364 <&ccusys CLK_CCU_LARB18>;
2834 clock-names = "apb", 2365 clock-names = "apb", "smi";
2835 power-domains = <&spm 2366 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2836 }; 2367 };
2837 2368
2838 video-codec@18000000 { <<
2839 compatible = "mediate <<
2840 mediatek,scp = <&scp> <<
2841 iommus = <&iommu_vdo <<
2842 #address-cells = <2>; <<
2843 #size-cells = <2>; <<
2844 reg = <0 0x18000000 0 <<
2845 <0 0x18004000 0 <<
2846 ranges = <0 0 0 0x180 <<
2847 <<
2848 video-codec@2000 { <<
2849 compatible = <<
2850 reg = <0 0x20 <<
2851 iommus = <&io <<
2852 <&io <<
2853 clocks = <&to <<
2854 <&vd <<
2855 <&vd <<
2856 <&to <<
2857 clock-names = <<
2858 assigned-cloc <<
2859 assigned-cloc <<
2860 power-domains <<
2861 }; <<
2862 <<
2863 video-codec@10000 { <<
2864 compatible = <<
2865 reg = <0 0x10 <<
2866 interrupts = <<
2867 iommus = <&io <<
2868 <&io <<
2869 <&io <<
2870 <&io <<
2871 <&io <<
2872 <&io <<
2873 clocks = <&to <<
2874 <&vd <<
2875 <&vd <<
2876 <&to <<
2877 clock-names = <<
2878 assigned-cloc <<
2879 assigned-cloc <<
2880 power-domains <<
2881 }; <<
2882 <<
2883 video-codec@25000 { <<
2884 compatible = <<
2885 reg = <0 0x25 <<
2886 interrupts = <<
2887 iommus = <&io <<
2888 <&io <<
2889 <&io <<
2890 <&io <<
2891 <&io <<
2892 <&io <<
2893 <&io <<
2894 <&io <<
2895 <&io <<
2896 <&io <<
2897 clocks = <&to <<
2898 <&vd <<
2899 <&vd <<
2900 <&to <<
2901 clock-names = <<
2902 assigned-cloc <<
2903 assigned-cloc <<
2904 power-domains <<
2905 }; <<
2906 }; <<
2907 <<
2908 larb24: larb@1800d000 { 2369 larb24: larb@1800d000 {
2909 compatible = "mediate 2370 compatible = "mediatek,mt8195-smi-larb";
2910 reg = <0 0x1800d000 0 2371 reg = <0 0x1800d000 0 0x1000>;
2911 mediatek,larb-id = <2 2372 mediatek,larb-id = <24>;
2912 mediatek,smi = <&smi_ 2373 mediatek,smi = <&smi_common_vdo>;
2913 clocks = <&vdecsys_so 2374 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2914 <&vdecsys_so 2375 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2915 clock-names = "apb", 2376 clock-names = "apb", "smi";
2916 power-domains = <&spm 2377 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2917 }; 2378 };
2918 2379
2919 larb23: larb@1800e000 { 2380 larb23: larb@1800e000 {
2920 compatible = "mediate 2381 compatible = "mediatek,mt8195-smi-larb";
2921 reg = <0 0x1800e000 0 2382 reg = <0 0x1800e000 0 0x1000>;
2922 mediatek,larb-id = <2 2383 mediatek,larb-id = <23>;
2923 mediatek,smi = <&smi_ 2384 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2924 clocks = <&vppsys0 CL 2385 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2925 <&vdecsys_so 2386 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2926 clock-names = "apb", 2387 clock-names = "apb", "smi";
2927 power-domains = <&spm 2388 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2928 }; 2389 };
2929 2390
2930 vdecsys_soc: clock-controller 2391 vdecsys_soc: clock-controller@1800f000 {
2931 compatible = "mediate 2392 compatible = "mediatek,mt8195-vdecsys_soc";
2932 reg = <0 0x1800f000 0 2393 reg = <0 0x1800f000 0 0x1000>;
2933 #clock-cells = <1>; 2394 #clock-cells = <1>;
2934 }; 2395 };
2935 2396
2936 larb21: larb@1802e000 { 2397 larb21: larb@1802e000 {
2937 compatible = "mediate 2398 compatible = "mediatek,mt8195-smi-larb";
2938 reg = <0 0x1802e000 0 2399 reg = <0 0x1802e000 0 0x1000>;
2939 mediatek,larb-id = <2 2400 mediatek,larb-id = <21>;
2940 mediatek,smi = <&smi_ 2401 mediatek,smi = <&smi_common_vdo>;
2941 clocks = <&vdecsys CL 2402 clocks = <&vdecsys CLK_VDEC_LARB1>,
2942 <&vdecsys CL 2403 <&vdecsys CLK_VDEC_LARB1>;
2943 clock-names = "apb", 2404 clock-names = "apb", "smi";
2944 power-domains = <&spm 2405 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2945 }; 2406 };
2946 2407
2947 vdecsys: clock-controller@180 2408 vdecsys: clock-controller@1802f000 {
2948 compatible = "mediate 2409 compatible = "mediatek,mt8195-vdecsys";
2949 reg = <0 0x1802f000 0 2410 reg = <0 0x1802f000 0 0x1000>;
2950 #clock-cells = <1>; 2411 #clock-cells = <1>;
2951 }; 2412 };
2952 2413
2953 larb22: larb@1803e000 { 2414 larb22: larb@1803e000 {
2954 compatible = "mediate 2415 compatible = "mediatek,mt8195-smi-larb";
2955 reg = <0 0x1803e000 0 2416 reg = <0 0x1803e000 0 0x1000>;
2956 mediatek,larb-id = <2 2417 mediatek,larb-id = <22>;
2957 mediatek,smi = <&smi_ 2418 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2958 clocks = <&vppsys0 CL 2419 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2959 <&vdecsys_co 2420 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2960 clock-names = "apb", 2421 clock-names = "apb", "smi";
2961 power-domains = <&spm 2422 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2962 }; 2423 };
2963 2424
2964 vdecsys_core1: clock-controll 2425 vdecsys_core1: clock-controller@1803f000 {
2965 compatible = "mediate 2426 compatible = "mediatek,mt8195-vdecsys_core1";
2966 reg = <0 0x1803f000 0 2427 reg = <0 0x1803f000 0 0x1000>;
2967 #clock-cells = <1>; 2428 #clock-cells = <1>;
2968 }; 2429 };
2969 2430
2970 apusys_pll: clock-controller@ 2431 apusys_pll: clock-controller@190f3000 {
2971 compatible = "mediate 2432 compatible = "mediatek,mt8195-apusys_pll";
2972 reg = <0 0x190f3000 0 2433 reg = <0 0x190f3000 0 0x1000>;
2973 #clock-cells = <1>; 2434 #clock-cells = <1>;
2974 }; 2435 };
2975 2436
2976 vencsys: clock-controller@1a0 2437 vencsys: clock-controller@1a000000 {
2977 compatible = "mediate 2438 compatible = "mediatek,mt8195-vencsys";
2978 reg = <0 0x1a000000 0 2439 reg = <0 0x1a000000 0 0x1000>;
2979 #clock-cells = <1>; 2440 #clock-cells = <1>;
2980 }; 2441 };
2981 2442
2982 larb19: larb@1a010000 { 2443 larb19: larb@1a010000 {
2983 compatible = "mediate 2444 compatible = "mediatek,mt8195-smi-larb";
2984 reg = <0 0x1a010000 0 2445 reg = <0 0x1a010000 0 0x1000>;
2985 mediatek,larb-id = <1 2446 mediatek,larb-id = <19>;
2986 mediatek,smi = <&smi_ 2447 mediatek,smi = <&smi_common_vdo>;
2987 clocks = <&vencsys CL 2448 clocks = <&vencsys CLK_VENC_VENC>,
2988 <&vencsys CL 2449 <&vencsys CLK_VENC_GALS>;
2989 clock-names = "apb", 2450 clock-names = "apb", "smi";
2990 power-domains = <&spm 2451 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2991 }; 2452 };
2992 2453
2993 venc: video-codec@1a020000 { 2454 venc: video-codec@1a020000 {
2994 compatible = "mediate 2455 compatible = "mediatek,mt8195-vcodec-enc";
2995 reg = <0 0x1a020000 0 2456 reg = <0 0x1a020000 0 0x10000>;
2996 iommus = <&iommu_vdo 2457 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2997 <&iommu_vdo 2458 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2998 <&iommu_vdo 2459 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2999 <&iommu_vdo 2460 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
3000 <&iommu_vdo 2461 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
3001 <&iommu_vdo 2462 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
3002 <&iommu_vdo 2463 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
3003 <&iommu_vdo 2464 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
3004 <&iommu_vdo 2465 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
3005 interrupts = <GIC_SPI 2466 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
3006 mediatek,scp = <&scp> 2467 mediatek,scp = <&scp>;
3007 clocks = <&vencsys CL 2468 clocks = <&vencsys CLK_VENC_VENC>;
3008 clock-names = "venc_s 2469 clock-names = "venc_sel";
3009 assigned-clocks = <&t 2470 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3010 assigned-clock-parent 2471 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3011 power-domains = <&spm 2472 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3012 #address-cells = <2>; 2473 #address-cells = <2>;
3013 #size-cells = <2>; 2474 #size-cells = <2>;
3014 }; 2475 };
3015 2476
3016 jpgdec-master { 2477 jpgdec-master {
3017 compatible = "mediate 2478 compatible = "mediatek,mt8195-jpgdec";
3018 power-domains = <&spm 2479 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3019 iommus = <&iommu_vdo 2480 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3020 <&iommu_vdo 2481 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3021 <&iommu_vdo 2482 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3022 <&iommu_vdo 2483 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3023 <&iommu_vdo 2484 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3024 <&iommu_vdo 2485 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3025 #address-cells = <2>; 2486 #address-cells = <2>;
3026 #size-cells = <2>; 2487 #size-cells = <2>;
3027 ranges; 2488 ranges;
3028 2489
3029 jpgdec@1a040000 { 2490 jpgdec@1a040000 {
3030 compatible = 2491 compatible = "mediatek,mt8195-jpgdec-hw";
3031 reg = <0 0x1a 2492 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3032 iommus = <&io 2493 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3033 <&io 2494 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3034 <&io 2495 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3035 <&io 2496 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3036 <&io 2497 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3037 <&io 2498 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3038 interrupts = 2499 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3039 clocks = <&ve 2500 clocks = <&vencsys CLK_VENC_JPGDEC>;
3040 clock-names = 2501 clock-names = "jpgdec";
3041 power-domains 2502 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3042 }; 2503 };
3043 2504
3044 jpgdec@1a050000 { 2505 jpgdec@1a050000 {
3045 compatible = 2506 compatible = "mediatek,mt8195-jpgdec-hw";
3046 reg = <0 0x1a 2507 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3047 iommus = <&io 2508 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3048 <&io 2509 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3049 <&io 2510 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3050 <&io 2511 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3051 <&io 2512 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3052 <&io 2513 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3053 interrupts = 2514 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3054 clocks = <&ve 2515 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3055 clock-names = 2516 clock-names = "jpgdec";
3056 power-domains 2517 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3057 }; 2518 };
3058 2519
3059 jpgdec@1b040000 { 2520 jpgdec@1b040000 {
3060 compatible = 2521 compatible = "mediatek,mt8195-jpgdec-hw";
3061 reg = <0 0x1b 2522 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3062 iommus = <&io 2523 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3063 <&io 2524 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3064 <&io 2525 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3065 <&io 2526 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3066 <&io 2527 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3067 <&io 2528 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3068 interrupts = 2529 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3069 clocks = <&ve 2530 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3070 clock-names = 2531 clock-names = "jpgdec";
3071 power-domains 2532 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3072 }; 2533 };
3073 }; 2534 };
3074 2535
3075 vencsys_core1: clock-controll 2536 vencsys_core1: clock-controller@1b000000 {
3076 compatible = "mediate 2537 compatible = "mediatek,mt8195-vencsys_core1";
3077 reg = <0 0x1b000000 0 2538 reg = <0 0x1b000000 0 0x1000>;
3078 #clock-cells = <1>; 2539 #clock-cells = <1>;
3079 }; 2540 };
3080 2541
3081 vdosys0: syscon@1c01a000 { 2542 vdosys0: syscon@1c01a000 {
3082 compatible = "mediate 2543 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3083 reg = <0 0x1c01a000 0 2544 reg = <0 0x1c01a000 0 0x1000>;
3084 mboxes = <&gce0 0 CMD 2545 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3085 #clock-cells = <1>; 2546 #clock-cells = <1>;
3086 mediatek,gce-client-r <<
3087 }; 2547 };
3088 2548
3089 2549
3090 jpgenc-master { 2550 jpgenc-master {
3091 compatible = "mediate 2551 compatible = "mediatek,mt8195-jpgenc";
3092 power-domains = <&spm 2552 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3093 iommus = <&iommu_vpp 2553 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3094 <&iom 2554 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3095 <&iom 2555 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3096 <&iom 2556 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3097 #address-cells = <2>; 2557 #address-cells = <2>;
3098 #size-cells = <2>; 2558 #size-cells = <2>;
3099 ranges; 2559 ranges;
3100 2560
3101 jpgenc@1a030000 { 2561 jpgenc@1a030000 {
3102 compatible = 2562 compatible = "mediatek,mt8195-jpgenc-hw";
3103 reg = <0 0x1a 2563 reg = <0 0x1a030000 0 0x10000>;
3104 iommus = <&io 2564 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3105 2565 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3106 2566 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3107 2567 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3108 interrupts = 2568 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3109 clocks = <&ve 2569 clocks = <&vencsys CLK_VENC_JPGENC>;
3110 clock-names = 2570 clock-names = "jpgenc";
3111 power-domains 2571 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3112 }; 2572 };
3113 2573
3114 jpgenc@1b030000 { 2574 jpgenc@1b030000 {
3115 compatible = 2575 compatible = "mediatek,mt8195-jpgenc-hw";
3116 reg = <0 0x1b 2576 reg = <0 0x1b030000 0 0x10000>;
3117 iommus = <&io 2577 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3118 2578 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3119 2579 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3120 2580 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3121 interrupts = 2581 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3122 clocks = <&ve 2582 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3123 clock-names = 2583 clock-names = "jpgenc";
3124 power-domains 2584 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3125 }; 2585 };
3126 }; 2586 };
3127 2587
3128 larb20: larb@1b010000 { 2588 larb20: larb@1b010000 {
3129 compatible = "mediate 2589 compatible = "mediatek,mt8195-smi-larb";
3130 reg = <0 0x1b010000 0 2590 reg = <0 0x1b010000 0 0x1000>;
3131 mediatek,larb-id = <2 2591 mediatek,larb-id = <20>;
3132 mediatek,smi = <&smi_ 2592 mediatek,smi = <&smi_common_vpp>;
3133 clocks = <&vencsys_co !! 2593 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
3134 <&vencsys_co 2594 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3135 <&vppsys0 CL 2595 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3136 clock-names = "apb", 2596 clock-names = "apb", "smi", "gals";
3137 power-domains = <&spm 2597 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3138 }; 2598 };
3139 2599
3140 ovl0: ovl@1c000000 { 2600 ovl0: ovl@1c000000 {
3141 compatible = "mediate 2601 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3142 reg = <0 0x1c000000 0 2602 reg = <0 0x1c000000 0 0x1000>;
3143 interrupts = <GIC_SPI 2603 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3144 power-domains = <&spm 2604 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3145 clocks = <&vdosys0 CL 2605 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3146 iommus = <&iommu_vdo 2606 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3147 mediatek,gce-client-r 2607 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3148 }; 2608 };
3149 2609
3150 rdma0: rdma@1c002000 { 2610 rdma0: rdma@1c002000 {
3151 compatible = "mediate 2611 compatible = "mediatek,mt8195-disp-rdma";
3152 reg = <0 0x1c002000 0 2612 reg = <0 0x1c002000 0 0x1000>;
3153 interrupts = <GIC_SPI 2613 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3154 power-domains = <&spm 2614 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3155 clocks = <&vdosys0 CL 2615 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3156 iommus = <&iommu_vdo 2616 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3157 mediatek,gce-client-r 2617 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3158 }; 2618 };
3159 2619
3160 color0: color@1c003000 { 2620 color0: color@1c003000 {
3161 compatible = "mediate 2621 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3162 reg = <0 0x1c003000 0 2622 reg = <0 0x1c003000 0 0x1000>;
3163 interrupts = <GIC_SPI 2623 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3164 power-domains = <&spm 2624 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3165 clocks = <&vdosys0 CL 2625 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3166 mediatek,gce-client-r 2626 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3167 }; 2627 };
3168 2628
3169 ccorr0: ccorr@1c004000 { 2629 ccorr0: ccorr@1c004000 {
3170 compatible = "mediate 2630 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3171 reg = <0 0x1c004000 0 2631 reg = <0 0x1c004000 0 0x1000>;
3172 interrupts = <GIC_SPI 2632 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3173 power-domains = <&spm 2633 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3174 clocks = <&vdosys0 CL 2634 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3175 mediatek,gce-client-r 2635 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3176 }; 2636 };
3177 2637
3178 aal0: aal@1c005000 { 2638 aal0: aal@1c005000 {
3179 compatible = "mediate 2639 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3180 reg = <0 0x1c005000 0 2640 reg = <0 0x1c005000 0 0x1000>;
3181 interrupts = <GIC_SPI 2641 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3182 power-domains = <&spm 2642 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3183 clocks = <&vdosys0 CL 2643 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3184 mediatek,gce-client-r 2644 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3185 }; 2645 };
3186 2646
3187 gamma0: gamma@1c006000 { 2647 gamma0: gamma@1c006000 {
3188 compatible = "mediate 2648 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3189 reg = <0 0x1c006000 0 2649 reg = <0 0x1c006000 0 0x1000>;
3190 interrupts = <GIC_SPI 2650 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3191 power-domains = <&spm 2651 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3192 clocks = <&vdosys0 CL 2652 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3193 mediatek,gce-client-r 2653 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3194 }; 2654 };
3195 2655
3196 dither0: dither@1c007000 { 2656 dither0: dither@1c007000 {
3197 compatible = "mediate 2657 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3198 reg = <0 0x1c007000 0 2658 reg = <0 0x1c007000 0 0x1000>;
3199 interrupts = <GIC_SPI 2659 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3200 power-domains = <&spm 2660 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3201 clocks = <&vdosys0 CL 2661 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3202 mediatek,gce-client-r 2662 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3203 }; 2663 };
3204 2664
3205 dsi0: dsi@1c008000 { <<
3206 compatible = "mediate <<
3207 reg = <0 0x1c008000 0 <<
3208 interrupts = <GIC_SPI <<
3209 power-domains = <&spm <<
3210 clocks = <&vdosys0 CL <<
3211 <&vdosys0 CL <<
3212 <&mipi_tx0>; <<
3213 clock-names = "engine <<
3214 phys = <&mipi_tx0>; <<
3215 phy-names = "dphy"; <<
3216 status = "disabled"; <<
3217 }; <<
3218 <<
3219 dsc0: dsc@1c009000 { 2665 dsc0: dsc@1c009000 {
3220 compatible = "mediate 2666 compatible = "mediatek,mt8195-disp-dsc";
3221 reg = <0 0x1c009000 0 2667 reg = <0 0x1c009000 0 0x1000>;
3222 interrupts = <GIC_SPI 2668 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3223 power-domains = <&spm 2669 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3224 clocks = <&vdosys0 CL 2670 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3225 mediatek,gce-client-r 2671 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3226 }; 2672 };
3227 2673
3228 dsi1: dsi@1c012000 { <<
3229 compatible = "mediate <<
3230 reg = <0 0x1c012000 0 <<
3231 interrupts = <GIC_SPI <<
3232 power-domains = <&spm <<
3233 clocks = <&vdosys0 CL <<
3234 <&vdosys0 CL <<
3235 <&mipi_tx1>; <<
3236 clock-names = "engine <<
3237 phys = <&mipi_tx1>; <<
3238 phy-names = "dphy"; <<
3239 status = "disabled"; <<
3240 }; <<
3241 <<
3242 merge0: merge@1c014000 { 2674 merge0: merge@1c014000 {
3243 compatible = "mediate 2675 compatible = "mediatek,mt8195-disp-merge";
3244 reg = <0 0x1c014000 0 2676 reg = <0 0x1c014000 0 0x1000>;
3245 interrupts = <GIC_SPI 2677 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3246 power-domains = <&spm 2678 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3247 clocks = <&vdosys0 CL 2679 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3248 mediatek,gce-client-r 2680 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3249 }; 2681 };
3250 2682
3251 dp_intf0: dp-intf@1c015000 { 2683 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediate 2684 compatible = "mediatek,mt8195-dp-intf";
3253 reg = <0 0x1c015000 0 2685 reg = <0 0x1c015000 0 0x1000>;
3254 interrupts = <GIC_SPI 2686 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3255 clocks = <&vdosys0 CL !! 2687 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
3256 <&vdosys0 C !! 2688 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3257 <&apmixedsys 2689 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3258 clock-names = "pixel" !! 2690 clock-names = "engine", "pixel", "pll";
3259 status = "disabled"; 2691 status = "disabled";
3260 }; 2692 };
3261 2693
3262 mutex: mutex@1c016000 { 2694 mutex: mutex@1c016000 {
3263 compatible = "mediate 2695 compatible = "mediatek,mt8195-disp-mutex";
3264 reg = <0 0x1c016000 0 2696 reg = <0 0x1c016000 0 0x1000>;
3265 interrupts = <GIC_SPI 2697 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3266 power-domains = <&spm 2698 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3267 clocks = <&vdosys0 CL 2699 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3268 mediatek,gce-client-r <<
3269 mediatek,gce-events = 2700 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3270 }; 2701 };
3271 2702
3272 larb0: larb@1c018000 { 2703 larb0: larb@1c018000 {
3273 compatible = "mediate 2704 compatible = "mediatek,mt8195-smi-larb";
3274 reg = <0 0x1c018000 0 2705 reg = <0 0x1c018000 0 0x1000>;
3275 mediatek,larb-id = <0 2706 mediatek,larb-id = <0>;
3276 mediatek,smi = <&smi_ 2707 mediatek,smi = <&smi_common_vdo>;
3277 clocks = <&vdosys0 CL 2708 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3278 <&vdosys0 CL 2709 <&vdosys0 CLK_VDO0_SMI_LARB>,
3279 <&vppsys0 CL 2710 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3280 clock-names = "apb", 2711 clock-names = "apb", "smi", "gals";
3281 power-domains = <&spm 2712 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3282 }; 2713 };
3283 2714
3284 larb1: larb@1c019000 { 2715 larb1: larb@1c019000 {
3285 compatible = "mediate 2716 compatible = "mediatek,mt8195-smi-larb";
3286 reg = <0 0x1c019000 0 2717 reg = <0 0x1c019000 0 0x1000>;
3287 mediatek,larb-id = <1 2718 mediatek,larb-id = <1>;
3288 mediatek,smi = <&smi_ 2719 mediatek,smi = <&smi_common_vpp>;
3289 clocks = <&vdosys0 CL 2720 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3290 <&vppsys0 CL 2721 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3291 <&vppsys0 CL 2722 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3292 clock-names = "apb", 2723 clock-names = "apb", "smi", "gals";
3293 power-domains = <&spm 2724 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294 }; 2725 };
3295 2726
3296 vdosys1: syscon@1c100000 { 2727 vdosys1: syscon@1c100000 {
3297 compatible = "mediate 2728 compatible = "mediatek,mt8195-vdosys1", "syscon";
3298 reg = <0 0x1c100000 0 2729 reg = <0 0x1c100000 0 0x1000>;
3299 mboxes = <&gce0 1 CMD 2730 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3300 mediatek,gce-client-r 2731 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3301 #clock-cells = <1>; 2732 #clock-cells = <1>;
3302 #reset-cells = <1>; 2733 #reset-cells = <1>;
3303 }; 2734 };
3304 2735
3305 smi_common_vdo: smi@1c01b000 2736 smi_common_vdo: smi@1c01b000 {
3306 compatible = "mediate 2737 compatible = "mediatek,mt8195-smi-common-vdo";
3307 reg = <0 0x1c01b000 0 2738 reg = <0 0x1c01b000 0 0x1000>;
3308 clocks = <&vdosys0 CL 2739 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3309 <&vdosys0 CL 2740 <&vdosys0 CLK_VDO0_SMI_EMI>,
3310 <&vdosys0 CL 2741 <&vdosys0 CLK_VDO0_SMI_RSI>,
3311 <&vdosys0 CL 2742 <&vdosys0 CLK_VDO0_SMI_GALS>;
3312 clock-names = "apb", 2743 clock-names = "apb", "smi", "gals0", "gals1";
3313 power-domains = <&spm 2744 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3314 2745
3315 }; 2746 };
3316 2747
3317 iommu_vdo: iommu@1c01f000 { 2748 iommu_vdo: iommu@1c01f000 {
3318 compatible = "mediate 2749 compatible = "mediatek,mt8195-iommu-vdo";
3319 reg = <0 0x1c01f000 0 2750 reg = <0 0x1c01f000 0 0x1000>;
3320 mediatek,larbs = <&la 2751 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3321 &la 2752 &larb10 &larb11 &larb13 &larb17
3322 &la 2753 &larb19 &larb21 &larb24 &larb25
3323 &la 2754 &larb28>;
3324 interrupts = <GIC_SPI 2755 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3325 #iommu-cells = <1>; 2756 #iommu-cells = <1>;
3326 clocks = <&vdosys0 CL 2757 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3327 clock-names = "bclk"; 2758 clock-names = "bclk";
3328 power-domains = <&spm 2759 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3329 }; 2760 };
3330 2761
3331 mutex1: mutex@1c101000 { 2762 mutex1: mutex@1c101000 {
3332 compatible = "mediate 2763 compatible = "mediatek,mt8195-disp-mutex";
3333 reg = <0 0x1c101000 0 2764 reg = <0 0x1c101000 0 0x1000>;
3334 reg-names = "vdo1_mut 2765 reg-names = "vdo1_mutex";
3335 interrupts = <GIC_SPI 2766 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3336 power-domains = <&spm 2767 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3337 clocks = <&vdosys1 CL 2768 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3338 clock-names = "vdo1_m 2769 clock-names = "vdo1_mutex";
3339 mediatek,gce-client-r <<
3340 mediatek,gce-events = 2770 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3341 }; 2771 };
3342 2772
3343 larb2: larb@1c102000 { 2773 larb2: larb@1c102000 {
3344 compatible = "mediate 2774 compatible = "mediatek,mt8195-smi-larb";
3345 reg = <0 0x1c102000 0 2775 reg = <0 0x1c102000 0 0x1000>;
3346 mediatek,larb-id = <2 2776 mediatek,larb-id = <2>;
3347 mediatek,smi = <&smi_ 2777 mediatek,smi = <&smi_common_vdo>;
3348 clocks = <&vdosys1 CL 2778 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CL 2779 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3350 <&vdosys1 CL 2780 <&vdosys1 CLK_VDO1_GALS>;
3351 clock-names = "apb", 2781 clock-names = "apb", "smi", "gals";
3352 power-domains = <&spm 2782 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3353 }; 2783 };
3354 2784
3355 larb3: larb@1c103000 { 2785 larb3: larb@1c103000 {
3356 compatible = "mediate 2786 compatible = "mediatek,mt8195-smi-larb";
3357 reg = <0 0x1c103000 0 2787 reg = <0 0x1c103000 0 0x1000>;
3358 mediatek,larb-id = <3 2788 mediatek,larb-id = <3>;
3359 mediatek,smi = <&smi_ 2789 mediatek,smi = <&smi_common_vpp>;
3360 clocks = <&vdosys1 CL 2790 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3361 <&vdosys1 CL 2791 <&vdosys1 CLK_VDO1_GALS>,
3362 <&vppsys0 CL 2792 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3363 clock-names = "apb", 2793 clock-names = "apb", "smi", "gals";
3364 power-domains = <&spm 2794 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3365 }; 2795 };
3366 2796
3367 vdo1_rdma0: dma-controller@1c !! 2797 vdo1_rdma0: rdma@1c104000 {
3368 compatible = "mediate 2798 compatible = "mediatek,mt8195-vdo1-rdma";
3369 reg = <0 0x1c104000 0 2799 reg = <0 0x1c104000 0 0x1000>;
3370 interrupts = <GIC_SPI 2800 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
3371 clocks = <&vdosys1 CL 2801 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3372 power-domains = <&spm 2802 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3373 iommus = <&iommu_vdo 2803 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
3374 mediatek,gce-client-r 2804 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3375 #dma-cells = <1>; <<
3376 }; 2805 };
3377 2806
3378 vdo1_rdma1: dma-controller@1c !! 2807 vdo1_rdma1: rdma@1c105000 {
3379 compatible = "mediate 2808 compatible = "mediatek,mt8195-vdo1-rdma";
3380 reg = <0 0x1c105000 0 2809 reg = <0 0x1c105000 0 0x1000>;
3381 interrupts = <GIC_SPI 2810 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
3382 clocks = <&vdosys1 CL 2811 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3383 power-domains = <&spm 2812 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3384 iommus = <&iommu_vpp 2813 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
3385 mediatek,gce-client-r 2814 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3386 #dma-cells = <1>; <<
3387 }; 2815 };
3388 2816
3389 vdo1_rdma2: dma-controller@1c !! 2817 vdo1_rdma2: rdma@1c106000 {
3390 compatible = "mediate 2818 compatible = "mediatek,mt8195-vdo1-rdma";
3391 reg = <0 0x1c106000 0 2819 reg = <0 0x1c106000 0 0x1000>;
3392 interrupts = <GIC_SPI 2820 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
3393 clocks = <&vdosys1 CL 2821 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3394 power-domains = <&spm 2822 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3395 iommus = <&iommu_vdo 2823 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
3396 mediatek,gce-client-r 2824 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3397 #dma-cells = <1>; <<
3398 }; 2825 };
3399 2826
3400 vdo1_rdma3: dma-controller@1c !! 2827 vdo1_rdma3: rdma@1c107000 {
3401 compatible = "mediate 2828 compatible = "mediatek,mt8195-vdo1-rdma";
3402 reg = <0 0x1c107000 0 2829 reg = <0 0x1c107000 0 0x1000>;
3403 interrupts = <GIC_SPI 2830 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
3404 clocks = <&vdosys1 CL 2831 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3405 power-domains = <&spm 2832 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3406 iommus = <&iommu_vpp 2833 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
3407 mediatek,gce-client-r 2834 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3408 #dma-cells = <1>; <<
3409 }; 2835 };
3410 2836
3411 vdo1_rdma4: dma-controller@1c !! 2837 vdo1_rdma4: rdma@1c108000 {
3412 compatible = "mediate 2838 compatible = "mediatek,mt8195-vdo1-rdma";
3413 reg = <0 0x1c108000 0 2839 reg = <0 0x1c108000 0 0x1000>;
3414 interrupts = <GIC_SPI 2840 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
3415 clocks = <&vdosys1 CL 2841 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3416 power-domains = <&spm 2842 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3417 iommus = <&iommu_vdo 2843 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
3418 mediatek,gce-client-r 2844 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3419 #dma-cells = <1>; <<
3420 }; 2845 };
3421 2846
3422 vdo1_rdma5: dma-controller@1c !! 2847 vdo1_rdma5: rdma@1c109000 {
3423 compatible = "mediate 2848 compatible = "mediatek,mt8195-vdo1-rdma";
3424 reg = <0 0x1c109000 0 2849 reg = <0 0x1c109000 0 0x1000>;
3425 interrupts = <GIC_SPI 2850 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
3426 clocks = <&vdosys1 CL 2851 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3427 power-domains = <&spm 2852 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3428 iommus = <&iommu_vpp 2853 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
3429 mediatek,gce-client-r 2854 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3430 #dma-cells = <1>; <<
3431 }; 2855 };
3432 2856
3433 vdo1_rdma6: dma-controller@1c !! 2857 vdo1_rdma6: rdma@1c10a000 {
3434 compatible = "mediate 2858 compatible = "mediatek,mt8195-vdo1-rdma";
3435 reg = <0 0x1c10a000 0 2859 reg = <0 0x1c10a000 0 0x1000>;
3436 interrupts = <GIC_SPI 2860 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
3437 clocks = <&vdosys1 CL 2861 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3438 power-domains = <&spm 2862 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3439 iommus = <&iommu_vdo 2863 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
3440 mediatek,gce-client-r 2864 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3441 #dma-cells = <1>; <<
3442 }; 2865 };
3443 2866
3444 vdo1_rdma7: dma-controller@1c !! 2867 vdo1_rdma7: rdma@1c10b000 {
3445 compatible = "mediate 2868 compatible = "mediatek,mt8195-vdo1-rdma";
3446 reg = <0 0x1c10b000 0 2869 reg = <0 0x1c10b000 0 0x1000>;
3447 interrupts = <GIC_SPI 2870 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
3448 clocks = <&vdosys1 CL 2871 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3449 power-domains = <&spm 2872 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3450 iommus = <&iommu_vpp 2873 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
3451 mediatek,gce-client-r 2874 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3452 #dma-cells = <1>; <<
3453 }; 2875 };
3454 2876
3455 merge1: vpp-merge@1c10c000 { 2877 merge1: vpp-merge@1c10c000 {
3456 compatible = "mediate 2878 compatible = "mediatek,mt8195-disp-merge";
3457 reg = <0 0x1c10c000 0 2879 reg = <0 0x1c10c000 0 0x1000>;
3458 interrupts = <GIC_SPI 2880 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
3459 clocks = <&vdosys1 CL 2881 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3460 <&vdosys1 CL 2882 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3461 clock-names = "merge" 2883 clock-names = "merge","merge_async";
3462 power-domains = <&spm 2884 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3463 mediatek,gce-client-r 2885 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3464 mediatek,merge-mute; !! 2886 mediatek,merge-mute = <1>;
3465 resets = <&vdosys1 MT 2887 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3466 }; 2888 };
3467 2889
3468 merge2: vpp-merge@1c10d000 { 2890 merge2: vpp-merge@1c10d000 {
3469 compatible = "mediate 2891 compatible = "mediatek,mt8195-disp-merge";
3470 reg = <0 0x1c10d000 0 2892 reg = <0 0x1c10d000 0 0x1000>;
3471 interrupts = <GIC_SPI 2893 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
3472 clocks = <&vdosys1 CL 2894 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3473 <&vdosys1 CL 2895 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3474 clock-names = "merge" 2896 clock-names = "merge","merge_async";
3475 power-domains = <&spm 2897 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3476 mediatek,gce-client-r 2898 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3477 mediatek,merge-mute; !! 2899 mediatek,merge-mute = <1>;
3478 resets = <&vdosys1 MT 2900 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3479 }; 2901 };
3480 2902
3481 merge3: vpp-merge@1c10e000 { 2903 merge3: vpp-merge@1c10e000 {
3482 compatible = "mediate 2904 compatible = "mediatek,mt8195-disp-merge";
3483 reg = <0 0x1c10e000 0 2905 reg = <0 0x1c10e000 0 0x1000>;
3484 interrupts = <GIC_SPI 2906 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
3485 clocks = <&vdosys1 CL 2907 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3486 <&vdosys1 CL 2908 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3487 clock-names = "merge" 2909 clock-names = "merge","merge_async";
3488 power-domains = <&spm 2910 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3489 mediatek,gce-client-r 2911 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3490 mediatek,merge-mute; !! 2912 mediatek,merge-mute = <1>;
3491 resets = <&vdosys1 MT 2913 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3492 }; 2914 };
3493 2915
3494 merge4: vpp-merge@1c10f000 { 2916 merge4: vpp-merge@1c10f000 {
3495 compatible = "mediate 2917 compatible = "mediatek,mt8195-disp-merge";
3496 reg = <0 0x1c10f000 0 2918 reg = <0 0x1c10f000 0 0x1000>;
3497 interrupts = <GIC_SPI 2919 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
3498 clocks = <&vdosys1 CL 2920 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3499 <&vdosys1 CL 2921 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3500 clock-names = "merge" 2922 clock-names = "merge","merge_async";
3501 power-domains = <&spm 2923 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3502 mediatek,gce-client-r 2924 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3503 mediatek,merge-mute; !! 2925 mediatek,merge-mute = <1>;
3504 resets = <&vdosys1 MT 2926 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3505 }; 2927 };
3506 2928
3507 merge5: vpp-merge@1c110000 { 2929 merge5: vpp-merge@1c110000 {
3508 compatible = "mediate 2930 compatible = "mediatek,mt8195-disp-merge";
3509 reg = <0 0x1c110000 0 2931 reg = <0 0x1c110000 0 0x1000>;
3510 interrupts = <GIC_SPI 2932 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3511 clocks = <&vdosys1 CL 2933 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3512 <&vdosys1 CL 2934 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3513 clock-names = "merge" 2935 clock-names = "merge","merge_async";
3514 power-domains = <&spm 2936 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3515 mediatek,gce-client-r 2937 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3516 mediatek,merge-fifo-e !! 2938 mediatek,merge-fifo-en = <1>;
3517 resets = <&vdosys1 MT 2939 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3518 }; 2940 };
3519 2941
3520 dp_intf1: dp-intf@1c113000 { 2942 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediate 2943 compatible = "mediatek,mt8195-dp-intf";
3522 reg = <0 0x1c113000 0 2944 reg = <0 0x1c113000 0 0x1000>;
3523 interrupts = <GIC_SPI 2945 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3524 power-domains = <&spm 2946 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3525 clocks = <&vdosys1 CL !! 2947 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3526 <&vdosys1 CL !! 2948 <&vdosys1 CLK_VDO1_DPINTF>,
3527 <&apmixedsys 2949 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3528 clock-names = "pixel" !! 2950 clock-names = "engine", "pixel", "pll";
3529 status = "disabled"; 2951 status = "disabled";
3530 }; 2952 };
3531 2953
3532 ethdr0: hdr-engine@1c114000 { 2954 ethdr0: hdr-engine@1c114000 {
3533 compatible = "mediate 2955 compatible = "mediatek,mt8195-disp-ethdr";
3534 reg = <0 0x1c114000 0 2956 reg = <0 0x1c114000 0 0x1000>,
3535 <0 0x1c115000 0 2957 <0 0x1c115000 0 0x1000>,
3536 <0 0x1c117000 0 2958 <0 0x1c117000 0 0x1000>,
3537 <0 0x1c119000 0 2959 <0 0x1c119000 0 0x1000>,
3538 <0 0x1c11a000 0 2960 <0 0x1c11a000 0 0x1000>,
3539 <0 0x1c11b000 0 2961 <0 0x1c11b000 0 0x1000>,
3540 <0 0x1c11c000 0 2962 <0 0x1c11c000 0 0x1000>;
3541 reg-names = "mixer", 2963 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3542 "vdo_be", 2964 "vdo_be", "adl_ds";
3543 mediatek,gce-client-r 2965 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3544 2966 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3545 2967 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3546 2968 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3547 2969 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3548 2970 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3549 2971 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3550 clocks = <&vdosys1 CL 2972 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3551 <&vdosys1 CL 2973 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3552 <&vdosys1 CL 2974 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3553 <&vdosys1 CL 2975 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3554 <&vdosys1 CL 2976 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3555 <&vdosys1 CL 2977 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3556 <&vdosys1 CL 2978 <&vdosys1 CLK_VDO1_26M_SLOW>,
3557 <&vdosys1 CL 2979 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3558 <&vdosys1 CL 2980 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3559 <&vdosys1 CL 2981 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3560 <&vdosys1 CL 2982 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3561 <&vdosys1 CL 2983 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3562 <&topckgen C 2984 <&topckgen CLK_TOP_ETHDR>;
3563 clock-names = "mixer" 2985 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3564 "vdo_be 2986 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3565 "gfx_fe 2987 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3566 "ethdr_ 2988 "ethdr_top";
3567 power-domains = <&spm 2989 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3568 iommus = <&iommu_vpp 2990 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3569 <&iommu_vpp 2991 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3570 interrupts = <GIC_SPI 2992 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3571 resets = <&vdosys1 MT 2993 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3572 <&vdosys1 MT 2994 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3573 <&vdosys1 MT 2995 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3574 <&vdosys1 MT 2996 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3575 <&vdosys1 MT 2997 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3576 reset-names = "vdo_fe 2998 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3577 "gfx_fe 2999 "gfx_fe1_async", "vdo_be_async";
3578 }; 3000 };
3579 3001
3580 edp_tx: edp-tx@1c500000 { 3002 edp_tx: edp-tx@1c500000 {
3581 compatible = "mediate 3003 compatible = "mediatek,mt8195-edp-tx";
3582 reg = <0 0x1c500000 0 3004 reg = <0 0x1c500000 0 0x8000>;
3583 nvmem-cells = <&dp_ca 3005 nvmem-cells = <&dp_calibration>;
3584 nvmem-cell-names = "d 3006 nvmem-cell-names = "dp_calibration_data";
3585 power-domains = <&spm 3007 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3586 interrupts = <GIC_SPI 3008 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3587 max-linkrate-mhz = <8 3009 max-linkrate-mhz = <8100>;
3588 status = "disabled"; 3010 status = "disabled";
3589 }; 3011 };
3590 3012
3591 dp_tx: dp-tx@1c600000 { 3013 dp_tx: dp-tx@1c600000 {
3592 compatible = "mediate 3014 compatible = "mediatek,mt8195-dp-tx";
3593 reg = <0 0x1c600000 0 3015 reg = <0 0x1c600000 0 0x8000>;
3594 nvmem-cells = <&dp_ca 3016 nvmem-cells = <&dp_calibration>;
3595 nvmem-cell-names = "d 3017 nvmem-cell-names = "dp_calibration_data";
3596 power-domains = <&spm 3018 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3597 interrupts = <GIC_SPI 3019 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3598 max-linkrate-mhz = <8 3020 max-linkrate-mhz = <8100>;
3599 status = "disabled"; 3021 status = "disabled";
3600 }; 3022 };
3601 }; 3023 };
3602 3024
3603 thermal_zones: thermal-zones { 3025 thermal_zones: thermal-zones {
3604 cpu0-thermal { 3026 cpu0-thermal {
3605 polling-delay = <1000 3027 polling-delay = <1000>;
3606 polling-delay-passive 3028 polling-delay-passive = <250>;
3607 thermal-sensors = <&l 3029 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3608 3030
3609 trips { 3031 trips {
3610 cpu0_alert: t 3032 cpu0_alert: trip-alert {
3611 tempe 3033 temperature = <85000>;
3612 hyste 3034 hysteresis = <2000>;
3613 type 3035 type = "passive";
3614 }; 3036 };
3615 3037
3616 cpu0_crit: tr 3038 cpu0_crit: trip-crit {
3617 tempe 3039 temperature = <100000>;
3618 hyste 3040 hysteresis = <2000>;
3619 type 3041 type = "critical";
3620 }; 3042 };
3621 }; 3043 };
3622 3044
3623 cooling-maps { 3045 cooling-maps {
3624 map0 { 3046 map0 {
3625 trip 3047 trip = <&cpu0_alert>;
3626 cooli 3048 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3627 3049 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628 3050 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3629 3051 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3630 }; 3052 };
3631 }; 3053 };
3632 }; 3054 };
3633 3055
3634 cpu1-thermal { 3056 cpu1-thermal {
3635 polling-delay = <1000 3057 polling-delay = <1000>;
3636 polling-delay-passive 3058 polling-delay-passive = <250>;
3637 thermal-sensors = <&l 3059 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3638 3060
3639 trips { 3061 trips {
3640 cpu1_alert: t 3062 cpu1_alert: trip-alert {
3641 tempe 3063 temperature = <85000>;
3642 hyste 3064 hysteresis = <2000>;
3643 type 3065 type = "passive";
3644 }; 3066 };
3645 3067
3646 cpu1_crit: tr 3068 cpu1_crit: trip-crit {
3647 tempe 3069 temperature = <100000>;
3648 hyste 3070 hysteresis = <2000>;
3649 type 3071 type = "critical";
3650 }; 3072 };
3651 }; 3073 };
3652 3074
3653 cooling-maps { 3075 cooling-maps {
3654 map0 { 3076 map0 {
3655 trip 3077 trip = <&cpu1_alert>;
3656 cooli 3078 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 3079 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658 3080 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659 3081 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3660 }; 3082 };
3661 }; 3083 };
3662 }; 3084 };
3663 3085
3664 cpu2-thermal { 3086 cpu2-thermal {
3665 polling-delay = <1000 3087 polling-delay = <1000>;
3666 polling-delay-passive 3088 polling-delay-passive = <250>;
3667 thermal-sensors = <&l 3089 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3668 3090
3669 trips { 3091 trips {
3670 cpu2_alert: t 3092 cpu2_alert: trip-alert {
3671 tempe 3093 temperature = <85000>;
3672 hyste 3094 hysteresis = <2000>;
3673 type 3095 type = "passive";
3674 }; 3096 };
3675 3097
3676 cpu2_crit: tr 3098 cpu2_crit: trip-crit {
3677 tempe 3099 temperature = <100000>;
3678 hyste 3100 hysteresis = <2000>;
3679 type 3101 type = "critical";
3680 }; 3102 };
3681 }; 3103 };
3682 3104
3683 cooling-maps { 3105 cooling-maps {
3684 map0 { 3106 map0 {
3685 trip 3107 trip = <&cpu2_alert>;
3686 cooli 3108 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687 3109 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 3110 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689 3111 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3690 }; 3112 };
3691 }; 3113 };
3692 }; 3114 };
3693 3115
3694 cpu3-thermal { 3116 cpu3-thermal {
3695 polling-delay = <1000 3117 polling-delay = <1000>;
3696 polling-delay-passive 3118 polling-delay-passive = <250>;
3697 thermal-sensors = <&l 3119 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3698 3120
3699 trips { 3121 trips {
3700 cpu3_alert: t 3122 cpu3_alert: trip-alert {
3701 tempe 3123 temperature = <85000>;
3702 hyste 3124 hysteresis = <2000>;
3703 type 3125 type = "passive";
3704 }; 3126 };
3705 3127
3706 cpu3_crit: tr 3128 cpu3_crit: trip-crit {
3707 tempe 3129 temperature = <100000>;
3708 hyste 3130 hysteresis = <2000>;
3709 type 3131 type = "critical";
3710 }; 3132 };
3711 }; 3133 };
3712 3134
3713 cooling-maps { 3135 cooling-maps {
3714 map0 { 3136 map0 {
3715 trip 3137 trip = <&cpu3_alert>;
3716 cooli 3138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717 3139 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718 3140 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719 3141 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3720 }; 3142 };
3721 }; 3143 };
3722 }; 3144 };
3723 3145
3724 cpu4-thermal { 3146 cpu4-thermal {
3725 polling-delay = <1000 3147 polling-delay = <1000>;
3726 polling-delay-passive 3148 polling-delay-passive = <250>;
3727 thermal-sensors = <&l 3149 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3728 3150
3729 trips { 3151 trips {
3730 cpu4_alert: t 3152 cpu4_alert: trip-alert {
3731 tempe 3153 temperature = <85000>;
3732 hyste 3154 hysteresis = <2000>;
3733 type 3155 type = "passive";
3734 }; 3156 };
3735 3157
3736 cpu4_crit: tr 3158 cpu4_crit: trip-crit {
3737 tempe 3159 temperature = <100000>;
3738 hyste 3160 hysteresis = <2000>;
3739 type 3161 type = "critical";
3740 }; 3162 };
3741 }; 3163 };
3742 3164
3743 cooling-maps { 3165 cooling-maps {
3744 map0 { 3166 map0 {
3745 trip 3167 trip = <&cpu4_alert>;
3746 cooli 3168 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 3169 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3748 3170 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3749 3171 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3750 }; 3172 };
3751 }; 3173 };
3752 }; 3174 };
3753 3175
3754 cpu5-thermal { 3176 cpu5-thermal {
3755 polling-delay = <1000 3177 polling-delay = <1000>;
3756 polling-delay-passive 3178 polling-delay-passive = <250>;
3757 thermal-sensors = <&l 3179 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3758 3180
3759 trips { 3181 trips {
3760 cpu5_alert: t 3182 cpu5_alert: trip-alert {
3761 tempe 3183 temperature = <85000>;
3762 hyste 3184 hysteresis = <2000>;
3763 type 3185 type = "passive";
3764 }; 3186 };
3765 3187
3766 cpu5_crit: tr 3188 cpu5_crit: trip-crit {
3767 tempe 3189 temperature = <100000>;
3768 hyste 3190 hysteresis = <2000>;
3769 type 3191 type = "critical";
3770 }; 3192 };
3771 }; 3193 };
3772 3194
3773 cooling-maps { 3195 cooling-maps {
3774 map0 { 3196 map0 {
3775 trip 3197 trip = <&cpu5_alert>;
3776 cooli 3198 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 3199 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 3200 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779 3201 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3780 }; 3202 };
3781 }; 3203 };
3782 }; 3204 };
3783 3205
3784 cpu6-thermal { 3206 cpu6-thermal {
3785 polling-delay = <1000 3207 polling-delay = <1000>;
3786 polling-delay-passive 3208 polling-delay-passive = <250>;
3787 thermal-sensors = <&l 3209 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3788 3210
3789 trips { 3211 trips {
3790 cpu6_alert: t 3212 cpu6_alert: trip-alert {
3791 tempe 3213 temperature = <85000>;
3792 hyste 3214 hysteresis = <2000>;
3793 type 3215 type = "passive";
3794 }; 3216 };
3795 3217
3796 cpu6_crit: tr 3218 cpu6_crit: trip-crit {
3797 tempe 3219 temperature = <100000>;
3798 hyste 3220 hysteresis = <2000>;
3799 type 3221 type = "critical";
3800 }; 3222 };
3801 }; 3223 };
3802 3224
3803 cooling-maps { 3225 cooling-maps {
3804 map0 { 3226 map0 {
3805 trip 3227 trip = <&cpu6_alert>;
3806 cooli 3228 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807 3229 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808 3230 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809 3231 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3810 }; 3232 };
3811 }; 3233 };
3812 }; 3234 };
3813 3235
3814 cpu7-thermal { 3236 cpu7-thermal {
3815 polling-delay = <1000 3237 polling-delay = <1000>;
3816 polling-delay-passive 3238 polling-delay-passive = <250>;
3817 thermal-sensors = <&l 3239 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3818 3240
3819 trips { 3241 trips {
3820 cpu7_alert: t 3242 cpu7_alert: trip-alert {
3821 tempe 3243 temperature = <85000>;
3822 hyste 3244 hysteresis = <2000>;
3823 type 3245 type = "passive";
3824 }; 3246 };
3825 3247
3826 cpu7_crit: tr 3248 cpu7_crit: trip-crit {
3827 tempe 3249 temperature = <100000>;
3828 hyste 3250 hysteresis = <2000>;
3829 type 3251 type = "critical";
3830 }; 3252 };
3831 }; 3253 };
3832 3254
3833 cooling-maps { 3255 cooling-maps {
3834 map0 { 3256 map0 {
3835 trip 3257 trip = <&cpu7_alert>;
3836 cooli 3258 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837 3259 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3838 3260 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3839 3261 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3840 }; <<
3841 }; <<
3842 }; <<
3843 <<
3844 vpu0-thermal { <<
3845 polling-delay = <1000 <<
3846 polling-delay-passive <<
3847 thermal-sensors = <&l <<
3848 <<
3849 trips { <<
3850 vpu0_alert: t <<
3851 tempe <<
3852 hyste <<
3853 type <<
3854 }; <<
3855 <<
3856 vpu0_crit: tr <<
3857 tempe <<
3858 hyste <<
3859 type <<
3860 }; <<
3861 }; <<
3862 }; <<
3863 <<
3864 vpu1-thermal { <<
3865 polling-delay = <1000 <<
3866 polling-delay-passive <<
3867 thermal-sensors = <&l <<
3868 <<
3869 trips { <<
3870 vpu1_alert: t <<
3871 tempe <<
3872 hyste <<
3873 type <<
3874 }; <<
3875 <<
3876 vpu1_crit: tr <<
3877 tempe <<
3878 hyste <<
3879 type <<
3880 }; <<
3881 }; <<
3882 }; <<
3883 <<
3884 gpu-thermal { <<
3885 polling-delay = <1000 <<
3886 polling-delay-passive <<
3887 thermal-sensors = <&l <<
3888 <<
3889 trips { <<
3890 gpu0_alert: t <<
3891 tempe <<
3892 hyste <<
3893 type <<
3894 }; <<
3895 <<
3896 gpu0_crit: tr <<
3897 tempe <<
3898 hyste <<
3899 type <<
3900 }; <<
3901 }; <<
3902 }; <<
3903 <<
3904 gpu1-thermal { <<
3905 polling-delay = <1000 <<
3906 polling-delay-passive <<
3907 thermal-sensors = <&l <<
3908 <<
3909 trips { <<
3910 gpu1_alert: t <<
3911 tempe <<
3912 hyste <<
3913 type <<
3914 }; <<
3915 <<
3916 gpu1_crit: tr <<
3917 tempe <<
3918 hyste <<
3919 type <<
3920 }; <<
3921 }; <<
3922 }; <<
3923 <<
3924 vdec-thermal { <<
3925 polling-delay = <1000 <<
3926 polling-delay-passive <<
3927 thermal-sensors = <&l <<
3928 <<
3929 trips { <<
3930 vdec_alert: t <<
3931 tempe <<
3932 hyste <<
3933 type <<
3934 }; <<
3935 <<
3936 vdec_crit: tr <<
3937 tempe <<
3938 hyste <<
3939 type <<
3940 }; <<
3941 }; <<
3942 }; <<
3943 <<
3944 img-thermal { <<
3945 polling-delay = <1000 <<
3946 polling-delay-passive <<
3947 thermal-sensors = <&l <<
3948 <<
3949 trips { <<
3950 img_alert: tr <<
3951 tempe <<
3952 hyste <<
3953 type <<
3954 }; <<
3955 <<
3956 img_crit: tri <<
3957 tempe <<
3958 hyste <<
3959 type <<
3960 }; <<
3961 }; <<
3962 }; <<
3963 <<
3964 infra-thermal { <<
3965 polling-delay = <1000 <<
3966 polling-delay-passive <<
3967 thermal-sensors = <&l <<
3968 <<
3969 trips { <<
3970 infra_alert: <<
3971 tempe <<
3972 hyste <<
3973 type <<
3974 }; <<
3975 <<
3976 infra_crit: t <<
3977 tempe <<
3978 hyste <<
3979 type <<
3980 }; <<
3981 }; <<
3982 }; <<
3983 <<
3984 cam0-thermal { <<
3985 polling-delay = <1000 <<
3986 polling-delay-passive <<
3987 thermal-sensors = <&l <<
3988 <<
3989 trips { <<
3990 cam0_alert: t <<
3991 tempe <<
3992 hyste <<
3993 type <<
3994 }; <<
3995 <<
3996 cam0_crit: tr <<
3997 tempe <<
3998 hyste <<
3999 type <<
4000 }; <<
4001 }; <<
4002 }; <<
4003 <<
4004 cam1-thermal { <<
4005 polling-delay = <1000 <<
4006 polling-delay-passive <<
4007 thermal-sensors = <&l <<
4008 <<
4009 trips { <<
4010 cam1_alert: t <<
4011 tempe <<
4012 hyste <<
4013 type <<
4014 }; <<
4015 <<
4016 cam1_crit: tr <<
4017 tempe <<
4018 hyste <<
4019 type <<
4020 }; 3262 };
4021 }; 3263 };
4022 }; 3264 };
4023 }; 3265 };
4024 }; 3266 };
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