1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 MediaTek Inc. 3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com> 4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h> 8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h> 9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-por 12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h> 15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h> 16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h> 17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-th 18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
19 19
20 / { 20 / {
21 compatible = "mediatek,mt8195"; 21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>; 22 interrupt-parent = <&gic>;
23 #address-cells = <2>; 23 #address-cells = <2>;
24 #size-cells = <2>; 24 #size-cells = <2>;
25 25
26 aliases { 26 aliases {
27 dp-intf0 = &dp_intf0; 27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1; 28 dp-intf1 = &dp_intf1;
29 gce0 = &gce0; 29 gce0 = &gce0;
30 gce1 = &gce1; 30 gce1 = &gce1;
31 ethdr0 = ðdr0; 31 ethdr0 = ðdr0;
32 mutex0 = &mutex; 32 mutex0 = &mutex;
33 mutex1 = &mutex1; 33 mutex1 = &mutex1;
34 merge1 = &merge1; 34 merge1 = &merge1;
35 merge2 = &merge2; 35 merge2 = &merge2;
36 merge3 = &merge3; 36 merge3 = &merge3;
37 merge4 = &merge4; 37 merge4 = &merge4;
38 merge5 = &merge5; 38 merge5 = &merge5;
39 vdo1-rdma0 = &vdo1_rdma0; 39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1; 40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2; 41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3; 42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4; 43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5; 44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6; 45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7; 46 vdo1-rdma7 = &vdo1_rdma7;
47 }; 47 };
48 48
49 cpus { 49 cpus {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 cpu0: cpu@0 { 53 cpu0: cpu@0 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a55";
56 reg = <0x000>; 56 reg = <0x000>;
57 enable-method = "psci" 57 enable-method = "psci";
58 performance-domains = 58 performance-domains = <&performance 0>;
59 clock-frequency = <170 59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = < 60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cp 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768> 62 i-cache-size = <32768>;
63 i-cache-line-size = <6 63 i-cache-line-size = <64>;
64 i-cache-sets = <128>; 64 i-cache-sets = <128>;
65 d-cache-size = <32768> 65 d-cache-size = <32768>;
66 d-cache-line-size = <6 66 d-cache-line-size = <64>;
67 d-cache-sets = <128>; 67 d-cache-sets = <128>;
68 next-level-cache = <&l 68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>; 69 #cooling-cells = <2>;
70 }; 70 };
71 71
72 cpu1: cpu@100 { 72 cpu1: cpu@100 {
73 device_type = "cpu"; 73 device_type = "cpu";
74 compatible = "arm,cort 74 compatible = "arm,cortex-a55";
75 reg = <0x100>; 75 reg = <0x100>;
76 enable-method = "psci" 76 enable-method = "psci";
77 performance-domains = 77 performance-domains = <&performance 0>;
78 clock-frequency = <170 78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = < 79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cp 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768> 81 i-cache-size = <32768>;
82 i-cache-line-size = <6 82 i-cache-line-size = <64>;
83 i-cache-sets = <128>; 83 i-cache-sets = <128>;
84 d-cache-size = <32768> 84 d-cache-size = <32768>;
85 d-cache-line-size = <6 85 d-cache-line-size = <64>;
86 d-cache-sets = <128>; 86 d-cache-sets = <128>;
87 next-level-cache = <&l 87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>; 88 #cooling-cells = <2>;
89 }; 89 };
90 90
91 cpu2: cpu@200 { 91 cpu2: cpu@200 {
92 device_type = "cpu"; 92 device_type = "cpu";
93 compatible = "arm,cort 93 compatible = "arm,cortex-a55";
94 reg = <0x200>; 94 reg = <0x200>;
95 enable-method = "psci" 95 enable-method = "psci";
96 performance-domains = 96 performance-domains = <&performance 0>;
97 clock-frequency = <170 97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cp 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768> 100 i-cache-size = <32768>;
101 i-cache-line-size = <6 101 i-cache-line-size = <64>;
102 i-cache-sets = <128>; 102 i-cache-sets = <128>;
103 d-cache-size = <32768> 103 d-cache-size = <32768>;
104 d-cache-line-size = <6 104 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 105 d-cache-sets = <128>;
106 next-level-cache = <&l 106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>; 107 #cooling-cells = <2>;
108 }; 108 };
109 109
110 cpu3: cpu@300 { 110 cpu3: cpu@300 {
111 device_type = "cpu"; 111 device_type = "cpu";
112 compatible = "arm,cort 112 compatible = "arm,cortex-a55";
113 reg = <0x300>; 113 reg = <0x300>;
114 enable-method = "psci" 114 enable-method = "psci";
115 performance-domains = 115 performance-domains = <&performance 0>;
116 clock-frequency = <170 116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = < 117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cp 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768> 119 i-cache-size = <32768>;
120 i-cache-line-size = <6 120 i-cache-line-size = <64>;
121 i-cache-sets = <128>; 121 i-cache-sets = <128>;
122 d-cache-size = <32768> 122 d-cache-size = <32768>;
123 d-cache-line-size = <6 123 d-cache-line-size = <64>;
124 d-cache-sets = <128>; 124 d-cache-sets = <128>;
125 next-level-cache = <&l 125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>; 126 #cooling-cells = <2>;
127 }; 127 };
128 128
129 cpu4: cpu@400 { 129 cpu4: cpu@400 {
130 device_type = "cpu"; 130 device_type = "cpu";
131 compatible = "arm,cort 131 compatible = "arm,cortex-a78";
132 reg = <0x400>; 132 reg = <0x400>;
133 enable-method = "psci" 133 enable-method = "psci";
134 performance-domains = 134 performance-domains = <&performance 1>;
135 clock-frequency = <217 135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = < 136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cp 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536> 138 i-cache-size = <65536>;
139 i-cache-line-size = <6 139 i-cache-line-size = <64>;
140 i-cache-sets = <256>; 140 i-cache-sets = <256>;
141 d-cache-size = <65536> 141 d-cache-size = <65536>;
142 d-cache-line-size = <6 142 d-cache-line-size = <64>;
143 d-cache-sets = <256>; 143 d-cache-sets = <256>;
144 next-level-cache = <&l 144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>; 145 #cooling-cells = <2>;
146 }; 146 };
147 147
148 cpu5: cpu@500 { 148 cpu5: cpu@500 {
149 device_type = "cpu"; 149 device_type = "cpu";
150 compatible = "arm,cort 150 compatible = "arm,cortex-a78";
151 reg = <0x500>; 151 reg = <0x500>;
152 enable-method = "psci" 152 enable-method = "psci";
153 performance-domains = 153 performance-domains = <&performance 1>;
154 clock-frequency = <217 154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = < 155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cp 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536> 157 i-cache-size = <65536>;
158 i-cache-line-size = <6 158 i-cache-line-size = <64>;
159 i-cache-sets = <256>; 159 i-cache-sets = <256>;
160 d-cache-size = <65536> 160 d-cache-size = <65536>;
161 d-cache-line-size = <6 161 d-cache-line-size = <64>;
162 d-cache-sets = <256>; 162 d-cache-sets = <256>;
163 next-level-cache = <&l 163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>; 164 #cooling-cells = <2>;
165 }; 165 };
166 166
167 cpu6: cpu@600 { 167 cpu6: cpu@600 {
168 device_type = "cpu"; 168 device_type = "cpu";
169 compatible = "arm,cort 169 compatible = "arm,cortex-a78";
170 reg = <0x600>; 170 reg = <0x600>;
171 enable-method = "psci" 171 enable-method = "psci";
172 performance-domains = 172 performance-domains = <&performance 1>;
173 clock-frequency = <217 173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = < 174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cp 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536> 176 i-cache-size = <65536>;
177 i-cache-line-size = <6 177 i-cache-line-size = <64>;
178 i-cache-sets = <256>; 178 i-cache-sets = <256>;
179 d-cache-size = <65536> 179 d-cache-size = <65536>;
180 d-cache-line-size = <6 180 d-cache-line-size = <64>;
181 d-cache-sets = <256>; 181 d-cache-sets = <256>;
182 next-level-cache = <&l 182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>; 183 #cooling-cells = <2>;
184 }; 184 };
185 185
186 cpu7: cpu@700 { 186 cpu7: cpu@700 {
187 device_type = "cpu"; 187 device_type = "cpu";
188 compatible = "arm,cort 188 compatible = "arm,cortex-a78";
189 reg = <0x700>; 189 reg = <0x700>;
190 enable-method = "psci" 190 enable-method = "psci";
191 performance-domains = 191 performance-domains = <&performance 1>;
192 clock-frequency = <217 192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = < 193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cp 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536> 195 i-cache-size = <65536>;
196 i-cache-line-size = <6 196 i-cache-line-size = <64>;
197 i-cache-sets = <256>; 197 i-cache-sets = <256>;
198 d-cache-size = <65536> 198 d-cache-size = <65536>;
199 d-cache-line-size = <6 199 d-cache-line-size = <64>;
200 d-cache-sets = <256>; 200 d-cache-sets = <256>;
201 next-level-cache = <&l 201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>; 202 #cooling-cells = <2>;
203 }; 203 };
204 204
205 cpu-map { 205 cpu-map {
206 cluster0 { 206 cluster0 {
207 core0 { 207 core0 {
208 cpu = 208 cpu = <&cpu0>;
209 }; 209 };
210 210
211 core1 { 211 core1 {
212 cpu = 212 cpu = <&cpu1>;
213 }; 213 };
214 214
215 core2 { 215 core2 {
216 cpu = 216 cpu = <&cpu2>;
217 }; 217 };
218 218
219 core3 { 219 core3 {
220 cpu = 220 cpu = <&cpu3>;
221 }; 221 };
222 222
223 core4 { 223 core4 {
224 cpu = 224 cpu = <&cpu4>;
225 }; 225 };
226 226
227 core5 { 227 core5 {
228 cpu = 228 cpu = <&cpu5>;
229 }; 229 };
230 230
231 core6 { 231 core6 {
232 cpu = 232 cpu = <&cpu6>;
233 }; 233 };
234 234
235 core7 { 235 core7 {
236 cpu = 236 cpu = <&cpu7>;
237 }; 237 };
238 }; 238 };
239 }; 239 };
240 240
241 idle-states { 241 idle-states {
242 entry-method = "psci"; 242 entry-method = "psci";
243 243
244 cpu_ret_l: cpu-retenti 244 cpu_ret_l: cpu-retention-l {
245 compatible = " 245 compatible = "arm,idle-state";
246 arm,psci-suspe 246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-st 247 local-timer-stop;
248 entry-latency- 248 entry-latency-us = <50>;
249 exit-latency-u 249 exit-latency-us = <95>;
250 min-residency- 250 min-residency-us = <580>;
251 }; 251 };
252 252
253 cpu_ret_b: cpu-retenti 253 cpu_ret_b: cpu-retention-b {
254 compatible = " 254 compatible = "arm,idle-state";
255 arm,psci-suspe 255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-st 256 local-timer-stop;
257 entry-latency- 257 entry-latency-us = <45>;
258 exit-latency-u 258 exit-latency-us = <140>;
259 min-residency- 259 min-residency-us = <740>;
260 }; 260 };
261 261
262 cpu_off_l: cpu-off-l { 262 cpu_off_l: cpu-off-l {
263 compatible = " 263 compatible = "arm,idle-state";
264 arm,psci-suspe 264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-st 265 local-timer-stop;
266 entry-latency- 266 entry-latency-us = <55>;
267 exit-latency-u 267 exit-latency-us = <155>;
268 min-residency- 268 min-residency-us = <840>;
269 }; 269 };
270 270
271 cpu_off_b: cpu-off-b { 271 cpu_off_b: cpu-off-b {
272 compatible = " 272 compatible = "arm,idle-state";
273 arm,psci-suspe 273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-st 274 local-timer-stop;
275 entry-latency- 275 entry-latency-us = <50>;
276 exit-latency-u 276 exit-latency-us = <200>;
277 min-residency- 277 min-residency-us = <1000>;
278 }; 278 };
279 }; 279 };
280 280
281 l2_0: l2-cache0 { 281 l2_0: l2-cache0 {
282 compatible = "cache"; 282 compatible = "cache";
283 cache-level = <2>; 283 cache-level = <2>;
284 cache-size = <131072>; 284 cache-size = <131072>;
285 cache-line-size = <64> 285 cache-line-size = <64>;
286 cache-sets = <512>; 286 cache-sets = <512>;
287 next-level-cache = <&l 287 next-level-cache = <&l3_0>;
288 cache-unified; 288 cache-unified;
289 }; 289 };
290 290
291 l2_1: l2-cache1 { 291 l2_1: l2-cache1 {
292 compatible = "cache"; 292 compatible = "cache";
293 cache-level = <2>; 293 cache-level = <2>;
294 cache-size = <262144>; 294 cache-size = <262144>;
295 cache-line-size = <64> 295 cache-line-size = <64>;
296 cache-sets = <512>; 296 cache-sets = <512>;
297 next-level-cache = <&l 297 next-level-cache = <&l3_0>;
298 cache-unified; 298 cache-unified;
299 }; 299 };
300 300
301 l3_0: l3-cache { 301 l3_0: l3-cache {
302 compatible = "cache"; 302 compatible = "cache";
303 cache-level = <3>; 303 cache-level = <3>;
304 cache-size = <2097152> 304 cache-size = <2097152>;
305 cache-line-size = <64> 305 cache-line-size = <64>;
306 cache-sets = <2048>; 306 cache-sets = <2048>;
307 cache-unified; 307 cache-unified;
308 }; 308 };
309 }; 309 };
310 310
311 dsu-pmu { 311 dsu-pmu {
312 compatible = "arm,dsu-pmu"; 312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_T 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail"; 316 status = "fail";
317 }; 317 };
318 318
319 dmic_codec: dmic-codec { 319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec"; 320 compatible = "dmic-codec";
321 num-channels = <2>; 321 num-channels = <2>;
322 wakeup-delay-ms = <50>; 322 wakeup-delay-ms = <50>;
323 }; 323 };
324 324
325 sound: mt8195-sound { 325 sound: mt8195-sound {
326 mediatek,platform = <&afe>; 326 mediatek,platform = <&afe>;
327 status = "disabled"; 327 status = "disabled";
328 }; 328 };
329 329
330 clk13m: fixed-factor-clock-13m { 330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clo 331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>; 332 #clock-cells = <0>;
333 clocks = <&clk26m>; 333 clocks = <&clk26m>;
334 clock-div = <2>; 334 clock-div = <2>;
335 clock-mult = <1>; 335 clock-mult = <1>;
336 clock-output-names = "clk13m"; 336 clock-output-names = "clk13m";
337 }; 337 };
338 338
339 clk26m: oscillator-26m { 339 clk26m: oscillator-26m {
340 compatible = "fixed-clock"; 340 compatible = "fixed-clock";
341 #clock-cells = <0>; 341 #clock-cells = <0>;
342 clock-frequency = <26000000>; 342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m"; 343 clock-output-names = "clk26m";
344 }; 344 };
345 345
346 clk32k: oscillator-32k { 346 clk32k: oscillator-32k {
347 compatible = "fixed-clock"; 347 compatible = "fixed-clock";
348 #clock-cells = <0>; 348 #clock-cells = <0>;
349 clock-frequency = <32768>; 349 clock-frequency = <32768>;
350 clock-output-names = "clk32k"; 350 clock-output-names = "clk32k";
351 }; 351 };
352 352
353 performance: performance-controller@11 353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq 354 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1 356 #performance-domain-cells = <1>;
357 }; 357 };
358 358
359 gpu_opp_table: opp-table-gpu { 359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points 360 compatible = "operating-points-v2";
361 opp-shared; 361 opp-shared;
362 362
363 opp-390000000 { 363 opp-390000000 {
364 opp-hz = /bits/ 64 <39 364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <62500 365 opp-microvolt = <625000>;
366 }; 366 };
367 opp-410000000 { 367 opp-410000000 {
368 opp-hz = /bits/ 64 <41 368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <63125 369 opp-microvolt = <631250>;
370 }; 370 };
371 opp-431000000 { 371 opp-431000000 {
372 opp-hz = /bits/ 64 <43 372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <63125 373 opp-microvolt = <631250>;
374 }; 374 };
375 opp-473000000 { 375 opp-473000000 {
376 opp-hz = /bits/ 64 <47 376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <63750 377 opp-microvolt = <637500>;
378 }; 378 };
379 opp-515000000 { 379 opp-515000000 {
380 opp-hz = /bits/ 64 <51 380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <63750 381 opp-microvolt = <637500>;
382 }; 382 };
383 opp-556000000 { 383 opp-556000000 {
384 opp-hz = /bits/ 64 <55 384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <64375 385 opp-microvolt = <643750>;
386 }; 386 };
387 opp-598000000 { 387 opp-598000000 {
388 opp-hz = /bits/ 64 <59 388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <65000 389 opp-microvolt = <650000>;
390 }; 390 };
391 opp-640000000 { 391 opp-640000000 {
392 opp-hz = /bits/ 64 <64 392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <65000 393 opp-microvolt = <650000>;
394 }; 394 };
395 opp-670000000 { 395 opp-670000000 {
396 opp-hz = /bits/ 64 <67 396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <66250 397 opp-microvolt = <662500>;
398 }; 398 };
399 opp-700000000 { 399 opp-700000000 {
400 opp-hz = /bits/ 64 <70 400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <67500 401 opp-microvolt = <675000>;
402 }; 402 };
403 opp-730000000 { 403 opp-730000000 {
404 opp-hz = /bits/ 64 <73 404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <68750 405 opp-microvolt = <687500>;
406 }; 406 };
407 opp-760000000 { 407 opp-760000000 {
408 opp-hz = /bits/ 64 <76 408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <70000 409 opp-microvolt = <700000>;
410 }; 410 };
411 opp-790000000 { 411 opp-790000000 {
412 opp-hz = /bits/ 64 <79 412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <71250 413 opp-microvolt = <712500>;
414 }; 414 };
415 opp-820000000 { 415 opp-820000000 {
416 opp-hz = /bits/ 64 <82 416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <72500 417 opp-microvolt = <725000>;
418 }; 418 };
419 opp-850000000 { 419 opp-850000000 {
420 opp-hz = /bits/ 64 <85 420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <73750 421 opp-microvolt = <737500>;
422 }; 422 };
423 opp-880000000 { 423 opp-880000000 {
424 opp-hz = /bits/ 64 <88 424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <75000 425 opp-microvolt = <750000>;
426 }; 426 };
427 }; 427 };
428 428
429 pmu-a55 { 429 pmu-a55 {
430 compatible = "arm,cortex-a55-p 430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>; 431 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TY 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 }; 433 };
434 434
435 pmu-a78 { 435 pmu-a78 {
436 compatible = "arm,cortex-a78-p 436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>; 437 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TY 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 }; 439 };
440 440
441 psci { 441 psci {
442 compatible = "arm,psci-1.0"; 442 compatible = "arm,psci-1.0";
443 method = "smc"; 443 method = "smc";
444 }; 444 };
445 445
446 timer: timer { 446 timer: timer {
447 compatible = "arm,armv8-timer" 447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>; 448 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_T 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_T 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_T 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_T 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 }; 453 };
454 454
455 soc { 455 soc {
456 #address-cells = <2>; 456 #address-cells = <2>;
457 #size-cells = <2>; 457 #size-cells = <2>;
458 compatible = "simple-bus"; 458 compatible = "simple-bus";
459 ranges; 459 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
461 461
462 gic: interrupt-controller@c000 462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic- 463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4> 464 #interrupt-cells = <4>;
465 #redistributor-regions 465 #redistributor-regions = <1>;
466 interrupt-parent = <&g 466 interrupt-parent = <&gic>;
467 interrupt-controller; 467 interrupt-controller;
468 reg = <0 0x0c000000 0 468 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 469 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471 471
472 ppi-partitions { 472 ppi-partitions {
473 ppi_cluster0: 473 ppi_cluster0: interrupt-partition-0 {
474 affini 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 }; 475 };
476 476
477 ppi_cluster1: 477 ppi_cluster1: interrupt-partition-1 {
478 affini 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 }; 479 };
480 }; 480 };
481 }; 481 };
482 482
483 topckgen: syscon@10000000 { 483 topckgen: syscon@10000000 {
484 compatible = "mediatek 484 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 485 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>; 486 #clock-cells = <1>;
487 }; 487 };
488 488
489 infracfg_ao: syscon@10001000 { 489 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
491 reg = <0 0x10001000 0 491 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>; 492 #clock-cells = <1>;
493 #reset-cells = <1>; 493 #reset-cells = <1>;
494 }; 494 };
495 495
496 pericfg: syscon@10003000 { 496 pericfg: syscon@10003000 {
497 compatible = "mediatek 497 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 498 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>; 499 #clock-cells = <1>;
500 }; 500 };
501 501
502 pio: pinctrl@10005000 { 502 pio: pinctrl@10005000 {
503 compatible = "mediatek 503 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 504 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 505 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 506 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 507 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 508 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 509 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 510 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 511 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br" 513 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl" 514 "iocfg_tl", "eint";
515 gpio-controller; 515 gpio-controller;
516 #gpio-cells = <2>; 516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller; 518 interrupt-controller;
519 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2> 520 #interrupt-cells = <2>;
521 }; 521 };
522 522
523 scpsys: syscon@10006000 { 523 scpsys: syscon@10006000 {
524 compatible = "mediatek 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 525 reg = <0 0x10006000 0 0x1000>;
526 526
527 /* System Power Manage 527 /* System Power Manager */
528 spm: power-controller 528 spm: power-controller {
529 compatible = " 529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells 530 #address-cells = <1>;
531 #size-cells = 531 #size-cells = <0>;
532 #power-domain- 532 #power-domain-cells = <1>;
533 533
534 /* power domai 534 /* power domain of the SoC */
535 mfg0: power-do 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = 536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #addre 537 #address-cells = <1>;
538 #size- 538 #size-cells = <0>;
539 #power 539 #power-domain-cells = <1>;
540 540
541 mfg1: 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 542 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 545 clock-names = "mfg", "alt";
546 546 mediatek,infracfg = <&infracfg_ao>;
547 547 #address-cells = <1>;
548 548 #size-cells = <0>;
549 549 #power-domain-cells = <1>;
550 550
551 551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 552 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 553 #power-domain-cells = <0>;
554 554 };
555 555
556 556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 557 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 558 #power-domain-cells = <0>;
559 559 };
560 560
561 561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 562 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 563 #power-domain-cells = <0>;
564 564 };
565 565
566 566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 567 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 568 #power-domain-cells = <0>;
569 569 };
570 570
571 571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 572 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 573 #power-domain-cells = <0>;
574 574 };
575 }; 575 };
576 }; 576 };
577 577
578 power-domain@M 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks 580 clocks = <&topckgen CLK_TOP_VPP>,
581 581 <&topckgen CLK_TOP_CAM>,
582 582 <&topckgen CLK_TOP_CCU>,
583 583 <&topckgen CLK_TOP_IMG>,
584 584 <&topckgen CLK_TOP_VENC>,
585 585 <&topckgen CLK_TOP_VDEC>,
586 586 <&topckgen CLK_TOP_WPE_VPP>,
587 587 <&topckgen CLK_TOP_CFG_VPP0>,
588 588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock- 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 614 "vppsys0-18";
615 mediat 615 mediatek,infracfg = <&infracfg_ao>;
616 #addre 616 #address-cells = <1>;
617 #size- 617 #size-cells = <0>;
618 #power 618 #power-domain-cells = <1>;
619 619
620 power- 620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 621 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 623 clock-names = "vdec1-0";
624 624 mediatek,infracfg = <&infracfg_ao>;
625 625 #power-domain-cells = <0>;
626 }; 626 };
627 627
628 power- 628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 630 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
631 631 clock-names = "venc1-larb";
632 632 mediatek,infracfg = <&infracfg_ao>;
633 633 #power-domain-cells = <0>;
634 }; 634 };
635 635
636 power- 636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 637 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 638 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 639 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 640 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 641 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 642 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 643 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 644 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 646 "vdosys0-2", "vdosys0-3",
647 647 "vdosys0-4", "vdosys0-5";
648 648 mediatek,infracfg = <&infracfg_ao>;
649 649 #address-cells = <1>;
650 650 #size-cells = <0>;
651 651 #power-domain-cells = <1>;
652 652
653 653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 654 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 655 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 656 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 657 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 658 clock-names = "vppsys1", "vppsys1-0",
659 659 "vppsys1-1";
660 660 mediatek,infracfg = <&infracfg_ao>;
661 661 #power-domain-cells = <0>;
662 662 };
663 663
664 664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 665 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 666 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 667 <&wpesys CLK_WPE_SMI_LARB8>,
668 668 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 669 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 671 "wepsys-3";
672 672 mediatek,infracfg = <&infracfg_ao>;
673 673 #power-domain-cells = <0>;
674 674 };
675 675
676 676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 677 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 678 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 679 clock-names = "vdec0-0";
680 680 mediatek,infracfg = <&infracfg_ao>;
681 681 #power-domain-cells = <0>;
682 682 };
683 683
684 684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 685 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 686 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 687 clock-names = "vdec2-0";
688 688 mediatek,infracfg = <&infracfg_ao>;
689 689 #power-domain-cells = <0>;
690 690 };
691 691
692 692 power-domain@MT8195_POWER_DOMAIN_VENC {
693 693 reg = <MT8195_POWER_DOMAIN_VENC>;
694 694 clocks = <&vencsys CLK_VENC_LARB>;
695 695 clock-names = "venc0-larb";
696 696 mediatek,infracfg = <&infracfg_ao>;
697 697 #power-domain-cells = <0>;
698 698 };
699 699
700 700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 701 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 702 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 703 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 704 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 705 <&vdosys1 CLK_VDO1_GALS>;
706 706 clock-names = "vdosys1", "vdosys1-0",
707 707 "vdosys1-1", "vdosys1-2";
708 708 mediatek,infracfg = <&infracfg_ao>;
709 709 #address-cells = <1>;
710 710 #size-cells = <0>;
711 711 #power-domain-cells = <1>;
712 712
713 713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 714 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 715 mediatek,infracfg = <&infracfg_ao>;
716 716 #power-domain-cells = <0>;
717 717 };
718 718
719 719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 720 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 721 mediatek,infracfg = <&infracfg_ao>;
722 722 #power-domain-cells = <0>;
723 723 };
724 724
725 725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 726 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 727 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 728 clock-names = "hdmi_tx";
729 729 #power-domain-cells = <0>;
730 730 };
731 731 };
732 732
733 733 power-domain@MT8195_POWER_DOMAIN_IMG {
734 734 reg = <MT8195_POWER_DOMAIN_IMG>;
735 735 clocks = <&imgsys CLK_IMG_LARB9>,
736 736 <&imgsys CLK_IMG_GALS>;
737 737 clock-names = "img-0", "img-1";
738 738 mediatek,infracfg = <&infracfg_ao>;
739 739 #address-cells = <1>;
740 740 #size-cells = <0>;
741 741 #power-domain-cells = <1>;
742 742
743 743 power-domain@MT8195_POWER_DOMAIN_DIP {
744 744 reg = <MT8195_POWER_DOMAIN_DIP>;
745 745 #power-domain-cells = <0>;
746 746 };
747 747
748 748 power-domain@MT8195_POWER_DOMAIN_IPE {
749 749 reg = <MT8195_POWER_DOMAIN_IPE>;
750 750 clocks = <&topckgen CLK_TOP_IPE>,
751 751 <&imgsys CLK_IMG_IPE>,
752 752 <&ipesys CLK_IPE_SMI_LARB12>;
753 753 clock-names = "ipe", "ipe-0", "ipe-1";
754 754 mediatek,infracfg = <&infracfg_ao>;
755 755 #power-domain-cells = <0>;
756 756 };
757 757 };
758 758
759 759 power-domain@MT8195_POWER_DOMAIN_CAM {
760 760 reg = <MT8195_POWER_DOMAIN_CAM>;
761 761 clocks = <&camsys CLK_CAM_LARB13>,
762 762 <&camsys CLK_CAM_LARB14>,
763 763 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 764 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 765 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 767 "cam-4";
768 768 mediatek,infracfg = <&infracfg_ao>;
769 769 #address-cells = <1>;
770 770 #size-cells = <0>;
771 771 #power-domain-cells = <1>;
772 772
773 773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 774 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 775 #power-domain-cells = <0>;
776 776 };
777 777
778 778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 779 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 780 #power-domain-cells = <0>;
781 781 };
782 782
783 783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 784 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 785 #power-domain-cells = <0>;
786 786 };
787 787 };
788 }; 788 };
789 }; 789 };
790 790
791 power-domain@M 791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = 792 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediat 793 mediatek,infracfg = <&infracfg_ao>;
794 #power 794 #power-domain-cells = <0>;
795 }; 795 };
796 796
797 power-domain@M 797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = 798 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediat 799 mediatek,infracfg = <&infracfg_ao>;
800 #power 800 #power-domain-cells = <0>;
801 }; 801 };
802 802
803 power-domain@M 803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = 804 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power 805 #power-domain-cells = <0>;
806 }; 806 };
807 807
808 power-domain@M 808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = 809 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power 810 #power-domain-cells = <0>;
811 }; 811 };
812 812
813 power-domain@M 813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = 814 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks 815 clocks = <&topckgen CLK_TOP_SENINF>,
816 816 <&topckgen CLK_TOP_SENINF2>;
817 clock- 817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power 818 #power-domain-cells = <0>;
819 }; 819 };
820 820
821 power-domain@M 821 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = 822 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks 823 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock- 824 clock-names = "ether";
825 #power 825 #power-domain-cells = <0>;
826 }; 826 };
827 827
828 power-domain@M 828 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = 829 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks 830 clocks = <&topckgen CLK_TOP_ADSP>,
831 831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock- 832 clock-names = "adsp", "adsp1";
833 #addre 833 #address-cells = <1>;
834 #size- 834 #size-cells = <0>;
835 mediat 835 mediatek,infracfg = <&infracfg_ao>;
836 #power 836 #power-domain-cells = <1>;
837 837
838 power- 838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 839 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 840 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 841 <&topckgen CLK_TOP_AUD_INTBUS>,
842 842 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 843 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 844 clock-names = "audio", "audio1", "audio2",
845 845 "audio3";
846 846 mediatek,infracfg = <&infracfg_ao>;
847 847 #power-domain-cells = <0>;
848 }; 848 };
849 }; 849 };
850 }; 850 };
851 }; 851 };
852 852
853 watchdog: watchdog@10007000 { 853 watchdog: watchdog@10007000 {
854 compatible = "mediatek 854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrs 855 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 856 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>; 857 #reset-cells = <1>;
858 }; 858 };
859 859
860 apmixedsys: syscon@1000c000 { 860 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek 861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 862 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>; 863 #clock-cells = <1>;
864 }; 864 };
865 865
866 systimer: timer@10017000 { 866 systimer: timer@10017000 {
867 compatible = "mediatek 867 compatible = "mediatek,mt8195-timer",
868 "mediatek 868 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 869 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 870 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>; 871 clocks = <&clk13m>;
872 }; 872 };
873 873
874 pwrap: pwrap@10024000 { 874 pwrap: pwrap@10024000 {
875 compatible = "mediatek 875 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 876 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap"; 877 reg-names = "pwrap";
878 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao 879 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao 880 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", " 881 clock-names = "spi", "wrap";
882 assigned-clocks = <&to 882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents 883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 }; 884 };
885 885
886 spmi: spmi@10027000 { 886 spmi: spmi@10027000 {
887 compatible = "mediatek 887 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 888 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 889 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "s 890 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao 891 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao 892 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CL 893 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sy 894 clock-names = "pmif_sys_ck",
895 "pmif_tm 895 "pmif_tmr_ck",
896 "spmimst 896 "spmimst_clk_mux";
897 assigned-clocks = <&to 897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents 898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 }; 899 };
900 900
901 iommu_infra: infra-iommu@10315 901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek 902 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 903 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 904 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 905 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 906 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 907 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 908 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>; 909 #iommu-cells = <1>;
910 }; 910 };
911 911
912 gce0: mailbox@10320000 { 912 gce0: mailbox@10320000 {
913 compatible = "mediatek 913 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 914 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 915 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>; 916 #mbox-cells = <2>;
917 clocks = <&infracfg_ao 917 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 }; 918 };
919 919
920 gce1: mailbox@10330000 { 920 gce1: mailbox@10330000 {
921 compatible = "mediatek 921 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 922 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 923 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>; 924 #mbox-cells = <2>;
925 clocks = <&infracfg_ao 925 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 }; 926 };
927 927
928 scp: scp@10500000 { 928 scp: scp@10500000 {
929 compatible = "mediatek 929 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 930 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 931 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 932 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "c 933 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled"; 935 status = "disabled";
936 }; 936 };
937 937
938 scp_adsp: clock-controller@107 938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek 939 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 940 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>; 941 #clock-cells = <1>;
942 }; 942 };
943 943
944 adsp: dsp@10803000 { 944 adsp: dsp@10803000 {
945 compatible = "mediatek 945 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 946 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 947 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sr 948 reg-names = "cfg", "sram";
949 clocks = <&topckgen CL 949 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>, 950 <&clk26m>,
951 <&topckgen CL 951 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CL 952 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CL 953 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CL 954 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_se 955 clock-names = "adsp_sel",
956 "clk26m_ck", 956 "clk26m_ck",
957 "audio_local_ 957 "audio_local_bus",
958 "mainpll_d7_d 958 "mainpll_d7_d2",
959 "scp_adsp_aud 959 "scp_adsp_audiodsp",
960 "audio_h"; 960 "audio_h";
961 power-domains = <&spm 961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx 962 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbo 963 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled"; 964 status = "disabled";
965 }; 965 };
966 966
967 adsp_mailbox0: mailbox@1081600 967 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek 968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>; 969 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 970 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 971 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 }; 972 };
973 973
974 adsp_mailbox1: mailbox@1081700 974 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek 975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>; 976 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 977 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 978 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 }; 979 };
980 980
981 afe: mt8195-afe-pcm@10890000 { 981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek 982 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 983 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <& 984 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm 985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14 987 resets = <&watchdog 14>;
988 reset-names = "audiosy 988 reset-names = "audiosys";
989 clocks = <&clk26m>, 989 clocks = <&clk26m>,
990 <&apmixedsys C 990 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys C 991 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK 992 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK 993 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK 994 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK 995 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK 996 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK 997 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK 998 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK 999 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CL 1000 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CL 1001 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CL 1002 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CL 1003 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CL 1004 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CL 1005 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao 1006 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CL 1007 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m 1008 clock-names = "clk26m",
1009 "apll1_ck", 1009 "apll1_ck",
1010 "apll2_ck", 1010 "apll2_ck",
1011 "apll12_div0" 1011 "apll12_div0",
1012 "apll12_div1" 1012 "apll12_div1",
1013 "apll12_div2" 1013 "apll12_div2",
1014 "apll12_div3" 1014 "apll12_div3",
1015 "apll12_div9" 1015 "apll12_div9",
1016 "a1sys_hp_sel 1016 "a1sys_hp_sel",
1017 "aud_intbus_s 1017 "aud_intbus_sel",
1018 "audio_h_sel" 1018 "audio_h_sel",
1019 "audio_local_ 1019 "audio_local_bus_sel",
1020 "dptx_m_sel", 1020 "dptx_m_sel",
1021 "i2so1_m_sel" 1021 "i2so1_m_sel",
1022 "i2so2_m_sel" 1022 "i2so2_m_sel",
1023 "i2si1_m_sel" 1023 "i2si1_m_sel",
1024 "i2si2_m_sel" 1024 "i2si2_m_sel",
1025 "infra_ao_aud 1025 "infra_ao_audio_26m_b",
1026 "scp_adsp_aud 1026 "scp_adsp_audiodsp";
1027 status = "disabled"; 1027 status = "disabled";
1028 }; 1028 };
1029 1029
1030 uart0: serial@11001100 { 1030 uart0: serial@11001100 {
1031 compatible = "mediate 1031 compatible = "mediatek,mt8195-uart",
1032 "mediate 1032 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 1033 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 1034 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, < 1035 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", 1036 clock-names = "baud", "bus";
1037 status = "disabled"; 1037 status = "disabled";
1038 }; 1038 };
1039 1039
1040 uart1: serial@11001200 { 1040 uart1: serial@11001200 {
1041 compatible = "mediate 1041 compatible = "mediatek,mt8195-uart",
1042 "mediate 1042 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 1043 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 1044 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, < 1045 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", 1046 clock-names = "baud", "bus";
1047 status = "disabled"; 1047 status = "disabled";
1048 }; 1048 };
1049 1049
1050 uart2: serial@11001300 { 1050 uart2: serial@11001300 {
1051 compatible = "mediate 1051 compatible = "mediatek,mt8195-uart",
1052 "mediate 1052 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 1053 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 1054 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, < 1055 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", 1056 clock-names = "baud", "bus";
1057 status = "disabled"; 1057 status = "disabled";
1058 }; 1058 };
1059 1059
1060 uart3: serial@11001400 { 1060 uart3: serial@11001400 {
1061 compatible = "mediate 1061 compatible = "mediatek,mt8195-uart",
1062 "mediate 1062 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 1063 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 1064 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, < 1065 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", 1066 clock-names = "baud", "bus";
1067 status = "disabled"; 1067 status = "disabled";
1068 }; 1068 };
1069 1069
1070 uart4: serial@11001500 { 1070 uart4: serial@11001500 {
1071 compatible = "mediate 1071 compatible = "mediatek,mt8195-uart",
1072 "mediate 1072 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 1073 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 1074 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, < 1075 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", 1076 clock-names = "baud", "bus";
1077 status = "disabled"; 1077 status = "disabled";
1078 }; 1078 };
1079 1079
1080 uart5: serial@11001600 { 1080 uart5: serial@11001600 {
1081 compatible = "mediate 1081 compatible = "mediatek,mt8195-uart",
1082 "mediate 1082 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 1083 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 1084 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, < 1085 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", 1086 clock-names = "baud", "bus";
1087 status = "disabled"; 1087 status = "disabled";
1088 }; 1088 };
1089 1089
1090 auxadc: auxadc@11002000 { 1090 auxadc: auxadc@11002000 {
1091 compatible = "mediate 1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediate 1092 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 1093 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_a 1094 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main"; 1095 clock-names = "main";
1096 #io-channel-cells = < 1096 #io-channel-cells = <1>;
1097 status = "disabled"; 1097 status = "disabled";
1098 }; 1098 };
1099 1099
1100 pericfg_ao: syscon@11003000 { 1100 pericfg_ao: syscon@11003000 {
1101 compatible = "mediate 1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 1102 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>; 1103 #clock-cells = <1>;
1104 }; 1104 };
1105 1105
1106 spi0: spi@1100a000 { 1106 spi0: spi@1100a000 {
1107 compatible = "mediate 1107 compatible = "mediatek,mt8195-spi",
1108 "mediate 1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>; 1109 #address-cells = <1>;
1110 #size-cells = <0>; 1110 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 1111 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 1112 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen C 1113 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen C 1114 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_a 1115 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent 1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled"; 1117 status = "disabled";
1118 }; 1118 };
1119 1119
1120 lvts_ap: thermal-sensor@1100b 1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediate 1121 compatible = "mediatek,mt8195-lvts-ap";
1122 reg = <0 0x1100b000 0 1122 reg = <0 0x1100b000 0 0xc00>;
1123 interrupts = <GIC_SPI 1123 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1124 clocks = <&infracfg_a 1124 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125 resets = <&infracfg_a 1125 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1126 nvmem-cells = <&lvts_ 1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "l 1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells 1128 #thermal-sensor-cells = <1>;
1129 }; 1129 };
1130 1130
1131 svs: svs@1100bc00 { 1131 svs: svs@1100bc00 {
1132 compatible = "mediate 1132 compatible = "mediatek,mt8195-svs";
1133 reg = <0 0x1100bc00 0 1133 reg = <0 0x1100bc00 0 0x400>;
1134 interrupts = <GIC_SPI 1134 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
1135 clocks = <&infracfg_a 1135 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1136 clock-names = "main"; 1136 clock-names = "main";
1137 nvmem-cells = <&svs_c 1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "s 1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1139 resets = <&infracfg_a 1139 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1140 reset-names = "svs_rs 1140 reset-names = "svs_rst";
1141 }; 1141 };
1142 1142
1143 disp_pwm0: pwm@1100e000 { 1143 disp_pwm0: pwm@1100e000 {
1144 compatible = "mediate 1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1145 reg = <0 0x1100e000 0 1145 reg = <0 0x1100e000 0 0x1000>;
1146 interrupts = <GIC_SPI 1146 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1147 power-domains = <&spm 1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>; 1148 #pwm-cells = <2>;
1149 clocks = <&topckgen C 1149 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1150 <&infracfg_a 1150 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1151 clock-names = "main", 1151 clock-names = "main", "mm";
1152 status = "disabled"; 1152 status = "disabled";
1153 }; 1153 };
1154 1154
1155 disp_pwm1: pwm@1100f000 { 1155 disp_pwm1: pwm@1100f000 {
1156 compatible = "mediate 1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1157 reg = <0 0x1100f000 0 1157 reg = <0 0x1100f000 0 0x1000>;
1158 interrupts = <GIC_SPI 1158 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1159 #pwm-cells = <2>; 1159 #pwm-cells = <2>;
1160 clocks = <&topckgen C 1160 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1161 <&infracfg_a 1161 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1162 clock-names = "main", 1162 clock-names = "main", "mm";
1163 status = "disabled"; 1163 status = "disabled";
1164 }; 1164 };
1165 1165
1166 spi1: spi@11010000 { 1166 spi1: spi@11010000 {
1167 compatible = "mediate 1167 compatible = "mediatek,mt8195-spi",
1168 "mediate 1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>; 1169 #address-cells = <1>;
1170 #size-cells = <0>; 1170 #size-cells = <0>;
1171 reg = <0 0x11010000 0 1171 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 1172 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen C 1173 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen C 1174 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_a 1175 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent 1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled"; 1177 status = "disabled";
1178 }; 1178 };
1179 1179
1180 spi2: spi@11012000 { 1180 spi2: spi@11012000 {
1181 compatible = "mediate 1181 compatible = "mediatek,mt8195-spi",
1182 "mediate 1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>; 1183 #address-cells = <1>;
1184 #size-cells = <0>; 1184 #size-cells = <0>;
1185 reg = <0 0x11012000 0 1185 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 1186 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen C 1187 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen C 1188 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_a 1189 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent 1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled"; 1191 status = "disabled";
1192 }; 1192 };
1193 1193
1194 spi3: spi@11013000 { 1194 spi3: spi@11013000 {
1195 compatible = "mediate 1195 compatible = "mediatek,mt8195-spi",
1196 "mediate 1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>; 1197 #address-cells = <1>;
1198 #size-cells = <0>; 1198 #size-cells = <0>;
1199 reg = <0 0x11013000 0 1199 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen C 1201 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen C 1202 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_a 1203 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent 1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled"; 1205 status = "disabled";
1206 }; 1206 };
1207 1207
1208 spi4: spi@11018000 { 1208 spi4: spi@11018000 {
1209 compatible = "mediate 1209 compatible = "mediatek,mt8195-spi",
1210 "mediate 1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>; 1211 #address-cells = <1>;
1212 #size-cells = <0>; 1212 #size-cells = <0>;
1213 reg = <0 0x11018000 0 1213 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 1214 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen C 1215 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen C 1216 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_a 1217 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent 1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled"; 1219 status = "disabled";
1220 }; 1220 };
1221 1221
1222 spi5: spi@11019000 { 1222 spi5: spi@11019000 {
1223 compatible = "mediate 1223 compatible = "mediatek,mt8195-spi",
1224 "mediate 1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>; 1225 #address-cells = <1>;
1226 #size-cells = <0>; 1226 #size-cells = <0>;
1227 reg = <0 0x11019000 0 1227 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 1228 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen C 1229 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen C 1230 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_a 1231 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent 1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled"; 1233 status = "disabled";
1234 }; 1234 };
1235 1235
1236 spis0: spi@1101d000 { 1236 spis0: spi@1101d000 {
1237 compatible = "mediate 1237 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 1238 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 1239 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_a 1240 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi"; 1241 clock-names = "spi";
1242 assigned-clocks = <&t 1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parent 1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled"; 1244 status = "disabled";
1245 }; 1245 };
1246 1246
1247 spis1: spi@1101e000 { 1247 spis1: spi@1101e000 {
1248 compatible = "mediate 1248 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 1249 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 1250 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_a 1251 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi"; 1252 clock-names = "spi";
1253 assigned-clocks = <&t 1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parent 1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled"; 1255 status = "disabled";
1256 }; 1256 };
1257 1257
1258 eth: ethernet@11021000 { 1258 eth: ethernet@11021000 {
1259 compatible = "mediate 1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260 reg = <0 0x11021000 0 1260 reg = <0 0x11021000 0 0x4000>;
1261 interrupts = <GIC_SPI 1261 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262 interrupt-names = "ma 1262 interrupt-names = "macirq";
1263 clock-names = "axi", 1263 clock-names = "axi",
1264 "apb", 1264 "apb",
1265 "mac_ma 1265 "mac_main",
1266 "ptp_re 1266 "ptp_ref",
1267 "rmii_i 1267 "rmii_internal",
1268 "mac_cg 1268 "mac_cg";
1269 clocks = <&pericfg_ao 1269 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270 <&pericfg_ao 1270 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271 <&topckgen C 1271 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen C 1272 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen C 1273 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274 <&pericfg_ao 1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275 assigned-clocks = <&t 1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&t 1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&t 1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parent 1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 1279 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 1280 <&topckgen CLK_TOP_ETHPLL_D10>;
1281 power-domains = <&spm 1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282 mediatek,pericfg = <& 1282 mediatek,pericfg = <&infracfg_ao>;
1283 snps,axi-config = <&s 1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = 1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = 1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1286 snps,txpbl = <16>; 1286 snps,txpbl = <16>;
1287 snps,rxpbl = <16>; 1287 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>; 1288 snps,clk-csr = <0>;
1289 status = "disabled"; 1289 status = "disabled";
1290 1290
1291 mdio { 1291 mdio {
1292 compatible = 1292 compatible = "snps,dwmac-mdio";
1293 #address-cell 1293 #address-cells = <1>;
1294 #size-cells = 1294 #size-cells = <0>;
1295 }; 1295 };
1296 1296
1297 stmmac_axi_setup: stm 1297 stmmac_axi_setup: stmmac-axi-config {
1298 snps,wr_osr_l 1298 snps,wr_osr_lmt = <0x7>;
1299 snps,rd_osr_l 1299 snps,rd_osr_lmt = <0x7>;
1300 snps,blen = < 1300 snps,blen = <0 0 0 0 16 8 4>;
1301 }; 1301 };
1302 1302
1303 mtl_rx_setup: rx-queu 1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queue 1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched 1305 snps,rx-sched-sp;
1306 queue0 { 1306 queue0 {
1307 snps, 1307 snps,dcb-algorithm;
1308 snps, 1308 snps,map-to-dma-channel = <0x0>;
1309 }; 1309 };
1310 queue1 { 1310 queue1 {
1311 snps, 1311 snps,dcb-algorithm;
1312 snps, 1312 snps,map-to-dma-channel = <0x0>;
1313 }; 1313 };
1314 queue2 { 1314 queue2 {
1315 snps, 1315 snps,dcb-algorithm;
1316 snps, 1316 snps,map-to-dma-channel = <0x0>;
1317 }; 1317 };
1318 queue3 { 1318 queue3 {
1319 snps, 1319 snps,dcb-algorithm;
1320 snps, 1320 snps,map-to-dma-channel = <0x0>;
1321 }; 1321 };
1322 }; 1322 };
1323 1323
1324 mtl_tx_setup: tx-queu 1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queue 1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched 1326 snps,tx-sched-wrr;
1327 queue0 { 1327 queue0 {
1328 snps, 1328 snps,weight = <0x10>;
1329 snps, 1329 snps,dcb-algorithm;
1330 snps, 1330 snps,priority = <0x0>;
1331 }; 1331 };
1332 queue1 { 1332 queue1 {
1333 snps, 1333 snps,weight = <0x11>;
1334 snps, 1334 snps,dcb-algorithm;
1335 snps, 1335 snps,priority = <0x1>;
1336 }; 1336 };
1337 queue2 { 1337 queue2 {
1338 snps, 1338 snps,weight = <0x12>;
1339 snps, 1339 snps,dcb-algorithm;
1340 snps, 1340 snps,priority = <0x2>;
1341 }; 1341 };
1342 queue3 { 1342 queue3 {
1343 snps, 1343 snps,weight = <0x13>;
1344 snps, 1344 snps,dcb-algorithm;
1345 snps, 1345 snps,priority = <0x3>;
1346 }; 1346 };
1347 }; 1347 };
1348 }; 1348 };
1349 1349
1350 ssusb0: usb@11201000 { !! 1350 xhci0: usb@11200000 {
1351 compatible = "mediate !! 1351 compatible = "mediatek,mt8195-xhci",
1352 reg = <0 0x11201000 0 !! 1352 "mediatek,mtk-xhci";
>> 1353 reg = <0 0x11200000 0 0x1000>,
>> 1354 <0 0x11203e00 0 0x0100>;
1353 reg-names = "mac", "i 1355 reg-names = "mac", "ippc";
1354 ranges = <0 0 0 0x112 !! 1356 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1355 #address-cells = <2>; !! 1357 phys = <&u2port0 PHY_TYPE_USB2>,
1356 #size-cells = <2>; !! 1358 <&u3port0 PHY_TYPE_USB3>;
1357 interrupts = <GIC_SPI !! 1359 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
>> 1360 <&topckgen CLK_TOP_SSUSB_XHCI>;
>> 1361 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
>> 1362 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1358 clocks = <&infracfg_a 1363 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen C 1364 <&topckgen CLK_TOP_SSUSB_REF>,
>> 1365 <&apmixedsys CLK_APMIXED_USB1PLL>,
>> 1366 <&clk26m>,
1360 <&infracfg_a 1367 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1361 clock-names = "sys_ck !! 1368 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1362 phys = <&u2port0 PHY_ !! 1369 "xhci_ck";
1363 wakeup-source; <<
1364 mediatek,syscon-wakeu 1370 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
>> 1371 wakeup-source;
1365 status = "disabled"; 1372 status = "disabled";
1366 <<
1367 xhci0: usb@0 { <<
1368 compatible = <<
1369 reg = <0 0 0 <<
1370 reg-names = " <<
1371 interrupts = <<
1372 assigned-cloc <<
1373 <<
1374 assigned-cloc <<
1375 <<
1376 clocks = <&in <<
1377 <&to <<
1378 <&ap <<
1379 <&cl <<
1380 <&in <<
1381 clock-names = <<
1382 status = "dis <<
1383 }; <<
1384 }; 1373 };
1385 1374
1386 mmc0: mmc@11230000 { 1375 mmc0: mmc@11230000 {
1387 compatible = "mediate 1376 compatible = "mediatek,mt8195-mmc",
1388 "mediate 1377 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 1378 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 1379 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen C 1381 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_a 1382 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_a 1383 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source 1384 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled"; 1385 status = "disabled";
1397 }; 1386 };
1398 1387
1399 mmc1: mmc@11240000 { 1388 mmc1: mmc@11240000 {
1400 compatible = "mediate 1389 compatible = "mediatek,mt8195-mmc",
1401 "mediate 1390 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 1391 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 1392 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 1393 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen C 1394 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_a 1395 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_a 1396 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source 1397 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&t 1398 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parent 1399 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled"; 1400 status = "disabled";
1412 }; 1401 };
1413 1402
1414 mmc2: mmc@11250000 { 1403 mmc2: mmc@11250000 {
1415 compatible = "mediate 1404 compatible = "mediatek,mt8195-mmc",
1416 "mediate 1405 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 1406 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 1407 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 1408 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen C 1409 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_a 1410 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_a 1411 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source 1412 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&t 1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parent 1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled"; 1415 status = "disabled";
1427 }; 1416 };
1428 1417
1429 lvts_mcu: thermal-sensor@1127 1418 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediate 1419 compatible = "mediatek,mt8195-lvts-mcu";
1431 reg = <0 0x11278000 0 1420 reg = <0 0x11278000 0 0x1000>;
1432 interrupts = <GIC_SPI 1421 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1433 clocks = <&infracfg_a 1422 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1434 resets = <&infracfg_a 1423 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1435 nvmem-cells = <&lvts_ 1424 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "l 1425 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells 1426 #thermal-sensor-cells = <1>;
1438 }; 1427 };
1439 1428
1440 xhci1: usb@11290000 { 1429 xhci1: usb@11290000 {
1441 compatible = "mediate 1430 compatible = "mediatek,mt8195-xhci",
1442 "mediate 1431 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 1432 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 1433 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "i 1434 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 1435 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_ !! 1436 phys = <&u2port1 PHY_TYPE_USB2>;
1448 assigned-clocks = <&t 1437 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&t 1438 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parent 1439 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 1440 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao 1441 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen C 1442 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys 1443 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>, 1444 <&clk26m>,
1456 <&pericfg_ao 1445 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck 1446 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_c 1447 "xhci_ck";
1459 mediatek,syscon-wakeu 1448 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source; 1449 wakeup-source;
1461 status = "disabled"; 1450 status = "disabled";
1462 }; 1451 };
1463 1452
1464 ssusb2: usb@112a1000 { !! 1453 xhci2: usb@112a0000 {
1465 compatible = "mediate !! 1454 compatible = "mediatek,mt8195-xhci",
1466 reg = <0 0x112a1000 0 !! 1455 "mediatek,mtk-xhci";
>> 1456 reg = <0 0x112a0000 0 0x1000>,
>> 1457 <0 0x112a3e00 0 0x0100>;
1467 reg-names = "mac", "i 1458 reg-names = "mac", "ippc";
1468 ranges = <0 0 0 0x112 !! 1459 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1469 #address-cells = <2>; !! 1460 phys = <&u2port2 PHY_TYPE_USB2>;
1470 #size-cells = <2>; !! 1461 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1471 interrupts = <GIC_SPI !! 1462 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1472 assigned-clocks = <&t !! 1463 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1473 assigned-clock-parent !! 1464 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1474 clocks = <&pericfg_ao 1465 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen C 1466 <&topckgen CLK_TOP_SSUSB_P2_REF>,
>> 1467 <&clk26m>,
>> 1468 <&clk26m>,
1476 <&pericfg_ao 1469 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1477 clock-names = "sys_ck !! 1470 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1478 phys = <&u2port2 PHY_ !! 1471 "xhci_ck";
1479 wakeup-source; <<
1480 mediatek,syscon-wakeu 1472 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
>> 1473 wakeup-source;
1481 status = "disabled"; 1474 status = "disabled";
1482 <<
1483 xhci2: usb@0 { <<
1484 compatible = <<
1485 reg = <0 0 0 <<
1486 reg-names = " <<
1487 interrupts = <<
1488 assigned-cloc <<
1489 assigned-cloc <<
1490 clocks = <&pe <<
1491 clock-names = <<
1492 status = "dis <<
1493 }; <<
1494 }; 1475 };
1495 1476
1496 ssusb3: usb@112b1000 { !! 1477 xhci3: usb@112b0000 {
1497 compatible = "mediate !! 1478 compatible = "mediatek,mt8195-xhci",
1498 reg = <0 0x112b1000 0 !! 1479 "mediatek,mtk-xhci";
>> 1480 reg = <0 0x112b0000 0 0x1000>,
>> 1481 <0 0x112b3e00 0 0x0100>;
1499 reg-names = "mac", "i 1482 reg-names = "mac", "ippc";
1500 ranges = <0 0 0 0x112 !! 1483 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1501 #address-cells = <2>; !! 1484 phys = <&u2port3 PHY_TYPE_USB2>;
1502 #size-cells = <2>; !! 1485 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1503 interrupts = <GIC_SPI !! 1486 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1504 assigned-clocks = <&t !! 1487 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1505 assigned-clock-parent !! 1488 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clocks = <&pericfg_ao 1489 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen C 1490 <&topckgen CLK_TOP_SSUSB_P3_REF>,
>> 1491 <&clk26m>,
>> 1492 <&clk26m>,
1508 <&pericfg_ao 1493 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1509 clock-names = "sys_ck !! 1494 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1510 phys = <&u2port3 PHY_ !! 1495 "xhci_ck";
1511 wakeup-source; <<
1512 mediatek,syscon-wakeu 1496 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
>> 1497 wakeup-source;
1513 status = "disabled"; 1498 status = "disabled";
1514 <<
1515 xhci3: usb@0 { <<
1516 compatible = <<
1517 reg = <0 0 0 <<
1518 reg-names = " <<
1519 interrupts = <<
1520 assigned-cloc <<
1521 assigned-cloc <<
1522 clocks = <&pe <<
1523 clock-names = <<
1524 status = "dis <<
1525 }; <<
1526 }; 1499 };
1527 1500
1528 pcie0: pcie@112f0000 { 1501 pcie0: pcie@112f0000 {
1529 compatible = "mediate 1502 compatible = "mediatek,mt8195-pcie",
1530 "mediate 1503 "mediatek,mt8192-pcie";
1531 device_type = "pci"; 1504 device_type = "pci";
1532 #address-cells = <3>; 1505 #address-cells = <3>;
1533 #size-cells = <2>; 1506 #size-cells = <2>;
1534 reg = <0 0x112f0000 0 1507 reg = <0 0x112f0000 0 0x4000>;
1535 reg-names = "pcie-mac 1508 reg-names = "pcie-mac";
1536 interrupts = <GIC_SPI 1509 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1537 bus-range = <0x00 0xf 1510 bus-range = <0x00 0xff>;
1538 ranges = <0x81000000 1511 ranges = <0x81000000 0 0x20000000
1539 0x0 0x20000 1512 0x0 0x20000000 0 0x200000>,
1540 <0x82000000 1513 <0x82000000 0 0x20200000
1541 0x0 0x20200 1514 0x0 0x20200000 0 0x3e00000>;
1542 1515
1543 iommu-map = <0 &iommu 1516 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0 1517 iommu-map-mask = <0x0>;
1545 1518
1546 clocks = <&infracfg_a 1519 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 <&infracfg_a 1520 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 <&infracfg_a 1521 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 <&infracfg_a 1522 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 <&infracfg_a 1523 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1551 <&pericfg_ao 1524 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1552 clock-names = "pl_250 1525 clock-names = "pl_250m", "tl_26m", "tl_96m",
1553 "tl_32k 1526 "tl_32k", "peri_26m", "peri_mem";
1554 assigned-clocks = <&t 1527 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parent 1528 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1556 1529
1557 phys = <&pciephy>; 1530 phys = <&pciephy>;
1558 phy-names = "pcie-phy 1531 phy-names = "pcie-phy";
1559 1532
1560 power-domains = <&spm 1533 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1561 1534
1562 resets = <&infracfg_a 1535 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1563 reset-names = "mac"; 1536 reset-names = "mac";
1564 1537
1565 #interrupt-cells = <1 1538 #interrupt-cells = <1>;
1566 interrupt-map-mask = 1539 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 1540 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 1541 <0 0 0 2 &pcie_intc0 1>,
1569 <0 0 1542 <0 0 0 3 &pcie_intc0 2>,
1570 <0 0 1543 <0 0 0 4 &pcie_intc0 3>;
1571 status = "disabled"; 1544 status = "disabled";
1572 1545
1573 pcie_intc0: interrupt 1546 pcie_intc0: interrupt-controller {
1574 interrupt-con 1547 interrupt-controller;
1575 #address-cell 1548 #address-cells = <0>;
1576 #interrupt-ce 1549 #interrupt-cells = <1>;
1577 }; 1550 };
1578 }; 1551 };
1579 1552
1580 pcie1: pcie@112f8000 { 1553 pcie1: pcie@112f8000 {
1581 compatible = "mediate 1554 compatible = "mediatek,mt8195-pcie",
1582 "mediate 1555 "mediatek,mt8192-pcie";
1583 device_type = "pci"; 1556 device_type = "pci";
1584 #address-cells = <3>; 1557 #address-cells = <3>;
1585 #size-cells = <2>; 1558 #size-cells = <2>;
1586 reg = <0 0x112f8000 0 1559 reg = <0 0x112f8000 0 0x4000>;
1587 reg-names = "pcie-mac 1560 reg-names = "pcie-mac";
1588 interrupts = <GIC_SPI 1561 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1589 bus-range = <0x00 0xf 1562 bus-range = <0x00 0xff>;
1590 ranges = <0x81000000 1563 ranges = <0x81000000 0 0x24000000
1591 0x0 0x24000 1564 0x0 0x24000000 0 0x200000>,
1592 <0x82000000 1565 <0x82000000 0 0x24200000
1593 0x0 0x24200 1566 0x0 0x24200000 0 0x3e00000>;
1594 1567
1595 iommu-map = <0 &iommu 1568 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0 1569 iommu-map-mask = <0x0>;
1597 1570
1598 clocks = <&infracfg_a 1571 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1599 <&clk26m>, 1572 <&clk26m>,
1600 <&infracfg_a 1573 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1601 <&clk26m>, 1574 <&clk26m>,
1602 <&infracfg_a 1575 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1603 /* Designer 1576 /* Designer has connect pcie1 with peri_mem_p0 clock */
1604 <&pericfg_ao 1577 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1605 clock-names = "pl_250 1578 clock-names = "pl_250m", "tl_26m", "tl_96m",
1606 "tl_32k 1579 "tl_32k", "peri_26m", "peri_mem";
1607 assigned-clocks = <&t 1580 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parent 1581 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1609 1582
1610 phys = <&u3port1 PHY_ 1583 phys = <&u3port1 PHY_TYPE_PCIE>;
1611 phy-names = "pcie-phy 1584 phy-names = "pcie-phy";
1612 power-domains = <&spm 1585 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1613 1586
1614 resets = <&infracfg_a 1587 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1615 reset-names = "mac"; 1588 reset-names = "mac";
1616 1589
1617 #interrupt-cells = <1 1590 #interrupt-cells = <1>;
1618 interrupt-map-mask = 1591 interrupt-map-mask = <0 0 0 7>;
1619 interrupt-map = <0 0 1592 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1620 <0 0 1593 <0 0 0 2 &pcie_intc1 1>,
1621 <0 0 1594 <0 0 0 3 &pcie_intc1 2>,
1622 <0 0 1595 <0 0 0 4 &pcie_intc1 3>;
1623 status = "disabled"; 1596 status = "disabled";
1624 1597
1625 pcie_intc1: interrupt 1598 pcie_intc1: interrupt-controller {
1626 interrupt-con 1599 interrupt-controller;
1627 #address-cell 1600 #address-cells = <0>;
1628 #interrupt-ce 1601 #interrupt-cells = <1>;
1629 }; 1602 };
1630 }; 1603 };
1631 1604
1632 nor_flash: spi@1132c000 { 1605 nor_flash: spi@1132c000 {
1633 compatible = "mediate 1606 compatible = "mediatek,mt8195-nor",
1634 "mediate 1607 "mediatek,mt8173-nor";
1635 reg = <0 0x1132c000 0 1608 reg = <0 0x1132c000 0 0x1000>;
1636 interrupts = <GIC_SPI 1609 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1637 clocks = <&topckgen C 1610 clocks = <&topckgen CLK_TOP_SPINOR>,
1638 <&pericfg_ao 1611 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1639 <&pericfg_ao 1612 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1640 clock-names = "spi", 1613 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>; 1614 #address-cells = <1>;
1642 #size-cells = <0>; 1615 #size-cells = <0>;
1643 status = "disabled"; 1616 status = "disabled";
1644 }; 1617 };
1645 1618
1646 efuse: efuse@11c10000 { 1619 efuse: efuse@11c10000 {
1647 compatible = "mediate 1620 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1648 reg = <0 0x11c10000 0 1621 reg = <0 0x11c10000 0 0x1000>;
1649 #address-cells = <1>; 1622 #address-cells = <1>;
1650 #size-cells = <1>; 1623 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx 1624 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 reg = <0x184 1625 reg = <0x184 0x1>;
1653 bits = <0 5>; 1626 bits = <0 5>;
1654 }; 1627 };
1655 u3_rx_imp_p0: usb3-rx 1628 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 reg = <0x184 1629 reg = <0x184 0x2>;
1657 bits = <5 5>; 1630 bits = <5 5>;
1658 }; 1631 };
1659 u3_intr_p0: usb3-intr 1632 u3_intr_p0: usb3-intr@185 {
1660 reg = <0x185 1633 reg = <0x185 0x1>;
1661 bits = <2 6>; 1634 bits = <2 6>;
1662 }; 1635 };
1663 comb_tx_imp_p1: usb3- 1636 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 reg = <0x186 1637 reg = <0x186 0x1>;
1665 bits = <0 5>; 1638 bits = <0 5>;
1666 }; 1639 };
1667 comb_rx_imp_p1: usb3- 1640 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 reg = <0x186 1641 reg = <0x186 0x2>;
1669 bits = <5 5>; 1642 bits = <5 5>;
1670 }; 1643 };
1671 comb_intr_p1: usb3-in 1644 comb_intr_p1: usb3-intr@187 {
1672 reg = <0x187 1645 reg = <0x187 0x1>;
1673 bits = <2 6>; 1646 bits = <2 6>;
1674 }; 1647 };
1675 u2_intr_p0: usb2-intr 1648 u2_intr_p0: usb2-intr-p0@188,1 {
1676 reg = <0x188 1649 reg = <0x188 0x1>;
1677 bits = <0 5>; 1650 bits = <0 5>;
1678 }; 1651 };
1679 u2_intr_p1: usb2-intr 1652 u2_intr_p1: usb2-intr-p1@188,2 {
1680 reg = <0x188 1653 reg = <0x188 0x2>;
1681 bits = <5 5>; 1654 bits = <5 5>;
1682 }; 1655 };
1683 u2_intr_p2: usb2-intr 1656 u2_intr_p2: usb2-intr-p2@189,1 {
1684 reg = <0x189 1657 reg = <0x189 0x1>;
1685 bits = <2 5>; 1658 bits = <2 5>;
1686 }; 1659 };
1687 u2_intr_p3: usb2-intr 1660 u2_intr_p3: usb2-intr-p3@189,2 {
1688 reg = <0x189 1661 reg = <0x189 0x2>;
1689 bits = <7 5>; 1662 bits = <7 5>;
1690 }; 1663 };
1691 pciephy_rx_ln1: pciep 1664 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1692 reg = <0x190 1665 reg = <0x190 0x1>;
1693 bits = <0 4>; 1666 bits = <0 4>;
1694 }; 1667 };
1695 pciephy_tx_ln1_nmos: 1668 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1696 reg = <0x190 1669 reg = <0x190 0x1>;
1697 bits = <4 4>; 1670 bits = <4 4>;
1698 }; 1671 };
1699 pciephy_tx_ln1_pmos: 1672 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1700 reg = <0x191 1673 reg = <0x191 0x1>;
1701 bits = <0 4>; 1674 bits = <0 4>;
1702 }; 1675 };
1703 pciephy_rx_ln0: pciep 1676 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1704 reg = <0x191 1677 reg = <0x191 0x1>;
1705 bits = <4 4>; 1678 bits = <4 4>;
1706 }; 1679 };
1707 pciephy_tx_ln0_nmos: 1680 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1708 reg = <0x192 1681 reg = <0x192 0x1>;
1709 bits = <0 4>; 1682 bits = <0 4>;
1710 }; 1683 };
1711 pciephy_tx_ln0_pmos: 1684 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1712 reg = <0x192 1685 reg = <0x192 0x1>;
1713 bits = <4 4>; 1686 bits = <4 4>;
1714 }; 1687 };
1715 pciephy_glb_intr: pci 1688 pciephy_glb_intr: pciephy-glb-intr@193 {
1716 reg = <0x193 1689 reg = <0x193 0x1>;
1717 bits = <0 4>; 1690 bits = <0 4>;
1718 }; 1691 };
1719 dp_calibration: dp-da 1692 dp_calibration: dp-data@1ac {
1720 reg = <0x1ac 1693 reg = <0x1ac 0x10>;
1721 }; 1694 };
1722 lvts_efuse_data1: lvt 1695 lvts_efuse_data1: lvts1-calib@1bc {
1723 reg = <0x1bc 1696 reg = <0x1bc 0x14>;
1724 }; 1697 };
1725 lvts_efuse_data2: lvt 1698 lvts_efuse_data2: lvts2-calib@1d0 {
1726 reg = <0x1d0 1699 reg = <0x1d0 0x38>;
1727 }; 1700 };
1728 svs_calib_data: svs-c 1701 svs_calib_data: svs-calib@580 {
1729 reg = <0x580 1702 reg = <0x580 0x64>;
1730 }; 1703 };
1731 socinfo-data1@7a0 { <<
1732 reg = <0x7a0 <<
1733 }; <<
1734 }; 1704 };
1735 1705
1736 u3phy2: t-phy@11c40000 { 1706 u3phy2: t-phy@11c40000 {
1737 compatible = "mediate 1707 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>; 1708 #address-cells = <1>;
1739 #size-cells = <1>; 1709 #size-cells = <1>;
1740 ranges = <0 0 0x11c40 1710 ranges = <0 0 0x11c40000 0x700>;
1741 status = "disabled"; 1711 status = "disabled";
1742 1712
1743 u2port2: usb-phy@0 { 1713 u2port2: usb-phy@0 {
1744 reg = <0x0 0x 1714 reg = <0x0 0x700>;
1745 clocks = <&to 1715 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1746 clock-names = 1716 clock-names = "ref";
1747 #phy-cells = 1717 #phy-cells = <1>;
1748 }; 1718 };
1749 }; 1719 };
1750 1720
1751 u3phy3: t-phy@11c50000 { 1721 u3phy3: t-phy@11c50000 {
1752 compatible = "mediate 1722 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>; 1723 #address-cells = <1>;
1754 #size-cells = <1>; 1724 #size-cells = <1>;
1755 ranges = <0 0 0x11c50 1725 ranges = <0 0 0x11c50000 0x700>;
1756 status = "disabled"; 1726 status = "disabled";
1757 1727
1758 u2port3: usb-phy@0 { 1728 u2port3: usb-phy@0 {
1759 reg = <0x0 0x 1729 reg = <0x0 0x700>;
1760 clocks = <&to 1730 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1761 clock-names = 1731 clock-names = "ref";
1762 #phy-cells = 1732 #phy-cells = <1>;
1763 }; 1733 };
1764 }; 1734 };
1765 1735
1766 mipi_tx0: dsi-phy@11c80000 { 1736 mipi_tx0: dsi-phy@11c80000 {
1767 compatible = "mediate 1737 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1768 reg = <0 0x11c80000 0 1738 reg = <0 0x11c80000 0 0x1000>;
1769 clocks = <&clk26m>; 1739 clocks = <&clk26m>;
1770 clock-output-names = 1740 clock-output-names = "mipi_tx0_pll";
1771 #clock-cells = <0>; 1741 #clock-cells = <0>;
1772 #phy-cells = <0>; 1742 #phy-cells = <0>;
1773 status = "disabled"; 1743 status = "disabled";
1774 }; 1744 };
1775 1745
1776 mipi_tx1: dsi-phy@11c90000 { 1746 mipi_tx1: dsi-phy@11c90000 {
1777 compatible = "mediate 1747 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1778 reg = <0 0x11c90000 0 1748 reg = <0 0x11c90000 0 0x1000>;
1779 clocks = <&clk26m>; 1749 clocks = <&clk26m>;
1780 clock-output-names = 1750 clock-output-names = "mipi_tx1_pll";
1781 #clock-cells = <0>; 1751 #clock-cells = <0>;
1782 #phy-cells = <0>; 1752 #phy-cells = <0>;
1783 status = "disabled"; 1753 status = "disabled";
1784 }; 1754 };
1785 1755
1786 i2c5: i2c@11d00000 { 1756 i2c5: i2c@11d00000 {
1787 compatible = "mediate 1757 compatible = "mediatek,mt8195-i2c",
1788 "mediate 1758 "mediatek,mt8192-i2c";
1789 reg = <0 0x11d00000 0 1759 reg = <0 0x11d00000 0 0x1000>,
1790 <0 0x10220580 0 1760 <0 0x10220580 0 0x80>;
1791 interrupts = <GIC_SPI 1761 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1792 clock-div = <1>; 1762 clock-div = <1>;
1793 clocks = <&imp_iic_wr 1763 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1794 <&infracfg_a 1764 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795 clock-names = "main", 1765 clock-names = "main", "dma";
1796 #address-cells = <1>; 1766 #address-cells = <1>;
1797 #size-cells = <0>; 1767 #size-cells = <0>;
1798 status = "disabled"; 1768 status = "disabled";
1799 }; 1769 };
1800 1770
1801 i2c6: i2c@11d01000 { 1771 i2c6: i2c@11d01000 {
1802 compatible = "mediate 1772 compatible = "mediatek,mt8195-i2c",
1803 "mediate 1773 "mediatek,mt8192-i2c";
1804 reg = <0 0x11d01000 0 1774 reg = <0 0x11d01000 0 0x1000>,
1805 <0 0x10220600 0 1775 <0 0x10220600 0 0x80>;
1806 interrupts = <GIC_SPI 1776 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1807 clock-div = <1>; 1777 clock-div = <1>;
1808 clocks = <&imp_iic_wr 1778 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1809 <&infracfg_a 1779 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1810 clock-names = "main", 1780 clock-names = "main", "dma";
1811 #address-cells = <1>; 1781 #address-cells = <1>;
1812 #size-cells = <0>; 1782 #size-cells = <0>;
1813 status = "disabled"; 1783 status = "disabled";
1814 }; 1784 };
1815 1785
1816 i2c7: i2c@11d02000 { 1786 i2c7: i2c@11d02000 {
1817 compatible = "mediate 1787 compatible = "mediatek,mt8195-i2c",
1818 "mediate 1788 "mediatek,mt8192-i2c";
1819 reg = <0 0x11d02000 0 1789 reg = <0 0x11d02000 0 0x1000>,
1820 <0 0x10220680 0 1790 <0 0x10220680 0 0x80>;
1821 interrupts = <GIC_SPI 1791 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1822 clock-div = <1>; 1792 clock-div = <1>;
1823 clocks = <&imp_iic_wr 1793 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1824 <&infracfg_a 1794 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1825 clock-names = "main", 1795 clock-names = "main", "dma";
1826 #address-cells = <1>; 1796 #address-cells = <1>;
1827 #size-cells = <0>; 1797 #size-cells = <0>;
1828 status = "disabled"; 1798 status = "disabled";
1829 }; 1799 };
1830 1800
1831 imp_iic_wrap_s: clock-control 1801 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediate 1802 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1833 reg = <0 0x11d03000 0 1803 reg = <0 0x11d03000 0 0x1000>;
1834 #clock-cells = <1>; 1804 #clock-cells = <1>;
1835 }; 1805 };
1836 1806
1837 i2c0: i2c@11e00000 { 1807 i2c0: i2c@11e00000 {
1838 compatible = "mediate 1808 compatible = "mediatek,mt8195-i2c",
1839 "mediate 1809 "mediatek,mt8192-i2c";
1840 reg = <0 0x11e00000 0 1810 reg = <0 0x11e00000 0 0x1000>,
1841 <0 0x10220080 0 1811 <0 0x10220080 0 0x80>;
1842 interrupts = <GIC_SPI 1812 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1843 clock-div = <1>; 1813 clock-div = <1>;
1844 clocks = <&imp_iic_wr 1814 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1845 <&infracfg_a 1815 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846 clock-names = "main", 1816 clock-names = "main", "dma";
1847 #address-cells = <1>; 1817 #address-cells = <1>;
1848 #size-cells = <0>; 1818 #size-cells = <0>;
1849 status = "disabled"; 1819 status = "disabled";
1850 }; 1820 };
1851 1821
1852 i2c1: i2c@11e01000 { 1822 i2c1: i2c@11e01000 {
1853 compatible = "mediate 1823 compatible = "mediatek,mt8195-i2c",
1854 "mediate 1824 "mediatek,mt8192-i2c";
1855 reg = <0 0x11e01000 0 1825 reg = <0 0x11e01000 0 0x1000>,
1856 <0 0x10220200 0 1826 <0 0x10220200 0 0x80>;
1857 interrupts = <GIC_SPI 1827 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clock-div = <1>; 1828 clock-div = <1>;
1859 clocks = <&imp_iic_wr 1829 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1860 <&infracfg_a 1830 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861 clock-names = "main", 1831 clock-names = "main", "dma";
1862 #address-cells = <1>; 1832 #address-cells = <1>;
1863 #size-cells = <0>; 1833 #size-cells = <0>;
1864 status = "disabled"; 1834 status = "disabled";
1865 }; 1835 };
1866 1836
1867 i2c2: i2c@11e02000 { 1837 i2c2: i2c@11e02000 {
1868 compatible = "mediate 1838 compatible = "mediatek,mt8195-i2c",
1869 "mediate 1839 "mediatek,mt8192-i2c";
1870 reg = <0 0x11e02000 0 1840 reg = <0 0x11e02000 0 0x1000>,
1871 <0 0x10220380 0 1841 <0 0x10220380 0 0x80>;
1872 interrupts = <GIC_SPI 1842 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1873 clock-div = <1>; 1843 clock-div = <1>;
1874 clocks = <&imp_iic_wr 1844 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1875 <&infracfg_a 1845 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876 clock-names = "main", 1846 clock-names = "main", "dma";
1877 #address-cells = <1>; 1847 #address-cells = <1>;
1878 #size-cells = <0>; 1848 #size-cells = <0>;
1879 status = "disabled"; 1849 status = "disabled";
1880 }; 1850 };
1881 1851
1882 i2c3: i2c@11e03000 { 1852 i2c3: i2c@11e03000 {
1883 compatible = "mediate 1853 compatible = "mediatek,mt8195-i2c",
1884 "mediate 1854 "mediatek,mt8192-i2c";
1885 reg = <0 0x11e03000 0 1855 reg = <0 0x11e03000 0 0x1000>,
1886 <0 0x10220480 0 1856 <0 0x10220480 0 0x80>;
1887 interrupts = <GIC_SPI 1857 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clock-div = <1>; 1858 clock-div = <1>;
1889 clocks = <&imp_iic_wr 1859 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1890 <&infracfg_a 1860 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1891 clock-names = "main", 1861 clock-names = "main", "dma";
1892 #address-cells = <1>; 1862 #address-cells = <1>;
1893 #size-cells = <0>; 1863 #size-cells = <0>;
1894 status = "disabled"; 1864 status = "disabled";
1895 }; 1865 };
1896 1866
1897 i2c4: i2c@11e04000 { 1867 i2c4: i2c@11e04000 {
1898 compatible = "mediate 1868 compatible = "mediatek,mt8195-i2c",
1899 "mediate 1869 "mediatek,mt8192-i2c";
1900 reg = <0 0x11e04000 0 1870 reg = <0 0x11e04000 0 0x1000>,
1901 <0 0x10220500 0 1871 <0 0x10220500 0 0x80>;
1902 interrupts = <GIC_SPI 1872 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1903 clock-div = <1>; 1873 clock-div = <1>;
1904 clocks = <&imp_iic_wr 1874 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1905 <&infracfg_a 1875 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1906 clock-names = "main", 1876 clock-names = "main", "dma";
1907 #address-cells = <1>; 1877 #address-cells = <1>;
1908 #size-cells = <0>; 1878 #size-cells = <0>;
1909 status = "disabled"; 1879 status = "disabled";
1910 }; 1880 };
1911 1881
1912 imp_iic_wrap_w: clock-control 1882 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediate 1883 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1914 reg = <0 0x11e05000 0 1884 reg = <0 0x11e05000 0 0x1000>;
1915 #clock-cells = <1>; 1885 #clock-cells = <1>;
1916 }; 1886 };
1917 1887
1918 u3phy1: t-phy@11e30000 { 1888 u3phy1: t-phy@11e30000 {
1919 compatible = "mediate 1889 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>; 1890 #address-cells = <1>;
1921 #size-cells = <1>; 1891 #size-cells = <1>;
1922 ranges = <0 0 0x11e30 1892 ranges = <0 0 0x11e30000 0xe00>;
1923 power-domains = <&spm 1893 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1924 status = "disabled"; 1894 status = "disabled";
1925 1895
1926 u2port1: usb-phy@0 { 1896 u2port1: usb-phy@0 {
1927 reg = <0x0 0x 1897 reg = <0x0 0x700>;
1928 clocks = <&to 1898 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1929 <&cl 1899 <&clk26m>;
1930 clock-names = 1900 clock-names = "ref", "da_ref";
1931 #phy-cells = 1901 #phy-cells = <1>;
1932 }; 1902 };
1933 1903
1934 u3port1: usb-phy@700 1904 u3port1: usb-phy@700 {
1935 reg = <0x700 1905 reg = <0x700 0x700>;
1936 clocks = <&ap 1906 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1937 <&to 1907 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1938 clock-names = 1908 clock-names = "ref", "da_ref";
1939 nvmem-cells = 1909 nvmem-cells = <&comb_intr_p1>,
1940 1910 <&comb_rx_imp_p1>,
1941 1911 <&comb_tx_imp_p1>;
1942 nvmem-cell-na 1912 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = 1913 #phy-cells = <1>;
1944 }; 1914 };
1945 }; 1915 };
1946 1916
1947 u3phy0: t-phy@11e40000 { 1917 u3phy0: t-phy@11e40000 {
1948 compatible = "mediate 1918 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>; 1919 #address-cells = <1>;
1950 #size-cells = <1>; 1920 #size-cells = <1>;
1951 ranges = <0 0 0x11e40 1921 ranges = <0 0 0x11e40000 0xe00>;
1952 status = "disabled"; 1922 status = "disabled";
1953 1923
1954 u2port0: usb-phy@0 { 1924 u2port0: usb-phy@0 {
1955 reg = <0x0 0x 1925 reg = <0x0 0x700>;
1956 clocks = <&to 1926 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1957 <&cl 1927 <&clk26m>;
1958 clock-names = 1928 clock-names = "ref", "da_ref";
1959 #phy-cells = 1929 #phy-cells = <1>;
1960 }; 1930 };
1961 1931
1962 u3port0: usb-phy@700 1932 u3port0: usb-phy@700 {
1963 reg = <0x700 1933 reg = <0x700 0x700>;
1964 clocks = <&ap 1934 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1965 <&to 1935 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1966 clock-names = 1936 clock-names = "ref", "da_ref";
1967 nvmem-cells = 1937 nvmem-cells = <&u3_intr_p0>,
1968 1938 <&u3_rx_imp_p0>,
1969 1939 <&u3_tx_imp_p0>;
1970 nvmem-cell-na 1940 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = 1941 #phy-cells = <1>;
1972 }; 1942 };
1973 }; 1943 };
1974 1944
1975 pciephy: phy@11e80000 { 1945 pciephy: phy@11e80000 {
1976 compatible = "mediate 1946 compatible = "mediatek,mt8195-pcie-phy";
1977 reg = <0 0x11e80000 0 1947 reg = <0 0x11e80000 0 0x10000>;
1978 reg-names = "sif"; 1948 reg-names = "sif";
1979 nvmem-cells = <&pciep 1949 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1980 <&pciep 1950 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1981 <&pciep 1951 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1982 <&pciep 1952 <&pciephy_rx_ln1>;
1983 nvmem-cell-names = "g 1953 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1984 "t 1954 "tx_ln0_nmos", "rx_ln0",
1985 "t 1955 "tx_ln1_pmos", "tx_ln1_nmos",
1986 "r 1956 "rx_ln1";
1987 power-domains = <&spm 1957 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1988 #phy-cells = <0>; 1958 #phy-cells = <0>;
1989 status = "disabled"; 1959 status = "disabled";
1990 }; 1960 };
1991 1961
1992 ufsphy: ufs-phy@11fa0000 { 1962 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediate 1963 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1994 reg = <0 0x11fa0000 0 1964 reg = <0 0x11fa0000 0 0xc000>;
1995 clocks = <&clk26m>, < 1965 clocks = <&clk26m>, <&clk26m>;
1996 clock-names = "unipro 1966 clock-names = "unipro", "mp";
1997 #phy-cells = <0>; 1967 #phy-cells = <0>;
1998 status = "disabled"; 1968 status = "disabled";
1999 }; 1969 };
2000 1970
2001 gpu: gpu@13000000 { 1971 gpu: gpu@13000000 {
2002 compatible = "mediate 1972 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2003 "arm,mal 1973 "arm,mali-valhall-jm";
2004 reg = <0 0x13000000 0 1974 reg = <0 0x13000000 0 0x4000>;
2005 1975
2006 clocks = <&mfgcfg CLK 1976 clocks = <&mfgcfg CLK_MFG_BG3D>;
2007 interrupts = <GIC_SPI 1977 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
2008 <GIC_SPI 1978 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
2009 <GIC_SPI 1979 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
2010 interrupt-names = "jo 1980 interrupt-names = "job", "mmu", "gpu";
2011 operating-points-v2 = 1981 operating-points-v2 = <&gpu_opp_table>;
2012 power-domains = <&spm 1982 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2013 <&spm 1983 <&spm MT8195_POWER_DOMAIN_MFG3>,
2014 <&spm 1984 <&spm MT8195_POWER_DOMAIN_MFG4>,
2015 <&spm 1985 <&spm MT8195_POWER_DOMAIN_MFG5>,
2016 <&spm 1986 <&spm MT8195_POWER_DOMAIN_MFG6>;
2017 power-domain-names = 1987 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2018 status = "disabled"; 1988 status = "disabled";
2019 }; 1989 };
2020 1990
2021 mfgcfg: clock-controller@13fb 1991 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediate 1992 compatible = "mediatek,mt8195-mfgcfg";
2023 reg = <0 0x13fbf000 0 1993 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>; 1994 #clock-cells = <1>;
2025 }; 1995 };
2026 1996
2027 vppsys0: syscon@14000000 { 1997 vppsys0: syscon@14000000 {
2028 compatible = "mediate 1998 compatible = "mediatek,mt8195-vppsys0", "syscon";
2029 reg = <0 0x14000000 0 1999 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>; 2000 #clock-cells = <1>;
2031 mediatek,gce-client-r 2001 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2032 }; 2002 };
2033 2003
2034 dma-controller@14001000 { 2004 dma-controller@14001000 {
2035 compatible = "mediate 2005 compatible = "mediatek,mt8195-mdp3-rdma";
2036 reg = <0 0x14001000 0 2006 reg = <0 0x14001000 0 0x1000>;
2037 mediatek,gce-client-r 2007 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = 2008 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2039 2009 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
2040 mediatek,scp = <&scp> <<
2041 power-domains = <&spm 2010 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2042 iommus = <&iommu_vpp 2011 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2043 clocks = <&vppsys0 CL 2012 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2044 mboxes = <&gce1 12 CM 2013 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2045 <&gce1 13 CM 2014 <&gce1 13 CMDQ_THR_PRIO_1>,
2046 <&gce1 14 CM 2015 <&gce1 14 CMDQ_THR_PRIO_1>,
2047 <&gce1 21 CM 2016 <&gce1 21 CMDQ_THR_PRIO_1>,
2048 <&gce1 22 CM 2017 <&gce1 22 CMDQ_THR_PRIO_1>;
2049 #dma-cells = <1>; 2018 #dma-cells = <1>;
2050 }; 2019 };
2051 2020
2052 display@14002000 { 2021 display@14002000 {
2053 compatible = "mediate 2022 compatible = "mediatek,mt8195-mdp3-fg";
2054 reg = <0 0x14002000 0 2023 reg = <0 0x14002000 0 0x1000>;
2055 mediatek,gce-client-r 2024 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2056 clocks = <&vppsys0 CL 2025 clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2057 }; 2026 };
2058 2027
2059 display@14003000 { 2028 display@14003000 {
2060 compatible = "mediate 2029 compatible = "mediatek,mt8195-mdp3-stitch";
2061 reg = <0 0x14003000 0 2030 reg = <0 0x14003000 0 0x1000>;
2062 mediatek,gce-client-r 2031 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2063 clocks = <&vppsys0 CL 2032 clocks = <&vppsys0 CLK_VPP0_STITCH>;
2064 }; 2033 };
2065 2034
2066 display@14004000 { 2035 display@14004000 {
2067 compatible = "mediate 2036 compatible = "mediatek,mt8195-mdp3-hdr";
2068 reg = <0 0x14004000 0 2037 reg = <0 0x14004000 0 0x1000>;
2069 mediatek,gce-client-r 2038 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2070 clocks = <&vppsys0 CL 2039 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2071 }; 2040 };
2072 2041
2073 display@14005000 { 2042 display@14005000 {
2074 compatible = "mediate 2043 compatible = "mediatek,mt8195-mdp3-aal";
2075 reg = <0 0x14005000 0 2044 reg = <0 0x14005000 0 0x1000>;
2076 interrupts = <GIC_SPI 2045 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
2077 mediatek,gce-client-r 2046 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2078 clocks = <&vppsys0 CL 2047 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2079 power-domains = <&spm 2048 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2080 }; 2049 };
2081 2050
2082 display@14006000 { 2051 display@14006000 {
2083 compatible = "mediate 2052 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2084 reg = <0 0x14006000 0 2053 reg = <0 0x14006000 0 0x1000>;
2085 mediatek,gce-client-r 2054 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2086 mediatek,gce-events = 2055 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2087 2056 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
2088 clocks = <&vppsys0 CL 2057 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2089 }; 2058 };
2090 2059
2091 display@14007000 { 2060 display@14007000 {
2092 compatible = "mediate 2061 compatible = "mediatek,mt8195-mdp3-tdshp";
2093 reg = <0 0x14007000 0 2062 reg = <0 0x14007000 0 0x1000>;
2094 mediatek,gce-client-r 2063 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2095 clocks = <&vppsys0 CL 2064 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2096 }; 2065 };
2097 2066
2098 display@14008000 { 2067 display@14008000 {
2099 compatible = "mediate 2068 compatible = "mediatek,mt8195-mdp3-color";
2100 reg = <0 0x14008000 0 2069 reg = <0 0x14008000 0 0x1000>;
2101 interrupts = <GIC_SPI 2070 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2102 mediatek,gce-client-r 2071 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2103 clocks = <&vppsys0 CL 2072 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2104 power-domains = <&spm 2073 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2105 }; 2074 };
2106 2075
2107 display@14009000 { 2076 display@14009000 {
2108 compatible = "mediate 2077 compatible = "mediatek,mt8195-mdp3-ovl";
2109 reg = <0 0x14009000 0 2078 reg = <0 0x14009000 0 0x1000>;
2110 interrupts = <GIC_SPI 2079 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2111 mediatek,gce-client-r 2080 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2112 clocks = <&vppsys0 CL 2081 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2113 power-domains = <&spm 2082 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2114 iommus = <&iommu_vpp 2083 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
2115 }; 2084 };
2116 2085
2117 display@1400a000 { 2086 display@1400a000 {
2118 compatible = "mediate 2087 compatible = "mediatek,mt8195-mdp3-padding";
2119 reg = <0 0x1400a000 0 2088 reg = <0 0x1400a000 0 0x1000>;
2120 mediatek,gce-client-r 2089 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2121 clocks = <&vppsys0 CL 2090 clocks = <&vppsys0 CLK_VPP0_PADDING>;
2122 power-domains = <&spm 2091 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2123 }; 2092 };
2124 2093
2125 display@1400b000 { 2094 display@1400b000 {
2126 compatible = "mediate 2095 compatible = "mediatek,mt8195-mdp3-tcc";
2127 reg = <0 0x1400b000 0 2096 reg = <0 0x1400b000 0 0x1000>;
2128 mediatek,gce-client-r 2097 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2129 clocks = <&vppsys0 CL 2098 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2130 }; 2099 };
2131 2100
2132 dma-controller@1400c000 { 2101 dma-controller@1400c000 {
2133 compatible = "mediate 2102 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2134 reg = <0 0x1400c000 0 2103 reg = <0 0x1400c000 0 0x1000>;
2135 mediatek,gce-client-r 2104 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2136 mediatek,gce-events = 2105 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2137 2106 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
2138 clocks = <&vppsys0 CL 2107 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2139 iommus = <&iommu_vpp 2108 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
2140 power-domains = <&spm 2109 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2141 #dma-cells = <1>; 2110 #dma-cells = <1>;
2142 }; 2111 };
2143 2112
2144 mutex@1400f000 { 2113 mutex@1400f000 {
2145 compatible = "mediate 2114 compatible = "mediatek,mt8195-vpp-mutex";
2146 reg = <0 0x1400f000 0 2115 reg = <0 0x1400f000 0 0x1000>;
2147 interrupts = <GIC_SPI 2116 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
2148 mediatek,gce-client-r 2117 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2149 clocks = <&vppsys0 CL 2118 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2150 power-domains = <&spm 2119 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2151 }; 2120 };
2152 2121
2153 smi_sub_common_vpp0_vpp1_2x1: 2122 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2154 compatible = "mediate 2123 compatible = "mediatek,mt8195-smi-sub-common";
2155 reg = <0 0x14010000 0 2124 reg = <0 0x14010000 0 0x1000>;
2156 clocks = <&vppsys0 CL 2125 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_ 2126 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2158 <&vppsys0 CLK_ 2127 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2159 clock-names = "apb", 2128 clock-names = "apb", "smi", "gals0";
2160 mediatek,smi = <&smi_ 2129 mediatek,smi = <&smi_common_vpp>;
2161 power-domains = <&spm 2130 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2162 }; 2131 };
2163 2132
2164 smi_sub_common_vdec_vpp0_2x1: 2133 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2165 compatible = "mediate 2134 compatible = "mediatek,mt8195-smi-sub-common";
2166 reg = <0 0x14011000 0 2135 reg = <0 0x14011000 0 0x1000>;
2167 clocks = <&vppsys0 CL 2136 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CL 2137 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2169 <&vppsys0 CL 2138 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2170 clock-names = "apb", 2139 clock-names = "apb", "smi", "gals0";
2171 mediatek,smi = <&smi_ 2140 mediatek,smi = <&smi_common_vpp>;
2172 power-domains = <&spm 2141 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2173 }; 2142 };
2174 2143
2175 smi_common_vpp: smi@14012000 2144 smi_common_vpp: smi@14012000 {
2176 compatible = "mediate 2145 compatible = "mediatek,mt8195-smi-common-vpp";
2177 reg = <0 0x14012000 0 2146 reg = <0 0x14012000 0 0x1000>;
2178 clocks = <&vppsys0 CL 2147 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_ 2148 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2180 <&vppsys0 CLK_ 2149 <&vppsys0 CLK_VPP0_SMI_RSI>,
2181 <&vppsys0 CLK_ 2150 <&vppsys0 CLK_VPP0_SMI_RSI>;
2182 clock-names = "apb", 2151 clock-names = "apb", "smi", "gals0", "gals1";
2183 power-domains = <&spm 2152 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2184 }; 2153 };
2185 2154
2186 larb4: larb@14013000 { 2155 larb4: larb@14013000 {
2187 compatible = "mediate 2156 compatible = "mediatek,mt8195-smi-larb";
2188 reg = <0 0x14013000 0 2157 reg = <0 0x14013000 0 0x1000>;
2189 mediatek,larb-id = <4 2158 mediatek,larb-id = <4>;
2190 mediatek,smi = <&smi_ 2159 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2191 clocks = <&vppsys0 CL 2160 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2192 <&vppsys0 CLK_ 2161 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2193 clock-names = "apb", 2162 clock-names = "apb", "smi";
2194 power-domains = <&spm 2163 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2195 }; 2164 };
2196 2165
2197 iommu_vpp: iommu@14018000 { 2166 iommu_vpp: iommu@14018000 {
2198 compatible = "mediate 2167 compatible = "mediatek,mt8195-iommu-vpp";
2199 reg = <0 0x14018000 0 2168 reg = <0 0x14018000 0 0x1000>;
2200 mediatek,larbs = <&la 2169 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2201 &la 2170 &larb12 &larb14 &larb16 &larb18
2202 &la 2171 &larb20 &larb22 &larb23 &larb26
2203 &la 2172 &larb27>;
2204 interrupts = <GIC_SPI 2173 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2205 clocks = <&vppsys0 CL 2174 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2206 clock-names = "bclk"; 2175 clock-names = "bclk";
2207 #iommu-cells = <1>; 2176 #iommu-cells = <1>;
2208 power-domains = <&spm 2177 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2209 }; 2178 };
2210 2179
2211 wpesys: clock-controller@14e0 2180 wpesys: clock-controller@14e00000 {
2212 compatible = "mediate 2181 compatible = "mediatek,mt8195-wpesys";
2213 reg = <0 0x14e00000 0 2182 reg = <0 0x14e00000 0 0x1000>;
2214 #clock-cells = <1>; 2183 #clock-cells = <1>;
2215 }; 2184 };
2216 2185
2217 wpesys_vpp0: clock-controller 2186 wpesys_vpp0: clock-controller@14e02000 {
2218 compatible = "mediate 2187 compatible = "mediatek,mt8195-wpesys_vpp0";
2219 reg = <0 0x14e02000 0 2188 reg = <0 0x14e02000 0 0x1000>;
2220 #clock-cells = <1>; 2189 #clock-cells = <1>;
2221 }; 2190 };
2222 2191
2223 wpesys_vpp1: clock-controller 2192 wpesys_vpp1: clock-controller@14e03000 {
2224 compatible = "mediate 2193 compatible = "mediatek,mt8195-wpesys_vpp1";
2225 reg = <0 0x14e03000 0 2194 reg = <0 0x14e03000 0 0x1000>;
2226 #clock-cells = <1>; 2195 #clock-cells = <1>;
2227 }; 2196 };
2228 2197
2229 larb7: larb@14e04000 { 2198 larb7: larb@14e04000 {
2230 compatible = "mediate 2199 compatible = "mediatek,mt8195-smi-larb";
2231 reg = <0 0x14e04000 0 2200 reg = <0 0x14e04000 0 0x1000>;
2232 mediatek,larb-id = <7 2201 mediatek,larb-id = <7>;
2233 mediatek,smi = <&smi_ 2202 mediatek,smi = <&smi_common_vdo>;
2234 clocks = <&wpesys CLK 2203 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2235 <&wpesys CLK 2204 <&wpesys CLK_WPE_SMI_LARB7>;
2236 clock-names = "apb", 2205 clock-names = "apb", "smi";
2237 power-domains = <&spm 2206 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2238 }; 2207 };
2239 2208
2240 larb8: larb@14e05000 { 2209 larb8: larb@14e05000 {
2241 compatible = "mediate 2210 compatible = "mediatek,mt8195-smi-larb";
2242 reg = <0 0x14e05000 0 2211 reg = <0 0x14e05000 0 0x1000>;
2243 mediatek,larb-id = <8 2212 mediatek,larb-id = <8>;
2244 mediatek,smi = <&smi_ 2213 mediatek,smi = <&smi_common_vpp>;
2245 clocks = <&wpesys CLK 2214 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2246 <&wpesys CLK_W 2215 <&wpesys CLK_WPE_SMI_LARB8>,
2247 <&vppsys0 CLK_ 2216 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2248 clock-names = "apb", 2217 clock-names = "apb", "smi", "gals";
2249 power-domains = <&spm 2218 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2250 }; 2219 };
2251 2220
2252 vppsys1: syscon@14f00000 { 2221 vppsys1: syscon@14f00000 {
2253 compatible = "mediate 2222 compatible = "mediatek,mt8195-vppsys1", "syscon";
2254 reg = <0 0x14f00000 0 2223 reg = <0 0x14f00000 0 0x1000>;
2255 #clock-cells = <1>; 2224 #clock-cells = <1>;
2256 mediatek,gce-client-r 2225 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2257 }; 2226 };
2258 2227
2259 mutex@14f01000 { 2228 mutex@14f01000 {
2260 compatible = "mediate 2229 compatible = "mediatek,mt8195-vpp-mutex";
2261 reg = <0 0x14f01000 0 2230 reg = <0 0x14f01000 0 0x1000>;
2262 interrupts = <GIC_SPI 2231 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2263 mediatek,gce-client-r 2232 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2264 clocks = <&vppsys1 CL 2233 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2265 power-domains = <&spm 2234 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2266 }; 2235 };
2267 2236
2268 larb5: larb@14f02000 { 2237 larb5: larb@14f02000 {
2269 compatible = "mediate 2238 compatible = "mediatek,mt8195-smi-larb";
2270 reg = <0 0x14f02000 0 2239 reg = <0 0x14f02000 0 0x1000>;
2271 mediatek,larb-id = <5 2240 mediatek,larb-id = <5>;
2272 mediatek,smi = <&smi_ 2241 mediatek,smi = <&smi_common_vdo>;
2273 clocks = <&vppsys1 CL 2242 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2274 <&vppsys1 CLK_ 2243 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2275 <&vppsys0 CLK_ 2244 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2276 clock-names = "apb", 2245 clock-names = "apb", "smi", "gals";
2277 power-domains = <&spm 2246 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2278 }; 2247 };
2279 2248
2280 larb6: larb@14f03000 { 2249 larb6: larb@14f03000 {
2281 compatible = "mediate 2250 compatible = "mediatek,mt8195-smi-larb";
2282 reg = <0 0x14f03000 0 2251 reg = <0 0x14f03000 0 0x1000>;
2283 mediatek,larb-id = <6 2252 mediatek,larb-id = <6>;
2284 mediatek,smi = <&smi_ 2253 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2285 clocks = <&vppsys1 CL 2254 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2286 <&vppsys1 CLK_ 2255 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2287 <&vppsys0 CLK_ 2256 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2288 clock-names = "apb", 2257 clock-names = "apb", "smi", "gals";
2289 power-domains = <&spm 2258 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2290 }; 2259 };
2291 2260
2292 display@14f06000 { 2261 display@14f06000 {
2293 compatible = "mediate 2262 compatible = "mediatek,mt8195-mdp3-split";
2294 reg = <0 0x14f06000 0 2263 reg = <0 0x14f06000 0 0x1000>;
2295 mediatek,gce-client-r 2264 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2296 clocks = <&vppsys1 CL 2265 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
2297 <&vppsys1 CL 2266 <&vppsys1 CLK_VPP1_HDMI_META>,
2298 <&vppsys1 CL 2267 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
2299 power-domains = <&spm 2268 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2300 }; 2269 };
2301 2270
2302 display@14f07000 { 2271 display@14f07000 {
2303 compatible = "mediate 2272 compatible = "mediatek,mt8195-mdp3-tcc";
2304 reg = <0 0x14f07000 0 2273 reg = <0 0x14f07000 0 0x1000>;
2305 mediatek,gce-client-r 2274 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2306 clocks = <&vppsys1 CL 2275 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
2307 }; 2276 };
2308 2277
2309 dma-controller@14f08000 { 2278 dma-controller@14f08000 {
2310 compatible = "mediate 2279 compatible = "mediatek,mt8195-mdp3-rdma";
2311 reg = <0 0x14f08000 0 2280 reg = <0 0x14f08000 0 0x1000>;
2312 mediatek,gce-client-r 2281 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2313 mediatek,gce-events = 2282 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2314 2283 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
2315 clocks = <&vppsys1 CL 2284 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
2316 iommus = <&iommu_vdo 2285 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
2317 power-domains = <&spm 2286 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2318 #dma-cells = <1>; 2287 #dma-cells = <1>;
2319 }; 2288 };
2320 2289
2321 dma-controller@14f09000 { 2290 dma-controller@14f09000 {
2322 compatible = "mediate 2291 compatible = "mediatek,mt8195-mdp3-rdma";
2323 reg = <0 0x14f09000 0 2292 reg = <0 0x14f09000 0 0x1000>;
2324 mediatek,gce-client-r 2293 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2325 mediatek,gce-events = 2294 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2326 2295 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
2327 clocks = <&vppsys1 CL 2296 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2328 iommus = <&iommu_vdo 2297 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
2329 power-domains = <&spm 2298 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2330 #dma-cells = <1>; 2299 #dma-cells = <1>;
2331 }; 2300 };
2332 2301
2333 dma-controller@14f0a000 { 2302 dma-controller@14f0a000 {
2334 compatible = "mediate 2303 compatible = "mediatek,mt8195-mdp3-rdma";
2335 reg = <0 0x14f0a000 0 2304 reg = <0 0x14f0a000 0 0x1000>;
2336 mediatek,gce-client-r 2305 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2337 mediatek,gce-events = 2306 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2338 2307 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
2339 clocks = <&vppsys1 CL 2308 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2340 iommus = <&iommu_vpp 2309 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
2341 power-domains = <&spm 2310 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2342 #dma-cells = <1>; 2311 #dma-cells = <1>;
2343 }; 2312 };
2344 2313
2345 display@14f0b000 { 2314 display@14f0b000 {
2346 compatible = "mediate 2315 compatible = "mediatek,mt8195-mdp3-fg";
2347 reg = <0 0x14f0b000 0 2316 reg = <0 0x14f0b000 0 0x1000>;
2348 mediatek,gce-client-r 2317 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2349 clocks = <&vppsys1 CL 2318 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
2350 }; 2319 };
2351 2320
2352 display@14f0c000 { 2321 display@14f0c000 {
2353 compatible = "mediate 2322 compatible = "mediatek,mt8195-mdp3-fg";
2354 reg = <0 0x14f0c000 0 2323 reg = <0 0x14f0c000 0 0x1000>;
2355 mediatek,gce-client-r 2324 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2356 clocks = <&vppsys1 CL 2325 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2357 }; 2326 };
2358 2327
2359 display@14f0d000 { 2328 display@14f0d000 {
2360 compatible = "mediate 2329 compatible = "mediatek,mt8195-mdp3-fg";
2361 reg = <0 0x14f0d000 0 2330 reg = <0 0x14f0d000 0 0x1000>;
2362 mediatek,gce-client-r 2331 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2363 clocks = <&vppsys1 CL 2332 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2364 }; 2333 };
2365 2334
2366 display@14f0e000 { 2335 display@14f0e000 {
2367 compatible = "mediate 2336 compatible = "mediatek,mt8195-mdp3-hdr";
2368 reg = <0 0x14f0e000 0 2337 reg = <0 0x14f0e000 0 0x1000>;
2369 mediatek,gce-client-r 2338 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2370 clocks = <&vppsys1 CL 2339 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
2371 }; 2340 };
2372 2341
2373 display@14f0f000 { 2342 display@14f0f000 {
2374 compatible = "mediate 2343 compatible = "mediatek,mt8195-mdp3-hdr";
2375 reg = <0 0x14f0f000 0 2344 reg = <0 0x14f0f000 0 0x1000>;
2376 mediatek,gce-client-r 2345 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2377 clocks = <&vppsys1 CL 2346 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2378 }; 2347 };
2379 2348
2380 display@14f10000 { 2349 display@14f10000 {
2381 compatible = "mediate 2350 compatible = "mediatek,mt8195-mdp3-hdr";
2382 reg = <0 0x14f10000 0 2351 reg = <0 0x14f10000 0 0x1000>;
2383 mediatek,gce-client-r 2352 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2384 clocks = <&vppsys1 CL 2353 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2385 }; 2354 };
2386 2355
2387 display@14f11000 { 2356 display@14f11000 {
2388 compatible = "mediate 2357 compatible = "mediatek,mt8195-mdp3-aal";
2389 reg = <0 0x14f11000 0 2358 reg = <0 0x14f11000 0 0x1000>;
2390 interrupts = <GIC_SPI 2359 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
2391 mediatek,gce-client-r 2360 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2392 clocks = <&vppsys1 CL 2361 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
2393 power-domains = <&spm 2362 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2394 }; 2363 };
2395 2364
2396 display@14f12000 { 2365 display@14f12000 {
2397 compatible = "mediate 2366 compatible = "mediatek,mt8195-mdp3-aal";
2398 reg = <0 0x14f12000 0 2367 reg = <0 0x14f12000 0 0x1000>;
2399 interrupts = <GIC_SPI 2368 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
2400 mediatek,gce-client-r 2369 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2401 clocks = <&vppsys1 CL 2370 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
2402 power-domains = <&spm 2371 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2403 }; 2372 };
2404 2373
2405 display@14f13000 { 2374 display@14f13000 {
2406 compatible = "mediate 2375 compatible = "mediatek,mt8195-mdp3-aal";
2407 reg = <0 0x14f13000 0 2376 reg = <0 0x14f13000 0 0x1000>;
2408 interrupts = <GIC_SPI 2377 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
2409 mediatek,gce-client-r 2378 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2410 clocks = <&vppsys1 CL 2379 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
2411 power-domains = <&spm 2380 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2412 }; 2381 };
2413 2382
2414 display@14f14000 { 2383 display@14f14000 {
2415 compatible = "mediate 2384 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2416 reg = <0 0x14f14000 0 2385 reg = <0 0x14f14000 0 0x1000>;
2417 mediatek,gce-client-r 2386 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2418 mediatek,gce-events = 2387 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2419 2388 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
2420 clocks = <&vppsys1 CL 2389 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
2421 }; 2390 };
2422 2391
2423 display@14f15000 { 2392 display@14f15000 {
2424 compatible = "mediate 2393 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2425 reg = <0 0x14f15000 0 2394 reg = <0 0x14f15000 0 0x1000>;
2426 mediatek,gce-client-r 2395 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2427 mediatek,gce-events = 2396 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2428 2397 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
2429 clocks = <&vppsys1 CL 2398 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
2430 }; 2399 };
2431 2400
2432 display@14f16000 { 2401 display@14f16000 {
2433 compatible = "mediate 2402 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2434 reg = <0 0x14f16000 0 2403 reg = <0 0x14f16000 0 0x1000>;
2435 mediatek,gce-client-r 2404 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2436 mediatek,gce-events = 2405 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2437 2406 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
2438 clocks = <&vppsys1 CL 2407 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
2439 }; 2408 };
2440 2409
2441 display@14f17000 { 2410 display@14f17000 {
2442 compatible = "mediate 2411 compatible = "mediatek,mt8195-mdp3-tdshp";
2443 reg = <0 0x14f17000 0 2412 reg = <0 0x14f17000 0 0x1000>;
2444 mediatek,gce-client-r 2413 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2445 clocks = <&vppsys1 CL 2414 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
2446 }; 2415 };
2447 2416
2448 display@14f18000 { 2417 display@14f18000 {
2449 compatible = "mediate 2418 compatible = "mediatek,mt8195-mdp3-tdshp";
2450 reg = <0 0x14f18000 0 2419 reg = <0 0x14f18000 0 0x1000>;
2451 mediatek,gce-client-r 2420 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2452 clocks = <&vppsys1 CL 2421 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2453 }; 2422 };
2454 2423
2455 display@14f19000 { 2424 display@14f19000 {
2456 compatible = "mediate 2425 compatible = "mediatek,mt8195-mdp3-tdshp";
2457 reg = <0 0x14f19000 0 2426 reg = <0 0x14f19000 0 0x1000>;
2458 mediatek,gce-client-r 2427 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2459 clocks = <&vppsys1 CL 2428 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2460 }; 2429 };
2461 2430
2462 display@14f1a000 { 2431 display@14f1a000 {
2463 compatible = "mediate 2432 compatible = "mediatek,mt8195-mdp3-merge";
2464 reg = <0 0x14f1a000 0 2433 reg = <0 0x14f1a000 0 0x1000>;
2465 mediatek,gce-client-r 2434 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2466 clocks = <&vppsys1 CL 2435 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2467 power-domains = <&spm 2436 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2468 }; 2437 };
2469 2438
2470 display@14f1b000 { 2439 display@14f1b000 {
2471 compatible = "mediate 2440 compatible = "mediatek,mt8195-mdp3-merge";
2472 reg = <0 0x14f1b000 0 2441 reg = <0 0x14f1b000 0 0x1000>;
2473 mediatek,gce-client-r 2442 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2474 clocks = <&vppsys1 CL 2443 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2475 power-domains = <&spm 2444 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2476 }; 2445 };
2477 2446
2478 display@14f1c000 { 2447 display@14f1c000 {
2479 compatible = "mediate 2448 compatible = "mediatek,mt8195-mdp3-color";
2480 reg = <0 0x14f1c000 0 2449 reg = <0 0x14f1c000 0 0x1000>;
2481 interrupts = <GIC_SPI 2450 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
2482 mediatek,gce-client-r 2451 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2483 clocks = <&vppsys1 CL 2452 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
2484 power-domains = <&spm 2453 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2485 }; 2454 };
2486 2455
2487 display@14f1d000 { 2456 display@14f1d000 {
2488 compatible = "mediate 2457 compatible = "mediatek,mt8195-mdp3-color";
2489 reg = <0 0x14f1d000 0 2458 reg = <0 0x14f1d000 0 0x1000>;
2490 mediatek,gce-client-r 2459 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2491 interrupts = <GIC_SPI 2460 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
2492 clocks = <&vppsys1 CL 2461 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
2493 power-domains = <&spm 2462 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2494 }; 2463 };
2495 2464
2496 display@14f1e000 { 2465 display@14f1e000 {
2497 compatible = "mediate 2466 compatible = "mediatek,mt8195-mdp3-color";
2498 reg = <0 0x14f1e000 0 2467 reg = <0 0x14f1e000 0 0x1000>;
2499 interrupts = <GIC_SPI 2468 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
2500 mediatek,gce-client-r 2469 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2501 clocks = <&vppsys1 CL 2470 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
2502 power-domains = <&spm 2471 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2503 }; 2472 };
2504 2473
2505 display@14f1f000 { 2474 display@14f1f000 {
2506 compatible = "mediate 2475 compatible = "mediatek,mt8195-mdp3-ovl";
2507 reg = <0 0x14f1f000 0 2476 reg = <0 0x14f1f000 0 0x1000>;
2508 interrupts = <GIC_SPI 2477 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
2509 mediatek,gce-client-r 2478 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2510 clocks = <&vppsys1 CL 2479 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
2511 power-domains = <&spm 2480 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2512 iommus = <&iommu_vdo 2481 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
2513 }; 2482 };
2514 2483
2515 display@14f20000 { 2484 display@14f20000 {
2516 compatible = "mediate 2485 compatible = "mediatek,mt8195-mdp3-padding";
2517 reg = <0 0x14f20000 0 2486 reg = <0 0x14f20000 0 0x1000>;
2518 mediatek,gce-client-r 2487 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2519 clocks = <&vppsys1 CL 2488 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
2520 power-domains = <&spm 2489 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2521 }; 2490 };
2522 2491
2523 display@14f21000 { 2492 display@14f21000 {
2524 compatible = "mediate 2493 compatible = "mediatek,mt8195-mdp3-padding";
2525 reg = <0 0x14f21000 0 2494 reg = <0 0x14f21000 0 0x1000>;
2526 mediatek,gce-client-r 2495 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2527 clocks = <&vppsys1 CL 2496 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
2528 power-domains = <&spm 2497 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2529 }; 2498 };
2530 2499
2531 display@14f22000 { 2500 display@14f22000 {
2532 compatible = "mediate 2501 compatible = "mediatek,mt8195-mdp3-padding";
2533 reg = <0 0x14f22000 0 2502 reg = <0 0x14f22000 0 0x1000>;
2534 mediatek,gce-client-r 2503 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2535 clocks = <&vppsys1 CL 2504 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
2536 power-domains = <&spm 2505 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2537 }; 2506 };
2538 2507
2539 dma-controller@14f23000 { 2508 dma-controller@14f23000 {
2540 compatible = "mediate 2509 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2541 reg = <0 0x14f23000 0 2510 reg = <0 0x14f23000 0 0x1000>;
2542 mediatek,gce-client-r 2511 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2543 mediatek,gce-events = 2512 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2544 2513 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
2545 clocks = <&vppsys1 CL 2514 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
2546 iommus = <&iommu_vdo 2515 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
2547 power-domains = <&spm 2516 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2548 #dma-cells = <1>; 2517 #dma-cells = <1>;
2549 }; 2518 };
2550 2519
2551 dma-controller@14f24000 { 2520 dma-controller@14f24000 {
2552 compatible = "mediate 2521 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2553 reg = <0 0x14f24000 0 2522 reg = <0 0x14f24000 0 0x1000>;
2554 mediatek,gce-client-r 2523 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2555 mediatek,gce-events = 2524 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2556 <CMDQ 2525 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
2557 clocks = <&vppsys1 CL 2526 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
2558 iommus = <&iommu_vdo 2527 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
2559 power-domains = <&spm 2528 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2560 #dma-cells = <1>; 2529 #dma-cells = <1>;
2561 }; 2530 };
2562 2531
2563 dma-controller@14f25000 { 2532 dma-controller@14f25000 {
2564 compatible = "mediate 2533 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2565 reg = <0 0x14f25000 0 2534 reg = <0 0x14f25000 0 0x1000>;
2566 mediatek,gce-client-r 2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2567 mediatek,gce-events = 2536 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2568 <CMDQ 2537 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
2569 clocks = <&vppsys1 CL 2538 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
2570 iommus = <&iommu_vpp 2539 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
2571 power-domains = <&spm 2540 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2572 #dma-cells = <1>; 2541 #dma-cells = <1>;
2573 }; 2542 };
2574 2543
2575 imgsys: clock-controller@1500 2544 imgsys: clock-controller@15000000 {
2576 compatible = "mediate 2545 compatible = "mediatek,mt8195-imgsys";
2577 reg = <0 0x15000000 0 2546 reg = <0 0x15000000 0 0x1000>;
2578 #clock-cells = <1>; 2547 #clock-cells = <1>;
2579 }; 2548 };
2580 2549
2581 larb9: larb@15001000 { 2550 larb9: larb@15001000 {
2582 compatible = "mediate 2551 compatible = "mediatek,mt8195-smi-larb";
2583 reg = <0 0x15001000 0 2552 reg = <0 0x15001000 0 0x1000>;
2584 mediatek,larb-id = <9 2553 mediatek,larb-id = <9>;
2585 mediatek,smi = <&smi_ 2554 mediatek,smi = <&smi_sub_common_img1_3x1>;
2586 clocks = <&imgsys CLK 2555 clocks = <&imgsys CLK_IMG_LARB9>,
2587 <&imgsys CLK 2556 <&imgsys CLK_IMG_LARB9>,
2588 <&imgsys CLK 2557 <&imgsys CLK_IMG_GALS>;
2589 clock-names = "apb", 2558 clock-names = "apb", "smi", "gals";
2590 power-domains = <&spm 2559 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2591 }; 2560 };
2592 2561
2593 smi_sub_common_img0_3x1: smi@ 2562 smi_sub_common_img0_3x1: smi@15002000 {
2594 compatible = "mediate 2563 compatible = "mediatek,mt8195-smi-sub-common";
2595 reg = <0 0x15002000 0 2564 reg = <0 0x15002000 0 0x1000>;
2596 clocks = <&imgsys CLK 2565 clocks = <&imgsys CLK_IMG_IPE>,
2597 <&imgsys CLK 2566 <&imgsys CLK_IMG_IPE>,
2598 <&vppsys0 CL 2567 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2599 clock-names = "apb", 2568 clock-names = "apb", "smi", "gals0";
2600 mediatek,smi = <&smi_ 2569 mediatek,smi = <&smi_common_vpp>;
2601 power-domains = <&spm 2570 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2602 }; 2571 };
2603 2572
2604 smi_sub_common_img1_3x1: smi@ 2573 smi_sub_common_img1_3x1: smi@15003000 {
2605 compatible = "mediate 2574 compatible = "mediatek,mt8195-smi-sub-common";
2606 reg = <0 0x15003000 0 2575 reg = <0 0x15003000 0 0x1000>;
2607 clocks = <&imgsys CLK 2576 clocks = <&imgsys CLK_IMG_LARB9>,
2608 <&imgsys CLK 2577 <&imgsys CLK_IMG_LARB9>,
2609 <&imgsys CLK 2578 <&imgsys CLK_IMG_GALS>;
2610 clock-names = "apb", 2579 clock-names = "apb", "smi", "gals0";
2611 mediatek,smi = <&smi_ 2580 mediatek,smi = <&smi_common_vdo>;
2612 power-domains = <&spm 2581 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2613 }; 2582 };
2614 2583
2615 imgsys1_dip_top: clock-contro 2584 imgsys1_dip_top: clock-controller@15110000 {
2616 compatible = "mediate 2585 compatible = "mediatek,mt8195-imgsys1_dip_top";
2617 reg = <0 0x15110000 0 2586 reg = <0 0x15110000 0 0x1000>;
2618 #clock-cells = <1>; 2587 #clock-cells = <1>;
2619 }; 2588 };
2620 2589
2621 larb10: larb@15120000 { 2590 larb10: larb@15120000 {
2622 compatible = "mediate 2591 compatible = "mediatek,mt8195-smi-larb";
2623 reg = <0 0x15120000 0 2592 reg = <0 0x15120000 0 0x1000>;
2624 mediatek,larb-id = <1 2593 mediatek,larb-id = <10>;
2625 mediatek,smi = <&smi_ 2594 mediatek,smi = <&smi_sub_common_img1_3x1>;
2626 clocks = <&imgsys CLK 2595 clocks = <&imgsys CLK_IMG_DIP0>,
2627 <&imgsys1_dip_ 2596 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2628 clock-names = "apb", 2597 clock-names = "apb", "smi";
2629 power-domains = <&spm 2598 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2630 }; 2599 };
2631 2600
2632 imgsys1_dip_nr: clock-control 2601 imgsys1_dip_nr: clock-controller@15130000 {
2633 compatible = "mediate 2602 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2634 reg = <0 0x15130000 0 2603 reg = <0 0x15130000 0 0x1000>;
2635 #clock-cells = <1>; 2604 #clock-cells = <1>;
2636 }; 2605 };
2637 2606
2638 imgsys1_wpe: clock-controller 2607 imgsys1_wpe: clock-controller@15220000 {
2639 compatible = "mediate 2608 compatible = "mediatek,mt8195-imgsys1_wpe";
2640 reg = <0 0x15220000 0 2609 reg = <0 0x15220000 0 0x1000>;
2641 #clock-cells = <1>; 2610 #clock-cells = <1>;
2642 }; 2611 };
2643 2612
2644 larb11: larb@15230000 { 2613 larb11: larb@15230000 {
2645 compatible = "mediate 2614 compatible = "mediatek,mt8195-smi-larb";
2646 reg = <0 0x15230000 0 2615 reg = <0 0x15230000 0 0x1000>;
2647 mediatek,larb-id = <1 2616 mediatek,larb-id = <11>;
2648 mediatek,smi = <&smi_ 2617 mediatek,smi = <&smi_sub_common_img1_3x1>;
2649 clocks = <&imgsys CLK 2618 clocks = <&imgsys CLK_IMG_WPE0>,
2650 <&imgsys1_wpe 2619 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2651 clock-names = "apb", 2620 clock-names = "apb", "smi";
2652 power-domains = <&spm 2621 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2653 }; 2622 };
2654 2623
2655 ipesys: clock-controller@1533 2624 ipesys: clock-controller@15330000 {
2656 compatible = "mediate 2625 compatible = "mediatek,mt8195-ipesys";
2657 reg = <0 0x15330000 0 2626 reg = <0 0x15330000 0 0x1000>;
2658 #clock-cells = <1>; 2627 #clock-cells = <1>;
2659 }; 2628 };
2660 2629
2661 larb12: larb@15340000 { 2630 larb12: larb@15340000 {
2662 compatible = "mediate 2631 compatible = "mediatek,mt8195-smi-larb";
2663 reg = <0 0x15340000 0 2632 reg = <0 0x15340000 0 0x1000>;
2664 mediatek,larb-id = <1 2633 mediatek,larb-id = <12>;
2665 mediatek,smi = <&smi_ 2634 mediatek,smi = <&smi_sub_common_img0_3x1>;
2666 clocks = <&ipesys CLK 2635 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2667 <&ipesys CLK 2636 <&ipesys CLK_IPE_SMI_LARB12>;
2668 clock-names = "apb", 2637 clock-names = "apb", "smi";
2669 power-domains = <&spm 2638 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2670 }; 2639 };
2671 2640
2672 camsys: clock-controller@1600 2641 camsys: clock-controller@16000000 {
2673 compatible = "mediate 2642 compatible = "mediatek,mt8195-camsys";
2674 reg = <0 0x16000000 0 2643 reg = <0 0x16000000 0 0x1000>;
2675 #clock-cells = <1>; 2644 #clock-cells = <1>;
2676 }; 2645 };
2677 2646
2678 larb13: larb@16001000 { 2647 larb13: larb@16001000 {
2679 compatible = "mediate 2648 compatible = "mediatek,mt8195-smi-larb";
2680 reg = <0 0x16001000 0 2649 reg = <0 0x16001000 0 0x1000>;
2681 mediatek,larb-id = <1 2650 mediatek,larb-id = <13>;
2682 mediatek,smi = <&smi_ 2651 mediatek,smi = <&smi_sub_common_cam_4x1>;
2683 clocks = <&camsys CLK 2652 clocks = <&camsys CLK_CAM_LARB13>,
2684 <&camsys CLK_C 2653 <&camsys CLK_CAM_LARB13>,
2685 <&camsys CLK_C 2654 <&camsys CLK_CAM_CAM2MM0_GALS>;
2686 clock-names = "apb", 2655 clock-names = "apb", "smi", "gals";
2687 power-domains = <&spm 2656 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688 }; 2657 };
2689 2658
2690 larb14: larb@16002000 { 2659 larb14: larb@16002000 {
2691 compatible = "mediate 2660 compatible = "mediatek,mt8195-smi-larb";
2692 reg = <0 0x16002000 0 2661 reg = <0 0x16002000 0 0x1000>;
2693 mediatek,larb-id = <1 2662 mediatek,larb-id = <14>;
2694 mediatek,smi = <&smi_ 2663 mediatek,smi = <&smi_sub_common_cam_7x1>;
2695 clocks = <&camsys CLK 2664 clocks = <&camsys CLK_CAM_LARB14>,
2696 <&camsys CLK 2665 <&camsys CLK_CAM_LARB14>;
2697 clock-names = "apb", 2666 clock-names = "apb", "smi";
2698 power-domains = <&spm 2667 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2699 }; 2668 };
2700 2669
2701 smi_sub_common_cam_4x1: smi@1 2670 smi_sub_common_cam_4x1: smi@16004000 {
2702 compatible = "mediate 2671 compatible = "mediatek,mt8195-smi-sub-common";
2703 reg = <0 0x16004000 0 2672 reg = <0 0x16004000 0 0x1000>;
2704 clocks = <&camsys CLK 2673 clocks = <&camsys CLK_CAM_LARB13>,
2705 <&camsys CLK 2674 <&camsys CLK_CAM_LARB13>,
2706 <&camsys CLK 2675 <&camsys CLK_CAM_CAM2MM0_GALS>;
2707 clock-names = "apb", 2676 clock-names = "apb", "smi", "gals0";
2708 mediatek,smi = <&smi_ 2677 mediatek,smi = <&smi_common_vdo>;
2709 power-domains = <&spm 2678 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2710 }; 2679 };
2711 2680
2712 smi_sub_common_cam_7x1: smi@1 2681 smi_sub_common_cam_7x1: smi@16005000 {
2713 compatible = "mediate 2682 compatible = "mediatek,mt8195-smi-sub-common";
2714 reg = <0 0x16005000 0 2683 reg = <0 0x16005000 0 0x1000>;
2715 clocks = <&camsys CLK 2684 clocks = <&camsys CLK_CAM_LARB14>,
2716 <&camsys CLK 2685 <&camsys CLK_CAM_CAM2MM1_GALS>,
2717 <&vppsys0 CL 2686 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2718 clock-names = "apb", 2687 clock-names = "apb", "smi", "gals0";
2719 mediatek,smi = <&smi_ 2688 mediatek,smi = <&smi_common_vpp>;
2720 power-domains = <&spm 2689 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2721 }; 2690 };
2722 2691
2723 larb16: larb@16012000 { 2692 larb16: larb@16012000 {
2724 compatible = "mediate 2693 compatible = "mediatek,mt8195-smi-larb";
2725 reg = <0 0x16012000 0 2694 reg = <0 0x16012000 0 0x1000>;
2726 mediatek,larb-id = <1 2695 mediatek,larb-id = <16>;
2727 mediatek,smi = <&smi_ 2696 mediatek,smi = <&smi_sub_common_cam_7x1>;
2728 clocks = <&camsys_raw 2697 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2729 <&camsys_raw 2698 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2730 clock-names = "apb", 2699 clock-names = "apb", "smi";
2731 power-domains = <&spm 2700 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2732 }; 2701 };
2733 2702
2734 larb17: larb@16013000 { 2703 larb17: larb@16013000 {
2735 compatible = "mediate 2704 compatible = "mediatek,mt8195-smi-larb";
2736 reg = <0 0x16013000 0 2705 reg = <0 0x16013000 0 0x1000>;
2737 mediatek,larb-id = <1 2706 mediatek,larb-id = <17>;
2738 mediatek,smi = <&smi_ 2707 mediatek,smi = <&smi_sub_common_cam_4x1>;
2739 clocks = <&camsys_yuv 2708 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2740 <&camsys_yuv 2709 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2741 clock-names = "apb", 2710 clock-names = "apb", "smi";
2742 power-domains = <&spm 2711 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2743 }; 2712 };
2744 2713
2745 larb27: larb@16014000 { 2714 larb27: larb@16014000 {
2746 compatible = "mediate 2715 compatible = "mediatek,mt8195-smi-larb";
2747 reg = <0 0x16014000 0 2716 reg = <0 0x16014000 0 0x1000>;
2748 mediatek,larb-id = <2 2717 mediatek,larb-id = <27>;
2749 mediatek,smi = <&smi_ 2718 mediatek,smi = <&smi_sub_common_cam_7x1>;
2750 clocks = <&camsys_raw 2719 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2751 <&camsys_raw 2720 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2752 clock-names = "apb", 2721 clock-names = "apb", "smi";
2753 power-domains = <&spm 2722 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2754 }; 2723 };
2755 2724
2756 larb28: larb@16015000 { 2725 larb28: larb@16015000 {
2757 compatible = "mediate 2726 compatible = "mediatek,mt8195-smi-larb";
2758 reg = <0 0x16015000 0 2727 reg = <0 0x16015000 0 0x1000>;
2759 mediatek,larb-id = <2 2728 mediatek,larb-id = <28>;
2760 mediatek,smi = <&smi_ 2729 mediatek,smi = <&smi_sub_common_cam_4x1>;
2761 clocks = <&camsys_yuv 2730 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2762 <&camsys_yuv 2731 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2763 clock-names = "apb", 2732 clock-names = "apb", "smi";
2764 power-domains = <&spm 2733 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2765 }; 2734 };
2766 2735
2767 camsys_rawa: clock-controller 2736 camsys_rawa: clock-controller@1604f000 {
2768 compatible = "mediate 2737 compatible = "mediatek,mt8195-camsys_rawa";
2769 reg = <0 0x1604f000 0 2738 reg = <0 0x1604f000 0 0x1000>;
2770 #clock-cells = <1>; 2739 #clock-cells = <1>;
2771 }; 2740 };
2772 2741
2773 camsys_yuva: clock-controller 2742 camsys_yuva: clock-controller@1606f000 {
2774 compatible = "mediate 2743 compatible = "mediatek,mt8195-camsys_yuva";
2775 reg = <0 0x1606f000 0 2744 reg = <0 0x1606f000 0 0x1000>;
2776 #clock-cells = <1>; 2745 #clock-cells = <1>;
2777 }; 2746 };
2778 2747
2779 camsys_rawb: clock-controller 2748 camsys_rawb: clock-controller@1608f000 {
2780 compatible = "mediate 2749 compatible = "mediatek,mt8195-camsys_rawb";
2781 reg = <0 0x1608f000 0 2750 reg = <0 0x1608f000 0 0x1000>;
2782 #clock-cells = <1>; 2751 #clock-cells = <1>;
2783 }; 2752 };
2784 2753
2785 camsys_yuvb: clock-controller 2754 camsys_yuvb: clock-controller@160af000 {
2786 compatible = "mediate 2755 compatible = "mediatek,mt8195-camsys_yuvb";
2787 reg = <0 0x160af000 0 2756 reg = <0 0x160af000 0 0x1000>;
2788 #clock-cells = <1>; 2757 #clock-cells = <1>;
2789 }; 2758 };
2790 2759
2791 camsys_mraw: clock-controller 2760 camsys_mraw: clock-controller@16140000 {
2792 compatible = "mediate 2761 compatible = "mediatek,mt8195-camsys_mraw";
2793 reg = <0 0x16140000 0 2762 reg = <0 0x16140000 0 0x1000>;
2794 #clock-cells = <1>; 2763 #clock-cells = <1>;
2795 }; 2764 };
2796 2765
2797 larb25: larb@16141000 { 2766 larb25: larb@16141000 {
2798 compatible = "mediate 2767 compatible = "mediatek,mt8195-smi-larb";
2799 reg = <0 0x16141000 0 2768 reg = <0 0x16141000 0 0x1000>;
2800 mediatek,larb-id = <2 2769 mediatek,larb-id = <25>;
2801 mediatek,smi = <&smi_ 2770 mediatek,smi = <&smi_sub_common_cam_4x1>;
2802 clocks = <&camsys CLK 2771 clocks = <&camsys CLK_CAM_LARB13>,
2803 <&camsys_mra 2772 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2804 <&camsys CLK 2773 <&camsys CLK_CAM_CAM2MM0_GALS>;
2805 clock-names = "apb", 2774 clock-names = "apb", "smi", "gals";
2806 power-domains = <&spm 2775 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2807 }; 2776 };
2808 2777
2809 larb26: larb@16142000 { 2778 larb26: larb@16142000 {
2810 compatible = "mediate 2779 compatible = "mediatek,mt8195-smi-larb";
2811 reg = <0 0x16142000 0 2780 reg = <0 0x16142000 0 0x1000>;
2812 mediatek,larb-id = <2 2781 mediatek,larb-id = <26>;
2813 mediatek,smi = <&smi_ 2782 mediatek,smi = <&smi_sub_common_cam_7x1>;
2814 clocks = <&camsys_mra 2783 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2815 <&camsys_mra 2784 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2816 clock-names = "apb", 2785 clock-names = "apb", "smi";
2817 power-domains = <&spm 2786 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2818 2787
2819 }; 2788 };
2820 2789
2821 ccusys: clock-controller@1720 2790 ccusys: clock-controller@17200000 {
2822 compatible = "mediate 2791 compatible = "mediatek,mt8195-ccusys";
2823 reg = <0 0x17200000 0 2792 reg = <0 0x17200000 0 0x1000>;
2824 #clock-cells = <1>; 2793 #clock-cells = <1>;
2825 }; 2794 };
2826 2795
2827 larb18: larb@17201000 { 2796 larb18: larb@17201000 {
2828 compatible = "mediate 2797 compatible = "mediatek,mt8195-smi-larb";
2829 reg = <0 0x17201000 0 2798 reg = <0 0x17201000 0 0x1000>;
2830 mediatek,larb-id = <1 2799 mediatek,larb-id = <18>;
2831 mediatek,smi = <&smi_ 2800 mediatek,smi = <&smi_sub_common_cam_7x1>;
2832 clocks = <&ccusys CLK 2801 clocks = <&ccusys CLK_CCU_LARB18>,
2833 <&ccusys CLK 2802 <&ccusys CLK_CCU_LARB18>;
2834 clock-names = "apb", 2803 clock-names = "apb", "smi";
2835 power-domains = <&spm 2804 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2836 }; 2805 };
2837 2806
2838 video-codec@18000000 { 2807 video-codec@18000000 {
2839 compatible = "mediate 2808 compatible = "mediatek,mt8195-vcodec-dec";
2840 mediatek,scp = <&scp> 2809 mediatek,scp = <&scp>;
2841 iommus = <&iommu_vdo 2810 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2842 #address-cells = <2>; 2811 #address-cells = <2>;
2843 #size-cells = <2>; 2812 #size-cells = <2>;
2844 reg = <0 0x18000000 0 2813 reg = <0 0x18000000 0 0x1000>,
2845 <0 0x18004000 0 2814 <0 0x18004000 0 0x1000>;
2846 ranges = <0 0 0 0x180 2815 ranges = <0 0 0 0x18000000 0 0x26000>;
2847 2816
2848 video-codec@2000 { 2817 video-codec@2000 {
2849 compatible = 2818 compatible = "mediatek,mtk-vcodec-lat-soc";
2850 reg = <0 0x20 2819 reg = <0 0x2000 0 0x800>;
2851 iommus = <&io 2820 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2852 <&io 2821 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2853 clocks = <&to 2822 clocks = <&topckgen CLK_TOP_VDEC>,
2854 <&vd 2823 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2855 <&vd 2824 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2856 <&to 2825 <&topckgen CLK_TOP_UNIVPLL_D4>;
2857 clock-names = 2826 clock-names = "sel", "vdec", "lat", "top";
2858 assigned-cloc 2827 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2859 assigned-cloc 2828 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2860 power-domains 2829 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2861 }; 2830 };
2862 2831
2863 video-codec@10000 { 2832 video-codec@10000 {
2864 compatible = 2833 compatible = "mediatek,mtk-vcodec-lat";
2865 reg = <0 0x10 2834 reg = <0 0x10000 0 0x800>;
2866 interrupts = 2835 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2867 iommus = <&io 2836 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2868 <&io 2837 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2869 <&io 2838 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2870 <&io 2839 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2871 <&io 2840 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2872 <&io 2841 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2873 clocks = <&to 2842 clocks = <&topckgen CLK_TOP_VDEC>,
2874 <&vd 2843 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2875 <&vd 2844 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2876 <&to 2845 <&topckgen CLK_TOP_UNIVPLL_D4>;
2877 clock-names = 2846 clock-names = "sel", "vdec", "lat", "top";
2878 assigned-cloc 2847 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2879 assigned-cloc 2848 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2880 power-domains 2849 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2881 }; 2850 };
2882 2851
2883 video-codec@25000 { 2852 video-codec@25000 {
2884 compatible = 2853 compatible = "mediatek,mtk-vcodec-core";
2885 reg = <0 0x25 2854 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
2886 interrupts = 2855 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2887 iommus = <&io 2856 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2888 <&io 2857 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2889 <&io 2858 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2890 <&io 2859 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2891 <&io 2860 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2892 <&io 2861 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2893 <&io 2862 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2894 <&io 2863 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2895 <&io 2864 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2896 <&io 2865 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2897 clocks = <&to 2866 clocks = <&topckgen CLK_TOP_VDEC>,
2898 <&vd 2867 <&vdecsys CLK_VDEC_VDEC>,
2899 <&vd 2868 <&vdecsys CLK_VDEC_LAT>,
2900 <&to 2869 <&topckgen CLK_TOP_UNIVPLL_D4>;
2901 clock-names = 2870 clock-names = "sel", "vdec", "lat", "top";
2902 assigned-cloc 2871 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2903 assigned-cloc 2872 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2904 power-domains 2873 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2905 }; 2874 };
2906 }; 2875 };
2907 2876
2908 larb24: larb@1800d000 { 2877 larb24: larb@1800d000 {
2909 compatible = "mediate 2878 compatible = "mediatek,mt8195-smi-larb";
2910 reg = <0 0x1800d000 0 2879 reg = <0 0x1800d000 0 0x1000>;
2911 mediatek,larb-id = <2 2880 mediatek,larb-id = <24>;
2912 mediatek,smi = <&smi_ 2881 mediatek,smi = <&smi_common_vdo>;
2913 clocks = <&vdecsys_so 2882 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2914 <&vdecsys_so 2883 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2915 clock-names = "apb", 2884 clock-names = "apb", "smi";
2916 power-domains = <&spm 2885 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2917 }; 2886 };
2918 2887
2919 larb23: larb@1800e000 { 2888 larb23: larb@1800e000 {
2920 compatible = "mediate 2889 compatible = "mediatek,mt8195-smi-larb";
2921 reg = <0 0x1800e000 0 2890 reg = <0 0x1800e000 0 0x1000>;
2922 mediatek,larb-id = <2 2891 mediatek,larb-id = <23>;
2923 mediatek,smi = <&smi_ 2892 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2924 clocks = <&vppsys0 CL 2893 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2925 <&vdecsys_so 2894 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2926 clock-names = "apb", 2895 clock-names = "apb", "smi";
2927 power-domains = <&spm 2896 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2928 }; 2897 };
2929 2898
2930 vdecsys_soc: clock-controller 2899 vdecsys_soc: clock-controller@1800f000 {
2931 compatible = "mediate 2900 compatible = "mediatek,mt8195-vdecsys_soc";
2932 reg = <0 0x1800f000 0 2901 reg = <0 0x1800f000 0 0x1000>;
2933 #clock-cells = <1>; 2902 #clock-cells = <1>;
2934 }; 2903 };
2935 2904
2936 larb21: larb@1802e000 { 2905 larb21: larb@1802e000 {
2937 compatible = "mediate 2906 compatible = "mediatek,mt8195-smi-larb";
2938 reg = <0 0x1802e000 0 2907 reg = <0 0x1802e000 0 0x1000>;
2939 mediatek,larb-id = <2 2908 mediatek,larb-id = <21>;
2940 mediatek,smi = <&smi_ 2909 mediatek,smi = <&smi_common_vdo>;
2941 clocks = <&vdecsys CL 2910 clocks = <&vdecsys CLK_VDEC_LARB1>,
2942 <&vdecsys CL 2911 <&vdecsys CLK_VDEC_LARB1>;
2943 clock-names = "apb", 2912 clock-names = "apb", "smi";
2944 power-domains = <&spm 2913 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2945 }; 2914 };
2946 2915
2947 vdecsys: clock-controller@180 2916 vdecsys: clock-controller@1802f000 {
2948 compatible = "mediate 2917 compatible = "mediatek,mt8195-vdecsys";
2949 reg = <0 0x1802f000 0 2918 reg = <0 0x1802f000 0 0x1000>;
2950 #clock-cells = <1>; 2919 #clock-cells = <1>;
2951 }; 2920 };
2952 2921
2953 larb22: larb@1803e000 { 2922 larb22: larb@1803e000 {
2954 compatible = "mediate 2923 compatible = "mediatek,mt8195-smi-larb";
2955 reg = <0 0x1803e000 0 2924 reg = <0 0x1803e000 0 0x1000>;
2956 mediatek,larb-id = <2 2925 mediatek,larb-id = <22>;
2957 mediatek,smi = <&smi_ 2926 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2958 clocks = <&vppsys0 CL 2927 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2959 <&vdecsys_co 2928 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2960 clock-names = "apb", 2929 clock-names = "apb", "smi";
2961 power-domains = <&spm 2930 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2962 }; 2931 };
2963 2932
2964 vdecsys_core1: clock-controll 2933 vdecsys_core1: clock-controller@1803f000 {
2965 compatible = "mediate 2934 compatible = "mediatek,mt8195-vdecsys_core1";
2966 reg = <0 0x1803f000 0 2935 reg = <0 0x1803f000 0 0x1000>;
2967 #clock-cells = <1>; 2936 #clock-cells = <1>;
2968 }; 2937 };
2969 2938
2970 apusys_pll: clock-controller@ 2939 apusys_pll: clock-controller@190f3000 {
2971 compatible = "mediate 2940 compatible = "mediatek,mt8195-apusys_pll";
2972 reg = <0 0x190f3000 0 2941 reg = <0 0x190f3000 0 0x1000>;
2973 #clock-cells = <1>; 2942 #clock-cells = <1>;
2974 }; 2943 };
2975 2944
2976 vencsys: clock-controller@1a0 2945 vencsys: clock-controller@1a000000 {
2977 compatible = "mediate 2946 compatible = "mediatek,mt8195-vencsys";
2978 reg = <0 0x1a000000 0 2947 reg = <0 0x1a000000 0 0x1000>;
2979 #clock-cells = <1>; 2948 #clock-cells = <1>;
2980 }; 2949 };
2981 2950
2982 larb19: larb@1a010000 { 2951 larb19: larb@1a010000 {
2983 compatible = "mediate 2952 compatible = "mediatek,mt8195-smi-larb";
2984 reg = <0 0x1a010000 0 2953 reg = <0 0x1a010000 0 0x1000>;
2985 mediatek,larb-id = <1 2954 mediatek,larb-id = <19>;
2986 mediatek,smi = <&smi_ 2955 mediatek,smi = <&smi_common_vdo>;
2987 clocks = <&vencsys CL 2956 clocks = <&vencsys CLK_VENC_VENC>,
2988 <&vencsys CL 2957 <&vencsys CLK_VENC_GALS>;
2989 clock-names = "apb", 2958 clock-names = "apb", "smi";
2990 power-domains = <&spm 2959 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2991 }; 2960 };
2992 2961
2993 venc: video-codec@1a020000 { 2962 venc: video-codec@1a020000 {
2994 compatible = "mediate 2963 compatible = "mediatek,mt8195-vcodec-enc";
2995 reg = <0 0x1a020000 0 2964 reg = <0 0x1a020000 0 0x10000>;
2996 iommus = <&iommu_vdo 2965 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2997 <&iommu_vdo 2966 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2998 <&iommu_vdo 2967 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2999 <&iommu_vdo 2968 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
3000 <&iommu_vdo 2969 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
3001 <&iommu_vdo 2970 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
3002 <&iommu_vdo 2971 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
3003 <&iommu_vdo 2972 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
3004 <&iommu_vdo 2973 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
3005 interrupts = <GIC_SPI 2974 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
3006 mediatek,scp = <&scp> 2975 mediatek,scp = <&scp>;
3007 clocks = <&vencsys CL 2976 clocks = <&vencsys CLK_VENC_VENC>;
3008 clock-names = "venc_s 2977 clock-names = "venc_sel";
3009 assigned-clocks = <&t 2978 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3010 assigned-clock-parent 2979 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3011 power-domains = <&spm 2980 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3012 #address-cells = <2>; 2981 #address-cells = <2>;
3013 #size-cells = <2>; 2982 #size-cells = <2>;
3014 }; 2983 };
3015 2984
3016 jpgdec-master { 2985 jpgdec-master {
3017 compatible = "mediate 2986 compatible = "mediatek,mt8195-jpgdec";
3018 power-domains = <&spm 2987 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3019 iommus = <&iommu_vdo 2988 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3020 <&iommu_vdo 2989 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3021 <&iommu_vdo 2990 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3022 <&iommu_vdo 2991 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3023 <&iommu_vdo 2992 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3024 <&iommu_vdo 2993 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3025 #address-cells = <2>; 2994 #address-cells = <2>;
3026 #size-cells = <2>; 2995 #size-cells = <2>;
3027 ranges; 2996 ranges;
3028 2997
3029 jpgdec@1a040000 { 2998 jpgdec@1a040000 {
3030 compatible = 2999 compatible = "mediatek,mt8195-jpgdec-hw";
3031 reg = <0 0x1a 3000 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3032 iommus = <&io 3001 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3033 <&io 3002 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3034 <&io 3003 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3035 <&io 3004 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3036 <&io 3005 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3037 <&io 3006 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3038 interrupts = 3007 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3039 clocks = <&ve 3008 clocks = <&vencsys CLK_VENC_JPGDEC>;
3040 clock-names = 3009 clock-names = "jpgdec";
3041 power-domains 3010 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3042 }; 3011 };
3043 3012
3044 jpgdec@1a050000 { 3013 jpgdec@1a050000 {
3045 compatible = 3014 compatible = "mediatek,mt8195-jpgdec-hw";
3046 reg = <0 0x1a 3015 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3047 iommus = <&io 3016 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3048 <&io 3017 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3049 <&io 3018 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3050 <&io 3019 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3051 <&io 3020 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3052 <&io 3021 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3053 interrupts = 3022 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3054 clocks = <&ve 3023 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3055 clock-names = 3024 clock-names = "jpgdec";
3056 power-domains 3025 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3057 }; 3026 };
3058 3027
3059 jpgdec@1b040000 { 3028 jpgdec@1b040000 {
3060 compatible = 3029 compatible = "mediatek,mt8195-jpgdec-hw";
3061 reg = <0 0x1b 3030 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3062 iommus = <&io 3031 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3063 <&io 3032 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3064 <&io 3033 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3065 <&io 3034 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3066 <&io 3035 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3067 <&io 3036 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3068 interrupts = 3037 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3069 clocks = <&ve 3038 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3070 clock-names = 3039 clock-names = "jpgdec";
3071 power-domains 3040 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3072 }; 3041 };
3073 }; 3042 };
3074 3043
3075 vencsys_core1: clock-controll 3044 vencsys_core1: clock-controller@1b000000 {
3076 compatible = "mediate 3045 compatible = "mediatek,mt8195-vencsys_core1";
3077 reg = <0 0x1b000000 0 3046 reg = <0 0x1b000000 0 0x1000>;
3078 #clock-cells = <1>; 3047 #clock-cells = <1>;
3079 }; 3048 };
3080 3049
3081 vdosys0: syscon@1c01a000 { 3050 vdosys0: syscon@1c01a000 {
3082 compatible = "mediate 3051 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3083 reg = <0 0x1c01a000 0 3052 reg = <0 0x1c01a000 0 0x1000>;
3084 mboxes = <&gce0 0 CMD 3053 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3085 #clock-cells = <1>; 3054 #clock-cells = <1>;
3086 mediatek,gce-client-r 3055 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3087 }; 3056 };
3088 3057
3089 3058
3090 jpgenc-master { 3059 jpgenc-master {
3091 compatible = "mediate 3060 compatible = "mediatek,mt8195-jpgenc";
3092 power-domains = <&spm 3061 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3093 iommus = <&iommu_vpp 3062 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3094 <&iom 3063 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3095 <&iom 3064 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3096 <&iom 3065 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3097 #address-cells = <2>; 3066 #address-cells = <2>;
3098 #size-cells = <2>; 3067 #size-cells = <2>;
3099 ranges; 3068 ranges;
3100 3069
3101 jpgenc@1a030000 { 3070 jpgenc@1a030000 {
3102 compatible = 3071 compatible = "mediatek,mt8195-jpgenc-hw";
3103 reg = <0 0x1a 3072 reg = <0 0x1a030000 0 0x10000>;
3104 iommus = <&io 3073 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3105 3074 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3106 3075 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3107 3076 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3108 interrupts = 3077 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3109 clocks = <&ve 3078 clocks = <&vencsys CLK_VENC_JPGENC>;
3110 clock-names = 3079 clock-names = "jpgenc";
3111 power-domains 3080 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3112 }; 3081 };
3113 3082
3114 jpgenc@1b030000 { 3083 jpgenc@1b030000 {
3115 compatible = 3084 compatible = "mediatek,mt8195-jpgenc-hw";
3116 reg = <0 0x1b 3085 reg = <0 0x1b030000 0 0x10000>;
3117 iommus = <&io 3086 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3118 3087 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3119 3088 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3120 3089 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3121 interrupts = 3090 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3122 clocks = <&ve 3091 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3123 clock-names = 3092 clock-names = "jpgenc";
3124 power-domains 3093 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3125 }; 3094 };
3126 }; 3095 };
3127 3096
3128 larb20: larb@1b010000 { 3097 larb20: larb@1b010000 {
3129 compatible = "mediate 3098 compatible = "mediatek,mt8195-smi-larb";
3130 reg = <0 0x1b010000 0 3099 reg = <0 0x1b010000 0 0x1000>;
3131 mediatek,larb-id = <2 3100 mediatek,larb-id = <20>;
3132 mediatek,smi = <&smi_ 3101 mediatek,smi = <&smi_common_vpp>;
3133 clocks = <&vencsys_co 3102 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
3134 <&vencsys_co 3103 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3135 <&vppsys0 CL 3104 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3136 clock-names = "apb", 3105 clock-names = "apb", "smi", "gals";
3137 power-domains = <&spm 3106 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3138 }; 3107 };
3139 3108
3140 ovl0: ovl@1c000000 { 3109 ovl0: ovl@1c000000 {
3141 compatible = "mediate 3110 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3142 reg = <0 0x1c000000 0 3111 reg = <0 0x1c000000 0 0x1000>;
3143 interrupts = <GIC_SPI 3112 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3144 power-domains = <&spm 3113 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3145 clocks = <&vdosys0 CL 3114 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3146 iommus = <&iommu_vdo 3115 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3147 mediatek,gce-client-r 3116 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3148 }; 3117 };
3149 3118
3150 rdma0: rdma@1c002000 { 3119 rdma0: rdma@1c002000 {
3151 compatible = "mediate 3120 compatible = "mediatek,mt8195-disp-rdma";
3152 reg = <0 0x1c002000 0 3121 reg = <0 0x1c002000 0 0x1000>;
3153 interrupts = <GIC_SPI 3122 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3154 power-domains = <&spm 3123 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3155 clocks = <&vdosys0 CL 3124 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3156 iommus = <&iommu_vdo 3125 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3157 mediatek,gce-client-r 3126 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3158 }; 3127 };
3159 3128
3160 color0: color@1c003000 { 3129 color0: color@1c003000 {
3161 compatible = "mediate 3130 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3162 reg = <0 0x1c003000 0 3131 reg = <0 0x1c003000 0 0x1000>;
3163 interrupts = <GIC_SPI 3132 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3164 power-domains = <&spm 3133 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3165 clocks = <&vdosys0 CL 3134 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3166 mediatek,gce-client-r 3135 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3167 }; 3136 };
3168 3137
3169 ccorr0: ccorr@1c004000 { 3138 ccorr0: ccorr@1c004000 {
3170 compatible = "mediate 3139 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3171 reg = <0 0x1c004000 0 3140 reg = <0 0x1c004000 0 0x1000>;
3172 interrupts = <GIC_SPI 3141 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3173 power-domains = <&spm 3142 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3174 clocks = <&vdosys0 CL 3143 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3175 mediatek,gce-client-r 3144 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3176 }; 3145 };
3177 3146
3178 aal0: aal@1c005000 { 3147 aal0: aal@1c005000 {
3179 compatible = "mediate 3148 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3180 reg = <0 0x1c005000 0 3149 reg = <0 0x1c005000 0 0x1000>;
3181 interrupts = <GIC_SPI 3150 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3182 power-domains = <&spm 3151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3183 clocks = <&vdosys0 CL 3152 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3184 mediatek,gce-client-r 3153 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3185 }; 3154 };
3186 3155
3187 gamma0: gamma@1c006000 { 3156 gamma0: gamma@1c006000 {
3188 compatible = "mediate 3157 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3189 reg = <0 0x1c006000 0 3158 reg = <0 0x1c006000 0 0x1000>;
3190 interrupts = <GIC_SPI 3159 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3191 power-domains = <&spm 3160 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3192 clocks = <&vdosys0 CL 3161 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3193 mediatek,gce-client-r 3162 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3194 }; 3163 };
3195 3164
3196 dither0: dither@1c007000 { 3165 dither0: dither@1c007000 {
3197 compatible = "mediate 3166 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3198 reg = <0 0x1c007000 0 3167 reg = <0 0x1c007000 0 0x1000>;
3199 interrupts = <GIC_SPI 3168 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3200 power-domains = <&spm 3169 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3201 clocks = <&vdosys0 CL 3170 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3202 mediatek,gce-client-r 3171 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3203 }; 3172 };
3204 3173
3205 dsi0: dsi@1c008000 { 3174 dsi0: dsi@1c008000 {
3206 compatible = "mediate 3175 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3207 reg = <0 0x1c008000 0 3176 reg = <0 0x1c008000 0 0x1000>;
3208 interrupts = <GIC_SPI 3177 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
3209 power-domains = <&spm 3178 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3210 clocks = <&vdosys0 CL 3179 clocks = <&vdosys0 CLK_VDO0_DSI0>,
3211 <&vdosys0 CL 3180 <&vdosys0 CLK_VDO0_DSI0_DSI>,
3212 <&mipi_tx0>; 3181 <&mipi_tx0>;
3213 clock-names = "engine 3182 clock-names = "engine", "digital", "hs";
3214 phys = <&mipi_tx0>; 3183 phys = <&mipi_tx0>;
3215 phy-names = "dphy"; 3184 phy-names = "dphy";
3216 status = "disabled"; 3185 status = "disabled";
3217 }; 3186 };
3218 3187
3219 dsc0: dsc@1c009000 { 3188 dsc0: dsc@1c009000 {
3220 compatible = "mediate 3189 compatible = "mediatek,mt8195-disp-dsc";
3221 reg = <0 0x1c009000 0 3190 reg = <0 0x1c009000 0 0x1000>;
3222 interrupts = <GIC_SPI 3191 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3223 power-domains = <&spm 3192 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3224 clocks = <&vdosys0 CL 3193 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3225 mediatek,gce-client-r 3194 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3226 }; 3195 };
3227 3196
3228 dsi1: dsi@1c012000 { 3197 dsi1: dsi@1c012000 {
3229 compatible = "mediate 3198 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3230 reg = <0 0x1c012000 0 3199 reg = <0 0x1c012000 0 0x1000>;
3231 interrupts = <GIC_SPI 3200 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
3232 power-domains = <&spm 3201 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3233 clocks = <&vdosys0 CL 3202 clocks = <&vdosys0 CLK_VDO0_DSI1>,
3234 <&vdosys0 CL 3203 <&vdosys0 CLK_VDO0_DSI1_DSI>,
3235 <&mipi_tx1>; 3204 <&mipi_tx1>;
3236 clock-names = "engine 3205 clock-names = "engine", "digital", "hs";
3237 phys = <&mipi_tx1>; 3206 phys = <&mipi_tx1>;
3238 phy-names = "dphy"; 3207 phy-names = "dphy";
3239 status = "disabled"; 3208 status = "disabled";
3240 }; 3209 };
3241 3210
3242 merge0: merge@1c014000 { 3211 merge0: merge@1c014000 {
3243 compatible = "mediate 3212 compatible = "mediatek,mt8195-disp-merge";
3244 reg = <0 0x1c014000 0 3213 reg = <0 0x1c014000 0 0x1000>;
3245 interrupts = <GIC_SPI 3214 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3246 power-domains = <&spm 3215 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3247 clocks = <&vdosys0 CL 3216 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3248 mediatek,gce-client-r 3217 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3249 }; 3218 };
3250 3219
3251 dp_intf0: dp-intf@1c015000 { 3220 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediate 3221 compatible = "mediatek,mt8195-dp-intf";
3253 reg = <0 0x1c015000 0 3222 reg = <0 0x1c015000 0 0x1000>;
3254 interrupts = <GIC_SPI 3223 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3255 clocks = <&vdosys0 CL !! 3224 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
3256 <&vdosys0 C !! 3225 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3257 <&apmixedsys 3226 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3258 clock-names = "pixel" !! 3227 clock-names = "engine", "pixel", "pll";
3259 status = "disabled"; 3228 status = "disabled";
3260 }; 3229 };
3261 3230
3262 mutex: mutex@1c016000 { 3231 mutex: mutex@1c016000 {
3263 compatible = "mediate 3232 compatible = "mediatek,mt8195-disp-mutex";
3264 reg = <0 0x1c016000 0 3233 reg = <0 0x1c016000 0 0x1000>;
3265 interrupts = <GIC_SPI 3234 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3266 power-domains = <&spm 3235 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3267 clocks = <&vdosys0 CL 3236 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3268 mediatek,gce-client-r 3237 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3269 mediatek,gce-events = 3238 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3270 }; 3239 };
3271 3240
3272 larb0: larb@1c018000 { 3241 larb0: larb@1c018000 {
3273 compatible = "mediate 3242 compatible = "mediatek,mt8195-smi-larb";
3274 reg = <0 0x1c018000 0 3243 reg = <0 0x1c018000 0 0x1000>;
3275 mediatek,larb-id = <0 3244 mediatek,larb-id = <0>;
3276 mediatek,smi = <&smi_ 3245 mediatek,smi = <&smi_common_vdo>;
3277 clocks = <&vdosys0 CL 3246 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3278 <&vdosys0 CL 3247 <&vdosys0 CLK_VDO0_SMI_LARB>,
3279 <&vppsys0 CL 3248 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3280 clock-names = "apb", 3249 clock-names = "apb", "smi", "gals";
3281 power-domains = <&spm 3250 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3282 }; 3251 };
3283 3252
3284 larb1: larb@1c019000 { 3253 larb1: larb@1c019000 {
3285 compatible = "mediate 3254 compatible = "mediatek,mt8195-smi-larb";
3286 reg = <0 0x1c019000 0 3255 reg = <0 0x1c019000 0 0x1000>;
3287 mediatek,larb-id = <1 3256 mediatek,larb-id = <1>;
3288 mediatek,smi = <&smi_ 3257 mediatek,smi = <&smi_common_vpp>;
3289 clocks = <&vdosys0 CL 3258 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3290 <&vppsys0 CL 3259 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3291 <&vppsys0 CL 3260 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3292 clock-names = "apb", 3261 clock-names = "apb", "smi", "gals";
3293 power-domains = <&spm 3262 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294 }; 3263 };
3295 3264
3296 vdosys1: syscon@1c100000 { 3265 vdosys1: syscon@1c100000 {
3297 compatible = "mediate 3266 compatible = "mediatek,mt8195-vdosys1", "syscon";
3298 reg = <0 0x1c100000 0 3267 reg = <0 0x1c100000 0 0x1000>;
3299 mboxes = <&gce0 1 CMD 3268 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3300 mediatek,gce-client-r 3269 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3301 #clock-cells = <1>; 3270 #clock-cells = <1>;
3302 #reset-cells = <1>; 3271 #reset-cells = <1>;
3303 }; 3272 };
3304 3273
3305 smi_common_vdo: smi@1c01b000 3274 smi_common_vdo: smi@1c01b000 {
3306 compatible = "mediate 3275 compatible = "mediatek,mt8195-smi-common-vdo";
3307 reg = <0 0x1c01b000 0 3276 reg = <0 0x1c01b000 0 0x1000>;
3308 clocks = <&vdosys0 CL 3277 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3309 <&vdosys0 CL 3278 <&vdosys0 CLK_VDO0_SMI_EMI>,
3310 <&vdosys0 CL 3279 <&vdosys0 CLK_VDO0_SMI_RSI>,
3311 <&vdosys0 CL 3280 <&vdosys0 CLK_VDO0_SMI_GALS>;
3312 clock-names = "apb", 3281 clock-names = "apb", "smi", "gals0", "gals1";
3313 power-domains = <&spm 3282 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3314 3283
3315 }; 3284 };
3316 3285
3317 iommu_vdo: iommu@1c01f000 { 3286 iommu_vdo: iommu@1c01f000 {
3318 compatible = "mediate 3287 compatible = "mediatek,mt8195-iommu-vdo";
3319 reg = <0 0x1c01f000 0 3288 reg = <0 0x1c01f000 0 0x1000>;
3320 mediatek,larbs = <&la 3289 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3321 &la 3290 &larb10 &larb11 &larb13 &larb17
3322 &la 3291 &larb19 &larb21 &larb24 &larb25
3323 &la 3292 &larb28>;
3324 interrupts = <GIC_SPI 3293 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3325 #iommu-cells = <1>; 3294 #iommu-cells = <1>;
3326 clocks = <&vdosys0 CL 3295 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3327 clock-names = "bclk"; 3296 clock-names = "bclk";
3328 power-domains = <&spm 3297 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3329 }; 3298 };
3330 3299
3331 mutex1: mutex@1c101000 { 3300 mutex1: mutex@1c101000 {
3332 compatible = "mediate 3301 compatible = "mediatek,mt8195-disp-mutex";
3333 reg = <0 0x1c101000 0 3302 reg = <0 0x1c101000 0 0x1000>;
3334 reg-names = "vdo1_mut 3303 reg-names = "vdo1_mutex";
3335 interrupts = <GIC_SPI 3304 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3336 power-domains = <&spm 3305 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3337 clocks = <&vdosys1 CL 3306 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3338 clock-names = "vdo1_m 3307 clock-names = "vdo1_mutex";
3339 mediatek,gce-client-r 3308 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3340 mediatek,gce-events = 3309 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3341 }; 3310 };
3342 3311
3343 larb2: larb@1c102000 { 3312 larb2: larb@1c102000 {
3344 compatible = "mediate 3313 compatible = "mediatek,mt8195-smi-larb";
3345 reg = <0 0x1c102000 0 3314 reg = <0 0x1c102000 0 0x1000>;
3346 mediatek,larb-id = <2 3315 mediatek,larb-id = <2>;
3347 mediatek,smi = <&smi_ 3316 mediatek,smi = <&smi_common_vdo>;
3348 clocks = <&vdosys1 CL 3317 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CL 3318 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3350 <&vdosys1 CL 3319 <&vdosys1 CLK_VDO1_GALS>;
3351 clock-names = "apb", 3320 clock-names = "apb", "smi", "gals";
3352 power-domains = <&spm 3321 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3353 }; 3322 };
3354 3323
3355 larb3: larb@1c103000 { 3324 larb3: larb@1c103000 {
3356 compatible = "mediate 3325 compatible = "mediatek,mt8195-smi-larb";
3357 reg = <0 0x1c103000 0 3326 reg = <0 0x1c103000 0 0x1000>;
3358 mediatek,larb-id = <3 3327 mediatek,larb-id = <3>;
3359 mediatek,smi = <&smi_ 3328 mediatek,smi = <&smi_common_vpp>;
3360 clocks = <&vdosys1 CL 3329 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3361 <&vdosys1 CL 3330 <&vdosys1 CLK_VDO1_GALS>,
3362 <&vppsys0 CL 3331 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3363 clock-names = "apb", 3332 clock-names = "apb", "smi", "gals";
3364 power-domains = <&spm 3333 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3365 }; 3334 };
3366 3335
3367 vdo1_rdma0: dma-controller@1c 3336 vdo1_rdma0: dma-controller@1c104000 {
3368 compatible = "mediate 3337 compatible = "mediatek,mt8195-vdo1-rdma";
3369 reg = <0 0x1c104000 0 3338 reg = <0 0x1c104000 0 0x1000>;
3370 interrupts = <GIC_SPI 3339 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
3371 clocks = <&vdosys1 CL 3340 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3372 power-domains = <&spm 3341 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3373 iommus = <&iommu_vdo 3342 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
3374 mediatek,gce-client-r 3343 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3375 #dma-cells = <1>; 3344 #dma-cells = <1>;
3376 }; 3345 };
3377 3346
3378 vdo1_rdma1: dma-controller@1c 3347 vdo1_rdma1: dma-controller@1c105000 {
3379 compatible = "mediate 3348 compatible = "mediatek,mt8195-vdo1-rdma";
3380 reg = <0 0x1c105000 0 3349 reg = <0 0x1c105000 0 0x1000>;
3381 interrupts = <GIC_SPI 3350 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
3382 clocks = <&vdosys1 CL 3351 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3383 power-domains = <&spm 3352 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3384 iommus = <&iommu_vpp 3353 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
3385 mediatek,gce-client-r 3354 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3386 #dma-cells = <1>; 3355 #dma-cells = <1>;
3387 }; 3356 };
3388 3357
3389 vdo1_rdma2: dma-controller@1c 3358 vdo1_rdma2: dma-controller@1c106000 {
3390 compatible = "mediate 3359 compatible = "mediatek,mt8195-vdo1-rdma";
3391 reg = <0 0x1c106000 0 3360 reg = <0 0x1c106000 0 0x1000>;
3392 interrupts = <GIC_SPI 3361 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
3393 clocks = <&vdosys1 CL 3362 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3394 power-domains = <&spm 3363 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3395 iommus = <&iommu_vdo 3364 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
3396 mediatek,gce-client-r 3365 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3397 #dma-cells = <1>; 3366 #dma-cells = <1>;
3398 }; 3367 };
3399 3368
3400 vdo1_rdma3: dma-controller@1c 3369 vdo1_rdma3: dma-controller@1c107000 {
3401 compatible = "mediate 3370 compatible = "mediatek,mt8195-vdo1-rdma";
3402 reg = <0 0x1c107000 0 3371 reg = <0 0x1c107000 0 0x1000>;
3403 interrupts = <GIC_SPI 3372 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
3404 clocks = <&vdosys1 CL 3373 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3405 power-domains = <&spm 3374 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3406 iommus = <&iommu_vpp 3375 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
3407 mediatek,gce-client-r 3376 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3408 #dma-cells = <1>; 3377 #dma-cells = <1>;
3409 }; 3378 };
3410 3379
3411 vdo1_rdma4: dma-controller@1c 3380 vdo1_rdma4: dma-controller@1c108000 {
3412 compatible = "mediate 3381 compatible = "mediatek,mt8195-vdo1-rdma";
3413 reg = <0 0x1c108000 0 3382 reg = <0 0x1c108000 0 0x1000>;
3414 interrupts = <GIC_SPI 3383 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
3415 clocks = <&vdosys1 CL 3384 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3416 power-domains = <&spm 3385 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3417 iommus = <&iommu_vdo 3386 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
3418 mediatek,gce-client-r 3387 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3419 #dma-cells = <1>; 3388 #dma-cells = <1>;
3420 }; 3389 };
3421 3390
3422 vdo1_rdma5: dma-controller@1c 3391 vdo1_rdma5: dma-controller@1c109000 {
3423 compatible = "mediate 3392 compatible = "mediatek,mt8195-vdo1-rdma";
3424 reg = <0 0x1c109000 0 3393 reg = <0 0x1c109000 0 0x1000>;
3425 interrupts = <GIC_SPI 3394 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
3426 clocks = <&vdosys1 CL 3395 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3427 power-domains = <&spm 3396 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3428 iommus = <&iommu_vpp 3397 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
3429 mediatek,gce-client-r 3398 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3430 #dma-cells = <1>; 3399 #dma-cells = <1>;
3431 }; 3400 };
3432 3401
3433 vdo1_rdma6: dma-controller@1c 3402 vdo1_rdma6: dma-controller@1c10a000 {
3434 compatible = "mediate 3403 compatible = "mediatek,mt8195-vdo1-rdma";
3435 reg = <0 0x1c10a000 0 3404 reg = <0 0x1c10a000 0 0x1000>;
3436 interrupts = <GIC_SPI 3405 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
3437 clocks = <&vdosys1 CL 3406 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3438 power-domains = <&spm 3407 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3439 iommus = <&iommu_vdo 3408 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
3440 mediatek,gce-client-r 3409 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3441 #dma-cells = <1>; 3410 #dma-cells = <1>;
3442 }; 3411 };
3443 3412
3444 vdo1_rdma7: dma-controller@1c 3413 vdo1_rdma7: dma-controller@1c10b000 {
3445 compatible = "mediate 3414 compatible = "mediatek,mt8195-vdo1-rdma";
3446 reg = <0 0x1c10b000 0 3415 reg = <0 0x1c10b000 0 0x1000>;
3447 interrupts = <GIC_SPI 3416 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
3448 clocks = <&vdosys1 CL 3417 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3449 power-domains = <&spm 3418 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3450 iommus = <&iommu_vpp 3419 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
3451 mediatek,gce-client-r 3420 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3452 #dma-cells = <1>; 3421 #dma-cells = <1>;
3453 }; 3422 };
3454 3423
3455 merge1: vpp-merge@1c10c000 { 3424 merge1: vpp-merge@1c10c000 {
3456 compatible = "mediate 3425 compatible = "mediatek,mt8195-disp-merge";
3457 reg = <0 0x1c10c000 0 3426 reg = <0 0x1c10c000 0 0x1000>;
3458 interrupts = <GIC_SPI 3427 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
3459 clocks = <&vdosys1 CL 3428 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3460 <&vdosys1 CL 3429 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3461 clock-names = "merge" 3430 clock-names = "merge","merge_async";
3462 power-domains = <&spm 3431 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3463 mediatek,gce-client-r 3432 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3464 mediatek,merge-mute; 3433 mediatek,merge-mute;
3465 resets = <&vdosys1 MT 3434 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3466 }; 3435 };
3467 3436
3468 merge2: vpp-merge@1c10d000 { 3437 merge2: vpp-merge@1c10d000 {
3469 compatible = "mediate 3438 compatible = "mediatek,mt8195-disp-merge";
3470 reg = <0 0x1c10d000 0 3439 reg = <0 0x1c10d000 0 0x1000>;
3471 interrupts = <GIC_SPI 3440 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
3472 clocks = <&vdosys1 CL 3441 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3473 <&vdosys1 CL 3442 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3474 clock-names = "merge" 3443 clock-names = "merge","merge_async";
3475 power-domains = <&spm 3444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3476 mediatek,gce-client-r 3445 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3477 mediatek,merge-mute; 3446 mediatek,merge-mute;
3478 resets = <&vdosys1 MT 3447 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3479 }; 3448 };
3480 3449
3481 merge3: vpp-merge@1c10e000 { 3450 merge3: vpp-merge@1c10e000 {
3482 compatible = "mediate 3451 compatible = "mediatek,mt8195-disp-merge";
3483 reg = <0 0x1c10e000 0 3452 reg = <0 0x1c10e000 0 0x1000>;
3484 interrupts = <GIC_SPI 3453 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
3485 clocks = <&vdosys1 CL 3454 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3486 <&vdosys1 CL 3455 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3487 clock-names = "merge" 3456 clock-names = "merge","merge_async";
3488 power-domains = <&spm 3457 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3489 mediatek,gce-client-r 3458 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3490 mediatek,merge-mute; 3459 mediatek,merge-mute;
3491 resets = <&vdosys1 MT 3460 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3492 }; 3461 };
3493 3462
3494 merge4: vpp-merge@1c10f000 { 3463 merge4: vpp-merge@1c10f000 {
3495 compatible = "mediate 3464 compatible = "mediatek,mt8195-disp-merge";
3496 reg = <0 0x1c10f000 0 3465 reg = <0 0x1c10f000 0 0x1000>;
3497 interrupts = <GIC_SPI 3466 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
3498 clocks = <&vdosys1 CL 3467 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3499 <&vdosys1 CL 3468 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3500 clock-names = "merge" 3469 clock-names = "merge","merge_async";
3501 power-domains = <&spm 3470 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3502 mediatek,gce-client-r 3471 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3503 mediatek,merge-mute; 3472 mediatek,merge-mute;
3504 resets = <&vdosys1 MT 3473 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3505 }; 3474 };
3506 3475
3507 merge5: vpp-merge@1c110000 { 3476 merge5: vpp-merge@1c110000 {
3508 compatible = "mediate 3477 compatible = "mediatek,mt8195-disp-merge";
3509 reg = <0 0x1c110000 0 3478 reg = <0 0x1c110000 0 0x1000>;
3510 interrupts = <GIC_SPI 3479 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3511 clocks = <&vdosys1 CL 3480 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3512 <&vdosys1 CL 3481 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3513 clock-names = "merge" 3482 clock-names = "merge","merge_async";
3514 power-domains = <&spm 3483 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3515 mediatek,gce-client-r 3484 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3516 mediatek,merge-fifo-e 3485 mediatek,merge-fifo-en;
3517 resets = <&vdosys1 MT 3486 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3518 }; 3487 };
3519 3488
3520 dp_intf1: dp-intf@1c113000 { 3489 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediate 3490 compatible = "mediatek,mt8195-dp-intf";
3522 reg = <0 0x1c113000 0 3491 reg = <0 0x1c113000 0 0x1000>;
3523 interrupts = <GIC_SPI 3492 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3524 power-domains = <&spm 3493 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3525 clocks = <&vdosys1 CL !! 3494 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3526 <&vdosys1 CL !! 3495 <&vdosys1 CLK_VDO1_DPINTF>,
3527 <&apmixedsys 3496 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3528 clock-names = "pixel" !! 3497 clock-names = "engine", "pixel", "pll";
3529 status = "disabled"; 3498 status = "disabled";
3530 }; 3499 };
3531 3500
3532 ethdr0: hdr-engine@1c114000 { 3501 ethdr0: hdr-engine@1c114000 {
3533 compatible = "mediate 3502 compatible = "mediatek,mt8195-disp-ethdr";
3534 reg = <0 0x1c114000 0 3503 reg = <0 0x1c114000 0 0x1000>,
3535 <0 0x1c115000 0 3504 <0 0x1c115000 0 0x1000>,
3536 <0 0x1c117000 0 3505 <0 0x1c117000 0 0x1000>,
3537 <0 0x1c119000 0 3506 <0 0x1c119000 0 0x1000>,
3538 <0 0x1c11a000 0 3507 <0 0x1c11a000 0 0x1000>,
3539 <0 0x1c11b000 0 3508 <0 0x1c11b000 0 0x1000>,
3540 <0 0x1c11c000 0 3509 <0 0x1c11c000 0 0x1000>;
3541 reg-names = "mixer", 3510 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3542 "vdo_be", 3511 "vdo_be", "adl_ds";
3543 mediatek,gce-client-r 3512 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3544 3513 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3545 3514 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3546 3515 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3547 3516 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3548 3517 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3549 3518 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3550 clocks = <&vdosys1 CL 3519 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3551 <&vdosys1 CL 3520 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3552 <&vdosys1 CL 3521 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3553 <&vdosys1 CL 3522 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3554 <&vdosys1 CL 3523 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3555 <&vdosys1 CL 3524 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3556 <&vdosys1 CL 3525 <&vdosys1 CLK_VDO1_26M_SLOW>,
3557 <&vdosys1 CL 3526 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3558 <&vdosys1 CL 3527 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3559 <&vdosys1 CL 3528 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3560 <&vdosys1 CL 3529 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3561 <&vdosys1 CL 3530 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3562 <&topckgen C 3531 <&topckgen CLK_TOP_ETHDR>;
3563 clock-names = "mixer" 3532 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3564 "vdo_be 3533 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3565 "gfx_fe 3534 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3566 "ethdr_ 3535 "ethdr_top";
3567 power-domains = <&spm 3536 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3568 iommus = <&iommu_vpp 3537 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3569 <&iommu_vpp 3538 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3570 interrupts = <GIC_SPI 3539 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3571 resets = <&vdosys1 MT 3540 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3572 <&vdosys1 MT 3541 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3573 <&vdosys1 MT 3542 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3574 <&vdosys1 MT 3543 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3575 <&vdosys1 MT 3544 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3576 reset-names = "vdo_fe 3545 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3577 "gfx_fe 3546 "gfx_fe1_async", "vdo_be_async";
3578 }; 3547 };
3579 3548
3580 edp_tx: edp-tx@1c500000 { 3549 edp_tx: edp-tx@1c500000 {
3581 compatible = "mediate 3550 compatible = "mediatek,mt8195-edp-tx";
3582 reg = <0 0x1c500000 0 3551 reg = <0 0x1c500000 0 0x8000>;
3583 nvmem-cells = <&dp_ca 3552 nvmem-cells = <&dp_calibration>;
3584 nvmem-cell-names = "d 3553 nvmem-cell-names = "dp_calibration_data";
3585 power-domains = <&spm 3554 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3586 interrupts = <GIC_SPI 3555 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3587 max-linkrate-mhz = <8 3556 max-linkrate-mhz = <8100>;
3588 status = "disabled"; 3557 status = "disabled";
3589 }; 3558 };
3590 3559
3591 dp_tx: dp-tx@1c600000 { 3560 dp_tx: dp-tx@1c600000 {
3592 compatible = "mediate 3561 compatible = "mediatek,mt8195-dp-tx";
3593 reg = <0 0x1c600000 0 3562 reg = <0 0x1c600000 0 0x8000>;
3594 nvmem-cells = <&dp_ca 3563 nvmem-cells = <&dp_calibration>;
3595 nvmem-cell-names = "d 3564 nvmem-cell-names = "dp_calibration_data";
3596 power-domains = <&spm 3565 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3597 interrupts = <GIC_SPI 3566 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3598 max-linkrate-mhz = <8 3567 max-linkrate-mhz = <8100>;
3599 status = "disabled"; 3568 status = "disabled";
3600 }; 3569 };
3601 }; 3570 };
3602 3571
3603 thermal_zones: thermal-zones { 3572 thermal_zones: thermal-zones {
3604 cpu0-thermal { 3573 cpu0-thermal {
3605 polling-delay = <1000 3574 polling-delay = <1000>;
3606 polling-delay-passive 3575 polling-delay-passive = <250>;
3607 thermal-sensors = <&l 3576 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3608 3577
3609 trips { 3578 trips {
3610 cpu0_alert: t 3579 cpu0_alert: trip-alert {
3611 tempe 3580 temperature = <85000>;
3612 hyste 3581 hysteresis = <2000>;
3613 type 3582 type = "passive";
3614 }; 3583 };
3615 3584
3616 cpu0_crit: tr 3585 cpu0_crit: trip-crit {
3617 tempe 3586 temperature = <100000>;
3618 hyste 3587 hysteresis = <2000>;
3619 type 3588 type = "critical";
3620 }; 3589 };
3621 }; 3590 };
3622 3591
3623 cooling-maps { 3592 cooling-maps {
3624 map0 { 3593 map0 {
3625 trip 3594 trip = <&cpu0_alert>;
3626 cooli 3595 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3627 3596 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628 3597 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3629 3598 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3630 }; 3599 };
3631 }; 3600 };
3632 }; 3601 };
3633 3602
3634 cpu1-thermal { 3603 cpu1-thermal {
3635 polling-delay = <1000 3604 polling-delay = <1000>;
3636 polling-delay-passive 3605 polling-delay-passive = <250>;
3637 thermal-sensors = <&l 3606 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3638 3607
3639 trips { 3608 trips {
3640 cpu1_alert: t 3609 cpu1_alert: trip-alert {
3641 tempe 3610 temperature = <85000>;
3642 hyste 3611 hysteresis = <2000>;
3643 type 3612 type = "passive";
3644 }; 3613 };
3645 3614
3646 cpu1_crit: tr 3615 cpu1_crit: trip-crit {
3647 tempe 3616 temperature = <100000>;
3648 hyste 3617 hysteresis = <2000>;
3649 type 3618 type = "critical";
3650 }; 3619 };
3651 }; 3620 };
3652 3621
3653 cooling-maps { 3622 cooling-maps {
3654 map0 { 3623 map0 {
3655 trip 3624 trip = <&cpu1_alert>;
3656 cooli 3625 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 3626 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658 3627 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659 3628 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3660 }; 3629 };
3661 }; 3630 };
3662 }; 3631 };
3663 3632
3664 cpu2-thermal { 3633 cpu2-thermal {
3665 polling-delay = <1000 3634 polling-delay = <1000>;
3666 polling-delay-passive 3635 polling-delay-passive = <250>;
3667 thermal-sensors = <&l 3636 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3668 3637
3669 trips { 3638 trips {
3670 cpu2_alert: t 3639 cpu2_alert: trip-alert {
3671 tempe 3640 temperature = <85000>;
3672 hyste 3641 hysteresis = <2000>;
3673 type 3642 type = "passive";
3674 }; 3643 };
3675 3644
3676 cpu2_crit: tr 3645 cpu2_crit: trip-crit {
3677 tempe 3646 temperature = <100000>;
3678 hyste 3647 hysteresis = <2000>;
3679 type 3648 type = "critical";
3680 }; 3649 };
3681 }; 3650 };
3682 3651
3683 cooling-maps { 3652 cooling-maps {
3684 map0 { 3653 map0 {
3685 trip 3654 trip = <&cpu2_alert>;
3686 cooli 3655 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687 3656 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 3657 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689 3658 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3690 }; 3659 };
3691 }; 3660 };
3692 }; 3661 };
3693 3662
3694 cpu3-thermal { 3663 cpu3-thermal {
3695 polling-delay = <1000 3664 polling-delay = <1000>;
3696 polling-delay-passive 3665 polling-delay-passive = <250>;
3697 thermal-sensors = <&l 3666 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3698 3667
3699 trips { 3668 trips {
3700 cpu3_alert: t 3669 cpu3_alert: trip-alert {
3701 tempe 3670 temperature = <85000>;
3702 hyste 3671 hysteresis = <2000>;
3703 type 3672 type = "passive";
3704 }; 3673 };
3705 3674
3706 cpu3_crit: tr 3675 cpu3_crit: trip-crit {
3707 tempe 3676 temperature = <100000>;
3708 hyste 3677 hysteresis = <2000>;
3709 type 3678 type = "critical";
3710 }; 3679 };
3711 }; 3680 };
3712 3681
3713 cooling-maps { 3682 cooling-maps {
3714 map0 { 3683 map0 {
3715 trip 3684 trip = <&cpu3_alert>;
3716 cooli 3685 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717 3686 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718 3687 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719 3688 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3720 }; 3689 };
3721 }; 3690 };
3722 }; 3691 };
3723 3692
3724 cpu4-thermal { 3693 cpu4-thermal {
3725 polling-delay = <1000 3694 polling-delay = <1000>;
3726 polling-delay-passive 3695 polling-delay-passive = <250>;
3727 thermal-sensors = <&l 3696 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3728 3697
3729 trips { 3698 trips {
3730 cpu4_alert: t 3699 cpu4_alert: trip-alert {
3731 tempe 3700 temperature = <85000>;
3732 hyste 3701 hysteresis = <2000>;
3733 type 3702 type = "passive";
3734 }; 3703 };
3735 3704
3736 cpu4_crit: tr 3705 cpu4_crit: trip-crit {
3737 tempe 3706 temperature = <100000>;
3738 hyste 3707 hysteresis = <2000>;
3739 type 3708 type = "critical";
3740 }; 3709 };
3741 }; 3710 };
3742 3711
3743 cooling-maps { 3712 cooling-maps {
3744 map0 { 3713 map0 {
3745 trip 3714 trip = <&cpu4_alert>;
3746 cooli 3715 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 3716 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3748 3717 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3749 3718 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3750 }; 3719 };
3751 }; 3720 };
3752 }; 3721 };
3753 3722
3754 cpu5-thermal { 3723 cpu5-thermal {
3755 polling-delay = <1000 3724 polling-delay = <1000>;
3756 polling-delay-passive 3725 polling-delay-passive = <250>;
3757 thermal-sensors = <&l 3726 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3758 3727
3759 trips { 3728 trips {
3760 cpu5_alert: t 3729 cpu5_alert: trip-alert {
3761 tempe 3730 temperature = <85000>;
3762 hyste 3731 hysteresis = <2000>;
3763 type 3732 type = "passive";
3764 }; 3733 };
3765 3734
3766 cpu5_crit: tr 3735 cpu5_crit: trip-crit {
3767 tempe 3736 temperature = <100000>;
3768 hyste 3737 hysteresis = <2000>;
3769 type 3738 type = "critical";
3770 }; 3739 };
3771 }; 3740 };
3772 3741
3773 cooling-maps { 3742 cooling-maps {
3774 map0 { 3743 map0 {
3775 trip 3744 trip = <&cpu5_alert>;
3776 cooli 3745 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 3746 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 3747 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779 3748 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3780 }; 3749 };
3781 }; 3750 };
3782 }; 3751 };
3783 3752
3784 cpu6-thermal { 3753 cpu6-thermal {
3785 polling-delay = <1000 3754 polling-delay = <1000>;
3786 polling-delay-passive 3755 polling-delay-passive = <250>;
3787 thermal-sensors = <&l 3756 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3788 3757
3789 trips { 3758 trips {
3790 cpu6_alert: t 3759 cpu6_alert: trip-alert {
3791 tempe 3760 temperature = <85000>;
3792 hyste 3761 hysteresis = <2000>;
3793 type 3762 type = "passive";
3794 }; 3763 };
3795 3764
3796 cpu6_crit: tr 3765 cpu6_crit: trip-crit {
3797 tempe 3766 temperature = <100000>;
3798 hyste 3767 hysteresis = <2000>;
3799 type 3768 type = "critical";
3800 }; 3769 };
3801 }; 3770 };
3802 3771
3803 cooling-maps { 3772 cooling-maps {
3804 map0 { 3773 map0 {
3805 trip 3774 trip = <&cpu6_alert>;
3806 cooli 3775 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807 3776 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808 3777 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809 3778 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3810 }; 3779 };
3811 }; 3780 };
3812 }; 3781 };
3813 3782
3814 cpu7-thermal { 3783 cpu7-thermal {
3815 polling-delay = <1000 3784 polling-delay = <1000>;
3816 polling-delay-passive 3785 polling-delay-passive = <250>;
3817 thermal-sensors = <&l 3786 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3818 3787
3819 trips { 3788 trips {
3820 cpu7_alert: t 3789 cpu7_alert: trip-alert {
3821 tempe 3790 temperature = <85000>;
3822 hyste 3791 hysteresis = <2000>;
3823 type 3792 type = "passive";
3824 }; 3793 };
3825 3794
3826 cpu7_crit: tr 3795 cpu7_crit: trip-crit {
3827 tempe 3796 temperature = <100000>;
3828 hyste 3797 hysteresis = <2000>;
3829 type 3798 type = "critical";
3830 }; 3799 };
3831 }; 3800 };
3832 3801
3833 cooling-maps { 3802 cooling-maps {
3834 map0 { 3803 map0 {
3835 trip 3804 trip = <&cpu7_alert>;
3836 cooli 3805 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837 3806 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3838 3807 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3839 3808 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3840 }; 3809 };
3841 }; 3810 };
3842 }; 3811 };
3843 3812
3844 vpu0-thermal { 3813 vpu0-thermal {
3845 polling-delay = <1000 3814 polling-delay = <1000>;
3846 polling-delay-passive 3815 polling-delay-passive = <250>;
3847 thermal-sensors = <&l 3816 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3848 3817
3849 trips { 3818 trips {
3850 vpu0_alert: t 3819 vpu0_alert: trip-alert {
3851 tempe 3820 temperature = <85000>;
3852 hyste 3821 hysteresis = <2000>;
3853 type 3822 type = "passive";
3854 }; 3823 };
3855 3824
3856 vpu0_crit: tr 3825 vpu0_crit: trip-crit {
3857 tempe 3826 temperature = <100000>;
3858 hyste 3827 hysteresis = <2000>;
3859 type 3828 type = "critical";
3860 }; 3829 };
3861 }; 3830 };
3862 }; 3831 };
3863 3832
3864 vpu1-thermal { 3833 vpu1-thermal {
3865 polling-delay = <1000 3834 polling-delay = <1000>;
3866 polling-delay-passive 3835 polling-delay-passive = <250>;
3867 thermal-sensors = <&l 3836 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3868 3837
3869 trips { 3838 trips {
3870 vpu1_alert: t 3839 vpu1_alert: trip-alert {
3871 tempe 3840 temperature = <85000>;
3872 hyste 3841 hysteresis = <2000>;
3873 type 3842 type = "passive";
3874 }; 3843 };
3875 3844
3876 vpu1_crit: tr 3845 vpu1_crit: trip-crit {
3877 tempe 3846 temperature = <100000>;
3878 hyste 3847 hysteresis = <2000>;
3879 type 3848 type = "critical";
3880 }; 3849 };
3881 }; 3850 };
3882 }; 3851 };
3883 3852
3884 gpu-thermal { !! 3853 gpu0-thermal {
3885 polling-delay = <1000 3854 polling-delay = <1000>;
3886 polling-delay-passive 3855 polling-delay-passive = <250>;
3887 thermal-sensors = <&l 3856 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3888 3857
3889 trips { 3858 trips {
3890 gpu0_alert: t 3859 gpu0_alert: trip-alert {
3891 tempe 3860 temperature = <85000>;
3892 hyste 3861 hysteresis = <2000>;
3893 type 3862 type = "passive";
3894 }; 3863 };
3895 3864
3896 gpu0_crit: tr 3865 gpu0_crit: trip-crit {
3897 tempe 3866 temperature = <100000>;
3898 hyste 3867 hysteresis = <2000>;
3899 type 3868 type = "critical";
3900 }; 3869 };
3901 }; 3870 };
3902 }; 3871 };
3903 3872
3904 gpu1-thermal { 3873 gpu1-thermal {
3905 polling-delay = <1000 3874 polling-delay = <1000>;
3906 polling-delay-passive 3875 polling-delay-passive = <250>;
3907 thermal-sensors = <&l 3876 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3908 3877
3909 trips { 3878 trips {
3910 gpu1_alert: t 3879 gpu1_alert: trip-alert {
3911 tempe 3880 temperature = <85000>;
3912 hyste 3881 hysteresis = <2000>;
3913 type 3882 type = "passive";
3914 }; 3883 };
3915 3884
3916 gpu1_crit: tr 3885 gpu1_crit: trip-crit {
3917 tempe 3886 temperature = <100000>;
3918 hyste 3887 hysteresis = <2000>;
3919 type 3888 type = "critical";
3920 }; 3889 };
3921 }; 3890 };
3922 }; 3891 };
3923 3892
3924 vdec-thermal { 3893 vdec-thermal {
3925 polling-delay = <1000 3894 polling-delay = <1000>;
3926 polling-delay-passive 3895 polling-delay-passive = <250>;
3927 thermal-sensors = <&l 3896 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3928 3897
3929 trips { 3898 trips {
3930 vdec_alert: t 3899 vdec_alert: trip-alert {
3931 tempe 3900 temperature = <85000>;
3932 hyste 3901 hysteresis = <2000>;
3933 type 3902 type = "passive";
3934 }; 3903 };
3935 3904
3936 vdec_crit: tr 3905 vdec_crit: trip-crit {
3937 tempe 3906 temperature = <100000>;
3938 hyste 3907 hysteresis = <2000>;
3939 type 3908 type = "critical";
3940 }; 3909 };
3941 }; 3910 };
3942 }; 3911 };
3943 3912
3944 img-thermal { 3913 img-thermal {
3945 polling-delay = <1000 3914 polling-delay = <1000>;
3946 polling-delay-passive 3915 polling-delay-passive = <250>;
3947 thermal-sensors = <&l 3916 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3948 3917
3949 trips { 3918 trips {
3950 img_alert: tr 3919 img_alert: trip-alert {
3951 tempe 3920 temperature = <85000>;
3952 hyste 3921 hysteresis = <2000>;
3953 type 3922 type = "passive";
3954 }; 3923 };
3955 3924
3956 img_crit: tri 3925 img_crit: trip-crit {
3957 tempe 3926 temperature = <100000>;
3958 hyste 3927 hysteresis = <2000>;
3959 type 3928 type = "critical";
3960 }; 3929 };
3961 }; 3930 };
3962 }; 3931 };
3963 3932
3964 infra-thermal { 3933 infra-thermal {
3965 polling-delay = <1000 3934 polling-delay = <1000>;
3966 polling-delay-passive 3935 polling-delay-passive = <250>;
3967 thermal-sensors = <&l 3936 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3968 3937
3969 trips { 3938 trips {
3970 infra_alert: 3939 infra_alert: trip-alert {
3971 tempe 3940 temperature = <85000>;
3972 hyste 3941 hysteresis = <2000>;
3973 type 3942 type = "passive";
3974 }; 3943 };
3975 3944
3976 infra_crit: t 3945 infra_crit: trip-crit {
3977 tempe 3946 temperature = <100000>;
3978 hyste 3947 hysteresis = <2000>;
3979 type 3948 type = "critical";
3980 }; 3949 };
3981 }; 3950 };
3982 }; 3951 };
3983 3952
3984 cam0-thermal { 3953 cam0-thermal {
3985 polling-delay = <1000 3954 polling-delay = <1000>;
3986 polling-delay-passive 3955 polling-delay-passive = <250>;
3987 thermal-sensors = <&l 3956 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3988 3957
3989 trips { 3958 trips {
3990 cam0_alert: t 3959 cam0_alert: trip-alert {
3991 tempe 3960 temperature = <85000>;
3992 hyste 3961 hysteresis = <2000>;
3993 type 3962 type = "passive";
3994 }; 3963 };
3995 3964
3996 cam0_crit: tr 3965 cam0_crit: trip-crit {
3997 tempe 3966 temperature = <100000>;
3998 hyste 3967 hysteresis = <2000>;
3999 type 3968 type = "critical";
4000 }; 3969 };
4001 }; 3970 };
4002 }; 3971 };
4003 3972
4004 cam1-thermal { 3973 cam1-thermal {
4005 polling-delay = <1000 3974 polling-delay = <1000>;
4006 polling-delay-passive 3975 polling-delay-passive = <250>;
4007 thermal-sensors = <&l 3976 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4008 3977
4009 trips { 3978 trips {
4010 cam1_alert: t 3979 cam1_alert: trip-alert {
4011 tempe 3980 temperature = <85000>;
4012 hyste 3981 hysteresis = <2000>;
4013 type 3982 type = "passive";
4014 }; 3983 };
4015 3984
4016 cam1_crit: tr 3985 cam1_crit: trip-crit {
4017 tempe 3986 temperature = <100000>;
4018 hyste 3987 hysteresis = <2000>;
4019 type 3988 type = "critical";
4020 }; 3989 };
4021 }; 3990 };
4022 }; 3991 };
4023 }; 3992 };
4024 }; 3993 };
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