1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10 /dts-v1/;
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h
15 #include "mt8365.dtsi"
16 #include "mt6357.dtsi"
17
18 / {
19 model = "MediaTek MT8365 Open Platform
20 compatible = "mediatek,mt8365-evk", "m
21
22 aliases {
23 serial0 = &uart0;
24 };
25
26 chosen {
27 stdout-path = "serial0:921600n
28 };
29
30 firmware {
31 optee {
32 compatible = "linaro,o
33 method = "smc";
34 };
35 };
36
37 gpio-keys {
38 compatible = "gpio-keys";
39 pinctrl-names = "default";
40 pinctrl-0 = <&gpio_keys>;
41
42 key-volume-up {
43 gpios = <&pio 24 GPIO_
44 label = "volume_up";
45 linux,code = <KEY_VOLU
46 wakeup-source;
47 debounce-interval = <1
48 };
49 };
50
51 memory@40000000 {
52 device_type = "memory";
53 reg = <0 0x40000000 0 0xc00000
54 };
55
56 usb_otg_vbus: regulator-0 {
57 compatible = "regulator-fixed"
58 regulator-name = "otg_vbus";
59 regulator-min-microvolt = <500
60 regulator-max-microvolt = <500
61 gpio = <&pio 16 GPIO_ACTIVE_HI
62 enable-active-high;
63 };
64
65 reserved-memory {
66 #address-cells = <2>;
67 #size-cells = <2>;
68 ranges;
69
70 /* 192 KiB reserved for ARM Tr
71 bl31_secmon_reserved: secmon@4
72 no-map;
73 reg = <0 0x43000000 0
74 };
75
76 /* 12 MiB reserved for OP-TEE
77 * +-----------------------+ 0
78 * | SHMEM 2MiB |
79 * +-----------------------+ 0
80 * | | TA_RAM 8MiB |
81 * + TZDRAM +--------------+ 0
82 * | | TEE_RAM 2MiB |
83 * +-----------------------+ 0
84 */
85 optee_reserved: optee@43200000
86 no-map;
87 reg = <0 0x43200000 0
88 };
89 };
90
91 sound: sound {
92 compatible = "mediatek,mt8365-
93 pinctrl-names = "default",
94 "dmic",
95 "miso_off",
96 "miso_on",
97 "mosi_off",
98 "mosi_on";
99 pinctrl-0 = <&aud_default_pins
100 pinctrl-1 = <&aud_dmic_pins>;
101 pinctrl-2 = <&aud_miso_off_pin
102 pinctrl-3 = <&aud_miso_on_pins
103 pinctrl-4 = <&aud_mosi_off_pin
104 pinctrl-5 = <&aud_mosi_on_pins
105 mediatek,platform = <&afe>;
106 };
107 };
108
109 &afe {
110 mediatek,dmic-mode = <1>;
111 status = "okay";
112 };
113
114 &cpu0 {
115 proc-supply = <&mt6357_vproc_reg>;
116 sram-supply = <&mt6357_vsram_proc_reg>
117 };
118
119 &cpu1 {
120 proc-supply = <&mt6357_vproc_reg>;
121 sram-supply = <&mt6357_vsram_proc_reg>
122 };
123
124 &cpu2 {
125 proc-supply = <&mt6357_vproc_reg>;
126 sram-supply = <&mt6357_vsram_proc_reg>
127 };
128
129 &cpu3 {
130 proc-supply = <&mt6357_vproc_reg>;
131 sram-supply = <&mt6357_vsram_proc_reg>
132 };
133
134 ðernet {
135 pinctrl-0 = <ðernet_pins>;
136 pinctrl-names = "default";
137 phy-handle = <ð_phy>;
138 phy-mode = "rmii";
139 /*
140 * Ethernet and HDMI (DSI0) are sharin
141 * Only one can be enabled at a time a
142 * SW2101 to be set on LAN position
143 * mt6357_vibr_reg and mt6357_vsim2_re
144 */
145 status = "disabled";
146
147 mdio {
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 eth_phy: ethernet-phy@0 {
152 reg = <0>;
153 };
154 };
155 };
156
157 &i2c0 {
158 clock-frequency = <100000>;
159 pinctrl-0 = <&i2c0_pins>;
160 pinctrl-names = "default";
161 status = "okay";
162 };
163
164 &mmc0 {
165 assigned-clock-parents = <&topckgen CL
166 assigned-clocks = <&topckgen CLK_TOP_M
167 bus-width = <8>;
168 cap-mmc-highspeed;
169 cap-mmc-hw-reset;
170 hs400-ds-delay = <0x12012>;
171 max-frequency = <200000000>;
172 mmc-hs200-1_8v;
173 mmc-hs400-1_8v;
174 no-sd;
175 no-sdio;
176 non-removable;
177 pinctrl-0 = <&mmc0_default_pins>;
178 pinctrl-1 = <&mmc0_uhs_pins>;
179 pinctrl-names = "default", "state_uhs"
180 vmmc-supply = <&mt6357_vemc_reg>;
181 vqmmc-supply = <&mt6357_vio18_reg>;
182 status = "okay";
183 };
184
185 &mmc1 {
186 bus-width = <4>;
187 cap-sd-highspeed;
188 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
189 max-frequency = <200000000>;
190 pinctrl-0 = <&mmc1_default_pins>;
191 pinctrl-1 = <&mmc1_uhs_pins>;
192 pinctrl-names = "default", "state_uhs"
193 sd-uhs-sdr104;
194 sd-uhs-sdr50;
195 vmmc-supply = <&mt6357_vmch_reg>;
196 vqmmc-supply = <&mt6357_vmc_reg>;
197 status = "okay";
198 };
199
200 &mt6357_pmic {
201 interrupts-extended = <&pio 145 IRQ_TY
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 mediatek,micbias0-microvolt = <1900000
205 mediatek,micbias1-microvolt = <1700000
206 };
207
208 &pio {
209 aud_default_pins: audiodefault-pins {
210 clk-dat-pins {
211 pinmux = <MT8365_PIN_7
212 <MT8365_PIN_7
213 <MT8365_PIN_7
214 <MT8365_PIN_7
215 };
216 };
217
218 aud_dmic_pins: audiodmic-pins {
219 clk-dat-pins {
220 pinmux = <MT8365_PIN_1
221 <MT8365_PIN_1
222 <MT8365_PIN_1
223 };
224 };
225
226 aud_miso_off_pins: misooff-pins {
227 clk-dat-pins {
228 pinmux = <MT8365_PIN_5
229 <MT8365_PIN_5
230 <MT8365_PIN_5
231 <MT8365_PIN_5
232 input-enable;
233 bias-pull-down;
234 drive-strength = <2>;
235 };
236 };
237
238 aud_miso_on_pins: misoon-pins {
239 clk-dat-pins {
240 pinmux = <MT8365_PIN_5
241 <MT8365_PIN_5
242 <MT8365_PIN_5
243 <MT8365_PIN_5
244 drive-strength = <6>;
245 };
246 };
247
248 aud_mosi_off_pins: mosioff-pins {
249 clk-dat-pins {
250 pinmux = <MT8365_PIN_4
251 <MT8365_PIN_5
252 <MT8365_PIN_5
253 <MT8365_PIN_5
254 input-enable;
255 bias-pull-down;
256 drive-strength = <2>;
257 };
258 };
259
260 aud_mosi_on_pins: mosion-pins {
261 clk-dat-pins {
262 pinmux = <MT8365_PIN_4
263 <MT8365_PIN_5
264 <MT8365_PIN_5
265 <MT8365_PIN_5
266 drive-strength = <6>;
267 };
268 };
269
270 ethernet_pins: ethernet-pins {
271 phy_reset_pins {
272 pinmux = <MT8365_PIN_1
273 };
274
275 rmii_pins {
276 pinmux = <MT8365_PIN_0
277 <MT8365_PIN_1
278 <MT8365_PIN_2
279 <MT8365_PIN_3
280 <MT8365_PIN_4
281 <MT8365_PIN_5
282 <MT8365_PIN_6
283 <MT8365_PIN_7
284 <MT8365_PIN_8
285 <MT8365_PIN_9
286 <MT8365_PIN_1
287 <MT8365_PIN_1
288 <MT8365_PIN_1
289 <MT8365_PIN_1
290 <MT8365_PIN_1
291 <MT8365_PIN_1
292 };
293 };
294
295 gpio_keys: gpio-keys-pins {
296 pins {
297 pinmux = <MT8365_PIN_2
298 bias-pull-up;
299 input-enable;
300 };
301 };
302
303 i2c0_pins: i2c0-pins {
304 pins {
305 pinmux = <MT8365_PIN_5
306 <MT8365_PIN_5
307 bias-pull-up;
308 };
309 };
310
311 mmc0_default_pins: mmc0-default-pins {
312 clk-pins {
313 pinmux = <MT8365_PIN_9
314 bias-pull-down;
315 };
316
317 cmd-dat-pins {
318 pinmux = <MT8365_PIN_1
319 <MT8365_PIN_1
320 <MT8365_PIN_1
321 <MT8365_PIN_1
322 <MT8365_PIN_9
323 <MT8365_PIN_9
324 <MT8365_PIN_9
325 <MT8365_PIN_9
326 <MT8365_PIN_9
327 input-enable;
328 bias-pull-up;
329 };
330
331 rst-pins {
332 pinmux = <MT8365_PIN_9
333 bias-pull-up;
334 };
335 };
336
337 mmc0_uhs_pins: mmc0-uhs-pins {
338 clk-pins {
339 pinmux = <MT8365_PIN_9
340 drive-strength = <MTK_
341 bias-pull-down = <MTK_
342 };
343
344 cmd-dat-pins {
345 pinmux = <MT8365_PIN_1
346 <MT8365_PIN_1
347 <MT8365_PIN_1
348 <MT8365_PIN_1
349 <MT8365_PIN_9
350 <MT8365_PIN_9
351 <MT8365_PIN_9
352 <MT8365_PIN_9
353 <MT8365_PIN_9
354 input-enable;
355 drive-strength = <MTK_
356 bias-pull-up = <MTK_PU
357 };
358
359 ds-pins {
360 pinmux = <MT8365_PIN_1
361 drive-strength = <MTK_
362 bias-pull-down = <MTK_
363 };
364
365 rst-pins {
366 pinmux = <MT8365_PIN_9
367 drive-strength = <MTK_
368 bias-pull-up;
369 };
370 };
371
372 mmc1_default_pins: mmc1-default-pins {
373 cd-pins {
374 pinmux = <MT8365_PIN_7
375 bias-pull-up;
376 };
377
378 clk-pins {
379 pinmux = <MT8365_PIN_8
380 bias-pull-down = <MTK_
381 };
382
383 cmd-dat-pins {
384 pinmux = <MT8365_PIN_8
385 <MT8365_PIN_9
386 <MT8365_PIN_9
387 <MT8365_PIN_9
388 <MT8365_PIN_8
389 input-enable;
390 bias-pull-up = <MTK_PU
391 };
392 };
393
394 mmc1_uhs_pins: mmc1-uhs-pins {
395 clk-pins {
396 pinmux = <MT8365_PIN_8
397 drive-strength = <8>;
398 bias-pull-down = <MTK_
399 };
400
401 cmd-dat-pins {
402 pinmux = <MT8365_PIN_8
403 <MT8365_PIN_9
404 <MT8365_PIN_9
405 <MT8365_PIN_9
406 <MT8365_PIN_8
407 input-enable;
408 drive-strength = <6>;
409 bias-pull-up = <MTK_PU
410 };
411 };
412
413 uart0_pins: uart0-pins {
414 pins {
415 pinmux = <MT8365_PIN_3
416 <MT8365_PIN_3
417 };
418 };
419
420 uart1_pins: uart1-pins {
421 pins {
422 pinmux = <MT8365_PIN_3
423 <MT8365_PIN_3
424 };
425 };
426
427 uart2_pins: uart2-pins {
428 pins {
429 pinmux = <MT8365_PIN_3
430 <MT8365_PIN_4
431 };
432 };
433
434 usb_pins: usb-pins {
435 id-pins {
436 pinmux = <MT8365_PIN_1
437 input-enable;
438 bias-pull-up;
439 };
440
441 usb0-vbus-pins {
442 pinmux = <MT8365_PIN_1
443 output-high;
444 };
445
446 usb1-vbus-pins {
447 pinmux = <MT8365_PIN_1
448 output-high;
449 };
450 };
451
452 pwm_pins: pwm-pins {
453 pins {
454 pinmux = <MT8365_PIN_1
455 <MT8365_PIN_1
456 };
457 };
458 };
459
460 &pwm {
461 pinctrl-0 = <&pwm_pins>;
462 pinctrl-names = "default";
463 status = "okay";
464 };
465
466 &ssusb {
467 dr_mode = "otg";
468 maximum-speed = "high-speed";
469 pinctrl-0 = <&usb_pins>;
470 pinctrl-names = "default";
471 usb-role-switch;
472 vusb33-supply = <&mt6357_vusb33_reg>;
473 status = "okay";
474
475 connector {
476 compatible = "gpio-usb-b-conne
477 id-gpios = <&pio 17 GPIO_ACTIV
478 type = "micro";
479 vbus-supply = <&usb_otg_vbus>;
480 };
481 };
482
483 &usb_host {
484 vusb33-supply = <&mt6357_vusb33_reg>;
485 status = "okay";
486 };
487
488 &uart0 {
489 pinctrl-0 = <&uart0_pins>;
490 pinctrl-names = "default";
491 status = "okay";
492 };
493
494 &uart1 {
495 pinctrl-0 = <&uart1_pins>;
496 pinctrl-names = "default";
497 status = "okay";
498 };
499
500 &uart2 {
501 pinctrl-0 = <&uart2_pins>;
502 pinctrl-names = "default";
503 status = "okay";
504 };
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