1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (c) 2021-2022 BayLibre, SAS. 3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors: 4 * Authors:
5 * Fabien Parent <fparent@baylibre.com> 5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com> <<
8 */ 7 */
9 8
10 /dts-v1/; 9 /dts-v1/;
11 10
12 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h 13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15 #include "mt8365.dtsi" 14 #include "mt8365.dtsi"
16 #include "mt6357.dtsi" 15 #include "mt6357.dtsi"
17 16
18 / { 17 / {
19 model = "MediaTek MT8365 Open Platform 18 model = "MediaTek MT8365 Open Platform EVK";
20 compatible = "mediatek,mt8365-evk", "m 19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21 20
22 aliases { 21 aliases {
23 serial0 = &uart0; 22 serial0 = &uart0;
24 }; 23 };
25 24
26 chosen { 25 chosen {
27 stdout-path = "serial0:921600n 26 stdout-path = "serial0:921600n8";
28 }; 27 };
29 28
30 firmware { 29 firmware {
31 optee { 30 optee {
32 compatible = "linaro,o 31 compatible = "linaro,optee-tz";
33 method = "smc"; 32 method = "smc";
34 }; 33 };
35 }; 34 };
36 35
37 gpio-keys { 36 gpio-keys {
38 compatible = "gpio-keys"; 37 compatible = "gpio-keys";
39 pinctrl-names = "default"; 38 pinctrl-names = "default";
40 pinctrl-0 = <&gpio_keys>; 39 pinctrl-0 = <&gpio_keys>;
41 40
42 key-volume-up { 41 key-volume-up {
43 gpios = <&pio 24 GPIO_ 42 gpios = <&pio 24 GPIO_ACTIVE_LOW>;
44 label = "volume_up"; 43 label = "volume_up";
45 linux,code = <KEY_VOLU 44 linux,code = <KEY_VOLUMEUP>;
46 wakeup-source; 45 wakeup-source;
47 debounce-interval = <1 46 debounce-interval = <15>;
48 }; 47 };
49 }; 48 };
50 49
51 memory@40000000 { 50 memory@40000000 {
52 device_type = "memory"; 51 device_type = "memory";
53 reg = <0 0x40000000 0 0xc00000 52 reg = <0 0x40000000 0 0xc0000000>;
54 }; 53 };
55 54
56 usb_otg_vbus: regulator-0 { 55 usb_otg_vbus: regulator-0 {
57 compatible = "regulator-fixed" 56 compatible = "regulator-fixed";
58 regulator-name = "otg_vbus"; 57 regulator-name = "otg_vbus";
59 regulator-min-microvolt = <500 58 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 59 regulator-max-microvolt = <5000000>;
61 gpio = <&pio 16 GPIO_ACTIVE_HI 60 gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
62 enable-active-high; 61 enable-active-high;
63 }; 62 };
64 63
65 reserved-memory { 64 reserved-memory {
66 #address-cells = <2>; 65 #address-cells = <2>;
67 #size-cells = <2>; 66 #size-cells = <2>;
68 ranges; 67 ranges;
69 68
70 /* 192 KiB reserved for ARM Tr 69 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
71 bl31_secmon_reserved: secmon@4 70 bl31_secmon_reserved: secmon@43000000 {
72 no-map; 71 no-map;
73 reg = <0 0x43000000 0 72 reg = <0 0x43000000 0 0x30000>;
74 }; 73 };
75 74
76 /* 12 MiB reserved for OP-TEE 75 /* 12 MiB reserved for OP-TEE (BL32)
77 * +-----------------------+ 0 76 * +-----------------------+ 0x43e0_0000
78 * | SHMEM 2MiB | 77 * | SHMEM 2MiB |
79 * +-----------------------+ 0 78 * +-----------------------+ 0x43c0_0000
80 * | | TA_RAM 8MiB | 79 * | | TA_RAM 8MiB |
81 * + TZDRAM +--------------+ 0 80 * + TZDRAM +--------------+ 0x4340_0000
82 * | | TEE_RAM 2MiB | 81 * | | TEE_RAM 2MiB |
83 * +-----------------------+ 0 82 * +-----------------------+ 0x4320_0000
84 */ 83 */
85 optee_reserved: optee@43200000 84 optee_reserved: optee@43200000 {
86 no-map; 85 no-map;
87 reg = <0 0x43200000 0 86 reg = <0 0x43200000 0 0x00c00000>;
88 }; 87 };
89 }; 88 };
90 <<
91 sound: sound { <<
92 compatible = "mediatek,mt8365- <<
93 pinctrl-names = "default", <<
94 "dmic", <<
95 "miso_off", <<
96 "miso_on", <<
97 "mosi_off", <<
98 "mosi_on"; <<
99 pinctrl-0 = <&aud_default_pins <<
100 pinctrl-1 = <&aud_dmic_pins>; <<
101 pinctrl-2 = <&aud_miso_off_pin <<
102 pinctrl-3 = <&aud_miso_on_pins <<
103 pinctrl-4 = <&aud_mosi_off_pin <<
104 pinctrl-5 = <&aud_mosi_on_pins <<
105 mediatek,platform = <&afe>; <<
106 }; <<
107 }; <<
108 <<
109 &afe { <<
110 mediatek,dmic-mode = <1>; <<
111 status = "okay"; <<
112 }; 89 };
113 90
114 &cpu0 { 91 &cpu0 {
115 proc-supply = <&mt6357_vproc_reg>; 92 proc-supply = <&mt6357_vproc_reg>;
116 sram-supply = <&mt6357_vsram_proc_reg> 93 sram-supply = <&mt6357_vsram_proc_reg>;
117 }; 94 };
118 95
119 &cpu1 { 96 &cpu1 {
120 proc-supply = <&mt6357_vproc_reg>; 97 proc-supply = <&mt6357_vproc_reg>;
121 sram-supply = <&mt6357_vsram_proc_reg> 98 sram-supply = <&mt6357_vsram_proc_reg>;
122 }; 99 };
123 100
124 &cpu2 { 101 &cpu2 {
125 proc-supply = <&mt6357_vproc_reg>; 102 proc-supply = <&mt6357_vproc_reg>;
126 sram-supply = <&mt6357_vsram_proc_reg> 103 sram-supply = <&mt6357_vsram_proc_reg>;
127 }; 104 };
128 105
129 &cpu3 { 106 &cpu3 {
130 proc-supply = <&mt6357_vproc_reg>; 107 proc-supply = <&mt6357_vproc_reg>;
131 sram-supply = <&mt6357_vsram_proc_reg> 108 sram-supply = <&mt6357_vsram_proc_reg>;
132 }; 109 };
133 110
134 ðernet { 111 ðernet {
135 pinctrl-0 = <ðernet_pins>; 112 pinctrl-0 = <ðernet_pins>;
136 pinctrl-names = "default"; 113 pinctrl-names = "default";
137 phy-handle = <ð_phy>; 114 phy-handle = <ð_phy>;
138 phy-mode = "rmii"; 115 phy-mode = "rmii";
139 /* 116 /*
140 * Ethernet and HDMI (DSI0) are sharin 117 * Ethernet and HDMI (DSI0) are sharing pins.
141 * Only one can be enabled at a time a 118 * Only one can be enabled at a time and require the physical switch
142 * SW2101 to be set on LAN position 119 * SW2101 to be set on LAN position
143 * mt6357_vibr_reg and mt6357_vsim2_re 120 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
144 */ 121 */
145 status = "disabled"; 122 status = "disabled";
146 123
147 mdio { 124 mdio {
148 #address-cells = <1>; 125 #address-cells = <1>;
149 #size-cells = <0>; 126 #size-cells = <0>;
150 127
151 eth_phy: ethernet-phy@0 { 128 eth_phy: ethernet-phy@0 {
152 reg = <0>; 129 reg = <0>;
153 }; 130 };
154 }; 131 };
155 }; 132 };
156 133
157 &i2c0 { 134 &i2c0 {
158 clock-frequency = <100000>; 135 clock-frequency = <100000>;
159 pinctrl-0 = <&i2c0_pins>; 136 pinctrl-0 = <&i2c0_pins>;
160 pinctrl-names = "default"; 137 pinctrl-names = "default";
161 status = "okay"; 138 status = "okay";
162 }; 139 };
163 140
164 &mmc0 { 141 &mmc0 {
165 assigned-clock-parents = <&topckgen CL 142 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
166 assigned-clocks = <&topckgen CLK_TOP_M 143 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
167 bus-width = <8>; 144 bus-width = <8>;
168 cap-mmc-highspeed; 145 cap-mmc-highspeed;
169 cap-mmc-hw-reset; 146 cap-mmc-hw-reset;
170 hs400-ds-delay = <0x12012>; 147 hs400-ds-delay = <0x12012>;
171 max-frequency = <200000000>; 148 max-frequency = <200000000>;
172 mmc-hs200-1_8v; 149 mmc-hs200-1_8v;
173 mmc-hs400-1_8v; 150 mmc-hs400-1_8v;
174 no-sd; 151 no-sd;
175 no-sdio; 152 no-sdio;
176 non-removable; 153 non-removable;
177 pinctrl-0 = <&mmc0_default_pins>; 154 pinctrl-0 = <&mmc0_default_pins>;
178 pinctrl-1 = <&mmc0_uhs_pins>; 155 pinctrl-1 = <&mmc0_uhs_pins>;
179 pinctrl-names = "default", "state_uhs" 156 pinctrl-names = "default", "state_uhs";
180 vmmc-supply = <&mt6357_vemc_reg>; 157 vmmc-supply = <&mt6357_vemc_reg>;
181 vqmmc-supply = <&mt6357_vio18_reg>; 158 vqmmc-supply = <&mt6357_vio18_reg>;
182 status = "okay"; 159 status = "okay";
183 }; 160 };
184 161
185 &mmc1 { 162 &mmc1 {
186 bus-width = <4>; 163 bus-width = <4>;
187 cap-sd-highspeed; 164 cap-sd-highspeed;
188 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; 165 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
189 max-frequency = <200000000>; 166 max-frequency = <200000000>;
190 pinctrl-0 = <&mmc1_default_pins>; 167 pinctrl-0 = <&mmc1_default_pins>;
191 pinctrl-1 = <&mmc1_uhs_pins>; 168 pinctrl-1 = <&mmc1_uhs_pins>;
192 pinctrl-names = "default", "state_uhs" 169 pinctrl-names = "default", "state_uhs";
193 sd-uhs-sdr104; 170 sd-uhs-sdr104;
194 sd-uhs-sdr50; 171 sd-uhs-sdr50;
195 vmmc-supply = <&mt6357_vmch_reg>; 172 vmmc-supply = <&mt6357_vmch_reg>;
196 vqmmc-supply = <&mt6357_vmc_reg>; 173 vqmmc-supply = <&mt6357_vmc_reg>;
197 status = "okay"; 174 status = "okay";
198 }; 175 };
199 176
200 &mt6357_pmic { 177 &mt6357_pmic {
201 interrupts-extended = <&pio 145 IRQ_TY 178 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-controller; 179 interrupt-controller;
203 #interrupt-cells = <2>; 180 #interrupt-cells = <2>;
204 mediatek,micbias0-microvolt = <1900000 <<
205 mediatek,micbias1-microvolt = <1700000 <<
206 }; 181 };
207 182
208 &pio { 183 &pio {
209 aud_default_pins: audiodefault-pins { <<
210 clk-dat-pins { <<
211 pinmux = <MT8365_PIN_7 <<
212 <MT8365_PIN_7 <<
213 <MT8365_PIN_7 <<
214 <MT8365_PIN_7 <<
215 }; <<
216 }; <<
217 <<
218 aud_dmic_pins: audiodmic-pins { <<
219 clk-dat-pins { <<
220 pinmux = <MT8365_PIN_1 <<
221 <MT8365_PIN_1 <<
222 <MT8365_PIN_1 <<
223 }; <<
224 }; <<
225 <<
226 aud_miso_off_pins: misooff-pins { <<
227 clk-dat-pins { <<
228 pinmux = <MT8365_PIN_5 <<
229 <MT8365_PIN_5 <<
230 <MT8365_PIN_5 <<
231 <MT8365_PIN_5 <<
232 input-enable; <<
233 bias-pull-down; <<
234 drive-strength = <2>; <<
235 }; <<
236 }; <<
237 <<
238 aud_miso_on_pins: misoon-pins { <<
239 clk-dat-pins { <<
240 pinmux = <MT8365_PIN_5 <<
241 <MT8365_PIN_5 <<
242 <MT8365_PIN_5 <<
243 <MT8365_PIN_5 <<
244 drive-strength = <6>; <<
245 }; <<
246 }; <<
247 <<
248 aud_mosi_off_pins: mosioff-pins { <<
249 clk-dat-pins { <<
250 pinmux = <MT8365_PIN_4 <<
251 <MT8365_PIN_5 <<
252 <MT8365_PIN_5 <<
253 <MT8365_PIN_5 <<
254 input-enable; <<
255 bias-pull-down; <<
256 drive-strength = <2>; <<
257 }; <<
258 }; <<
259 <<
260 aud_mosi_on_pins: mosion-pins { <<
261 clk-dat-pins { <<
262 pinmux = <MT8365_PIN_4 <<
263 <MT8365_PIN_5 <<
264 <MT8365_PIN_5 <<
265 <MT8365_PIN_5 <<
266 drive-strength = <6>; <<
267 }; <<
268 }; <<
269 <<
270 ethernet_pins: ethernet-pins { 184 ethernet_pins: ethernet-pins {
271 phy_reset_pins { 185 phy_reset_pins {
272 pinmux = <MT8365_PIN_1 186 pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
273 }; 187 };
274 188
275 rmii_pins { 189 rmii_pins {
276 pinmux = <MT8365_PIN_0 190 pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
277 <MT8365_PIN_1 191 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
278 <MT8365_PIN_2 192 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
279 <MT8365_PIN_3 193 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
280 <MT8365_PIN_4 194 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
281 <MT8365_PIN_5 195 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
282 <MT8365_PIN_6 196 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
283 <MT8365_PIN_7 197 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
284 <MT8365_PIN_8 198 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
285 <MT8365_PIN_9 199 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
286 <MT8365_PIN_1 200 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
287 <MT8365_PIN_1 201 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
288 <MT8365_PIN_1 202 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
289 <MT8365_PIN_1 203 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
290 <MT8365_PIN_1 204 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
291 <MT8365_PIN_1 205 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
292 }; 206 };
293 }; 207 };
294 208
295 gpio_keys: gpio-keys-pins { 209 gpio_keys: gpio-keys-pins {
296 pins { 210 pins {
297 pinmux = <MT8365_PIN_2 211 pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
298 bias-pull-up; 212 bias-pull-up;
299 input-enable; 213 input-enable;
300 }; 214 };
301 }; 215 };
302 216
303 i2c0_pins: i2c0-pins { 217 i2c0_pins: i2c0-pins {
304 pins { 218 pins {
305 pinmux = <MT8365_PIN_5 219 pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
306 <MT8365_PIN_5 220 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
307 bias-pull-up; 221 bias-pull-up;
308 }; 222 };
309 }; 223 };
310 224
311 mmc0_default_pins: mmc0-default-pins { 225 mmc0_default_pins: mmc0-default-pins {
312 clk-pins { 226 clk-pins {
313 pinmux = <MT8365_PIN_9 227 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
314 bias-pull-down; 228 bias-pull-down;
315 }; 229 };
316 230
317 cmd-dat-pins { 231 cmd-dat-pins {
318 pinmux = <MT8365_PIN_1 232 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
319 <MT8365_PIN_1 233 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
320 <MT8365_PIN_1 234 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
321 <MT8365_PIN_1 235 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
322 <MT8365_PIN_9 236 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
323 <MT8365_PIN_9 237 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
324 <MT8365_PIN_9 238 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
325 <MT8365_PIN_9 239 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
326 <MT8365_PIN_9 240 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
327 input-enable; 241 input-enable;
328 bias-pull-up; 242 bias-pull-up;
329 }; 243 };
330 244
331 rst-pins { 245 rst-pins {
332 pinmux = <MT8365_PIN_9 246 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
333 bias-pull-up; 247 bias-pull-up;
334 }; 248 };
335 }; 249 };
336 250
337 mmc0_uhs_pins: mmc0-uhs-pins { 251 mmc0_uhs_pins: mmc0-uhs-pins {
338 clk-pins { 252 clk-pins {
339 pinmux = <MT8365_PIN_9 253 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
340 drive-strength = <MTK_ 254 drive-strength = <MTK_DRIVE_10mA>;
341 bias-pull-down = <MTK_ 255 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
342 }; 256 };
343 257
344 cmd-dat-pins { 258 cmd-dat-pins {
345 pinmux = <MT8365_PIN_1 259 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
346 <MT8365_PIN_1 260 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
347 <MT8365_PIN_1 261 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
348 <MT8365_PIN_1 262 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
349 <MT8365_PIN_9 263 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
350 <MT8365_PIN_9 264 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
351 <MT8365_PIN_9 265 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
352 <MT8365_PIN_9 266 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
353 <MT8365_PIN_9 267 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
354 input-enable; 268 input-enable;
355 drive-strength = <MTK_ 269 drive-strength = <MTK_DRIVE_10mA>;
356 bias-pull-up = <MTK_PU 270 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
357 }; 271 };
358 272
359 ds-pins { 273 ds-pins {
360 pinmux = <MT8365_PIN_1 274 pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
361 drive-strength = <MTK_ 275 drive-strength = <MTK_DRIVE_10mA>;
362 bias-pull-down = <MTK_ 276 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
363 }; 277 };
364 278
365 rst-pins { 279 rst-pins {
366 pinmux = <MT8365_PIN_9 280 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
367 drive-strength = <MTK_ 281 drive-strength = <MTK_DRIVE_10mA>;
368 bias-pull-up; 282 bias-pull-up;
369 }; 283 };
370 }; 284 };
371 285
372 mmc1_default_pins: mmc1-default-pins { 286 mmc1_default_pins: mmc1-default-pins {
373 cd-pins { 287 cd-pins {
374 pinmux = <MT8365_PIN_7 288 pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
375 bias-pull-up; 289 bias-pull-up;
376 }; 290 };
377 291
378 clk-pins { 292 clk-pins {
379 pinmux = <MT8365_PIN_8 293 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
380 bias-pull-down = <MTK_ 294 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
381 }; 295 };
382 296
383 cmd-dat-pins { 297 cmd-dat-pins {
384 pinmux = <MT8365_PIN_8 298 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
385 <MT8365_PIN_9 299 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
386 <MT8365_PIN_9 300 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
387 <MT8365_PIN_9 301 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
388 <MT8365_PIN_8 302 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
389 input-enable; 303 input-enable;
390 bias-pull-up = <MTK_PU 304 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
391 }; 305 };
392 }; 306 };
393 307
394 mmc1_uhs_pins: mmc1-uhs-pins { 308 mmc1_uhs_pins: mmc1-uhs-pins {
395 clk-pins { 309 clk-pins {
396 pinmux = <MT8365_PIN_8 310 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
397 drive-strength = <8>; !! 311 drive-strength = <MTK_DRIVE_8mA>;
398 bias-pull-down = <MTK_ 312 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
399 }; 313 };
400 314
401 cmd-dat-pins { 315 cmd-dat-pins {
402 pinmux = <MT8365_PIN_8 316 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
403 <MT8365_PIN_9 317 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
404 <MT8365_PIN_9 318 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
405 <MT8365_PIN_9 319 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
406 <MT8365_PIN_8 320 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
407 input-enable; 321 input-enable;
408 drive-strength = <6>; !! 322 drive-strength = <MTK_DRIVE_6mA>;
409 bias-pull-up = <MTK_PU 323 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
410 }; 324 };
411 }; 325 };
412 326
413 uart0_pins: uart0-pins { 327 uart0_pins: uart0-pins {
414 pins { 328 pins {
415 pinmux = <MT8365_PIN_3 329 pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
416 <MT8365_PIN_3 330 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
417 }; 331 };
418 }; 332 };
419 333
420 uart1_pins: uart1-pins { 334 uart1_pins: uart1-pins {
421 pins { 335 pins {
422 pinmux = <MT8365_PIN_3 336 pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
423 <MT8365_PIN_3 337 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
424 }; 338 };
425 }; 339 };
426 340
427 uart2_pins: uart2-pins { 341 uart2_pins: uart2-pins {
428 pins { 342 pins {
429 pinmux = <MT8365_PIN_3 343 pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
430 <MT8365_PIN_4 344 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
431 }; 345 };
432 }; 346 };
433 347
434 usb_pins: usb-pins { 348 usb_pins: usb-pins {
435 id-pins { 349 id-pins {
436 pinmux = <MT8365_PIN_1 350 pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
437 input-enable; 351 input-enable;
438 bias-pull-up; 352 bias-pull-up;
439 }; 353 };
440 354
441 usb0-vbus-pins { 355 usb0-vbus-pins {
442 pinmux = <MT8365_PIN_1 356 pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
443 output-high; 357 output-high;
444 }; 358 };
445 359
446 usb1-vbus-pins { 360 usb1-vbus-pins {
447 pinmux = <MT8365_PIN_1 361 pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
448 output-high; 362 output-high;
449 }; 363 };
450 }; 364 };
451 365
452 pwm_pins: pwm-pins { 366 pwm_pins: pwm-pins {
453 pins { 367 pins {
454 pinmux = <MT8365_PIN_1 368 pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
455 <MT8365_PIN_1 369 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
456 }; 370 };
457 }; 371 };
458 }; 372 };
459 373
460 &pwm { 374 &pwm {
461 pinctrl-0 = <&pwm_pins>; 375 pinctrl-0 = <&pwm_pins>;
462 pinctrl-names = "default"; 376 pinctrl-names = "default";
463 status = "okay"; 377 status = "okay";
464 }; 378 };
465 379
466 &ssusb { 380 &ssusb {
467 dr_mode = "otg"; 381 dr_mode = "otg";
468 maximum-speed = "high-speed"; 382 maximum-speed = "high-speed";
469 pinctrl-0 = <&usb_pins>; 383 pinctrl-0 = <&usb_pins>;
470 pinctrl-names = "default"; 384 pinctrl-names = "default";
471 usb-role-switch; 385 usb-role-switch;
472 vusb33-supply = <&mt6357_vusb33_reg>; 386 vusb33-supply = <&mt6357_vusb33_reg>;
473 status = "okay"; 387 status = "okay";
474 388
475 connector { 389 connector {
476 compatible = "gpio-usb-b-conne 390 compatible = "gpio-usb-b-connector", "usb-b-connector";
477 id-gpios = <&pio 17 GPIO_ACTIV 391 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
478 type = "micro"; 392 type = "micro";
479 vbus-supply = <&usb_otg_vbus>; 393 vbus-supply = <&usb_otg_vbus>;
480 }; 394 };
481 }; 395 };
482 396
483 &usb_host { 397 &usb_host {
484 vusb33-supply = <&mt6357_vusb33_reg>; 398 vusb33-supply = <&mt6357_vusb33_reg>;
485 status = "okay"; 399 status = "okay";
486 }; 400 };
487 401
488 &uart0 { 402 &uart0 {
489 pinctrl-0 = <&uart0_pins>; 403 pinctrl-0 = <&uart0_pins>;
490 pinctrl-names = "default"; 404 pinctrl-names = "default";
491 status = "okay"; 405 status = "okay";
492 }; 406 };
493 407
494 &uart1 { 408 &uart1 {
495 pinctrl-0 = <&uart1_pins>; 409 pinctrl-0 = <&uart1_pins>;
496 pinctrl-names = "default"; 410 pinctrl-names = "default";
497 status = "okay"; 411 status = "okay";
498 }; 412 };
499 413
500 &uart2 { 414 &uart2 {
501 pinctrl-0 = <&uart2_pins>; 415 pinctrl-0 = <&uart2_pins>;
502 pinctrl-names = "default"; 416 pinctrl-names = "default";
503 status = "okay"; 417 status = "okay";
504 }; 418 };
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