1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/linux-event-codes. 4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/gpio-keys.h>
6 6
7 #include "tegra186-p3310.dtsi" 7 #include "tegra186-p3310.dtsi"
8 8
9 / { 9 / {
10 model = "NVIDIA Jetson TX2 Developer K 10 model = "NVIDIA Jetson TX2 Developer Kit";
11 compatible = "nvidia,p2771-0000", "nvi 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
12 12
13 aconnect@2900000 { 13 aconnect@2900000 {
14 status = "okay"; 14 status = "okay";
15 15
16 ahub@2900800 { 16 ahub@2900800 {
17 status = "okay"; 17 status = "okay";
18 18
19 i2s@2901000 { 19 i2s@2901000 {
20 status = "okay 20 status = "okay";
21 21
22 ports { 22 ports {
23 #addre 23 #address-cells = <1>;
24 #size- 24 #size-cells = <0>;
25 25
26 port@0 26 port@0 {
27 27 reg = <0>;
28 28
29 29 i2s1_cif_ep: endpoint {
30 30 remote-endpoint = <&xbar_i2s1_ep>;
31 31 };
32 }; 32 };
33 33
34 i2s1_p 34 i2s1_port: port@1 {
35 35 reg = <1>;
36 36
37 37 i2s1_dap_ep: endpoint {
38 38 dai-format = "i2s";
39 39 /* Placeholder for external Codec */
40 40 };
41 }; 41 };
42 }; 42 };
43 }; 43 };
44 44
45 i2s@2901100 { 45 i2s@2901100 {
46 status = "okay 46 status = "okay";
47 47
48 ports { 48 ports {
49 #addre 49 #address-cells = <1>;
50 #size- 50 #size-cells = <0>;
51 51
52 port@0 52 port@0 {
53 53 reg = <0>;
54 54
55 55 i2s2_cif_ep: endpoint {
56 56 remote-endpoint = <&xbar_i2s2_ep>;
57 57 };
58 }; 58 };
59 59
60 i2s2_p 60 i2s2_port: port@1 {
61 61 reg = <1>;
62 62
63 63 i2s2_dap_ep: endpoint {
64 64 dai-format = "i2s";
65 65 /* Placeholder for external Codec */
66 66 };
67 }; 67 };
68 }; 68 };
69 }; 69 };
70 70
71 i2s@2901200 { 71 i2s@2901200 {
72 status = "okay 72 status = "okay";
73 73
74 ports { 74 ports {
75 #addre 75 #address-cells = <1>;
76 #size- 76 #size-cells = <0>;
77 77
78 port@0 78 port@0 {
79 79 reg = <0>;
80 80
81 81 i2s3_cif_ep: endpoint {
82 82 remote-endpoint = <&xbar_i2s3_ep>;
83 83 };
84 }; 84 };
85 85
86 i2s3_p 86 i2s3_port: port@1 {
87 87 reg = <1>;
88 88
89 89 i2s3_dap_ep: endpoint {
90 90 dai-format = "i2s";
91 91 /* Placeholder for external Codec */
92 92 };
93 }; 93 };
94 }; 94 };
95 }; 95 };
96 96
97 i2s@2901300 { 97 i2s@2901300 {
98 status = "okay 98 status = "okay";
99 99
100 ports { 100 ports {
101 #addre 101 #address-cells = <1>;
102 #size- 102 #size-cells = <0>;
103 103
104 port@0 104 port@0 {
105 105 reg = <0>;
106 106
107 107 i2s4_cif_ep: endpoint {
108 108 remote-endpoint = <&xbar_i2s4_ep>;
109 109 };
110 }; 110 };
111 111
112 i2s4_p 112 i2s4_port: port@1 {
113 113 reg = <1>;
114 114
115 115 i2s4_dap_ep: endpoint {
116 116 dai-format = "i2s";
117 117 /* Placeholder for external Codec */
118 118 };
119 }; 119 };
120 }; 120 };
121 }; 121 };
122 122
123 i2s@2901400 { 123 i2s@2901400 {
124 status = "okay 124 status = "okay";
125 125
126 ports { 126 ports {
127 #addre 127 #address-cells = <1>;
128 #size- 128 #size-cells = <0>;
129 129
130 port@0 130 port@0 {
131 131 reg = <0>;
132 132
133 133 i2s5_cif_ep: endpoint {
134 134 remote-endpoint = <&xbar_i2s5_ep>;
135 135 };
136 }; 136 };
137 137
138 i2s5_p 138 i2s5_port: port@1 {
139 139 reg = <1>;
140 140
141 141 i2s5_dap_ep: endpoint {
142 142 dai-format = "i2s";
143 143 /* Placeholder for external Codec */
144 144 };
145 }; 145 };
146 }; 146 };
147 }; 147 };
148 148
149 i2s@2901500 { 149 i2s@2901500 {
150 status = "okay 150 status = "okay";
151 151
152 ports { 152 ports {
153 #addre 153 #address-cells = <1>;
154 #size- 154 #size-cells = <0>;
155 155
156 port@0 156 port@0 {
157 157 reg = <0>;
158 158
159 159 i2s6_cif_ep: endpoint {
160 160 remote-endpoint = <&xbar_i2s6_ep>;
161 161 };
162 }; 162 };
163 163
164 i2s6_p 164 i2s6_port: port@1 {
165 165 reg = <1>;
166 166
167 167 i2s6_dap_ep: endpoint {
168 168 dai-format = "i2s";
169 169 /* Placeholder for external Codec */
170 170 };
171 }; 171 };
172 }; 172 };
173 }; 173 };
174 174
175 sfc@2902000 { 175 sfc@2902000 {
176 status = "okay 176 status = "okay";
177 177
178 ports { 178 ports {
179 #addre 179 #address-cells = <1>;
180 #size- 180 #size-cells = <0>;
181 181
182 port@0 182 port@0 {
183 183 reg = <0>;
184 184
185 185 sfc1_cif_in_ep: endpoint {
186 186 remote-endpoint = <&xbar_sfc1_in_ep>;
187 187 convert-rate = <44100>;
188 188 };
189 }; 189 };
190 190
191 sfc1_o 191 sfc1_out_port: port@1 {
192 192 reg = <1>;
193 193
194 194 sfc1_cif_out_ep: endpoint {
195 195 remote-endpoint = <&xbar_sfc1_out_ep>;
196 196 convert-rate = <48000>;
197 197 };
198 }; 198 };
199 }; 199 };
200 }; 200 };
201 201
202 sfc@2902200 { 202 sfc@2902200 {
203 status = "okay 203 status = "okay";
204 204
205 ports { 205 ports {
206 #addre 206 #address-cells = <1>;
207 #size- 207 #size-cells = <0>;
208 208
209 port@0 209 port@0 {
210 210 reg = <0>;
211 211
212 212 sfc2_cif_in_ep: endpoint {
213 213 remote-endpoint = <&xbar_sfc2_in_ep>;
214 214 };
215 }; 215 };
216 216
217 sfc2_o 217 sfc2_out_port: port@1 {
218 218 reg = <1>;
219 219
220 220 sfc2_cif_out_ep: endpoint {
221 221 remote-endpoint = <&xbar_sfc2_out_ep>;
222 222 };
223 }; 223 };
224 }; 224 };
225 }; 225 };
226 226
227 sfc@2902400 { 227 sfc@2902400 {
228 status = "okay 228 status = "okay";
229 229
230 ports { 230 ports {
231 #addre 231 #address-cells = <1>;
232 #size- 232 #size-cells = <0>;
233 233
234 port@0 234 port@0 {
235 235 reg = <0>;
236 236
237 237 sfc3_cif_in_ep: endpoint {
238 238 remote-endpoint = <&xbar_sfc3_in_ep>;
239 239 };
240 }; 240 };
241 241
242 sfc3_o 242 sfc3_out_port: port@1 {
243 243 reg = <1>;
244 244
245 245 sfc3_cif_out_ep: endpoint {
246 246 remote-endpoint = <&xbar_sfc3_out_ep>;
247 247 };
248 }; 248 };
249 }; 249 };
250 }; 250 };
251 251
252 sfc@2902600 { 252 sfc@2902600 {
253 status = "okay 253 status = "okay";
254 254
255 ports { 255 ports {
256 #addre 256 #address-cells = <1>;
257 #size- 257 #size-cells = <0>;
258 258
259 port@0 259 port@0 {
260 260 reg = <0>;
261 261
262 262 sfc4_cif_in_ep: endpoint {
263 263 remote-endpoint = <&xbar_sfc4_in_ep>;
264 264 };
265 }; 265 };
266 266
267 sfc4_o 267 sfc4_out_port: port@1 {
268 268 reg = <1>;
269 269
270 270 sfc4_cif_out_ep: endpoint {
271 271 remote-endpoint = <&xbar_sfc4_out_ep>;
272 272 };
273 }; 273 };
274 }; 274 };
275 }; 275 };
276 276
277 amx@2903000 { 277 amx@2903000 {
278 status = "okay 278 status = "okay";
279 279
280 ports { 280 ports {
281 #addre 281 #address-cells = <1>;
282 #size- 282 #size-cells = <0>;
283 283
284 port@0 284 port@0 {
285 285 reg = <0>;
286 286
287 287 amx1_in1_ep: endpoint {
288 288 remote-endpoint = <&xbar_amx1_in1_ep>;
289 289 };
290 }; 290 };
291 291
292 port@1 292 port@1 {
293 293 reg = <1>;
294 294
295 295 amx1_in2_ep: endpoint {
296 296 remote-endpoint = <&xbar_amx1_in2_ep>;
297 297 };
298 }; 298 };
299 299
300 port@2 300 port@2 {
301 301 reg = <2>;
302 302
303 303 amx1_in3_ep: endpoint {
304 304 remote-endpoint = <&xbar_amx1_in3_ep>;
305 305 };
306 }; 306 };
307 307
308 port@3 308 port@3 {
309 309 reg = <3>;
310 310
311 311 amx1_in4_ep: endpoint {
312 312 remote-endpoint = <&xbar_amx1_in4_ep>;
313 313 };
314 }; 314 };
315 315
316 amx1_o 316 amx1_out_port: port@4 {
317 317 reg = <4>;
318 318
319 319 amx1_out_ep: endpoint {
320 320 remote-endpoint = <&xbar_amx1_out_ep>;
321 321 };
322 }; 322 };
323 }; 323 };
324 }; 324 };
325 325
326 amx@2903100 { 326 amx@2903100 {
327 status = "okay 327 status = "okay";
328 328
329 ports { 329 ports {
330 #addre 330 #address-cells = <1>;
331 #size- 331 #size-cells = <0>;
332 332
333 port@0 333 port@0 {
334 334 reg = <0>;
335 335
336 336 amx2_in1_ep: endpoint {
337 337 remote-endpoint = <&xbar_amx2_in1_ep>;
338 338 };
339 }; 339 };
340 340
341 port@1 341 port@1 {
342 342 reg = <1>;
343 343
344 344 amx2_in2_ep: endpoint {
345 345 remote-endpoint = <&xbar_amx2_in2_ep>;
346 346 };
347 }; 347 };
348 348
349 amx2_i 349 amx2_in3_port: port@2 {
350 350 reg = <2>;
351 351
352 352 amx2_in3_ep: endpoint {
353 353 remote-endpoint = <&xbar_amx2_in3_ep>;
354 354 };
355 }; 355 };
356 356
357 amx2_i 357 amx2_in4_port: port@3 {
358 358 reg = <3>;
359 359
360 360 amx2_in4_ep: endpoint {
361 361 remote-endpoint = <&xbar_amx2_in4_ep>;
362 362 };
363 }; 363 };
364 364
365 amx2_o 365 amx2_out_port: port@4 {
366 366 reg = <4>;
367 367
368 368 amx2_out_ep: endpoint {
369 369 remote-endpoint = <&xbar_amx2_out_ep>;
370 370 };
371 }; 371 };
372 }; 372 };
373 }; 373 };
374 374
375 amx@2903200 { 375 amx@2903200 {
376 status = "okay 376 status = "okay";
377 377
378 ports { 378 ports {
379 #addre 379 #address-cells = <1>;
380 #size- 380 #size-cells = <0>;
381 381
382 port@0 382 port@0 {
383 383 reg = <0>;
384 384
385 385 amx3_in1_ep: endpoint {
386 386 remote-endpoint = <&xbar_amx3_in1_ep>;
387 387 };
388 }; 388 };
389 389
390 port@1 390 port@1 {
391 391 reg = <1>;
392 392
393 393 amx3_in2_ep: endpoint {
394 394 remote-endpoint = <&xbar_amx3_in2_ep>;
395 395 };
396 }; 396 };
397 397
398 port@2 398 port@2 {
399 399 reg = <2>;
400 400
401 401 amx3_in3_ep: endpoint {
402 402 remote-endpoint = <&xbar_amx3_in3_ep>;
403 403 };
404 }; 404 };
405 405
406 port@3 406 port@3 {
407 407 reg = <3>;
408 408
409 409 amx3_in4_ep: endpoint {
410 410 remote-endpoint = <&xbar_amx3_in4_ep>;
411 411 };
412 }; 412 };
413 413
414 amx3_o 414 amx3_out_port: port@4 {
415 415 reg = <4>;
416 416
417 417 amx3_out_ep: endpoint {
418 418 remote-endpoint = <&xbar_amx3_out_ep>;
419 419 };
420 }; 420 };
421 }; 421 };
422 }; 422 };
423 423
424 amx@2903300 { 424 amx@2903300 {
425 status = "okay 425 status = "okay";
426 426
427 ports { 427 ports {
428 #addre 428 #address-cells = <1>;
429 #size- 429 #size-cells = <0>;
430 430
431 port@0 431 port@0 {
432 432 reg = <0>;
433 433
434 434 amx4_in1_ep: endpoint {
435 435 remote-endpoint = <&xbar_amx4_in1_ep>;
436 436 };
437 }; 437 };
438 438
439 port@1 439 port@1 {
440 440 reg = <1>;
441 441
442 442 amx4_in2_ep: endpoint {
443 443 remote-endpoint = <&xbar_amx4_in2_ep>;
444 444 };
445 }; 445 };
446 446
447 port@2 447 port@2 {
448 448 reg = <2>;
449 449
450 450 amx4_in3_ep: endpoint {
451 451 remote-endpoint = <&xbar_amx4_in3_ep>;
452 452 };
453 }; 453 };
454 454
455 port@3 455 port@3 {
456 456 reg = <3>;
457 457
458 458 amx4_in4_ep: endpoint {
459 459 remote-endpoint = <&xbar_amx4_in4_ep>;
460 460 };
461 }; 461 };
462 462
463 amx4_o 463 amx4_out_port: port@4 {
464 464 reg = <4>;
465 465
466 466 amx4_out_ep: endpoint {
467 467 remote-endpoint = <&xbar_amx4_out_ep>;
468 468 };
469 }; 469 };
470 }; 470 };
471 }; 471 };
472 472
473 adx@2903800 { 473 adx@2903800 {
474 status = "okay 474 status = "okay";
475 475
476 ports { 476 ports {
477 #addre 477 #address-cells = <1>;
478 #size- 478 #size-cells = <0>;
479 479
480 port@0 480 port@0 {
481 481 reg = <0>;
482 482
483 483 adx1_in_ep: endpoint {
484 484 remote-endpoint = <&xbar_adx1_in_ep>;
485 485 };
486 }; 486 };
487 487
488 adx1_o 488 adx1_out1_port: port@1 {
489 489 reg = <1>;
490 490
491 491 adx1_out1_ep: endpoint {
492 492 remote-endpoint = <&xbar_adx1_out1_ep>;
493 493 };
494 }; 494 };
495 495
496 adx1_o 496 adx1_out2_port: port@2 {
497 497 reg = <2>;
498 498
499 499 adx1_out2_ep: endpoint {
500 500 remote-endpoint = <&xbar_adx1_out2_ep>;
501 501 };
502 }; 502 };
503 503
504 adx1_o 504 adx1_out3_port: port@3 {
505 505 reg = <3>;
506 506
507 507 adx1_out3_ep: endpoint {
508 508 remote-endpoint = <&xbar_adx1_out3_ep>;
509 509 };
510 }; 510 };
511 511
512 adx1_o 512 adx1_out4_port: port@4 {
513 513 reg = <4>;
514 514
515 515 adx1_out4_ep: endpoint {
516 516 remote-endpoint = <&xbar_adx1_out4_ep>;
517 517 };
518 }; 518 };
519 }; 519 };
520 }; 520 };
521 521
522 adx@2903900 { 522 adx@2903900 {
523 status = "okay 523 status = "okay";
524 524
525 ports { 525 ports {
526 #addre 526 #address-cells = <1>;
527 #size- 527 #size-cells = <0>;
528 528
529 port@0 529 port@0 {
530 530 reg = <0>;
531 531
532 532 adx2_in_ep: endpoint {
533 533 remote-endpoint = <&xbar_adx2_in_ep>;
534 534 };
535 }; 535 };
536 536
537 adx2_o 537 adx2_out1_port: port@1 {
538 538 reg = <1>;
539 539
540 540 adx2_out1_ep: endpoint {
541 541 remote-endpoint = <&xbar_adx2_out1_ep>;
542 542 };
543 }; 543 };
544 544
545 adx2_o 545 adx2_out2_port: port@2 {
546 546 reg = <2>;
547 547
548 548 adx2_out2_ep: endpoint {
549 549 remote-endpoint = <&xbar_adx2_out2_ep>;
550 550 };
551 }; 551 };
552 552
553 adx2_o 553 adx2_out3_port: port@3 {
554 554 reg = <3>;
555 555
556 556 adx2_out3_ep: endpoint {
557 557 remote-endpoint = <&xbar_adx2_out3_ep>;
558 558 };
559 }; 559 };
560 560
561 adx2_o 561 adx2_out4_port: port@4 {
562 562 reg = <4>;
563 563
564 564 adx2_out4_ep: endpoint {
565 565 remote-endpoint = <&xbar_adx2_out4_ep>;
566 566 };
567 }; 567 };
568 }; 568 };
569 }; 569 };
570 570
571 adx@2903a00 { 571 adx@2903a00 {
572 status = "okay 572 status = "okay";
573 573
574 ports { 574 ports {
575 #addre 575 #address-cells = <1>;
576 #size- 576 #size-cells = <0>;
577 577
578 port@0 578 port@0 {
579 579 reg = <0>;
580 580
581 581 adx3_in_ep: endpoint {
582 582 remote-endpoint = <&xbar_adx3_in_ep>;
583 583 };
584 }; 584 };
585 585
586 adx3_o 586 adx3_out1_port: port@1 {
587 587 reg = <1>;
588 588
589 589 adx3_out1_ep: endpoint {
590 590 remote-endpoint = <&xbar_adx3_out1_ep>;
591 591 };
592 }; 592 };
593 593
594 adx3_o 594 adx3_out2_port: port@2 {
595 595 reg = <2>;
596 596
597 597 adx3_out2_ep: endpoint {
598 598 remote-endpoint = <&xbar_adx3_out2_ep>;
599 599 };
600 }; 600 };
601 601
602 adx3_o 602 adx3_out3_port: port@3 {
603 603 reg = <3>;
604 604
605 605 adx3_out3_ep: endpoint {
606 606 remote-endpoint = <&xbar_adx3_out3_ep>;
607 607 };
608 }; 608 };
609 609
610 adx3_o 610 adx3_out4_port: port@4 {
611 611 reg = <4>;
612 612
613 613 adx3_out4_ep: endpoint {
614 614 remote-endpoint = <&xbar_adx3_out4_ep>;
615 615 };
616 }; 616 };
617 }; 617 };
618 }; 618 };
619 619
620 adx@2903b00 { 620 adx@2903b00 {
621 status = "okay 621 status = "okay";
622 622
623 ports { 623 ports {
624 #addre 624 #address-cells = <1>;
625 #size- 625 #size-cells = <0>;
626 626
627 port@0 627 port@0 {
628 628 reg = <0>;
629 629
630 630 adx4_in_ep: endpoint {
631 631 remote-endpoint = <&xbar_adx4_in_ep>;
632 632 };
633 }; 633 };
634 634
635 adx4_o 635 adx4_out1_port: port@1 {
636 636 reg = <1>;
637 637
638 638 adx4_out1_ep: endpoint {
639 639 remote-endpoint = <&xbar_adx4_out1_ep>;
640 640 };
641 }; 641 };
642 642
643 adx4_o 643 adx4_out2_port: port@2 {
644 644 reg = <2>;
645 645
646 646 adx4_out2_ep: endpoint {
647 647 remote-endpoint = <&xbar_adx4_out2_ep>;
648 648 };
649 }; 649 };
650 650
651 adx4_o 651 adx4_out3_port: port@3 {
652 652 reg = <3>;
653 653
654 654 adx4_out3_ep: endpoint {
655 655 remote-endpoint = <&xbar_adx4_out3_ep>;
656 656 };
657 }; 657 };
658 658
659 adx4_o 659 adx4_out4_port: port@4 {
660 660 reg = <4>;
661 661
662 662 adx4_out4_ep: endpoint {
663 663 remote-endpoint = <&xbar_adx4_out4_ep>;
664 664 };
665 }; 665 };
666 }; 666 };
667 }; 667 };
668 668
669 dmic@2904000 { 669 dmic@2904000 {
670 status = "okay 670 status = "okay";
671 671
672 ports { 672 ports {
673 #addre 673 #address-cells = <1>;
674 #size- 674 #size-cells = <0>;
675 675
676 port@0 676 port@0 {
677 677 reg = <0>;
678 678
679 679 dmic1_cif_ep: endpoint {
680 680 remote-endpoint = <&xbar_dmic1_ep>;
681 681 };
682 }; 682 };
683 683
684 dmic1_ 684 dmic1_port: port@1 {
685 685 reg = <1>;
686 686
687 687 dmic1_dap_ep: endpoint {
688 688 /* Place holder for external Codec */
689 689 };
690 }; 690 };
691 }; 691 };
692 }; 692 };
693 693
694 dmic@2904100 { 694 dmic@2904100 {
695 status = "okay 695 status = "okay";
696 696
697 ports { 697 ports {
698 #addre 698 #address-cells = <1>;
699 #size- 699 #size-cells = <0>;
700 700
701 port@0 701 port@0 {
702 702 reg = <0>;
703 703
704 704 dmic2_cif_ep: endpoint {
705 705 remote-endpoint = <&xbar_dmic2_ep>;
706 706 };
707 }; 707 };
708 708
709 dmic2_ 709 dmic2_port: port@1 {
710 710 reg = <1>;
711 711
712 712 dmic2_dap_ep: endpoint {
713 713 /* Place holder for external Codec */
714 714 };
715 }; 715 };
716 }; 716 };
717 }; 717 };
718 718
719 dmic@2904200 { 719 dmic@2904200 {
720 status = "okay 720 status = "okay";
721 721
722 ports { 722 ports {
723 #addre 723 #address-cells = <1>;
724 #size- 724 #size-cells = <0>;
725 725
726 port@0 726 port@0 {
727 727 reg = <0>;
728 728
729 729 dmic3_cif_ep: endpoint {
730 730 remote-endpoint = <&xbar_dmic3_ep>;
731 731 };
732 }; 732 };
733 733
734 dmic3_ 734 dmic3_port: port@1 {
735 735 reg = <1>;
736 736
737 737 dmic3_dap_ep: endpoint {
738 738 /* Place holder for external Codec */
739 739 };
740 }; 740 };
741 }; 741 };
742 }; 742 };
743 743
744 dspk@2905000 { 744 dspk@2905000 {
745 status = "okay 745 status = "okay";
746 746
747 ports { 747 ports {
748 #addre 748 #address-cells = <1>;
749 #size- 749 #size-cells = <0>;
750 750
751 port@0 751 port@0 {
752 752 reg = <0>;
753 753
754 754 dspk1_cif_ep: endpoint {
755 755 remote-endpoint = <&xbar_dspk1_ep>;
756 756 };
757 }; 757 };
758 758
759 dspk1_ 759 dspk1_port: port@1 {
760 760 reg = <1>;
761 761
762 762 dspk1_dap_ep: endpoint {
763 763 /* Place holder for external Codec */
764 764 };
765 }; 765 };
766 }; 766 };
767 }; 767 };
768 768
769 dspk@2905100 { 769 dspk@2905100 {
770 status = "okay 770 status = "okay";
771 771
772 ports { 772 ports {
773 #addre 773 #address-cells = <1>;
774 #size- 774 #size-cells = <0>;
775 775
776 port@0 776 port@0 {
777 777 reg = <0>;
778 778
779 779 dspk2_cif_ep: endpoint {
780 780 remote-endpoint = <&xbar_dspk2_ep>;
781 781 };
782 }; 782 };
783 783
784 dspk2_ 784 dspk2_port: port@1 {
785 785 reg = <1>;
786 786
787 787 dspk2_dap_ep: endpoint {
788 788 /* Place holder for external Codec */
789 789 };
790 }; 790 };
791 }; 791 };
792 }; 792 };
793 793
794 processing-engine@2908 794 processing-engine@2908000 {
795 status = "okay 795 status = "okay";
796 796
797 ports { 797 ports {
798 #addre 798 #address-cells = <1>;
799 #size- 799 #size-cells = <0>;
800 800
801 port@0 801 port@0 {
802 802 reg = <0x0>;
803 803
804 804 ope1_cif_in_ep: endpoint {
805 805 remote-endpoint = <&xbar_ope1_in_ep>;
806 806 };
807 }; 807 };
808 808
809 ope1_o 809 ope1_out_port: port@1 {
810 810 reg = <0x1>;
811 811
812 812 ope1_cif_out_ep: endpoint {
813 813 remote-endpoint = <&xbar_ope1_out_ep>;
814 814 };
815 }; 815 };
816 }; 816 };
817 }; 817 };
818 818
819 mvc@290a000 { 819 mvc@290a000 {
820 status = "okay 820 status = "okay";
821 821
822 ports { 822 ports {
823 #addre 823 #address-cells = <1>;
824 #size- 824 #size-cells = <0>;
825 825
826 port@0 826 port@0 {
827 827 reg = <0>;
828 828
829 829 mvc1_cif_in_ep: endpoint {
830 830 remote-endpoint = <&xbar_mvc1_in_ep>;
831 831 };
832 }; 832 };
833 833
834 mvc1_o 834 mvc1_out_port: port@1 {
835 835 reg = <1>;
836 836
837 837 mvc1_cif_out_ep: endpoint {
838 838 remote-endpoint = <&xbar_mvc1_out_ep>;
839 839 };
840 }; 840 };
841 }; 841 };
842 }; 842 };
843 843
844 mvc@290a200 { 844 mvc@290a200 {
845 status = "okay 845 status = "okay";
846 846
847 ports { 847 ports {
848 #addre 848 #address-cells = <1>;
849 #size- 849 #size-cells = <0>;
850 850
851 port@0 851 port@0 {
852 852 reg = <0>;
853 853
854 854 mvc2_cif_in_ep: endpoint {
855 855 remote-endpoint = <&xbar_mvc2_in_ep>;
856 856 };
857 }; 857 };
858 858
859 mvc2_o 859 mvc2_out_port: port@1 {
860 860 reg = <1>;
861 861
862 862 mvc2_cif_out_ep: endpoint {
863 863 remote-endpoint = <&xbar_mvc2_out_ep>;
864 864 };
865 }; 865 };
866 }; 866 };
867 }; 867 };
868 868
869 amixer@290bb00 { 869 amixer@290bb00 {
870 status = "okay 870 status = "okay";
871 871
872 ports { 872 ports {
873 #addre 873 #address-cells = <1>;
874 #size- 874 #size-cells = <0>;
875 875
876 port@0 876 port@0 {
877 877 reg = <0x0>;
878 878
879 879 mixer_in1_ep: endpoint {
880 880 remote-endpoint = <&xbar_mixer_in1_ep>;
881 881 };
882 }; 882 };
883 883
884 port@1 884 port@1 {
885 885 reg = <0x1>;
886 886
887 887 mixer_in2_ep: endpoint {
888 888 remote-endpoint = <&xbar_mixer_in2_ep>;
889 889 };
890 }; 890 };
891 891
892 port@2 892 port@2 {
893 893 reg = <0x2>;
894 894
895 895 mixer_in3_ep: endpoint {
896 896 remote-endpoint = <&xbar_mixer_in3_ep>;
897 897 };
898 }; 898 };
899 899
900 port@3 900 port@3 {
901 901 reg = <0x3>;
902 902
903 903 mixer_in4_ep: endpoint {
904 904 remote-endpoint = <&xbar_mixer_in4_ep>;
905 905 };
906 }; 906 };
907 907
908 port@4 908 port@4 {
909 909 reg = <0x4>;
910 910
911 911 mixer_in5_ep: endpoint {
912 912 remote-endpoint = <&xbar_mixer_in5_ep>;
913 913 };
914 }; 914 };
915 915
916 port@5 916 port@5 {
917 917 reg = <0x5>;
918 918
919 919 mixer_in6_ep: endpoint {
920 920 remote-endpoint = <&xbar_mixer_in6_ep>;
921 921 };
922 }; 922 };
923 923
924 port@6 924 port@6 {
925 925 reg = <0x6>;
926 926
927 927 mixer_in7_ep: endpoint {
928 928 remote-endpoint = <&xbar_mixer_in7_ep>;
929 929 };
930 }; 930 };
931 931
932 port@7 932 port@7 {
933 933 reg = <0x7>;
934 934
935 935 mixer_in8_ep: endpoint {
936 936 remote-endpoint = <&xbar_mixer_in8_ep>;
937 937 };
938 }; 938 };
939 939
940 port@8 940 port@8 {
941 941 reg = <0x8>;
942 942
943 943 mixer_in9_ep: endpoint {
944 944 remote-endpoint = <&xbar_mixer_in9_ep>;
945 945 };
946 }; 946 };
947 947
948 port@9 948 port@9 {
949 949 reg = <0x9>;
950 950
951 951 mixer_in10_ep: endpoint {
952 952 remote-endpoint = <&xbar_mixer_in10_ep>;
953 953 };
954 }; 954 };
955 955
956 mixer_ 956 mixer_out1_port: port@a {
957 957 reg = <0xa>;
958 958
959 959 mixer_out1_ep: endpoint {
960 960 remote-endpoint = <&xbar_mixer_out1_ep>;
961 961 };
962 }; 962 };
963 963
964 mixer_ 964 mixer_out2_port: port@b {
965 965 reg = <0xb>;
966 966
967 967 mixer_out2_ep: endpoint {
968 968 remote-endpoint = <&xbar_mixer_out2_ep>;
969 969 };
970 }; 970 };
971 971
972 mixer_ 972 mixer_out3_port: port@c {
973 973 reg = <0xc>;
974 974
975 975 mixer_out3_ep: endpoint {
976 976 remote-endpoint = <&xbar_mixer_out3_ep>;
977 977 };
978 }; 978 };
979 979
980 mixer_ 980 mixer_out4_port: port@d {
981 981 reg = <0xd>;
982 982
983 983 mixer_out4_ep: endpoint {
984 984 remote-endpoint = <&xbar_mixer_out4_ep>;
985 985 };
986 }; 986 };
987 987
988 mixer_ 988 mixer_out5_port: port@e {
989 989 reg = <0xe>;
990 990
991 991 mixer_out5_ep: endpoint {
992 992 remote-endpoint = <&xbar_mixer_out5_ep>;
993 993 };
994 }; 994 };
995 }; 995 };
996 }; 996 };
997 997
998 admaif@290f000 { 998 admaif@290f000 {
999 status = "okay 999 status = "okay";
1000 1000
1001 ports { 1001 ports {
1002 #addr 1002 #address-cells = <1>;
1003 #size 1003 #size-cells = <0>;
1004 1004
1005 admai 1005 admaif0_port: port@0 {
1006 1006 reg = <0x0>;
1007 1007
1008 1008 admaif0_ep: endpoint {
1009 1009 remote-endpoint = <&xbar_admaif0_ep>;
1010 1010 };
1011 }; 1011 };
1012 1012
1013 admai 1013 admaif1_port: port@1 {
1014 1014 reg = <0x1>;
1015 1015
1016 1016 admaif1_ep: endpoint {
1017 1017 remote-endpoint = <&xbar_admaif1_ep>;
1018 1018 };
1019 }; 1019 };
1020 1020
1021 admai 1021 admaif2_port: port@2 {
1022 1022 reg = <0x2>;
1023 1023
1024 1024 admaif2_ep: endpoint {
1025 1025 remote-endpoint = <&xbar_admaif2_ep>;
1026 1026 };
1027 }; 1027 };
1028 1028
1029 admai 1029 admaif3_port: port@3 {
1030 1030 reg = <0x3>;
1031 1031
1032 1032 admaif3_ep: endpoint {
1033 1033 remote-endpoint = <&xbar_admaif3_ep>;
1034 1034 };
1035 }; 1035 };
1036 1036
1037 admai 1037 admaif4_port: port@4 {
1038 1038 reg = <0x4>;
1039 1039
1040 1040 admaif4_ep: endpoint {
1041 1041 remote-endpoint = <&xbar_admaif4_ep>;
1042 1042 };
1043 }; 1043 };
1044 1044
1045 admai 1045 admaif5_port: port@5 {
1046 1046 reg = <0x5>;
1047 1047
1048 1048 admaif5_ep: endpoint {
1049 1049 remote-endpoint = <&xbar_admaif5_ep>;
1050 1050 };
1051 }; 1051 };
1052 1052
1053 admai 1053 admaif6_port: port@6 {
1054 1054 reg = <0x6>;
1055 1055
1056 1056 admaif6_ep: endpoint {
1057 1057 remote-endpoint = <&xbar_admaif6_ep>;
1058 1058 };
1059 }; 1059 };
1060 1060
1061 admai 1061 admaif7_port: port@7 {
1062 1062 reg = <0x7>;
1063 1063
1064 1064 admaif7_ep: endpoint {
1065 1065 remote-endpoint = <&xbar_admaif7_ep>;
1066 1066 };
1067 }; 1067 };
1068 1068
1069 admai 1069 admaif8_port: port@8 {
1070 1070 reg = <0x8>;
1071 1071
1072 1072 admaif8_ep: endpoint {
1073 1073 remote-endpoint = <&xbar_admaif8_ep>;
1074 1074 };
1075 }; 1075 };
1076 1076
1077 admai 1077 admaif9_port: port@9 {
1078 1078 reg = <0x9>;
1079 1079
1080 1080 admaif9_ep: endpoint {
1081 1081 remote-endpoint = <&xbar_admaif9_ep>;
1082 1082 };
1083 }; 1083 };
1084 1084
1085 admai 1085 admaif10_port: port@a {
1086 1086 reg = <0xa>;
1087 1087
1088 1088 admaif10_ep: endpoint {
1089 1089 remote-endpoint = <&xbar_admaif10_ep>;
1090 1090 };
1091 }; 1091 };
1092 1092
1093 admai 1093 admaif11_port: port@b {
1094 1094 reg = <0xb>;
1095 1095
1096 1096 admaif11_ep: endpoint {
1097 1097 remote-endpoint = <&xbar_admaif11_ep>;
1098 1098 };
1099 }; 1099 };
1100 1100
1101 admai 1101 admaif12_port: port@c {
1102 1102 reg = <0xc>;
1103 1103
1104 1104 admaif12_ep: endpoint {
1105 1105 remote-endpoint = <&xbar_admaif12_ep>;
1106 1106 };
1107 }; 1107 };
1108 1108
1109 admai 1109 admaif13_port: port@d {
1110 1110 reg = <0xd>;
1111 1111
1112 1112 admaif13_ep: endpoint {
1113 1113 remote-endpoint = <&xbar_admaif13_ep>;
1114 1114 };
1115 }; 1115 };
1116 1116
1117 admai 1117 admaif14_port: port@e {
1118 1118 reg = <0xe>;
1119 1119
1120 1120 admaif14_ep: endpoint {
1121 1121 remote-endpoint = <&xbar_admaif14_ep>;
1122 1122 };
1123 }; 1123 };
1124 1124
1125 admai 1125 admaif15_port: port@f {
1126 1126 reg = <0xf>;
1127 1127
1128 1128 admaif15_ep: endpoint {
1129 1129 remote-endpoint = <&xbar_admaif15_ep>;
1130 1130 };
1131 }; 1131 };
1132 1132
1133 admai 1133 admaif16_port: port@10 {
1134 1134 reg = <0x10>;
1135 1135
1136 1136 admaif16_ep: endpoint {
1137 1137 remote-endpoint = <&xbar_admaif16_ep>;
1138 1138 };
1139 }; 1139 };
1140 1140
1141 admai 1141 admaif17_port: port@11 {
1142 1142 reg = <0x11>;
1143 1143
1144 1144 admaif17_ep: endpoint {
1145 1145 remote-endpoint = <&xbar_admaif17_ep>;
1146 1146 };
1147 }; 1147 };
1148 1148
1149 admai 1149 admaif18_port: port@12 {
1150 1150 reg = <0x12>;
1151 1151
1152 1152 admaif18_ep: endpoint {
1153 1153 remote-endpoint = <&xbar_admaif18_ep>;
1154 1154 };
1155 }; 1155 };
1156 1156
1157 admai 1157 admaif19_port: port@13 {
1158 1158 reg = <0x13>;
1159 1159
1160 1160 admaif19_ep: endpoint {
1161 1161 remote-endpoint = <&xbar_admaif19_ep>;
1162 1162 };
1163 }; 1163 };
1164 }; 1164 };
1165 }; 1165 };
1166 1166
1167 asrc@2910000 { 1167 asrc@2910000 {
1168 status = "oka 1168 status = "okay";
1169 1169
1170 ports { 1170 ports {
1171 #addr 1171 #address-cells = <1>;
1172 #size 1172 #size-cells = <0>;
1173 1173
1174 port@ 1174 port@0 {
1175 1175 reg = <0x0>;
1176 1176
1177 1177 asrc_in1_ep: endpoint {
1178 1178 remote-endpoint = <&xbar_asrc_in1_ep>;
1179 1179 };
1180 }; 1180 };
1181 1181
1182 port@ 1182 port@1 {
1183 1183 reg = <0x1>;
1184 1184
1185 1185 asrc_in2_ep: endpoint {
1186 1186 remote-endpoint = <&xbar_asrc_in2_ep>;
1187 1187 };
1188 }; 1188 };
1189 1189
1190 port@ 1190 port@2 {
1191 1191 reg = <0x2>;
1192 1192
1193 1193 asrc_in3_ep: endpoint {
1194 1194 remote-endpoint = <&xbar_asrc_in3_ep>;
1195 1195 };
1196 }; 1196 };
1197 1197
1198 port@ 1198 port@3 {
1199 1199 reg = <0x3>;
1200 1200
1201 1201 asrc_in4_ep: endpoint {
1202 1202 remote-endpoint = <&xbar_asrc_in4_ep>;
1203 1203 };
1204 }; 1204 };
1205 1205
1206 port@ 1206 port@4 {
1207 1207 reg = <0x4>;
1208 1208
1209 1209 asrc_in5_ep: endpoint {
1210 1210 remote-endpoint = <&xbar_asrc_in5_ep>;
1211 1211 };
1212 }; 1212 };
1213 1213
1214 port@ 1214 port@5 {
1215 1215 reg = <0x5>;
1216 1216
1217 1217 asrc_in6_ep: endpoint {
1218 1218 remote-endpoint = <&xbar_asrc_in6_ep>;
1219 1219 };
1220 }; 1220 };
1221 1221
1222 port@ 1222 port@6 {
1223 1223 reg = <0x6>;
1224 1224
1225 1225 asrc_in7_ep: endpoint {
1226 1226 remote-endpoint = <&xbar_asrc_in7_ep>;
1227 1227 };
1228 }; 1228 };
1229 1229
1230 asrc_ 1230 asrc_out1_port: port@7 {
1231 1231 reg = <0x7>;
1232 1232
1233 1233 asrc_out1_ep: endpoint {
1234 1234 remote-endpoint = <&xbar_asrc_out1_ep>;
1235 1235 };
1236 }; 1236 };
1237 1237
1238 asrc_ 1238 asrc_out2_port: port@8 {
1239 1239 reg = <0x8>;
1240 1240
1241 1241 asrc_out2_ep: endpoint {
1242 1242 remote-endpoint = <&xbar_asrc_out2_ep>;
1243 1243 };
1244 }; 1244 };
1245 1245
1246 asrc_ 1246 asrc_out3_port: port@9 {
1247 1247 reg = <0x9>;
1248 1248
1249 1249 asrc_out3_ep: endpoint {
1250 1250 remote-endpoint = <&xbar_asrc_out3_ep>;
1251 1251 };
1252 }; 1252 };
1253 1253
1254 asrc_ 1254 asrc_out4_port: port@a {
1255 1255 reg = <0xa>;
1256 1256
1257 1257 asrc_out4_ep: endpoint {
1258 1258 remote-endpoint = <&xbar_asrc_out4_ep>;
1259 1259 };
1260 }; 1260 };
1261 1261
1262 asrc_ 1262 asrc_out5_port: port@b {
1263 1263 reg = <0xb>;
1264 1264
1265 1265 asrc_out5_ep: endpoint {
1266 1266 remote-endpoint = <&xbar_asrc_out5_ep>;
1267 1267 };
1268 }; 1268 };
1269 1269
1270 asrc_ 1270 asrc_out6_port: port@c {
1271 1271 reg = <0xc>;
1272 1272
1273 1273 asrc_out6_ep: endpoint {
1274 1274 remote-endpoint = <&xbar_asrc_out6_ep>;
1275 1275 };
1276 }; 1276 };
1277 }; 1277 };
1278 }; 1278 };
1279 1279
1280 ports { 1280 ports {
1281 #address-cell 1281 #address-cells = <1>;
1282 #size-cells = 1282 #size-cells = <0>;
1283 1283
1284 port@0 { 1284 port@0 {
1285 reg = 1285 reg = <0x0>;
1286 1286
1287 xbar_ 1287 xbar_admaif0_ep: endpoint {
1288 1288 remote-endpoint = <&admaif0_ep>;
1289 }; 1289 };
1290 }; 1290 };
1291 1291
1292 port@1 { 1292 port@1 {
1293 reg = 1293 reg = <0x1>;
1294 1294
1295 xbar_ 1295 xbar_admaif1_ep: endpoint {
1296 1296 remote-endpoint = <&admaif1_ep>;
1297 }; 1297 };
1298 }; 1298 };
1299 1299
1300 port@2 { 1300 port@2 {
1301 reg = 1301 reg = <0x2>;
1302 1302
1303 xbar_ 1303 xbar_admaif2_ep: endpoint {
1304 1304 remote-endpoint = <&admaif2_ep>;
1305 }; 1305 };
1306 }; 1306 };
1307 1307
1308 port@3 { 1308 port@3 {
1309 reg = 1309 reg = <0x3>;
1310 1310
1311 xbar_ 1311 xbar_admaif3_ep: endpoint {
1312 1312 remote-endpoint = <&admaif3_ep>;
1313 }; 1313 };
1314 }; 1314 };
1315 1315
1316 port@4 { 1316 port@4 {
1317 reg = 1317 reg = <0x4>;
1318 1318
1319 xbar_ 1319 xbar_admaif4_ep: endpoint {
1320 1320 remote-endpoint = <&admaif4_ep>;
1321 }; 1321 };
1322 }; 1322 };
1323 1323
1324 port@5 { 1324 port@5 {
1325 reg = 1325 reg = <0x5>;
1326 1326
1327 xbar_ 1327 xbar_admaif5_ep: endpoint {
1328 1328 remote-endpoint = <&admaif5_ep>;
1329 }; 1329 };
1330 }; 1330 };
1331 1331
1332 port@6 { 1332 port@6 {
1333 reg = 1333 reg = <0x6>;
1334 1334
1335 xbar_ 1335 xbar_admaif6_ep: endpoint {
1336 1336 remote-endpoint = <&admaif6_ep>;
1337 }; 1337 };
1338 }; 1338 };
1339 1339
1340 port@7 { 1340 port@7 {
1341 reg = 1341 reg = <0x7>;
1342 1342
1343 xbar_ 1343 xbar_admaif7_ep: endpoint {
1344 1344 remote-endpoint = <&admaif7_ep>;
1345 }; 1345 };
1346 }; 1346 };
1347 1347
1348 port@8 { 1348 port@8 {
1349 reg = 1349 reg = <0x8>;
1350 1350
1351 xbar_ 1351 xbar_admaif8_ep: endpoint {
1352 1352 remote-endpoint = <&admaif8_ep>;
1353 }; 1353 };
1354 }; 1354 };
1355 1355
1356 port@9 { 1356 port@9 {
1357 reg = 1357 reg = <0x9>;
1358 1358
1359 xbar_ 1359 xbar_admaif9_ep: endpoint {
1360 1360 remote-endpoint = <&admaif9_ep>;
1361 }; 1361 };
1362 }; 1362 };
1363 1363
1364 port@a { 1364 port@a {
1365 reg = 1365 reg = <0xa>;
1366 1366
1367 xbar_ 1367 xbar_admaif10_ep: endpoint {
1368 1368 remote-endpoint = <&admaif10_ep>;
1369 }; 1369 };
1370 }; 1370 };
1371 1371
1372 port@b { 1372 port@b {
1373 reg = 1373 reg = <0xb>;
1374 1374
1375 xbar_ 1375 xbar_admaif11_ep: endpoint {
1376 1376 remote-endpoint = <&admaif11_ep>;
1377 }; 1377 };
1378 }; 1378 };
1379 1379
1380 port@c { 1380 port@c {
1381 reg = 1381 reg = <0xc>;
1382 1382
1383 xbar_ 1383 xbar_admaif12_ep: endpoint {
1384 1384 remote-endpoint = <&admaif12_ep>;
1385 }; 1385 };
1386 }; 1386 };
1387 1387
1388 port@d { 1388 port@d {
1389 reg = 1389 reg = <0xd>;
1390 1390
1391 xbar_ 1391 xbar_admaif13_ep: endpoint {
1392 1392 remote-endpoint = <&admaif13_ep>;
1393 }; 1393 };
1394 }; 1394 };
1395 1395
1396 port@e { 1396 port@e {
1397 reg = 1397 reg = <0xe>;
1398 1398
1399 xbar_ 1399 xbar_admaif14_ep: endpoint {
1400 1400 remote-endpoint = <&admaif14_ep>;
1401 }; 1401 };
1402 }; 1402 };
1403 1403
1404 port@f { 1404 port@f {
1405 reg = 1405 reg = <0xf>;
1406 1406
1407 xbar_ 1407 xbar_admaif15_ep: endpoint {
1408 1408 remote-endpoint = <&admaif15_ep>;
1409 }; 1409 };
1410 }; 1410 };
1411 1411
1412 port@10 { 1412 port@10 {
1413 reg = 1413 reg = <0x10>;
1414 1414
1415 xbar_ 1415 xbar_admaif16_ep: endpoint {
1416 1416 remote-endpoint = <&admaif16_ep>;
1417 }; 1417 };
1418 }; 1418 };
1419 1419
1420 port@11 { 1420 port@11 {
1421 reg = 1421 reg = <0x11>;
1422 1422
1423 xbar_ 1423 xbar_admaif17_ep: endpoint {
1424 1424 remote-endpoint = <&admaif17_ep>;
1425 }; 1425 };
1426 }; 1426 };
1427 1427
1428 port@12 { 1428 port@12 {
1429 reg = 1429 reg = <0x12>;
1430 1430
1431 xbar_ 1431 xbar_admaif18_ep: endpoint {
1432 1432 remote-endpoint = <&admaif18_ep>;
1433 }; 1433 };
1434 }; 1434 };
1435 1435
1436 port@13 { 1436 port@13 {
1437 reg = 1437 reg = <0x13>;
1438 1438
1439 xbar_ 1439 xbar_admaif19_ep: endpoint {
1440 1440 remote-endpoint = <&admaif19_ep>;
1441 }; 1441 };
1442 }; 1442 };
1443 1443
1444 xbar_i2s1_por 1444 xbar_i2s1_port: port@14 {
1445 reg = 1445 reg = <0x14>;
1446 1446
1447 xbar_ 1447 xbar_i2s1_ep: endpoint {
1448 1448 remote-endpoint = <&i2s1_cif_ep>;
1449 }; 1449 };
1450 }; 1450 };
1451 1451
1452 xbar_i2s2_por 1452 xbar_i2s2_port: port@15 {
1453 reg = 1453 reg = <0x15>;
1454 1454
1455 xbar_ 1455 xbar_i2s2_ep: endpoint {
1456 1456 remote-endpoint = <&i2s2_cif_ep>;
1457 }; 1457 };
1458 }; 1458 };
1459 1459
1460 xbar_i2s3_por 1460 xbar_i2s3_port: port@16 {
1461 reg = 1461 reg = <0x16>;
1462 1462
1463 xbar_ 1463 xbar_i2s3_ep: endpoint {
1464 1464 remote-endpoint = <&i2s3_cif_ep>;
1465 }; 1465 };
1466 }; 1466 };
1467 1467
1468 xbar_i2s4_por 1468 xbar_i2s4_port: port@17 {
1469 reg = 1469 reg = <0x17>;
1470 1470
1471 xbar_ 1471 xbar_i2s4_ep: endpoint {
1472 1472 remote-endpoint = <&i2s4_cif_ep>;
1473 }; 1473 };
1474 }; 1474 };
1475 1475
1476 xbar_i2s5_por 1476 xbar_i2s5_port: port@18 {
1477 reg = 1477 reg = <0x18>;
1478 1478
1479 xbar_ 1479 xbar_i2s5_ep: endpoint {
1480 1480 remote-endpoint = <&i2s5_cif_ep>;
1481 }; 1481 };
1482 }; 1482 };
1483 1483
1484 xbar_i2s6_por 1484 xbar_i2s6_port: port@19 {
1485 reg = 1485 reg = <0x19>;
1486 1486
1487 xbar_ 1487 xbar_i2s6_ep: endpoint {
1488 1488 remote-endpoint = <&i2s6_cif_ep>;
1489 }; 1489 };
1490 }; 1490 };
1491 1491
1492 xbar_dmic1_po 1492 xbar_dmic1_port: port@1a {
1493 reg = 1493 reg = <0x1a>;
1494 1494
1495 xbar_ 1495 xbar_dmic1_ep: endpoint {
1496 1496 remote-endpoint = <&dmic1_cif_ep>;
1497 }; 1497 };
1498 }; 1498 };
1499 1499
1500 xbar_dmic2_po 1500 xbar_dmic2_port: port@1b {
1501 reg = 1501 reg = <0x1b>;
1502 1502
1503 xbar_ 1503 xbar_dmic2_ep: endpoint {
1504 1504 remote-endpoint = <&dmic2_cif_ep>;
1505 }; 1505 };
1506 }; 1506 };
1507 1507
1508 xbar_dmic3_po 1508 xbar_dmic3_port: port@1c {
1509 reg = 1509 reg = <0x1c>;
1510 1510
1511 xbar_ 1511 xbar_dmic3_ep: endpoint {
1512 1512 remote-endpoint = <&dmic3_cif_ep>;
1513 }; 1513 };
1514 }; 1514 };
1515 1515
1516 xbar_dspk1_po 1516 xbar_dspk1_port: port@1e {
1517 reg = 1517 reg = <0x1e>;
1518 1518
1519 xbar_ 1519 xbar_dspk1_ep: endpoint {
1520 1520 remote-endpoint = <&dspk1_cif_ep>;
1521 }; 1521 };
1522 }; 1522 };
1523 1523
1524 xbar_dspk2_po 1524 xbar_dspk2_port: port@1f {
1525 reg = 1525 reg = <0x1f>;
1526 1526
1527 xbar_ 1527 xbar_dspk2_ep: endpoint {
1528 1528 remote-endpoint = <&dspk2_cif_ep>;
1529 }; 1529 };
1530 }; 1530 };
1531 1531
1532 xbar_sfc1_in_ 1532 xbar_sfc1_in_port: port@20 {
1533 reg = 1533 reg = <0x20>;
1534 1534
1535 xbar_ 1535 xbar_sfc1_in_ep: endpoint {
1536 1536 remote-endpoint = <&sfc1_cif_in_ep>;
1537 }; 1537 };
1538 }; 1538 };
1539 1539
1540 port@21 { 1540 port@21 {
1541 reg = 1541 reg = <0x21>;
1542 1542
1543 xbar_ 1543 xbar_sfc1_out_ep: endpoint {
1544 1544 remote-endpoint = <&sfc1_cif_out_ep>;
1545 }; 1545 };
1546 }; 1546 };
1547 1547
1548 xbar_sfc2_in_ 1548 xbar_sfc2_in_port: port@22 {
1549 reg = 1549 reg = <0x22>;
1550 1550
1551 xbar_ 1551 xbar_sfc2_in_ep: endpoint {
1552 1552 remote-endpoint = <&sfc2_cif_in_ep>;
1553 }; 1553 };
1554 }; 1554 };
1555 1555
1556 port@23 { 1556 port@23 {
1557 reg = 1557 reg = <0x23>;
1558 1558
1559 xbar_ 1559 xbar_sfc2_out_ep: endpoint {
1560 1560 remote-endpoint = <&sfc2_cif_out_ep>;
1561 }; 1561 };
1562 }; 1562 };
1563 1563
1564 xbar_sfc3_in_ 1564 xbar_sfc3_in_port: port@24 {
1565 reg = 1565 reg = <0x24>;
1566 1566
1567 xbar_ 1567 xbar_sfc3_in_ep: endpoint {
1568 1568 remote-endpoint = <&sfc3_cif_in_ep>;
1569 }; 1569 };
1570 }; 1570 };
1571 1571
1572 port@25 { 1572 port@25 {
1573 reg = 1573 reg = <0x25>;
1574 1574
1575 xbar_ 1575 xbar_sfc3_out_ep: endpoint {
1576 1576 remote-endpoint = <&sfc3_cif_out_ep>;
1577 }; 1577 };
1578 }; 1578 };
1579 1579
1580 xbar_sfc4_in_ 1580 xbar_sfc4_in_port: port@26 {
1581 reg = 1581 reg = <0x26>;
1582 1582
1583 xbar_ 1583 xbar_sfc4_in_ep: endpoint {
1584 1584 remote-endpoint = <&sfc4_cif_in_ep>;
1585 }; 1585 };
1586 }; 1586 };
1587 1587
1588 port@27 { 1588 port@27 {
1589 reg = 1589 reg = <0x27>;
1590 1590
1591 xbar_ 1591 xbar_sfc4_out_ep: endpoint {
1592 1592 remote-endpoint = <&sfc4_cif_out_ep>;
1593 }; 1593 };
1594 }; 1594 };
1595 1595
1596 xbar_mvc1_in_ 1596 xbar_mvc1_in_port: port@28 {
1597 reg = 1597 reg = <0x28>;
1598 1598
1599 xbar_ 1599 xbar_mvc1_in_ep: endpoint {
1600 1600 remote-endpoint = <&mvc1_cif_in_ep>;
1601 }; 1601 };
1602 }; 1602 };
1603 1603
1604 port@29 { 1604 port@29 {
1605 reg = 1605 reg = <0x29>;
1606 1606
1607 xbar_ 1607 xbar_mvc1_out_ep: endpoint {
1608 1608 remote-endpoint = <&mvc1_cif_out_ep>;
1609 }; 1609 };
1610 }; 1610 };
1611 1611
1612 xbar_mvc2_in_ 1612 xbar_mvc2_in_port: port@2a {
1613 reg = 1613 reg = <0x2a>;
1614 1614
1615 xbar_ 1615 xbar_mvc2_in_ep: endpoint {
1616 1616 remote-endpoint = <&mvc2_cif_in_ep>;
1617 }; 1617 };
1618 }; 1618 };
1619 1619
1620 port@2b { 1620 port@2b {
1621 reg = 1621 reg = <0x2b>;
1622 1622
1623 xbar_ 1623 xbar_mvc2_out_ep: endpoint {
1624 1624 remote-endpoint = <&mvc2_cif_out_ep>;
1625 }; 1625 };
1626 }; 1626 };
1627 1627
1628 xbar_amx1_in1 1628 xbar_amx1_in1_port: port@2c {
1629 reg = 1629 reg = <0x2c>;
1630 1630
1631 xbar_ 1631 xbar_amx1_in1_ep: endpoint {
1632 1632 remote-endpoint = <&amx1_in1_ep>;
1633 }; 1633 };
1634 }; 1634 };
1635 1635
1636 xbar_amx1_in2 1636 xbar_amx1_in2_port: port@2d {
1637 reg = 1637 reg = <0x2d>;
1638 1638
1639 xbar_ 1639 xbar_amx1_in2_ep: endpoint {
1640 1640 remote-endpoint = <&amx1_in2_ep>;
1641 }; 1641 };
1642 }; 1642 };
1643 1643
1644 xbar_amx1_in3 1644 xbar_amx1_in3_port: port@2e {
1645 reg = 1645 reg = <0x2e>;
1646 1646
1647 xbar_ 1647 xbar_amx1_in3_ep: endpoint {
1648 1648 remote-endpoint = <&amx1_in3_ep>;
1649 }; 1649 };
1650 }; 1650 };
1651 1651
1652 xbar_amx1_in4 1652 xbar_amx1_in4_port: port@2f {
1653 reg = 1653 reg = <0x2f>;
1654 1654
1655 xbar_ 1655 xbar_amx1_in4_ep: endpoint {
1656 1656 remote-endpoint = <&amx1_in4_ep>;
1657 }; 1657 };
1658 }; 1658 };
1659 1659
1660 port@30 { 1660 port@30 {
1661 reg = 1661 reg = <0x30>;
1662 1662
1663 xbar_ 1663 xbar_amx1_out_ep: endpoint {
1664 1664 remote-endpoint = <&amx1_out_ep>;
1665 }; 1665 };
1666 }; 1666 };
1667 1667
1668 xbar_amx2_in1 1668 xbar_amx2_in1_port: port@31 {
1669 reg = 1669 reg = <0x31>;
1670 1670
1671 xbar_ 1671 xbar_amx2_in1_ep: endpoint {
1672 1672 remote-endpoint = <&amx2_in1_ep>;
1673 }; 1673 };
1674 }; 1674 };
1675 1675
1676 xbar_amx2_in2 1676 xbar_amx2_in2_port: port@32 {
1677 reg = 1677 reg = <0x32>;
1678 1678
1679 xbar_ 1679 xbar_amx2_in2_ep: endpoint {
1680 1680 remote-endpoint = <&amx2_in2_ep>;
1681 }; 1681 };
1682 }; 1682 };
1683 1683
1684 xbar_amx2_in3 1684 xbar_amx2_in3_port: port@33 {
1685 reg = 1685 reg = <0x33>;
1686 1686
1687 xbar_ 1687 xbar_amx2_in3_ep: endpoint {
1688 1688 remote-endpoint = <&amx2_in3_ep>;
1689 }; 1689 };
1690 }; 1690 };
1691 1691
1692 xbar_amx2_in4 1692 xbar_amx2_in4_port: port@34 {
1693 reg = 1693 reg = <0x34>;
1694 1694
1695 xbar_ 1695 xbar_amx2_in4_ep: endpoint {
1696 1696 remote-endpoint = <&amx2_in4_ep>;
1697 }; 1697 };
1698 }; 1698 };
1699 1699
1700 port@35 { 1700 port@35 {
1701 reg = 1701 reg = <0x35>;
1702 1702
1703 xbar_ 1703 xbar_amx2_out_ep: endpoint {
1704 1704 remote-endpoint = <&amx2_out_ep>;
1705 }; 1705 };
1706 }; 1706 };
1707 1707
1708 xbar_amx3_in1 1708 xbar_amx3_in1_port: port@36 {
1709 reg = 1709 reg = <0x36>;
1710 1710
1711 xbar_ 1711 xbar_amx3_in1_ep: endpoint {
1712 1712 remote-endpoint = <&amx3_in1_ep>;
1713 }; 1713 };
1714 }; 1714 };
1715 1715
1716 xbar_amx3_in2 1716 xbar_amx3_in2_port: port@37 {
1717 reg = 1717 reg = <0x37>;
1718 1718
1719 xbar_ 1719 xbar_amx3_in2_ep: endpoint {
1720 1720 remote-endpoint = <&amx3_in2_ep>;
1721 }; 1721 };
1722 }; 1722 };
1723 1723
1724 xbar_amx3_in3 1724 xbar_amx3_in3_port: port@38 {
1725 reg = 1725 reg = <0x38>;
1726 1726
1727 xbar_ 1727 xbar_amx3_in3_ep: endpoint {
1728 1728 remote-endpoint = <&amx3_in3_ep>;
1729 }; 1729 };
1730 }; 1730 };
1731 1731
1732 xbar_amx3_in4 1732 xbar_amx3_in4_port: port@39 {
1733 reg = 1733 reg = <0x39>;
1734 1734
1735 xbar_ 1735 xbar_amx3_in4_ep: endpoint {
1736 1736 remote-endpoint = <&amx3_in4_ep>;
1737 }; 1737 };
1738 }; 1738 };
1739 1739
1740 port@3a { 1740 port@3a {
1741 reg = 1741 reg = <0x3a>;
1742 1742
1743 xbar_ 1743 xbar_amx3_out_ep: endpoint {
1744 1744 remote-endpoint = <&amx3_out_ep>;
1745 }; 1745 };
1746 }; 1746 };
1747 1747
1748 xbar_amx4_in1 1748 xbar_amx4_in1_port: port@3b {
1749 reg = 1749 reg = <0x3b>;
1750 1750
1751 xbar_ 1751 xbar_amx4_in1_ep: endpoint {
1752 1752 remote-endpoint = <&amx4_in1_ep>;
1753 }; 1753 };
1754 }; 1754 };
1755 1755
1756 xbar_amx4_in2 1756 xbar_amx4_in2_port: port@3c {
1757 reg = 1757 reg = <0x3c>;
1758 1758
1759 xbar_ 1759 xbar_amx4_in2_ep: endpoint {
1760 1760 remote-endpoint = <&amx4_in2_ep>;
1761 }; 1761 };
1762 }; 1762 };
1763 1763
1764 xbar_amx4_in3 1764 xbar_amx4_in3_port: port@3d {
1765 reg = 1765 reg = <0x3d>;
1766 1766
1767 xbar_ 1767 xbar_amx4_in3_ep: endpoint {
1768 1768 remote-endpoint = <&amx4_in3_ep>;
1769 }; 1769 };
1770 }; 1770 };
1771 1771
1772 xbar_amx4_in4 1772 xbar_amx4_in4_port: port@3e {
1773 reg = 1773 reg = <0x3e>;
1774 1774
1775 xbar_ 1775 xbar_amx4_in4_ep: endpoint {
1776 1776 remote-endpoint = <&amx4_in4_ep>;
1777 }; 1777 };
1778 }; 1778 };
1779 1779
1780 port@3f { 1780 port@3f {
1781 reg = 1781 reg = <0x3f>;
1782 1782
1783 xbar_ 1783 xbar_amx4_out_ep: endpoint {
1784 1784 remote-endpoint = <&amx4_out_ep>;
1785 }; 1785 };
1786 }; 1786 };
1787 1787
1788 xbar_adx1_in_ 1788 xbar_adx1_in_port: port@40 {
1789 reg = 1789 reg = <0x40>;
1790 1790
1791 xbar_ 1791 xbar_adx1_in_ep: endpoint {
1792 1792 remote-endpoint = <&adx1_in_ep>;
1793 }; 1793 };
1794 }; 1794 };
1795 1795
1796 port@41 { 1796 port@41 {
1797 reg = 1797 reg = <0x41>;
1798 1798
1799 xbar_ 1799 xbar_adx1_out1_ep: endpoint {
1800 1800 remote-endpoint = <&adx1_out1_ep>;
1801 }; 1801 };
1802 }; 1802 };
1803 1803
1804 port@42 { 1804 port@42 {
1805 reg = 1805 reg = <0x42>;
1806 1806
1807 xbar_ 1807 xbar_adx1_out2_ep: endpoint {
1808 1808 remote-endpoint = <&adx1_out2_ep>;
1809 }; 1809 };
1810 }; 1810 };
1811 1811
1812 port@43 { 1812 port@43 {
1813 reg = 1813 reg = <0x43>;
1814 1814
1815 xbar_ 1815 xbar_adx1_out3_ep: endpoint {
1816 1816 remote-endpoint = <&adx1_out3_ep>;
1817 }; 1817 };
1818 }; 1818 };
1819 1819
1820 port@44 { 1820 port@44 {
1821 reg = 1821 reg = <0x44>;
1822 1822
1823 xbar_ 1823 xbar_adx1_out4_ep: endpoint {
1824 1824 remote-endpoint = <&adx1_out4_ep>;
1825 }; 1825 };
1826 }; 1826 };
1827 1827
1828 xbar_adx2_in_ 1828 xbar_adx2_in_port: port@45 {
1829 reg = 1829 reg = <0x45>;
1830 1830
1831 xbar_ 1831 xbar_adx2_in_ep: endpoint {
1832 1832 remote-endpoint = <&adx2_in_ep>;
1833 }; 1833 };
1834 }; 1834 };
1835 1835
1836 port@46 { 1836 port@46 {
1837 reg = 1837 reg = <0x46>;
1838 1838
1839 xbar_ 1839 xbar_adx2_out1_ep: endpoint {
1840 1840 remote-endpoint = <&adx2_out1_ep>;
1841 }; 1841 };
1842 }; 1842 };
1843 1843
1844 port@47 { 1844 port@47 {
1845 reg = 1845 reg = <0x47>;
1846 1846
1847 xbar_ 1847 xbar_adx2_out2_ep: endpoint {
1848 1848 remote-endpoint = <&adx2_out2_ep>;
1849 }; 1849 };
1850 }; 1850 };
1851 1851
1852 port@48 { 1852 port@48 {
1853 reg = 1853 reg = <0x48>;
1854 1854
1855 xbar_ 1855 xbar_adx2_out3_ep: endpoint {
1856 1856 remote-endpoint = <&adx2_out3_ep>;
1857 }; 1857 };
1858 }; 1858 };
1859 1859
1860 port@49 { 1860 port@49 {
1861 reg = 1861 reg = <0x49>;
1862 1862
1863 xbar_ 1863 xbar_adx2_out4_ep: endpoint {
1864 1864 remote-endpoint = <&adx2_out4_ep>;
1865 }; 1865 };
1866 }; 1866 };
1867 1867
1868 xbar_adx3_in_ 1868 xbar_adx3_in_port: port@4a {
1869 reg = 1869 reg = <0x4a>;
1870 1870
1871 xbar_ 1871 xbar_adx3_in_ep: endpoint {
1872 1872 remote-endpoint = <&adx3_in_ep>;
1873 }; 1873 };
1874 }; 1874 };
1875 1875
1876 port@4b { 1876 port@4b {
1877 reg = 1877 reg = <0x4b>;
1878 1878
1879 xbar_ 1879 xbar_adx3_out1_ep: endpoint {
1880 1880 remote-endpoint = <&adx3_out1_ep>;
1881 }; 1881 };
1882 }; 1882 };
1883 1883
1884 port@4c { 1884 port@4c {
1885 reg = 1885 reg = <0x4c>;
1886 1886
1887 xbar_ 1887 xbar_adx3_out2_ep: endpoint {
1888 1888 remote-endpoint = <&adx3_out2_ep>;
1889 }; 1889 };
1890 }; 1890 };
1891 1891
1892 port@4d { 1892 port@4d {
1893 reg = 1893 reg = <0x4d>;
1894 1894
1895 xbar_ 1895 xbar_adx3_out3_ep: endpoint {
1896 1896 remote-endpoint = <&adx3_out3_ep>;
1897 }; 1897 };
1898 }; 1898 };
1899 1899
1900 port@4e { 1900 port@4e {
1901 reg = 1901 reg = <0x4e>;
1902 1902
1903 xbar_ 1903 xbar_adx3_out4_ep: endpoint {
1904 1904 remote-endpoint = <&adx3_out4_ep>;
1905 }; 1905 };
1906 }; 1906 };
1907 1907
1908 xbar_adx4_in_ 1908 xbar_adx4_in_port: port@4f {
1909 reg = 1909 reg = <0x4f>;
1910 1910
1911 xbar_ 1911 xbar_adx4_in_ep: endpoint {
1912 1912 remote-endpoint = <&adx4_in_ep>;
1913 }; 1913 };
1914 }; 1914 };
1915 1915
1916 port@50 { 1916 port@50 {
1917 reg = 1917 reg = <0x50>;
1918 1918
1919 xbar_ 1919 xbar_adx4_out1_ep: endpoint {
1920 1920 remote-endpoint = <&adx4_out1_ep>;
1921 }; 1921 };
1922 }; 1922 };
1923 1923
1924 port@51 { 1924 port@51 {
1925 reg = 1925 reg = <0x51>;
1926 1926
1927 xbar_ 1927 xbar_adx4_out2_ep: endpoint {
1928 1928 remote-endpoint = <&adx4_out2_ep>;
1929 }; 1929 };
1930 }; 1930 };
1931 1931
1932 port@52 { 1932 port@52 {
1933 reg = 1933 reg = <0x52>;
1934 1934
1935 xbar_ 1935 xbar_adx4_out3_ep: endpoint {
1936 1936 remote-endpoint = <&adx4_out3_ep>;
1937 }; 1937 };
1938 }; 1938 };
1939 1939
1940 port@53 { 1940 port@53 {
1941 reg = 1941 reg = <0x53>;
1942 1942
1943 xbar_ 1943 xbar_adx4_out4_ep: endpoint {
1944 1944 remote-endpoint = <&adx4_out4_ep>;
1945 }; 1945 };
1946 }; 1946 };
1947 1947
1948 xbar_mixer_in 1948 xbar_mixer_in1_port: port@54 {
1949 reg = 1949 reg = <0x54>;
1950 1950
1951 xbar_ 1951 xbar_mixer_in1_ep: endpoint {
1952 1952 remote-endpoint = <&mixer_in1_ep>;
1953 }; 1953 };
1954 }; 1954 };
1955 1955
1956 xbar_mixer_in 1956 xbar_mixer_in2_port: port@55 {
1957 reg = 1957 reg = <0x55>;
1958 1958
1959 xbar_ 1959 xbar_mixer_in2_ep: endpoint {
1960 1960 remote-endpoint = <&mixer_in2_ep>;
1961 }; 1961 };
1962 }; 1962 };
1963 1963
1964 xbar_mixer_in 1964 xbar_mixer_in3_port: port@56 {
1965 reg = 1965 reg = <0x56>;
1966 1966
1967 xbar_ 1967 xbar_mixer_in3_ep: endpoint {
1968 1968 remote-endpoint = <&mixer_in3_ep>;
1969 }; 1969 };
1970 }; 1970 };
1971 1971
1972 xbar_mixer_in 1972 xbar_mixer_in4_port: port@57 {
1973 reg = 1973 reg = <0x57>;
1974 1974
1975 xbar_ 1975 xbar_mixer_in4_ep: endpoint {
1976 1976 remote-endpoint = <&mixer_in4_ep>;
1977 }; 1977 };
1978 }; 1978 };
1979 1979
1980 xbar_mixer_in 1980 xbar_mixer_in5_port: port@58 {
1981 reg = 1981 reg = <0x58>;
1982 1982
1983 xbar_ 1983 xbar_mixer_in5_ep: endpoint {
1984 1984 remote-endpoint = <&mixer_in5_ep>;
1985 }; 1985 };
1986 }; 1986 };
1987 1987
1988 xbar_mixer_in 1988 xbar_mixer_in6_port: port@59 {
1989 reg = 1989 reg = <0x59>;
1990 1990
1991 xbar_ 1991 xbar_mixer_in6_ep: endpoint {
1992 1992 remote-endpoint = <&mixer_in6_ep>;
1993 }; 1993 };
1994 }; 1994 };
1995 1995
1996 xbar_mixer_in 1996 xbar_mixer_in7_port: port@5a {
1997 reg = 1997 reg = <0x5a>;
1998 1998
1999 xbar_ 1999 xbar_mixer_in7_ep: endpoint {
2000 2000 remote-endpoint = <&mixer_in7_ep>;
2001 }; 2001 };
2002 }; 2002 };
2003 2003
2004 xbar_mixer_in 2004 xbar_mixer_in8_port: port@5b {
2005 reg = 2005 reg = <0x5b>;
2006 2006
2007 xbar_ 2007 xbar_mixer_in8_ep: endpoint {
2008 2008 remote-endpoint = <&mixer_in8_ep>;
2009 }; 2009 };
2010 }; 2010 };
2011 2011
2012 xbar_mixer_in 2012 xbar_mixer_in9_port: port@5c {
2013 reg = 2013 reg = <0x5c>;
2014 2014
2015 xbar_ 2015 xbar_mixer_in9_ep: endpoint {
2016 2016 remote-endpoint = <&mixer_in9_ep>;
2017 }; 2017 };
2018 }; 2018 };
2019 2019
2020 xbar_mixer_in 2020 xbar_mixer_in10_port: port@5d {
2021 reg = 2021 reg = <0x5d>;
2022 2022
2023 xbar_ 2023 xbar_mixer_in10_ep: endpoint {
2024 2024 remote-endpoint = <&mixer_in10_ep>;
2025 }; 2025 };
2026 }; 2026 };
2027 2027
2028 port@5e { 2028 port@5e {
2029 reg = 2029 reg = <0x5e>;
2030 2030
2031 xbar_ 2031 xbar_mixer_out1_ep: endpoint {
2032 2032 remote-endpoint = <&mixer_out1_ep>;
2033 }; 2033 };
2034 }; 2034 };
2035 2035
2036 port@5f { 2036 port@5f {
2037 reg = 2037 reg = <0x5f>;
2038 2038
2039 xbar_ 2039 xbar_mixer_out2_ep: endpoint {
2040 2040 remote-endpoint = <&mixer_out2_ep>;
2041 }; 2041 };
2042 }; 2042 };
2043 2043
2044 port@60 { 2044 port@60 {
2045 reg = 2045 reg = <0x60>;
2046 2046
2047 xbar_ 2047 xbar_mixer_out3_ep: endpoint {
2048 2048 remote-endpoint = <&mixer_out3_ep>;
2049 }; 2049 };
2050 }; 2050 };
2051 2051
2052 port@61 { 2052 port@61 {
2053 reg = 2053 reg = <0x61>;
2054 2054
2055 xbar_ 2055 xbar_mixer_out4_ep: endpoint {
2056 2056 remote-endpoint = <&mixer_out4_ep>;
2057 }; 2057 };
2058 }; 2058 };
2059 2059
2060 port@62 { 2060 port@62 {
2061 reg = 2061 reg = <0x62>;
2062 2062
2063 xbar_ 2063 xbar_mixer_out5_ep: endpoint {
2064 2064 remote-endpoint = <&mixer_out5_ep>;
2065 }; 2065 };
2066 }; 2066 };
2067 2067
2068 xbar_asrc_in1 2068 xbar_asrc_in1_port: port@63 {
2069 reg = 2069 reg = <0x63>;
2070 2070
2071 xbar_ 2071 xbar_asrc_in1_ep: endpoint {
2072 2072 remote-endpoint = <&asrc_in1_ep>;
2073 }; 2073 };
2074 }; 2074 };
2075 2075
2076 port@64 { 2076 port@64 {
2077 reg = 2077 reg = <0x64>;
2078 2078
2079 xbar_ 2079 xbar_asrc_out1_ep: endpoint {
2080 2080 remote-endpoint = <&asrc_out1_ep>;
2081 }; 2081 };
2082 }; 2082 };
2083 2083
2084 xbar_asrc_in2 2084 xbar_asrc_in2_port: port@65 {
2085 reg = 2085 reg = <0x65>;
2086 2086
2087 xbar_ 2087 xbar_asrc_in2_ep: endpoint {
2088 2088 remote-endpoint = <&asrc_in2_ep>;
2089 }; 2089 };
2090 }; 2090 };
2091 2091
2092 port@66 { 2092 port@66 {
2093 reg = 2093 reg = <0x66>;
2094 2094
2095 xbar_ 2095 xbar_asrc_out2_ep: endpoint {
2096 2096 remote-endpoint = <&asrc_out2_ep>;
2097 }; 2097 };
2098 }; 2098 };
2099 2099
2100 xbar_asrc_in3 2100 xbar_asrc_in3_port: port@67 {
2101 reg = 2101 reg = <0x67>;
2102 2102
2103 xbar_ 2103 xbar_asrc_in3_ep: endpoint {
2104 2104 remote-endpoint = <&asrc_in3_ep>;
2105 }; 2105 };
2106 }; 2106 };
2107 2107
2108 port@68 { 2108 port@68 {
2109 reg = 2109 reg = <0x68>;
2110 2110
2111 xbar_ 2111 xbar_asrc_out3_ep: endpoint {
2112 2112 remote-endpoint = <&asrc_out3_ep>;
2113 }; 2113 };
2114 }; 2114 };
2115 2115
2116 xbar_asrc_in4 2116 xbar_asrc_in4_port: port@69 {
2117 reg = 2117 reg = <0x69>;
2118 2118
2119 xbar_ 2119 xbar_asrc_in4_ep: endpoint {
2120 2120 remote-endpoint = <&asrc_in4_ep>;
2121 }; 2121 };
2122 }; 2122 };
2123 2123
2124 port@6a { 2124 port@6a {
2125 reg = 2125 reg = <0x6a>;
2126 2126
2127 xbar_ 2127 xbar_asrc_out4_ep: endpoint {
2128 2128 remote-endpoint = <&asrc_out4_ep>;
2129 }; 2129 };
2130 }; 2130 };
2131 2131
2132 xbar_asrc_in5 2132 xbar_asrc_in5_port: port@6b {
2133 reg = 2133 reg = <0x6b>;
2134 2134
2135 xbar_ 2135 xbar_asrc_in5_ep: endpoint {
2136 2136 remote-endpoint = <&asrc_in5_ep>;
2137 }; 2137 };
2138 }; 2138 };
2139 2139
2140 port@6c { 2140 port@6c {
2141 reg = 2141 reg = <0x6c>;
2142 2142
2143 xbar_ 2143 xbar_asrc_out5_ep: endpoint {
2144 2144 remote-endpoint = <&asrc_out5_ep>;
2145 }; 2145 };
2146 }; 2146 };
2147 2147
2148 xbar_asrc_in6 2148 xbar_asrc_in6_port: port@6d {
2149 reg = 2149 reg = <0x6d>;
2150 2150
2151 xbar_ 2151 xbar_asrc_in6_ep: endpoint {
2152 2152 remote-endpoint = <&asrc_in6_ep>;
2153 }; 2153 };
2154 }; 2154 };
2155 2155
2156 port@6e { 2156 port@6e {
2157 reg = 2157 reg = <0x6e>;
2158 2158
2159 xbar_ 2159 xbar_asrc_out6_ep: endpoint {
2160 2160 remote-endpoint = <&asrc_out6_ep>;
2161 }; 2161 };
2162 }; 2162 };
2163 2163
2164 xbar_asrc_in7 2164 xbar_asrc_in7_port: port@6f {
2165 reg = 2165 reg = <0x6f>;
2166 2166
2167 xbar_ 2167 xbar_asrc_in7_ep: endpoint {
2168 2168 remote-endpoint = <&asrc_in7_ep>;
2169 }; 2169 };
2170 }; 2170 };
2171 2171
2172 xbar_ope1_in_ 2172 xbar_ope1_in_port: port@70 {
2173 reg = 2173 reg = <0x70>;
2174 2174
2175 xbar_ 2175 xbar_ope1_in_ep: endpoint {
2176 2176 remote-endpoint = <&ope1_cif_in_ep>;
2177 }; 2177 };
2178 }; 2178 };
2179 2179
2180 port@71 { 2180 port@71 {
2181 reg = 2181 reg = <0x71>;
2182 2182
2183 xbar_ 2183 xbar_ope1_out_ep: endpoint {
2184 2184 remote-endpoint = <&ope1_cif_out_ep>;
2185 }; 2185 };
2186 }; 2186 };
2187 }; 2187 };
2188 }; 2188 };
2189 2189
2190 dma-controller@2930000 { 2190 dma-controller@2930000 {
2191 status = "okay"; 2191 status = "okay";
2192 }; 2192 };
2193 2193
2194 interrupt-controller@2a40000 2194 interrupt-controller@2a40000 {
2195 status = "okay"; 2195 status = "okay";
2196 }; 2196 };
2197 }; 2197 };
2198 2198
2199 i2c@3160000 { 2199 i2c@3160000 {
2200 power-monitor@42 { 2200 power-monitor@42 {
2201 compatible = "ti,ina3 2201 compatible = "ti,ina3221";
2202 reg = <0x42>; 2202 reg = <0x42>;
2203 #address-cells = <1>; 2203 #address-cells = <1>;
2204 #size-cells = <0>; 2204 #size-cells = <0>;
2205 2205
2206 input@0 { 2206 input@0 {
2207 reg = <0x0>; 2207 reg = <0x0>;
2208 label = "VDD_ 2208 label = "VDD_MUX";
2209 shunt-resisto 2209 shunt-resistor-micro-ohms = <20000>;
2210 }; 2210 };
2211 2211
2212 input@1 { 2212 input@1 {
2213 reg = <0x1>; 2213 reg = <0x1>;
2214 label = "VDD_ 2214 label = "VDD_5V0_IO_SYS";
2215 shunt-resisto 2215 shunt-resistor-micro-ohms = <5000>;
2216 }; 2216 };
2217 2217
2218 input@2 { 2218 input@2 {
2219 reg = <0x2>; 2219 reg = <0x2>;
2220 label = "VDD_ 2220 label = "VDD_3V3_SYS";
2221 shunt-resisto 2221 shunt-resistor-micro-ohms = <10000>;
2222 }; 2222 };
2223 }; 2223 };
2224 2224
2225 power-monitor@43 { 2225 power-monitor@43 {
2226 compatible = "ti,ina3 2226 compatible = "ti,ina3221";
2227 reg = <0x43>; 2227 reg = <0x43>;
2228 #address-cells = <1>; 2228 #address-cells = <1>;
2229 #size-cells = <0>; 2229 #size-cells = <0>;
2230 2230
2231 input@0 { 2231 input@0 {
2232 reg = <0x0>; 2232 reg = <0x0>;
2233 label = "VDD_ 2233 label = "VDD_3V3_IO_SLP";
2234 shunt-resisto 2234 shunt-resistor-micro-ohms = <10000>;
2235 }; 2235 };
2236 2236
2237 input@1 { 2237 input@1 {
2238 reg = <0x1>; 2238 reg = <0x1>;
2239 label = "VDD_ 2239 label = "VDD_1V8_IO";
2240 shunt-resisto 2240 shunt-resistor-micro-ohms = <10000>;
2241 }; 2241 };
2242 2242
2243 input@2 { 2243 input@2 {
2244 reg = <0x2>; 2244 reg = <0x2>;
2245 label = "VDD_ 2245 label = "VDD_M2_IN";
2246 shunt-resisto 2246 shunt-resistor-micro-ohms = <10000>;
2247 }; 2247 };
2248 }; 2248 };
2249 2249
2250 exp1: gpio@74 { 2250 exp1: gpio@74 {
2251 compatible = "ti,tca9 2251 compatible = "ti,tca9539";
2252 reg = <0x74>; 2252 reg = <0x74>;
2253 2253
2254 interrupt-parent = <& 2254 interrupt-parent = <&gpio>;
2255 interrupts = <TEGRA18 2255 interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
2256 GPIO_AC 2256 GPIO_ACTIVE_LOW>;
2257 2257
2258 #gpio-cells = <2>; 2258 #gpio-cells = <2>;
2259 gpio-controller; 2259 gpio-controller;
2260 2260
2261 vcc-supply = <&vdd_3v 2261 vcc-supply = <&vdd_3v3_sys>;
2262 }; 2262 };
2263 2263
2264 exp2: gpio@77 { 2264 exp2: gpio@77 {
2265 compatible = "ti,tca9 2265 compatible = "ti,tca9539";
2266 reg = <0x77>; 2266 reg = <0x77>;
2267 2267
2268 interrupt-parent = <& 2268 interrupt-parent = <&gpio>;
2269 interrupts = <TEGRA18 2269 interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
2270 GPIO_AC 2270 GPIO_ACTIVE_LOW>;
2271 2271
2272 #gpio-cells = <2>; 2272 #gpio-cells = <2>;
2273 gpio-controller; 2273 gpio-controller;
2274 2274
2275 vcc-supply = <&vdd_1v 2275 vcc-supply = <&vdd_1v8>;
2276 }; 2276 };
2277 }; 2277 };
2278 2278
2279 /* SDMMC1 (SD/MMC) */ 2279 /* SDMMC1 (SD/MMC) */
2280 mmc@3400000 { 2280 mmc@3400000 {
2281 status = "okay"; 2281 status = "okay";
2282 2282
2283 vmmc-supply = <&vdd_sd>; 2283 vmmc-supply = <&vdd_sd>;
2284 }; 2284 };
2285 2285
2286 sata@3507000 { 2286 sata@3507000 {
2287 status = "okay"; 2287 status = "okay";
2288 }; 2288 };
2289 2289
2290 hda@3510000 { 2290 hda@3510000 {
2291 nvidia,model = "NVIDIA Jetson 2291 nvidia,model = "NVIDIA Jetson TX2 HDA";
2292 status = "okay"; 2292 status = "okay";
2293 }; 2293 };
2294 2294
2295 padctl@3520000 { 2295 padctl@3520000 {
2296 status = "okay"; 2296 status = "okay";
2297 2297
2298 avdd-pll-erefeut-supply = <&v 2298 avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
2299 avdd-usb-supply = <&vdd_3v3_s 2299 avdd-usb-supply = <&vdd_3v3_sys>;
2300 vclamp-usb-supply = <&vdd_1v8 2300 vclamp-usb-supply = <&vdd_1v8>;
2301 vddio-hsic-supply = <&gnd>; 2301 vddio-hsic-supply = <&gnd>;
2302 2302
2303 pads { 2303 pads {
2304 usb2 { 2304 usb2 {
2305 status = "oka 2305 status = "okay";
2306 2306
2307 lanes { 2307 lanes {
2308 micro 2308 micro_b: usb2-0 {
2309 2309 nvidia,function = "xusb";
2310 2310 status = "okay";
2311 }; 2311 };
2312 2312
2313 usb2- 2313 usb2-1 {
2314 2314 nvidia,function = "xusb";
2315 2315 status = "okay";
2316 }; 2316 };
2317 2317
2318 usb2- 2318 usb2-2 {
2319 2319 nvidia,function = "xusb";
2320 2320 status = "okay";
2321 }; 2321 };
2322 }; 2322 };
2323 }; 2323 };
2324 2324
2325 usb3 { 2325 usb3 {
2326 status = "oka 2326 status = "okay";
2327 2327
2328 lanes { 2328 lanes {
2329 usb3- 2329 usb3-0 {
2330 2330 nvidia,function = "xusb";
2331 2331 status = "okay";
2332 }; 2332 };
2333 2333
2334 usb3- 2334 usb3-1 {
2335 2335 nvidia,function = "xusb";
2336 2336 status = "okay";
2337 }; 2337 };
2338 2338
2339 usb3- 2339 usb3-2 {
2340 2340 nvidia,function = "xusb";
2341 2341 status = "okay";
2342 }; 2342 };
2343 }; 2343 };
2344 }; 2344 };
2345 }; 2345 };
2346 2346
2347 ports { 2347 ports {
2348 usb2-0 { 2348 usb2-0 {
2349 status = "oka 2349 status = "okay";
2350 mode = "otg"; 2350 mode = "otg";
2351 vbus-supply = 2351 vbus-supply = <&vdd_usb0>;
2352 usb-role-swit 2352 usb-role-switch;
2353 2353
2354 connector { 2354 connector {
2355 compa 2355 compatible = "gpio-usb-b-connector",
2356 2356 "usb-b-connector";
2357 label 2357 label = "micro-USB";
2358 type 2358 type = "micro";
2359 vbus- 2359 vbus-gpios = <&gpio
2360 2360 TEGRA186_MAIN_GPIO(X, 7)
2361 2361 GPIO_ACTIVE_LOW>;
2362 id-gp 2362 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
2363 }; 2363 };
2364 }; 2364 };
2365 2365
2366 usb2-1 { 2366 usb2-1 {
2367 status = "oka 2367 status = "okay";
2368 mode = "host" 2368 mode = "host";
2369 2369
2370 vbus-supply = 2370 vbus-supply = <&vdd_usb1>;
2371 }; 2371 };
2372 2372
2373 usb3-0 { 2373 usb3-0 {
2374 nvidia,usb2-c 2374 nvidia,usb2-companion = <1>;
2375 vbus-supply = 2375 vbus-supply = <&vdd_usb1>;
2376 status = "oka 2376 status = "okay";
2377 }; 2377 };
2378 }; 2378 };
2379 }; 2379 };
2380 2380
2381 usb@3530000 { 2381 usb@3530000 {
2382 status = "okay"; 2382 status = "okay";
2383 2383
2384 phys = <&{/padctl@3520000/pads 2384 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
2385 <&{/padctl@3520000/pads 2385 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
2386 <&{/padctl@3520000/pads 2386 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
2387 phy-names = "usb2-0", "usb2-1 2387 phy-names = "usb2-0", "usb2-1", "usb3-0";
2388 }; 2388 };
2389 2389
2390 usb@3550000 { 2390 usb@3550000 {
2391 status = "okay"; 2391 status = "okay";
2392 2392
2393 phys = <µ_b>; 2393 phys = <µ_b>;
2394 phy-names = "usb2-0"; 2394 phy-names = "usb2-0";
2395 }; 2395 };
2396 2396
2397 i2c@c250000 { 2397 i2c@c250000 {
2398 /* carrier board ID EEPROM */ 2398 /* carrier board ID EEPROM */
2399 eeprom@57 { 2399 eeprom@57 {
2400 compatible = "atmel,2 2400 compatible = "atmel,24c02";
2401 reg = <0x57>; 2401 reg = <0x57>;
2402 2402
2403 label = "system"; 2403 label = "system";
2404 vcc-supply = <&vdd_1v 2404 vcc-supply = <&vdd_1v8>;
2405 address-width = <8>; 2405 address-width = <8>;
2406 pagesize = <8>; 2406 pagesize = <8>;
2407 size = <256>; 2407 size = <256>;
2408 read-only; 2408 read-only;
2409 }; 2409 };
2410 }; 2410 };
2411 2411
2412 pcie@10003000 { 2412 pcie@10003000 {
2413 status = "okay"; 2413 status = "okay";
2414 2414
2415 dvdd-pex-supply = <&vdd_pex>; 2415 dvdd-pex-supply = <&vdd_pex>;
2416 hvdd-pex-pll-supply = <&vdd_1 2416 hvdd-pex-pll-supply = <&vdd_1v8>;
2417 hvdd-pex-supply = <&vdd_1v8>; 2417 hvdd-pex-supply = <&vdd_1v8>;
2418 vddio-pexctl-aud-supply = <&v 2418 vddio-pexctl-aud-supply = <&vdd_1v8>;
2419 2419
2420 pci@1,0 { 2420 pci@1,0 {
2421 nvidia,num-lanes = <4 2421 nvidia,num-lanes = <4>;
2422 status = "okay"; 2422 status = "okay";
2423 }; 2423 };
2424 2424
2425 pci@2,0 { 2425 pci@2,0 {
2426 nvidia,num-lanes = <0 2426 nvidia,num-lanes = <0>;
2427 status = "disabled"; 2427 status = "disabled";
2428 }; 2428 };
2429 2429
2430 pci@3,0 { 2430 pci@3,0 {
2431 nvidia,num-lanes = <1 2431 nvidia,num-lanes = <1>;
2432 status = "disabled"; 2432 status = "disabled";
2433 }; 2433 };
2434 }; 2434 };
2435 2435
2436 host1x@13e00000 { 2436 host1x@13e00000 {
2437 status = "okay"; 2437 status = "okay";
2438 2438
2439 dpaux@15040000 { 2439 dpaux@15040000 {
2440 status = "okay"; 2440 status = "okay";
2441 }; 2441 };
2442 2442
2443 display-hub@15200000 { 2443 display-hub@15200000 {
2444 status = "okay"; 2444 status = "okay";
2445 }; 2445 };
2446 2446
2447 dsi@15300000 { 2447 dsi@15300000 {
2448 status = "disabled"; 2448 status = "disabled";
2449 }; 2449 };
2450 2450
2451 /* DP on E3320 */ 2451 /* DP on E3320 */
2452 sor@15540000 { 2452 sor@15540000 {
2453 status = "okay"; 2453 status = "okay";
2454 2454
2455 avdd-io-hdmi-dp-suppl 2455 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2456 vdd-hdmi-dp-pll-suppl 2456 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2457 2457
2458 nvidia,dpaux = <&dpau 2458 nvidia,dpaux = <&dpaux>;
2459 }; 2459 };
2460 2460
2461 sor@15580000 { 2461 sor@15580000 {
2462 status = "okay"; 2462 status = "okay";
2463 2463
2464 avdd-io-hdmi-dp-suppl 2464 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2465 vdd-hdmi-dp-pll-suppl 2465 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2466 hdmi-supply = <&vdd_h 2466 hdmi-supply = <&vdd_hdmi>;
2467 2467
2468 nvidia,ddc-i2c-bus = 2468 nvidia,ddc-i2c-bus = <&ddc>;
2469 nvidia,hpd-gpio = <&g 2469 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
2470 2470 GPIO_ACTIVE_LOW>;
2471 }; 2471 };
2472 2472
2473 dpaux@155c0000 { 2473 dpaux@155c0000 {
2474 status = "okay"; 2474 status = "okay";
2475 }; 2475 };
2476 }; 2476 };
2477 2477
2478 gpio-keys { 2478 gpio-keys {
2479 compatible = "gpio-keys"; 2479 compatible = "gpio-keys";
2480 2480
2481 key-power { 2481 key-power {
2482 label = "Power"; 2482 label = "Power";
2483 gpios = <&gpio_aon TE 2483 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
2484 GP 2484 GPIO_ACTIVE_LOW>;
2485 linux,input-type = <E 2485 linux,input-type = <EV_KEY>;
2486 linux,code = <KEY_POW 2486 linux,code = <KEY_POWER>;
2487 debounce-interval = < 2487 debounce-interval = <10>;
2488 wakeup-event-action = 2488 wakeup-event-action = <EV_ACT_ASSERTED>;
2489 wakeup-source; 2489 wakeup-source;
2490 }; 2490 };
2491 2491
2492 key-volume-down { 2492 key-volume-down {
2493 label = "Volume Down" 2493 label = "Volume Down";
2494 gpios = <&gpio_aon TE 2494 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
2495 GP 2495 GPIO_ACTIVE_LOW>;
2496 linux,input-type = <E 2496 linux,input-type = <EV_KEY>;
2497 linux,code = <KEY_VOL 2497 linux,code = <KEY_VOLUMEDOWN>;
2498 debounce-interval = < 2498 debounce-interval = <10>;
2499 }; 2499 };
2500 2500
2501 key-volume-up { 2501 key-volume-up {
2502 label = "Volume Up"; 2502 label = "Volume Up";
2503 gpios = <&gpio_aon TE 2503 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
2504 GP 2504 GPIO_ACTIVE_LOW>;
2505 linux,input-type = <E 2505 linux,input-type = <EV_KEY>;
2506 linux,code = <KEY_VOL 2506 linux,code = <KEY_VOLUMEUP>;
2507 debounce-interval = < 2507 debounce-interval = <10>;
2508 }; 2508 };
2509 }; 2509 };
2510 2510
2511 vdd_sd: regulator-vdd-sd { 2511 vdd_sd: regulator-vdd-sd {
2512 compatible = "regulator-fixed 2512 compatible = "regulator-fixed";
2513 regulator-name = "SD_CARD_SW_ 2513 regulator-name = "SD_CARD_SW_PWR";
2514 regulator-min-microvolt = <33 2514 regulator-min-microvolt = <3300000>;
2515 regulator-max-microvolt = <33 2515 regulator-max-microvolt = <3300000>;
2516 2516
2517 gpio = <&gpio TEGRA186_MAIN_G 2517 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
2518 enable-active-high; 2518 enable-active-high;
2519 2519
2520 vin-supply = <&vdd_3v3_sys>; 2520 vin-supply = <&vdd_3v3_sys>;
2521 }; 2521 };
2522 2522
2523 vdd_hdmi: regulator-vdd-hdmi { 2523 vdd_hdmi: regulator-vdd-hdmi {
2524 compatible = "regulator-fixed 2524 compatible = "regulator-fixed";
2525 regulator-name = "VDD_HDMI_5V 2525 regulator-name = "VDD_HDMI_5V0";
2526 regulator-min-microvolt = <50 2526 regulator-min-microvolt = <5000000>;
2527 regulator-max-microvolt = <50 2527 regulator-max-microvolt = <5000000>;
2528 2528
2529 gpio = <&exp1 14 GPIO_ACTIVE_ 2529 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
2530 enable-active-high; 2530 enable-active-high;
2531 2531
2532 vin-supply = <&vdd_5v0_sys>; 2532 vin-supply = <&vdd_5v0_sys>;
2533 }; 2533 };
2534 2534
2535 vdd_usb0: regulator-vdd-usb0 { 2535 vdd_usb0: regulator-vdd-usb0 {
2536 compatible = "regulator-fixed 2536 compatible = "regulator-fixed";
2537 regulator-name = "VDD_USB0"; 2537 regulator-name = "VDD_USB0";
2538 regulator-min-microvolt = <50 2538 regulator-min-microvolt = <5000000>;
2539 regulator-max-microvolt = <50 2539 regulator-max-microvolt = <5000000>;
2540 2540
2541 gpio = <&gpio TEGRA186_MAIN_G 2541 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
2542 enable-active-high; 2542 enable-active-high;
2543 2543
2544 vin-supply = <&vdd_5v0_sys>; 2544 vin-supply = <&vdd_5v0_sys>;
2545 }; 2545 };
2546 2546
2547 vdd_usb1: regulator-vdd-usb1 { 2547 vdd_usb1: regulator-vdd-usb1 {
2548 compatible = "regulator-fixed 2548 compatible = "regulator-fixed";
2549 regulator-name = "VDD_USB1"; 2549 regulator-name = "VDD_USB1";
2550 regulator-min-microvolt = <50 2550 regulator-min-microvolt = <5000000>;
2551 regulator-max-microvolt = <50 2551 regulator-max-microvolt = <5000000>;
2552 2552
2553 gpio = <&gpio TEGRA186_MAIN_G 2553 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
2554 enable-active-high; 2554 enable-active-high;
2555 2555
2556 vin-supply = <&vdd_5v0_sys>; 2556 vin-supply = <&vdd_5v0_sys>;
2557 }; 2557 };
2558 2558
2559 sound { 2559 sound {
2560 compatible = "nvidia,tegra186 2560 compatible = "nvidia,tegra186-audio-graph-card";
2561 status = "okay"; 2561 status = "okay";
2562 2562
2563 dais = /* FE */ 2563 dais = /* FE */
2564 <&admaif0_port>, <&adm 2564 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
2565 <&admaif4_port>, <&adm 2565 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
2566 <&admaif8_port>, <&adm 2566 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
2567 <&admaif12_port>, <&ad 2567 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
2568 <&admaif16_port>, <&ad 2568 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
2569 /* Router */ 2569 /* Router */
2570 <&xbar_i2s1_port>, <&x 2570 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
2571 <&xbar_i2s4_port>, <&x 2571 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
2572 <&xbar_dmic1_port>, <& 2572 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
2573 <&xbar_dspk1_port>, <& 2573 <&xbar_dspk1_port>, <&xbar_dspk2_port>,
2574 <&xbar_sfc1_in_port>, 2574 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
2575 <&xbar_sfc3_in_port>, 2575 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
2576 <&xbar_mvc1_in_port>, 2576 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
2577 <&xbar_amx1_in1_port>, 2577 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
2578 <&xbar_amx1_in3_port>, 2578 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
2579 <&xbar_amx2_in1_port>, 2579 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
2580 <&xbar_amx2_in3_port>, 2580 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
2581 <&xbar_amx3_in1_port>, 2581 <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
2582 <&xbar_amx3_in3_port>, 2582 <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
2583 <&xbar_amx4_in1_port>, 2583 <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
2584 <&xbar_amx4_in3_port>, 2584 <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
2585 <&xbar_adx1_in_port>, 2585 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
2586 <&xbar_adx3_in_port>, 2586 <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
2587 <&xbar_mixer_in1_port> 2587 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
2588 <&xbar_mixer_in3_port> 2588 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
2589 <&xbar_mixer_in5_port> 2589 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
2590 <&xbar_mixer_in7_port> 2590 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
2591 <&xbar_mixer_in9_port> 2591 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
2592 <&xbar_asrc_in1_port>, 2592 <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
2593 <&xbar_asrc_in3_port>, 2593 <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
2594 <&xbar_asrc_in5_port>, 2594 <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
2595 <&xbar_asrc_in7_port>, 2595 <&xbar_asrc_in7_port>,
2596 <&xbar_ope1_in_port>, 2596 <&xbar_ope1_in_port>,
2597 /* HW accelerators */ 2597 /* HW accelerators */
2598 <&sfc1_out_port>, <&sf 2598 <&sfc1_out_port>, <&sfc2_out_port>,
2599 <&sfc3_out_port>, <&sf 2599 <&sfc3_out_port>, <&sfc4_out_port>,
2600 <&mvc1_out_port>, <&mv 2600 <&mvc1_out_port>, <&mvc2_out_port>,
2601 <&amx1_out_port>, <&am 2601 <&amx1_out_port>, <&amx2_out_port>,
2602 <&amx3_out_port>, <&am 2602 <&amx3_out_port>, <&amx4_out_port>,
2603 <&adx1_out1_port>, <&a 2603 <&adx1_out1_port>, <&adx1_out2_port>,
2604 <&adx1_out3_port>, <&a 2604 <&adx1_out3_port>, <&adx1_out4_port>,
2605 <&adx2_out1_port>, <&a 2605 <&adx2_out1_port>, <&adx2_out2_port>,
2606 <&adx2_out3_port>, <&a 2606 <&adx2_out3_port>, <&adx2_out4_port>,
2607 <&adx3_out1_port>, <&a 2607 <&adx3_out1_port>, <&adx3_out2_port>,
2608 <&adx3_out3_port>, <&a 2608 <&adx3_out3_port>, <&adx3_out4_port>,
2609 <&adx4_out1_port>, <&a 2609 <&adx4_out1_port>, <&adx4_out2_port>,
2610 <&adx4_out3_port>, <&a 2610 <&adx4_out3_port>, <&adx4_out4_port>,
2611 <&mixer_out1_port>, <& 2611 <&mixer_out1_port>, <&mixer_out2_port>,
2612 <&mixer_out3_port>, <& 2612 <&mixer_out3_port>, <&mixer_out4_port>,
2613 <&mixer_out5_port>, 2613 <&mixer_out5_port>,
2614 <&asrc_out1_port>, <&a 2614 <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
2615 <&asrc_out4_port>, <&a 2615 <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
2616 <&ope1_out_port>, 2616 <&ope1_out_port>,
2617 /* I/O */ 2617 /* I/O */
2618 <&i2s1_port>, <&i2s2_p 2618 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
2619 <&i2s5_port>, <&i2s6_p 2619 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
2620 <&dmic3_port>, <&dspk1 2620 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
2621 2621
2622 label = "NVIDIA Jetson TX2 AP 2622 label = "NVIDIA Jetson TX2 APE";
2623 }; 2623 };
2624 }; 2624 };
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