1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/input/linux-event-codes.
5 #include <dt-bindings/input/gpio-keys.h>
6
7 #include "tegra186-p3310.dtsi"
8
9 / {
10 model = "NVIDIA Jetson TX2 Developer K
11 compatible = "nvidia,p2771-0000", "nvi
12
13 aconnect@2900000 {
14 status = "okay";
15
16 ahub@2900800 {
17 status = "okay";
18
19 i2s@2901000 {
20 status = "okay
21
22 ports {
23 #addre
24 #size-
25
26 port@0
27
28
29
30
31
32 };
33
34 i2s1_p
35
36
37
38
39
40
41 };
42 };
43 };
44
45 i2s@2901100 {
46 status = "okay
47
48 ports {
49 #addre
50 #size-
51
52 port@0
53
54
55
56
57
58 };
59
60 i2s2_p
61
62
63
64
65
66
67 };
68 };
69 };
70
71 i2s@2901200 {
72 status = "okay
73
74 ports {
75 #addre
76 #size-
77
78 port@0
79
80
81
82
83
84 };
85
86 i2s3_p
87
88
89
90
91
92
93 };
94 };
95 };
96
97 i2s@2901300 {
98 status = "okay
99
100 ports {
101 #addre
102 #size-
103
104 port@0
105
106
107
108
109
110 };
111
112 i2s4_p
113
114
115
116
117
118
119 };
120 };
121 };
122
123 i2s@2901400 {
124 status = "okay
125
126 ports {
127 #addre
128 #size-
129
130 port@0
131
132
133
134
135
136 };
137
138 i2s5_p
139
140
141
142
143
144
145 };
146 };
147 };
148
149 i2s@2901500 {
150 status = "okay
151
152 ports {
153 #addre
154 #size-
155
156 port@0
157
158
159
160
161
162 };
163
164 i2s6_p
165
166
167
168
169
170
171 };
172 };
173 };
174
175 sfc@2902000 {
176 status = "okay
177
178 ports {
179 #addre
180 #size-
181
182 port@0
183
184
185
186
187
188
189 };
190
191 sfc1_o
192
193
194
195
196
197
198 };
199 };
200 };
201
202 sfc@2902200 {
203 status = "okay
204
205 ports {
206 #addre
207 #size-
208
209 port@0
210
211
212
213
214
215 };
216
217 sfc2_o
218
219
220
221
222
223 };
224 };
225 };
226
227 sfc@2902400 {
228 status = "okay
229
230 ports {
231 #addre
232 #size-
233
234 port@0
235
236
237
238
239
240 };
241
242 sfc3_o
243
244
245
246
247
248 };
249 };
250 };
251
252 sfc@2902600 {
253 status = "okay
254
255 ports {
256 #addre
257 #size-
258
259 port@0
260
261
262
263
264
265 };
266
267 sfc4_o
268
269
270
271
272
273 };
274 };
275 };
276
277 amx@2903000 {
278 status = "okay
279
280 ports {
281 #addre
282 #size-
283
284 port@0
285
286
287
288
289
290 };
291
292 port@1
293
294
295
296
297
298 };
299
300 port@2
301
302
303
304
305
306 };
307
308 port@3
309
310
311
312
313
314 };
315
316 amx1_o
317
318
319
320
321
322 };
323 };
324 };
325
326 amx@2903100 {
327 status = "okay
328
329 ports {
330 #addre
331 #size-
332
333 port@0
334
335
336
337
338
339 };
340
341 port@1
342
343
344
345
346
347 };
348
349 amx2_i
350
351
352
353
354
355 };
356
357 amx2_i
358
359
360
361
362
363 };
364
365 amx2_o
366
367
368
369
370
371 };
372 };
373 };
374
375 amx@2903200 {
376 status = "okay
377
378 ports {
379 #addre
380 #size-
381
382 port@0
383
384
385
386
387
388 };
389
390 port@1
391
392
393
394
395
396 };
397
398 port@2
399
400
401
402
403
404 };
405
406 port@3
407
408
409
410
411
412 };
413
414 amx3_o
415
416
417
418
419
420 };
421 };
422 };
423
424 amx@2903300 {
425 status = "okay
426
427 ports {
428 #addre
429 #size-
430
431 port@0
432
433
434
435
436
437 };
438
439 port@1
440
441
442
443
444
445 };
446
447 port@2
448
449
450
451
452
453 };
454
455 port@3
456
457
458
459
460
461 };
462
463 amx4_o
464
465
466
467
468
469 };
470 };
471 };
472
473 adx@2903800 {
474 status = "okay
475
476 ports {
477 #addre
478 #size-
479
480 port@0
481
482
483
484
485
486 };
487
488 adx1_o
489
490
491
492
493
494 };
495
496 adx1_o
497
498
499
500
501
502 };
503
504 adx1_o
505
506
507
508
509
510 };
511
512 adx1_o
513
514
515
516
517
518 };
519 };
520 };
521
522 adx@2903900 {
523 status = "okay
524
525 ports {
526 #addre
527 #size-
528
529 port@0
530
531
532
533
534
535 };
536
537 adx2_o
538
539
540
541
542
543 };
544
545 adx2_o
546
547
548
549
550
551 };
552
553 adx2_o
554
555
556
557
558
559 };
560
561 adx2_o
562
563
564
565
566
567 };
568 };
569 };
570
571 adx@2903a00 {
572 status = "okay
573
574 ports {
575 #addre
576 #size-
577
578 port@0
579
580
581
582
583
584 };
585
586 adx3_o
587
588
589
590
591
592 };
593
594 adx3_o
595
596
597
598
599
600 };
601
602 adx3_o
603
604
605
606
607
608 };
609
610 adx3_o
611
612
613
614
615
616 };
617 };
618 };
619
620 adx@2903b00 {
621 status = "okay
622
623 ports {
624 #addre
625 #size-
626
627 port@0
628
629
630
631
632
633 };
634
635 adx4_o
636
637
638
639
640
641 };
642
643 adx4_o
644
645
646
647
648
649 };
650
651 adx4_o
652
653
654
655
656
657 };
658
659 adx4_o
660
661
662
663
664
665 };
666 };
667 };
668
669 dmic@2904000 {
670 status = "okay
671
672 ports {
673 #addre
674 #size-
675
676 port@0
677
678
679
680
681
682 };
683
684 dmic1_
685
686
687
688
689
690 };
691 };
692 };
693
694 dmic@2904100 {
695 status = "okay
696
697 ports {
698 #addre
699 #size-
700
701 port@0
702
703
704
705
706
707 };
708
709 dmic2_
710
711
712
713
714
715 };
716 };
717 };
718
719 dmic@2904200 {
720 status = "okay
721
722 ports {
723 #addre
724 #size-
725
726 port@0
727
728
729
730
731
732 };
733
734 dmic3_
735
736
737
738
739
740 };
741 };
742 };
743
744 dspk@2905000 {
745 status = "okay
746
747 ports {
748 #addre
749 #size-
750
751 port@0
752
753
754
755
756
757 };
758
759 dspk1_
760
761
762
763
764
765 };
766 };
767 };
768
769 dspk@2905100 {
770 status = "okay
771
772 ports {
773 #addre
774 #size-
775
776 port@0
777
778
779
780
781
782 };
783
784 dspk2_
785
786
787
788
789
790 };
791 };
792 };
793
794 processing-engine@2908
795 status = "okay
796
797 ports {
798 #addre
799 #size-
800
801 port@0
802
803
804
805
806
807 };
808
809 ope1_o
810
811
812
813
814
815 };
816 };
817 };
818
819 mvc@290a000 {
820 status = "okay
821
822 ports {
823 #addre
824 #size-
825
826 port@0
827
828
829
830
831
832 };
833
834 mvc1_o
835
836
837
838
839
840 };
841 };
842 };
843
844 mvc@290a200 {
845 status = "okay
846
847 ports {
848 #addre
849 #size-
850
851 port@0
852
853
854
855
856
857 };
858
859 mvc2_o
860
861
862
863
864
865 };
866 };
867 };
868
869 amixer@290bb00 {
870 status = "okay
871
872 ports {
873 #addre
874 #size-
875
876 port@0
877
878
879
880
881
882 };
883
884 port@1
885
886
887
888
889
890 };
891
892 port@2
893
894
895
896
897
898 };
899
900 port@3
901
902
903
904
905
906 };
907
908 port@4
909
910
911
912
913
914 };
915
916 port@5
917
918
919
920
921
922 };
923
924 port@6
925
926
927
928
929
930 };
931
932 port@7
933
934
935
936
937
938 };
939
940 port@8
941
942
943
944
945
946 };
947
948 port@9
949
950
951
952
953
954 };
955
956 mixer_
957
958
959
960
961
962 };
963
964 mixer_
965
966
967
968
969
970 };
971
972 mixer_
973
974
975
976
977
978 };
979
980 mixer_
981
982
983
984
985
986 };
987
988 mixer_
989
990
991
992
993
994 };
995 };
996 };
997
998 admaif@290f000 {
999 status = "okay
1000
1001 ports {
1002 #addr
1003 #size
1004
1005 admai
1006
1007
1008
1009
1010
1011 };
1012
1013 admai
1014
1015
1016
1017
1018
1019 };
1020
1021 admai
1022
1023
1024
1025
1026
1027 };
1028
1029 admai
1030
1031
1032
1033
1034
1035 };
1036
1037 admai
1038
1039
1040
1041
1042
1043 };
1044
1045 admai
1046
1047
1048
1049
1050
1051 };
1052
1053 admai
1054
1055
1056
1057
1058
1059 };
1060
1061 admai
1062
1063
1064
1065
1066
1067 };
1068
1069 admai
1070
1071
1072
1073
1074
1075 };
1076
1077 admai
1078
1079
1080
1081
1082
1083 };
1084
1085 admai
1086
1087
1088
1089
1090
1091 };
1092
1093 admai
1094
1095
1096
1097
1098
1099 };
1100
1101 admai
1102
1103
1104
1105
1106
1107 };
1108
1109 admai
1110
1111
1112
1113
1114
1115 };
1116
1117 admai
1118
1119
1120
1121
1122
1123 };
1124
1125 admai
1126
1127
1128
1129
1130
1131 };
1132
1133 admai
1134
1135
1136
1137
1138
1139 };
1140
1141 admai
1142
1143
1144
1145
1146
1147 };
1148
1149 admai
1150
1151
1152
1153
1154
1155 };
1156
1157 admai
1158
1159
1160
1161
1162
1163 };
1164 };
1165 };
1166
1167 asrc@2910000 {
1168 status = "oka
1169
1170 ports {
1171 #addr
1172 #size
1173
1174 port@
1175
1176
1177
1178
1179
1180 };
1181
1182 port@
1183
1184
1185
1186
1187
1188 };
1189
1190 port@
1191
1192
1193
1194
1195
1196 };
1197
1198 port@
1199
1200
1201
1202
1203
1204 };
1205
1206 port@
1207
1208
1209
1210
1211
1212 };
1213
1214 port@
1215
1216
1217
1218
1219
1220 };
1221
1222 port@
1223
1224
1225
1226
1227
1228 };
1229
1230 asrc_
1231
1232
1233
1234
1235
1236 };
1237
1238 asrc_
1239
1240
1241
1242
1243
1244 };
1245
1246 asrc_
1247
1248
1249
1250
1251
1252 };
1253
1254 asrc_
1255
1256
1257
1258
1259
1260 };
1261
1262 asrc_
1263
1264
1265
1266
1267
1268 };
1269
1270 asrc_
1271
1272
1273
1274
1275
1276 };
1277 };
1278 };
1279
1280 ports {
1281 #address-cell
1282 #size-cells =
1283
1284 port@0 {
1285 reg =
1286
1287 xbar_
1288
1289 };
1290 };
1291
1292 port@1 {
1293 reg =
1294
1295 xbar_
1296
1297 };
1298 };
1299
1300 port@2 {
1301 reg =
1302
1303 xbar_
1304
1305 };
1306 };
1307
1308 port@3 {
1309 reg =
1310
1311 xbar_
1312
1313 };
1314 };
1315
1316 port@4 {
1317 reg =
1318
1319 xbar_
1320
1321 };
1322 };
1323
1324 port@5 {
1325 reg =
1326
1327 xbar_
1328
1329 };
1330 };
1331
1332 port@6 {
1333 reg =
1334
1335 xbar_
1336
1337 };
1338 };
1339
1340 port@7 {
1341 reg =
1342
1343 xbar_
1344
1345 };
1346 };
1347
1348 port@8 {
1349 reg =
1350
1351 xbar_
1352
1353 };
1354 };
1355
1356 port@9 {
1357 reg =
1358
1359 xbar_
1360
1361 };
1362 };
1363
1364 port@a {
1365 reg =
1366
1367 xbar_
1368
1369 };
1370 };
1371
1372 port@b {
1373 reg =
1374
1375 xbar_
1376
1377 };
1378 };
1379
1380 port@c {
1381 reg =
1382
1383 xbar_
1384
1385 };
1386 };
1387
1388 port@d {
1389 reg =
1390
1391 xbar_
1392
1393 };
1394 };
1395
1396 port@e {
1397 reg =
1398
1399 xbar_
1400
1401 };
1402 };
1403
1404 port@f {
1405 reg =
1406
1407 xbar_
1408
1409 };
1410 };
1411
1412 port@10 {
1413 reg =
1414
1415 xbar_
1416
1417 };
1418 };
1419
1420 port@11 {
1421 reg =
1422
1423 xbar_
1424
1425 };
1426 };
1427
1428 port@12 {
1429 reg =
1430
1431 xbar_
1432
1433 };
1434 };
1435
1436 port@13 {
1437 reg =
1438
1439 xbar_
1440
1441 };
1442 };
1443
1444 xbar_i2s1_por
1445 reg =
1446
1447 xbar_
1448
1449 };
1450 };
1451
1452 xbar_i2s2_por
1453 reg =
1454
1455 xbar_
1456
1457 };
1458 };
1459
1460 xbar_i2s3_por
1461 reg =
1462
1463 xbar_
1464
1465 };
1466 };
1467
1468 xbar_i2s4_por
1469 reg =
1470
1471 xbar_
1472
1473 };
1474 };
1475
1476 xbar_i2s5_por
1477 reg =
1478
1479 xbar_
1480
1481 };
1482 };
1483
1484 xbar_i2s6_por
1485 reg =
1486
1487 xbar_
1488
1489 };
1490 };
1491
1492 xbar_dmic1_po
1493 reg =
1494
1495 xbar_
1496
1497 };
1498 };
1499
1500 xbar_dmic2_po
1501 reg =
1502
1503 xbar_
1504
1505 };
1506 };
1507
1508 xbar_dmic3_po
1509 reg =
1510
1511 xbar_
1512
1513 };
1514 };
1515
1516 xbar_dspk1_po
1517 reg =
1518
1519 xbar_
1520
1521 };
1522 };
1523
1524 xbar_dspk2_po
1525 reg =
1526
1527 xbar_
1528
1529 };
1530 };
1531
1532 xbar_sfc1_in_
1533 reg =
1534
1535 xbar_
1536
1537 };
1538 };
1539
1540 port@21 {
1541 reg =
1542
1543 xbar_
1544
1545 };
1546 };
1547
1548 xbar_sfc2_in_
1549 reg =
1550
1551 xbar_
1552
1553 };
1554 };
1555
1556 port@23 {
1557 reg =
1558
1559 xbar_
1560
1561 };
1562 };
1563
1564 xbar_sfc3_in_
1565 reg =
1566
1567 xbar_
1568
1569 };
1570 };
1571
1572 port@25 {
1573 reg =
1574
1575 xbar_
1576
1577 };
1578 };
1579
1580 xbar_sfc4_in_
1581 reg =
1582
1583 xbar_
1584
1585 };
1586 };
1587
1588 port@27 {
1589 reg =
1590
1591 xbar_
1592
1593 };
1594 };
1595
1596 xbar_mvc1_in_
1597 reg =
1598
1599 xbar_
1600
1601 };
1602 };
1603
1604 port@29 {
1605 reg =
1606
1607 xbar_
1608
1609 };
1610 };
1611
1612 xbar_mvc2_in_
1613 reg =
1614
1615 xbar_
1616
1617 };
1618 };
1619
1620 port@2b {
1621 reg =
1622
1623 xbar_
1624
1625 };
1626 };
1627
1628 xbar_amx1_in1
1629 reg =
1630
1631 xbar_
1632
1633 };
1634 };
1635
1636 xbar_amx1_in2
1637 reg =
1638
1639 xbar_
1640
1641 };
1642 };
1643
1644 xbar_amx1_in3
1645 reg =
1646
1647 xbar_
1648
1649 };
1650 };
1651
1652 xbar_amx1_in4
1653 reg =
1654
1655 xbar_
1656
1657 };
1658 };
1659
1660 port@30 {
1661 reg =
1662
1663 xbar_
1664
1665 };
1666 };
1667
1668 xbar_amx2_in1
1669 reg =
1670
1671 xbar_
1672
1673 };
1674 };
1675
1676 xbar_amx2_in2
1677 reg =
1678
1679 xbar_
1680
1681 };
1682 };
1683
1684 xbar_amx2_in3
1685 reg =
1686
1687 xbar_
1688
1689 };
1690 };
1691
1692 xbar_amx2_in4
1693 reg =
1694
1695 xbar_
1696
1697 };
1698 };
1699
1700 port@35 {
1701 reg =
1702
1703 xbar_
1704
1705 };
1706 };
1707
1708 xbar_amx3_in1
1709 reg =
1710
1711 xbar_
1712
1713 };
1714 };
1715
1716 xbar_amx3_in2
1717 reg =
1718
1719 xbar_
1720
1721 };
1722 };
1723
1724 xbar_amx3_in3
1725 reg =
1726
1727 xbar_
1728
1729 };
1730 };
1731
1732 xbar_amx3_in4
1733 reg =
1734
1735 xbar_
1736
1737 };
1738 };
1739
1740 port@3a {
1741 reg =
1742
1743 xbar_
1744
1745 };
1746 };
1747
1748 xbar_amx4_in1
1749 reg =
1750
1751 xbar_
1752
1753 };
1754 };
1755
1756 xbar_amx4_in2
1757 reg =
1758
1759 xbar_
1760
1761 };
1762 };
1763
1764 xbar_amx4_in3
1765 reg =
1766
1767 xbar_
1768
1769 };
1770 };
1771
1772 xbar_amx4_in4
1773 reg =
1774
1775 xbar_
1776
1777 };
1778 };
1779
1780 port@3f {
1781 reg =
1782
1783 xbar_
1784
1785 };
1786 };
1787
1788 xbar_adx1_in_
1789 reg =
1790
1791 xbar_
1792
1793 };
1794 };
1795
1796 port@41 {
1797 reg =
1798
1799 xbar_
1800
1801 };
1802 };
1803
1804 port@42 {
1805 reg =
1806
1807 xbar_
1808
1809 };
1810 };
1811
1812 port@43 {
1813 reg =
1814
1815 xbar_
1816
1817 };
1818 };
1819
1820 port@44 {
1821 reg =
1822
1823 xbar_
1824
1825 };
1826 };
1827
1828 xbar_adx2_in_
1829 reg =
1830
1831 xbar_
1832
1833 };
1834 };
1835
1836 port@46 {
1837 reg =
1838
1839 xbar_
1840
1841 };
1842 };
1843
1844 port@47 {
1845 reg =
1846
1847 xbar_
1848
1849 };
1850 };
1851
1852 port@48 {
1853 reg =
1854
1855 xbar_
1856
1857 };
1858 };
1859
1860 port@49 {
1861 reg =
1862
1863 xbar_
1864
1865 };
1866 };
1867
1868 xbar_adx3_in_
1869 reg =
1870
1871 xbar_
1872
1873 };
1874 };
1875
1876 port@4b {
1877 reg =
1878
1879 xbar_
1880
1881 };
1882 };
1883
1884 port@4c {
1885 reg =
1886
1887 xbar_
1888
1889 };
1890 };
1891
1892 port@4d {
1893 reg =
1894
1895 xbar_
1896
1897 };
1898 };
1899
1900 port@4e {
1901 reg =
1902
1903 xbar_
1904
1905 };
1906 };
1907
1908 xbar_adx4_in_
1909 reg =
1910
1911 xbar_
1912
1913 };
1914 };
1915
1916 port@50 {
1917 reg =
1918
1919 xbar_
1920
1921 };
1922 };
1923
1924 port@51 {
1925 reg =
1926
1927 xbar_
1928
1929 };
1930 };
1931
1932 port@52 {
1933 reg =
1934
1935 xbar_
1936
1937 };
1938 };
1939
1940 port@53 {
1941 reg =
1942
1943 xbar_
1944
1945 };
1946 };
1947
1948 xbar_mixer_in
1949 reg =
1950
1951 xbar_
1952
1953 };
1954 };
1955
1956 xbar_mixer_in
1957 reg =
1958
1959 xbar_
1960
1961 };
1962 };
1963
1964 xbar_mixer_in
1965 reg =
1966
1967 xbar_
1968
1969 };
1970 };
1971
1972 xbar_mixer_in
1973 reg =
1974
1975 xbar_
1976
1977 };
1978 };
1979
1980 xbar_mixer_in
1981 reg =
1982
1983 xbar_
1984
1985 };
1986 };
1987
1988 xbar_mixer_in
1989 reg =
1990
1991 xbar_
1992
1993 };
1994 };
1995
1996 xbar_mixer_in
1997 reg =
1998
1999 xbar_
2000
2001 };
2002 };
2003
2004 xbar_mixer_in
2005 reg =
2006
2007 xbar_
2008
2009 };
2010 };
2011
2012 xbar_mixer_in
2013 reg =
2014
2015 xbar_
2016
2017 };
2018 };
2019
2020 xbar_mixer_in
2021 reg =
2022
2023 xbar_
2024
2025 };
2026 };
2027
2028 port@5e {
2029 reg =
2030
2031 xbar_
2032
2033 };
2034 };
2035
2036 port@5f {
2037 reg =
2038
2039 xbar_
2040
2041 };
2042 };
2043
2044 port@60 {
2045 reg =
2046
2047 xbar_
2048
2049 };
2050 };
2051
2052 port@61 {
2053 reg =
2054
2055 xbar_
2056
2057 };
2058 };
2059
2060 port@62 {
2061 reg =
2062
2063 xbar_
2064
2065 };
2066 };
2067
2068 xbar_asrc_in1
2069 reg =
2070
2071 xbar_
2072
2073 };
2074 };
2075
2076 port@64 {
2077 reg =
2078
2079 xbar_
2080
2081 };
2082 };
2083
2084 xbar_asrc_in2
2085 reg =
2086
2087 xbar_
2088
2089 };
2090 };
2091
2092 port@66 {
2093 reg =
2094
2095 xbar_
2096
2097 };
2098 };
2099
2100 xbar_asrc_in3
2101 reg =
2102
2103 xbar_
2104
2105 };
2106 };
2107
2108 port@68 {
2109 reg =
2110
2111 xbar_
2112
2113 };
2114 };
2115
2116 xbar_asrc_in4
2117 reg =
2118
2119 xbar_
2120
2121 };
2122 };
2123
2124 port@6a {
2125 reg =
2126
2127 xbar_
2128
2129 };
2130 };
2131
2132 xbar_asrc_in5
2133 reg =
2134
2135 xbar_
2136
2137 };
2138 };
2139
2140 port@6c {
2141 reg =
2142
2143 xbar_
2144
2145 };
2146 };
2147
2148 xbar_asrc_in6
2149 reg =
2150
2151 xbar_
2152
2153 };
2154 };
2155
2156 port@6e {
2157 reg =
2158
2159 xbar_
2160
2161 };
2162 };
2163
2164 xbar_asrc_in7
2165 reg =
2166
2167 xbar_
2168
2169 };
2170 };
2171
2172 xbar_ope1_in_
2173 reg =
2174
2175 xbar_
2176
2177 };
2178 };
2179
2180 port@71 {
2181 reg =
2182
2183 xbar_
2184
2185 };
2186 };
2187 };
2188 };
2189
2190 dma-controller@2930000 {
2191 status = "okay";
2192 };
2193
2194 interrupt-controller@2a40000
2195 status = "okay";
2196 };
2197 };
2198
2199 i2c@3160000 {
2200 power-monitor@42 {
2201 compatible = "ti,ina3
2202 reg = <0x42>;
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2205
2206 input@0 {
2207 reg = <0x0>;
2208 label = "VDD_
2209 shunt-resisto
2210 };
2211
2212 input@1 {
2213 reg = <0x1>;
2214 label = "VDD_
2215 shunt-resisto
2216 };
2217
2218 input@2 {
2219 reg = <0x2>;
2220 label = "VDD_
2221 shunt-resisto
2222 };
2223 };
2224
2225 power-monitor@43 {
2226 compatible = "ti,ina3
2227 reg = <0x43>;
2228 #address-cells = <1>;
2229 #size-cells = <0>;
2230
2231 input@0 {
2232 reg = <0x0>;
2233 label = "VDD_
2234 shunt-resisto
2235 };
2236
2237 input@1 {
2238 reg = <0x1>;
2239 label = "VDD_
2240 shunt-resisto
2241 };
2242
2243 input@2 {
2244 reg = <0x2>;
2245 label = "VDD_
2246 shunt-resisto
2247 };
2248 };
2249
2250 exp1: gpio@74 {
2251 compatible = "ti,tca9
2252 reg = <0x74>;
2253
2254 interrupt-parent = <&
2255 interrupts = <TEGRA18
2256 GPIO_AC
2257
2258 #gpio-cells = <2>;
2259 gpio-controller;
2260
2261 vcc-supply = <&vdd_3v
2262 };
2263
2264 exp2: gpio@77 {
2265 compatible = "ti,tca9
2266 reg = <0x77>;
2267
2268 interrupt-parent = <&
2269 interrupts = <TEGRA18
2270 GPIO_AC
2271
2272 #gpio-cells = <2>;
2273 gpio-controller;
2274
2275 vcc-supply = <&vdd_1v
2276 };
2277 };
2278
2279 /* SDMMC1 (SD/MMC) */
2280 mmc@3400000 {
2281 status = "okay";
2282
2283 vmmc-supply = <&vdd_sd>;
2284 };
2285
2286 sata@3507000 {
2287 status = "okay";
2288 };
2289
2290 hda@3510000 {
2291 nvidia,model = "NVIDIA Jetson
2292 status = "okay";
2293 };
2294
2295 padctl@3520000 {
2296 status = "okay";
2297
2298 avdd-pll-erefeut-supply = <&v
2299 avdd-usb-supply = <&vdd_3v3_s
2300 vclamp-usb-supply = <&vdd_1v8
2301 vddio-hsic-supply = <&gnd>;
2302
2303 pads {
2304 usb2 {
2305 status = "oka
2306
2307 lanes {
2308 micro
2309
2310
2311 };
2312
2313 usb2-
2314
2315
2316 };
2317
2318 usb2-
2319
2320
2321 };
2322 };
2323 };
2324
2325 usb3 {
2326 status = "oka
2327
2328 lanes {
2329 usb3-
2330
2331
2332 };
2333
2334 usb3-
2335
2336
2337 };
2338
2339 usb3-
2340
2341
2342 };
2343 };
2344 };
2345 };
2346
2347 ports {
2348 usb2-0 {
2349 status = "oka
2350 mode = "otg";
2351 vbus-supply =
2352 usb-role-swit
2353
2354 connector {
2355 compa
2356
2357 label
2358 type
2359 vbus-
2360
2361
2362 id-gp
2363 };
2364 };
2365
2366 usb2-1 {
2367 status = "oka
2368 mode = "host"
2369
2370 vbus-supply =
2371 };
2372
2373 usb3-0 {
2374 nvidia,usb2-c
2375 vbus-supply =
2376 status = "oka
2377 };
2378 };
2379 };
2380
2381 usb@3530000 {
2382 status = "okay";
2383
2384 phys = <&{/padctl@3520000/pads
2385 <&{/padctl@3520000/pads
2386 <&{/padctl@3520000/pads
2387 phy-names = "usb2-0", "usb2-1
2388 };
2389
2390 usb@3550000 {
2391 status = "okay";
2392
2393 phys = <µ_b>;
2394 phy-names = "usb2-0";
2395 };
2396
2397 i2c@c250000 {
2398 /* carrier board ID EEPROM */
2399 eeprom@57 {
2400 compatible = "atmel,2
2401 reg = <0x57>;
2402
2403 label = "system";
2404 vcc-supply = <&vdd_1v
2405 address-width = <8>;
2406 pagesize = <8>;
2407 size = <256>;
2408 read-only;
2409 };
2410 };
2411
2412 pcie@10003000 {
2413 status = "okay";
2414
2415 dvdd-pex-supply = <&vdd_pex>;
2416 hvdd-pex-pll-supply = <&vdd_1
2417 hvdd-pex-supply = <&vdd_1v8>;
2418 vddio-pexctl-aud-supply = <&v
2419
2420 pci@1,0 {
2421 nvidia,num-lanes = <4
2422 status = "okay";
2423 };
2424
2425 pci@2,0 {
2426 nvidia,num-lanes = <0
2427 status = "disabled";
2428 };
2429
2430 pci@3,0 {
2431 nvidia,num-lanes = <1
2432 status = "disabled";
2433 };
2434 };
2435
2436 host1x@13e00000 {
2437 status = "okay";
2438
2439 dpaux@15040000 {
2440 status = "okay";
2441 };
2442
2443 display-hub@15200000 {
2444 status = "okay";
2445 };
2446
2447 dsi@15300000 {
2448 status = "disabled";
2449 };
2450
2451 /* DP on E3320 */
2452 sor@15540000 {
2453 status = "okay";
2454
2455 avdd-io-hdmi-dp-suppl
2456 vdd-hdmi-dp-pll-suppl
2457
2458 nvidia,dpaux = <&dpau
2459 };
2460
2461 sor@15580000 {
2462 status = "okay";
2463
2464 avdd-io-hdmi-dp-suppl
2465 vdd-hdmi-dp-pll-suppl
2466 hdmi-supply = <&vdd_h
2467
2468 nvidia,ddc-i2c-bus =
2469 nvidia,hpd-gpio = <&g
2470
2471 };
2472
2473 dpaux@155c0000 {
2474 status = "okay";
2475 };
2476 };
2477
2478 gpio-keys {
2479 compatible = "gpio-keys";
2480
2481 key-power {
2482 label = "Power";
2483 gpios = <&gpio_aon TE
2484 GP
2485 linux,input-type = <E
2486 linux,code = <KEY_POW
2487 debounce-interval = <
2488 wakeup-event-action =
2489 wakeup-source;
2490 };
2491
2492 key-volume-down {
2493 label = "Volume Down"
2494 gpios = <&gpio_aon TE
2495 GP
2496 linux,input-type = <E
2497 linux,code = <KEY_VOL
2498 debounce-interval = <
2499 };
2500
2501 key-volume-up {
2502 label = "Volume Up";
2503 gpios = <&gpio_aon TE
2504 GP
2505 linux,input-type = <E
2506 linux,code = <KEY_VOL
2507 debounce-interval = <
2508 };
2509 };
2510
2511 vdd_sd: regulator-vdd-sd {
2512 compatible = "regulator-fixed
2513 regulator-name = "SD_CARD_SW_
2514 regulator-min-microvolt = <33
2515 regulator-max-microvolt = <33
2516
2517 gpio = <&gpio TEGRA186_MAIN_G
2518 enable-active-high;
2519
2520 vin-supply = <&vdd_3v3_sys>;
2521 };
2522
2523 vdd_hdmi: regulator-vdd-hdmi {
2524 compatible = "regulator-fixed
2525 regulator-name = "VDD_HDMI_5V
2526 regulator-min-microvolt = <50
2527 regulator-max-microvolt = <50
2528
2529 gpio = <&exp1 14 GPIO_ACTIVE_
2530 enable-active-high;
2531
2532 vin-supply = <&vdd_5v0_sys>;
2533 };
2534
2535 vdd_usb0: regulator-vdd-usb0 {
2536 compatible = "regulator-fixed
2537 regulator-name = "VDD_USB0";
2538 regulator-min-microvolt = <50
2539 regulator-max-microvolt = <50
2540
2541 gpio = <&gpio TEGRA186_MAIN_G
2542 enable-active-high;
2543
2544 vin-supply = <&vdd_5v0_sys>;
2545 };
2546
2547 vdd_usb1: regulator-vdd-usb1 {
2548 compatible = "regulator-fixed
2549 regulator-name = "VDD_USB1";
2550 regulator-min-microvolt = <50
2551 regulator-max-microvolt = <50
2552
2553 gpio = <&gpio TEGRA186_MAIN_G
2554 enable-active-high;
2555
2556 vin-supply = <&vdd_5v0_sys>;
2557 };
2558
2559 sound {
2560 compatible = "nvidia,tegra186
2561 status = "okay";
2562
2563 dais = /* FE */
2564 <&admaif0_port>, <&adm
2565 <&admaif4_port>, <&adm
2566 <&admaif8_port>, <&adm
2567 <&admaif12_port>, <&ad
2568 <&admaif16_port>, <&ad
2569 /* Router */
2570 <&xbar_i2s1_port>, <&x
2571 <&xbar_i2s4_port>, <&x
2572 <&xbar_dmic1_port>, <&
2573 <&xbar_dspk1_port>, <&
2574 <&xbar_sfc1_in_port>,
2575 <&xbar_sfc3_in_port>,
2576 <&xbar_mvc1_in_port>,
2577 <&xbar_amx1_in1_port>,
2578 <&xbar_amx1_in3_port>,
2579 <&xbar_amx2_in1_port>,
2580 <&xbar_amx2_in3_port>,
2581 <&xbar_amx3_in1_port>,
2582 <&xbar_amx3_in3_port>,
2583 <&xbar_amx4_in1_port>,
2584 <&xbar_amx4_in3_port>,
2585 <&xbar_adx1_in_port>,
2586 <&xbar_adx3_in_port>,
2587 <&xbar_mixer_in1_port>
2588 <&xbar_mixer_in3_port>
2589 <&xbar_mixer_in5_port>
2590 <&xbar_mixer_in7_port>
2591 <&xbar_mixer_in9_port>
2592 <&xbar_asrc_in1_port>,
2593 <&xbar_asrc_in3_port>,
2594 <&xbar_asrc_in5_port>,
2595 <&xbar_asrc_in7_port>,
2596 <&xbar_ope1_in_port>,
2597 /* HW accelerators */
2598 <&sfc1_out_port>, <&sf
2599 <&sfc3_out_port>, <&sf
2600 <&mvc1_out_port>, <&mv
2601 <&amx1_out_port>, <&am
2602 <&amx3_out_port>, <&am
2603 <&adx1_out1_port>, <&a
2604 <&adx1_out3_port>, <&a
2605 <&adx2_out1_port>, <&a
2606 <&adx2_out3_port>, <&a
2607 <&adx3_out1_port>, <&a
2608 <&adx3_out3_port>, <&a
2609 <&adx4_out1_port>, <&a
2610 <&adx4_out3_port>, <&a
2611 <&mixer_out1_port>, <&
2612 <&mixer_out3_port>, <&
2613 <&mixer_out5_port>,
2614 <&asrc_out1_port>, <&a
2615 <&asrc_out4_port>, <&a
2616 <&ope1_out_port>,
2617 /* I/O */
2618 <&i2s1_port>, <&i2s2_p
2619 <&i2s5_port>, <&i2s6_p
2620 <&dmic3_port>, <&dspk1
2621
2622 label = "NVIDIA Jetson TX2 AP
2623 };
2624 };
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