1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/linux-event-codes. 4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/gpio-keys.h>
6 6
7 #include "tegra186-p3310.dtsi" 7 #include "tegra186-p3310.dtsi"
8 8
9 / { 9 / {
10 model = "NVIDIA Jetson TX2 Developer K 10 model = "NVIDIA Jetson TX2 Developer Kit";
11 compatible = "nvidia,p2771-0000", "nvi 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
12 12
13 aconnect@2900000 { 13 aconnect@2900000 {
14 status = "okay"; 14 status = "okay";
15 15
16 ahub@2900800 { !! 16 dma-controller@2930000 {
17 status = "okay"; 17 status = "okay";
>> 18 };
18 19
19 i2s@2901000 { !! 20 interrupt-controller@2a40000 {
20 status = "okay !! 21 status = "okay";
21 !! 22 };
22 ports { <<
23 #addre <<
24 #size- <<
25 <<
26 port@0 <<
27 <<
28 <<
29 <<
30 <<
31 <<
32 }; <<
33 <<
34 i2s1_p <<
35 <<
36 <<
37 <<
38 <<
39 <<
40 <<
41 }; <<
42 }; <<
43 }; <<
44 <<
45 i2s@2901100 { <<
46 status = "okay <<
47 <<
48 ports { <<
49 #addre <<
50 #size- <<
51 <<
52 port@0 <<
53 <<
54 <<
55 <<
56 <<
57 <<
58 }; <<
59 <<
60 i2s2_p <<
61 <<
62 <<
63 <<
64 <<
65 <<
66 <<
67 }; <<
68 }; <<
69 }; <<
70 <<
71 i2s@2901200 { <<
72 status = "okay <<
73 <<
74 ports { <<
75 #addre <<
76 #size- <<
77 <<
78 port@0 <<
79 <<
80 <<
81 <<
82 <<
83 <<
84 }; <<
85 <<
86 i2s3_p <<
87 <<
88 <<
89 <<
90 <<
91 <<
92 <<
93 }; <<
94 }; <<
95 }; <<
96 <<
97 i2s@2901300 { <<
98 status = "okay <<
99 <<
100 ports { <<
101 #addre <<
102 #size- <<
103 <<
104 port@0 <<
105 <<
106 <<
107 <<
108 <<
109 <<
110 }; <<
111 <<
112 i2s4_p <<
113 <<
114 <<
115 <<
116 <<
117 <<
118 <<
119 }; <<
120 }; <<
121 }; <<
122 <<
123 i2s@2901400 { <<
124 status = "okay <<
125 <<
126 ports { <<
127 #addre <<
128 #size- <<
129 <<
130 port@0 <<
131 <<
132 <<
133 <<
134 <<
135 <<
136 }; <<
137 <<
138 i2s5_p <<
139 <<
140 <<
141 <<
142 <<
143 <<
144 <<
145 }; <<
146 }; <<
147 }; <<
148 <<
149 i2s@2901500 { <<
150 status = "okay <<
151 <<
152 ports { <<
153 #addre <<
154 #size- <<
155 <<
156 port@0 <<
157 <<
158 <<
159 <<
160 <<
161 <<
162 }; <<
163 <<
164 i2s6_p <<
165 <<
166 <<
167 <<
168 <<
169 <<
170 <<
171 }; <<
172 }; <<
173 }; <<
174 <<
175 sfc@2902000 { <<
176 status = "okay <<
177 <<
178 ports { <<
179 #addre <<
180 #size- <<
181 <<
182 port@0 <<
183 <<
184 <<
185 <<
186 <<
187 <<
188 <<
189 }; <<
190 <<
191 sfc1_o <<
192 <<
193 <<
194 <<
195 <<
196 <<
197 <<
198 }; <<
199 }; <<
200 }; <<
201 <<
202 sfc@2902200 { <<
203 status = "okay <<
204 <<
205 ports { <<
206 #addre <<
207 #size- <<
208 <<
209 port@0 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 }; <<
216 <<
217 sfc2_o <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 }; <<
224 }; <<
225 }; <<
226 <<
227 sfc@2902400 { <<
228 status = "okay <<
229 <<
230 ports { <<
231 #addre <<
232 #size- <<
233 <<
234 port@0 <<
235 <<
236 <<
237 <<
238 <<
239 <<
240 }; <<
241 <<
242 sfc3_o <<
243 <<
244 <<
245 <<
246 <<
247 <<
248 }; <<
249 }; <<
250 }; <<
251 <<
252 sfc@2902600 { <<
253 status = "okay <<
254 <<
255 ports { <<
256 #addre <<
257 #size- <<
258 <<
259 port@0 <<
260 <<
261 <<
262 <<
263 <<
264 <<
265 }; <<
266 <<
267 sfc4_o <<
268 <<
269 <<
270 <<
271 <<
272 <<
273 }; <<
274 }; <<
275 }; <<
276 <<
277 amx@2903000 { <<
278 status = "okay <<
279 <<
280 ports { <<
281 #addre <<
282 #size- <<
283 <<
284 port@0 <<
285 <<
286 <<
287 <<
288 <<
289 <<
290 }; <<
291 <<
292 port@1 <<
293 <<
294 <<
295 <<
296 <<
297 <<
298 }; <<
299 <<
300 port@2 <<
301 <<
302 <<
303 <<
304 <<
305 <<
306 }; <<
307 <<
308 port@3 <<
309 <<
310 <<
311 <<
312 <<
313 <<
314 }; <<
315 <<
316 amx1_o <<
317 <<
318 <<
319 <<
320 <<
321 <<
322 }; <<
323 }; <<
324 }; <<
325 <<
326 amx@2903100 { <<
327 status = "okay <<
328 <<
329 ports { <<
330 #addre <<
331 #size- <<
332 <<
333 port@0 <<
334 <<
335 <<
336 <<
337 <<
338 <<
339 }; <<
340 <<
341 port@1 <<
342 <<
343 <<
344 <<
345 <<
346 <<
347 }; <<
348 <<
349 amx2_i <<
350 <<
351 <<
352 <<
353 <<
354 <<
355 }; <<
356 <<
357 amx2_i <<
358 <<
359 <<
360 <<
361 <<
362 <<
363 }; <<
364 <<
365 amx2_o <<
366 <<
367 <<
368 <<
369 <<
370 <<
371 }; <<
372 }; <<
373 }; <<
374 <<
375 amx@2903200 { <<
376 status = "okay <<
377 <<
378 ports { <<
379 #addre <<
380 #size- <<
381 <<
382 port@0 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 }; <<
389 <<
390 port@1 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 }; <<
397 <<
398 port@2 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 }; <<
405 <<
406 port@3 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 }; <<
413 <<
414 amx3_o <<
415 <<
416 <<
417 <<
418 <<
419 <<
420 }; <<
421 }; <<
422 }; <<
423 <<
424 amx@2903300 { <<
425 status = "okay <<
426 <<
427 ports { <<
428 #addre <<
429 #size- <<
430 <<
431 port@0 <<
432 <<
433 <<
434 <<
435 <<
436 <<
437 }; <<
438 <<
439 port@1 <<
440 <<
441 <<
442 <<
443 <<
444 <<
445 }; <<
446 <<
447 port@2 <<
448 <<
449 <<
450 <<
451 <<
452 <<
453 }; <<
454 <<
455 port@3 <<
456 <<
457 <<
458 <<
459 <<
460 <<
461 }; <<
462 <<
463 amx4_o <<
464 <<
465 <<
466 <<
467 <<
468 <<
469 }; <<
470 }; <<
471 }; <<
472 <<
473 adx@2903800 { <<
474 status = "okay <<
475 <<
476 ports { <<
477 #addre <<
478 #size- <<
479 <<
480 port@0 <<
481 <<
482 <<
483 <<
484 <<
485 <<
486 }; <<
487 <<
488 adx1_o <<
489 <<
490 <<
491 <<
492 <<
493 <<
494 }; <<
495 <<
496 adx1_o <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 }; <<
503 <<
504 adx1_o <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 }; <<
511 <<
512 adx1_o <<
513 <<
514 <<
515 <<
516 <<
517 <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 adx@2903900 { <<
523 status = "okay <<
524 <<
525 ports { <<
526 #addre <<
527 #size- <<
528 <<
529 port@0 <<
530 <<
531 <<
532 <<
533 <<
534 <<
535 }; <<
536 <<
537 adx2_o <<
538 <<
539 <<
540 <<
541 <<
542 <<
543 }; <<
544 <<
545 adx2_o <<
546 <<
547 <<
548 <<
549 <<
550 <<
551 }; <<
552 <<
553 adx2_o <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 }; <<
560 <<
561 adx2_o <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 }; <<
568 }; <<
569 }; <<
570 <<
571 adx@2903a00 { <<
572 status = "okay <<
573 <<
574 ports { <<
575 #addre <<
576 #size- <<
577 <<
578 port@0 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 }; <<
585 <<
586 adx3_o <<
587 <<
588 <<
589 <<
590 <<
591 <<
592 }; <<
593 <<
594 adx3_o <<
595 <<
596 <<
597 <<
598 <<
599 <<
600 }; <<
601 <<
602 adx3_o <<
603 <<
604 <<
605 <<
606 <<
607 <<
608 }; <<
609 <<
610 adx3_o <<
611 <<
612 <<
613 <<
614 <<
615 <<
616 }; <<
617 }; <<
618 }; <<
619 <<
620 adx@2903b00 { <<
621 status = "okay <<
622 <<
623 ports { <<
624 #addre <<
625 #size- <<
626 <<
627 port@0 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 }; <<
634 <<
635 adx4_o <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 }; <<
642 <<
643 adx4_o <<
644 <<
645 <<
646 <<
647 <<
648 <<
649 }; <<
650 <<
651 adx4_o <<
652 <<
653 <<
654 <<
655 <<
656 <<
657 }; <<
658 <<
659 adx4_o <<
660 <<
661 <<
662 <<
663 <<
664 <<
665 }; <<
666 }; <<
667 }; <<
668 <<
669 dmic@2904000 { <<
670 status = "okay <<
671 <<
672 ports { <<
673 #addre <<
674 #size- <<
675 <<
676 port@0 <<
677 <<
678 <<
679 <<
680 <<
681 <<
682 }; <<
683 <<
684 dmic1_ <<
685 <<
686 <<
687 <<
688 <<
689 <<
690 }; <<
691 }; <<
692 }; <<
693 <<
694 dmic@2904100 { <<
695 status = "okay <<
696 <<
697 ports { <<
698 #addre <<
699 #size- <<
700 <<
701 port@0 <<
702 <<
703 <<
704 <<
705 <<
706 <<
707 }; <<
708 <<
709 dmic2_ <<
710 <<
711 <<
712 <<
713 <<
714 <<
715 }; <<
716 }; <<
717 }; <<
718 <<
719 dmic@2904200 { <<
720 status = "okay <<
721 <<
722 ports { <<
723 #addre <<
724 #size- <<
725 <<
726 port@0 <<
727 <<
728 <<
729 <<
730 <<
731 <<
732 }; <<
733 <<
734 dmic3_ <<
735 <<
736 <<
737 <<
738 <<
739 <<
740 }; <<
741 }; <<
742 }; <<
743 <<
744 dspk@2905000 { <<
745 status = "okay <<
746 <<
747 ports { <<
748 #addre <<
749 #size- <<
750 <<
751 port@0 <<
752 <<
753 <<
754 <<
755 <<
756 <<
757 }; <<
758 <<
759 dspk1_ <<
760 <<
761 <<
762 <<
763 <<
764 <<
765 }; <<
766 }; <<
767 }; <<
768 <<
769 dspk@2905100 { <<
770 status = "okay <<
771 <<
772 ports { <<
773 #addre <<
774 #size- <<
775 <<
776 port@0 <<
777 <<
778 <<
779 <<
780 <<
781 <<
782 }; <<
783 <<
784 dspk2_ <<
785 <<
786 <<
787 <<
788 <<
789 <<
790 }; <<
791 }; <<
792 }; <<
793 <<
794 processing-engine@2908 <<
795 status = "okay <<
796 <<
797 ports { <<
798 #addre <<
799 #size- <<
800 <<
801 port@0 <<
802 <<
803 <<
804 <<
805 <<
806 <<
807 }; <<
808 <<
809 ope1_o <<
810 <<
811 <<
812 <<
813 <<
814 <<
815 }; <<
816 }; <<
817 }; <<
818 <<
819 mvc@290a000 { <<
820 status = "okay <<
821 <<
822 ports { <<
823 #addre <<
824 #size- <<
825 <<
826 port@0 <<
827 <<
828 <<
829 <<
830 <<
831 <<
832 }; <<
833 <<
834 mvc1_o <<
835 <<
836 <<
837 <<
838 <<
839 <<
840 }; <<
841 }; <<
842 }; <<
843 <<
844 mvc@290a200 { <<
845 status = "okay <<
846 <<
847 ports { <<
848 #addre <<
849 #size- <<
850 <<
851 port@0 <<
852 <<
853 <<
854 <<
855 <<
856 <<
857 }; <<
858 <<
859 mvc2_o <<
860 <<
861 <<
862 <<
863 <<
864 <<
865 }; <<
866 }; <<
867 }; <<
868 <<
869 amixer@290bb00 { <<
870 status = "okay <<
871 <<
872 ports { <<
873 #addre <<
874 #size- <<
875 <<
876 port@0 <<
877 <<
878 <<
879 <<
880 <<
881 <<
882 }; <<
883 <<
884 port@1 <<
885 <<
886 <<
887 <<
888 <<
889 <<
890 }; <<
891 <<
892 port@2 <<
893 <<
894 <<
895 <<
896 <<
897 <<
898 }; <<
899 <<
900 port@3 <<
901 <<
902 <<
903 <<
904 <<
905 <<
906 }; <<
907 <<
908 port@4 <<
909 <<
910 <<
911 <<
912 <<
913 <<
914 }; <<
915 <<
916 port@5 <<
917 <<
918 <<
919 <<
920 <<
921 <<
922 }; <<
923 <<
924 port@6 <<
925 <<
926 <<
927 <<
928 <<
929 <<
930 }; <<
931 <<
932 port@7 <<
933 <<
934 <<
935 <<
936 <<
937 <<
938 }; <<
939 <<
940 port@8 <<
941 <<
942 <<
943 <<
944 <<
945 <<
946 }; <<
947 <<
948 port@9 <<
949 <<
950 <<
951 <<
952 <<
953 <<
954 }; <<
955 <<
956 mixer_ <<
957 <<
958 <<
959 <<
960 <<
961 <<
962 }; <<
963 <<
964 mixer_ <<
965 <<
966 <<
967 <<
968 <<
969 <<
970 }; <<
971 <<
972 mixer_ <<
973 <<
974 <<
975 <<
976 <<
977 <<
978 }; <<
979 <<
980 mixer_ <<
981 <<
982 <<
983 <<
984 <<
985 <<
986 }; <<
987 <<
988 mixer_ <<
989 <<
990 <<
991 <<
992 <<
993 <<
994 }; <<
995 }; <<
996 }; <<
997 <<
998 admaif@290f000 { <<
999 status = "okay <<
1000 <<
1001 ports { <<
1002 #addr <<
1003 #size <<
1004 <<
1005 admai <<
1006 <<
1007 <<
1008 <<
1009 <<
1010 <<
1011 }; <<
1012 <<
1013 admai <<
1014 <<
1015 <<
1016 <<
1017 <<
1018 <<
1019 }; <<
1020 <<
1021 admai <<
1022 <<
1023 <<
1024 <<
1025 <<
1026 <<
1027 }; <<
1028 <<
1029 admai <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 <<
1035 }; <<
1036 <<
1037 admai <<
1038 <<
1039 <<
1040 <<
1041 <<
1042 <<
1043 }; <<
1044 <<
1045 admai <<
1046 <<
1047 <<
1048 <<
1049 <<
1050 <<
1051 }; <<
1052 <<
1053 admai <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 <<
1059 }; <<
1060 <<
1061 admai <<
1062 <<
1063 <<
1064 <<
1065 <<
1066 <<
1067 }; <<
1068 <<
1069 admai <<
1070 <<
1071 <<
1072 <<
1073 <<
1074 <<
1075 }; <<
1076 <<
1077 admai <<
1078 <<
1079 <<
1080 <<
1081 <<
1082 <<
1083 }; <<
1084 <<
1085 admai <<
1086 <<
1087 <<
1088 <<
1089 <<
1090 <<
1091 }; <<
1092 <<
1093 admai <<
1094 <<
1095 <<
1096 <<
1097 <<
1098 <<
1099 }; <<
1100 <<
1101 admai <<
1102 <<
1103 <<
1104 <<
1105 <<
1106 <<
1107 }; <<
1108 <<
1109 admai <<
1110 <<
1111 <<
1112 <<
1113 <<
1114 <<
1115 }; <<
1116 <<
1117 admai <<
1118 <<
1119 <<
1120 <<
1121 <<
1122 <<
1123 }; <<
1124 <<
1125 admai <<
1126 <<
1127 <<
1128 <<
1129 <<
1130 <<
1131 }; <<
1132 <<
1133 admai <<
1134 <<
1135 <<
1136 <<
1137 <<
1138 <<
1139 }; <<
1140 <<
1141 admai <<
1142 <<
1143 <<
1144 <<
1145 <<
1146 <<
1147 }; <<
1148 <<
1149 admai <<
1150 <<
1151 <<
1152 <<
1153 <<
1154 <<
1155 }; <<
1156 <<
1157 admai <<
1158 <<
1159 <<
1160 <<
1161 <<
1162 <<
1163 }; <<
1164 }; <<
1165 }; <<
1166 <<
1167 asrc@2910000 { <<
1168 status = "oka <<
1169 <<
1170 ports { <<
1171 #addr <<
1172 #size <<
1173 <<
1174 port@ <<
1175 <<
1176 <<
1177 <<
1178 <<
1179 <<
1180 }; <<
1181 <<
1182 port@ <<
1183 <<
1184 <<
1185 <<
1186 <<
1187 <<
1188 }; <<
1189 <<
1190 port@ <<
1191 <<
1192 <<
1193 <<
1194 <<
1195 <<
1196 }; <<
1197 <<
1198 port@ <<
1199 <<
1200 <<
1201 <<
1202 <<
1203 <<
1204 }; <<
1205 <<
1206 port@ <<
1207 <<
1208 <<
1209 <<
1210 <<
1211 <<
1212 }; <<
1213 <<
1214 port@ <<
1215 <<
1216 <<
1217 <<
1218 <<
1219 <<
1220 }; <<
1221 <<
1222 port@ <<
1223 <<
1224 <<
1225 <<
1226 <<
1227 <<
1228 }; <<
1229 <<
1230 asrc_ <<
1231 <<
1232 <<
1233 <<
1234 <<
1235 <<
1236 }; <<
1237 <<
1238 asrc_ <<
1239 <<
1240 <<
1241 <<
1242 <<
1243 <<
1244 }; <<
1245 <<
1246 asrc_ <<
1247 <<
1248 <<
1249 <<
1250 <<
1251 <<
1252 }; <<
1253 <<
1254 asrc_ <<
1255 <<
1256 <<
1257 <<
1258 <<
1259 <<
1260 }; <<
1261 <<
1262 asrc_ <<
1263 <<
1264 <<
1265 <<
1266 <<
1267 <<
1268 }; <<
1269 <<
1270 asrc_ <<
1271 <<
1272 23
1273 !! 24 ahub@2900800 {
1274 !! 25 status = "okay";
1275 <<
1276 }; <<
1277 }; <<
1278 }; <<
1279 26
1280 ports { 27 ports {
1281 #address-cell 28 #address-cells = <1>;
1282 #size-cells = 29 #size-cells = <0>;
1283 30
1284 port@0 { 31 port@0 {
1285 reg = 32 reg = <0x0>;
1286 33
1287 xbar_ 34 xbar_admaif0_ep: endpoint {
1288 35 remote-endpoint = <&admaif0_ep>;
1289 }; 36 };
1290 }; 37 };
1291 38
1292 port@1 { 39 port@1 {
1293 reg = 40 reg = <0x1>;
1294 41
1295 xbar_ 42 xbar_admaif1_ep: endpoint {
1296 43 remote-endpoint = <&admaif1_ep>;
1297 }; 44 };
1298 }; 45 };
1299 46
1300 port@2 { 47 port@2 {
1301 reg = 48 reg = <0x2>;
1302 49
1303 xbar_ 50 xbar_admaif2_ep: endpoint {
1304 51 remote-endpoint = <&admaif2_ep>;
1305 }; 52 };
1306 }; 53 };
1307 54
1308 port@3 { 55 port@3 {
1309 reg = 56 reg = <0x3>;
1310 57
1311 xbar_ 58 xbar_admaif3_ep: endpoint {
1312 59 remote-endpoint = <&admaif3_ep>;
1313 }; 60 };
1314 }; 61 };
1315 62
1316 port@4 { 63 port@4 {
1317 reg = 64 reg = <0x4>;
1318 65
1319 xbar_ 66 xbar_admaif4_ep: endpoint {
1320 67 remote-endpoint = <&admaif4_ep>;
1321 }; 68 };
1322 }; 69 };
1323 70
1324 port@5 { 71 port@5 {
1325 reg = 72 reg = <0x5>;
1326 73
1327 xbar_ 74 xbar_admaif5_ep: endpoint {
1328 75 remote-endpoint = <&admaif5_ep>;
1329 }; 76 };
1330 }; 77 };
1331 78
1332 port@6 { 79 port@6 {
1333 reg = 80 reg = <0x6>;
1334 81
1335 xbar_ 82 xbar_admaif6_ep: endpoint {
1336 83 remote-endpoint = <&admaif6_ep>;
1337 }; 84 };
1338 }; 85 };
1339 86
1340 port@7 { 87 port@7 {
1341 reg = 88 reg = <0x7>;
1342 89
1343 xbar_ 90 xbar_admaif7_ep: endpoint {
1344 91 remote-endpoint = <&admaif7_ep>;
1345 }; 92 };
1346 }; 93 };
1347 94
1348 port@8 { 95 port@8 {
1349 reg = 96 reg = <0x8>;
1350 97
1351 xbar_ 98 xbar_admaif8_ep: endpoint {
1352 99 remote-endpoint = <&admaif8_ep>;
1353 }; 100 };
1354 }; 101 };
1355 102
1356 port@9 { 103 port@9 {
1357 reg = 104 reg = <0x9>;
1358 105
1359 xbar_ 106 xbar_admaif9_ep: endpoint {
1360 107 remote-endpoint = <&admaif9_ep>;
1361 }; 108 };
1362 }; 109 };
1363 110
1364 port@a { 111 port@a {
1365 reg = 112 reg = <0xa>;
1366 113
1367 xbar_ 114 xbar_admaif10_ep: endpoint {
1368 115 remote-endpoint = <&admaif10_ep>;
1369 }; 116 };
1370 }; 117 };
1371 118
1372 port@b { 119 port@b {
1373 reg = 120 reg = <0xb>;
1374 121
1375 xbar_ 122 xbar_admaif11_ep: endpoint {
1376 123 remote-endpoint = <&admaif11_ep>;
1377 }; 124 };
1378 }; 125 };
1379 126
1380 port@c { 127 port@c {
1381 reg = 128 reg = <0xc>;
1382 129
1383 xbar_ 130 xbar_admaif12_ep: endpoint {
1384 131 remote-endpoint = <&admaif12_ep>;
1385 }; 132 };
1386 }; 133 };
1387 134
1388 port@d { 135 port@d {
1389 reg = 136 reg = <0xd>;
1390 137
1391 xbar_ 138 xbar_admaif13_ep: endpoint {
1392 139 remote-endpoint = <&admaif13_ep>;
1393 }; 140 };
1394 }; 141 };
1395 142
1396 port@e { 143 port@e {
1397 reg = 144 reg = <0xe>;
1398 145
1399 xbar_ 146 xbar_admaif14_ep: endpoint {
1400 147 remote-endpoint = <&admaif14_ep>;
1401 }; 148 };
1402 }; 149 };
1403 150
1404 port@f { 151 port@f {
1405 reg = 152 reg = <0xf>;
1406 153
1407 xbar_ 154 xbar_admaif15_ep: endpoint {
1408 155 remote-endpoint = <&admaif15_ep>;
1409 }; 156 };
1410 }; 157 };
1411 158
1412 port@10 { 159 port@10 {
1413 reg = 160 reg = <0x10>;
1414 161
1415 xbar_ 162 xbar_admaif16_ep: endpoint {
1416 163 remote-endpoint = <&admaif16_ep>;
1417 }; 164 };
1418 }; 165 };
1419 166
1420 port@11 { 167 port@11 {
1421 reg = 168 reg = <0x11>;
1422 169
1423 xbar_ 170 xbar_admaif17_ep: endpoint {
1424 171 remote-endpoint = <&admaif17_ep>;
1425 }; 172 };
1426 }; 173 };
1427 174
1428 port@12 { 175 port@12 {
1429 reg = 176 reg = <0x12>;
1430 177
1431 xbar_ 178 xbar_admaif18_ep: endpoint {
1432 179 remote-endpoint = <&admaif18_ep>;
1433 }; 180 };
1434 }; 181 };
1435 182
1436 port@13 { 183 port@13 {
1437 reg = 184 reg = <0x13>;
1438 185
1439 xbar_ 186 xbar_admaif19_ep: endpoint {
1440 187 remote-endpoint = <&admaif19_ep>;
1441 }; 188 };
1442 }; 189 };
1443 190
1444 xbar_i2s1_por 191 xbar_i2s1_port: port@14 {
1445 reg = 192 reg = <0x14>;
1446 193
1447 xbar_ 194 xbar_i2s1_ep: endpoint {
1448 195 remote-endpoint = <&i2s1_cif_ep>;
1449 }; 196 };
1450 }; 197 };
1451 198
1452 xbar_i2s2_por 199 xbar_i2s2_port: port@15 {
1453 reg = 200 reg = <0x15>;
1454 201
1455 xbar_ 202 xbar_i2s2_ep: endpoint {
1456 203 remote-endpoint = <&i2s2_cif_ep>;
1457 }; 204 };
1458 }; 205 };
1459 206
1460 xbar_i2s3_por 207 xbar_i2s3_port: port@16 {
1461 reg = 208 reg = <0x16>;
1462 209
1463 xbar_ 210 xbar_i2s3_ep: endpoint {
1464 211 remote-endpoint = <&i2s3_cif_ep>;
1465 }; 212 };
1466 }; 213 };
1467 214
1468 xbar_i2s4_por 215 xbar_i2s4_port: port@17 {
1469 reg = 216 reg = <0x17>;
1470 217
1471 xbar_ 218 xbar_i2s4_ep: endpoint {
1472 219 remote-endpoint = <&i2s4_cif_ep>;
1473 }; 220 };
1474 }; 221 };
1475 222
1476 xbar_i2s5_por 223 xbar_i2s5_port: port@18 {
1477 reg = 224 reg = <0x18>;
1478 225
1479 xbar_ 226 xbar_i2s5_ep: endpoint {
1480 227 remote-endpoint = <&i2s5_cif_ep>;
1481 }; 228 };
1482 }; 229 };
1483 230
1484 xbar_i2s6_por 231 xbar_i2s6_port: port@19 {
1485 reg = 232 reg = <0x19>;
1486 233
1487 xbar_ 234 xbar_i2s6_ep: endpoint {
1488 235 remote-endpoint = <&i2s6_cif_ep>;
1489 }; 236 };
1490 }; 237 };
1491 238
1492 xbar_dmic1_po 239 xbar_dmic1_port: port@1a {
1493 reg = 240 reg = <0x1a>;
1494 241
1495 xbar_ 242 xbar_dmic1_ep: endpoint {
1496 243 remote-endpoint = <&dmic1_cif_ep>;
1497 }; 244 };
1498 }; 245 };
1499 246
1500 xbar_dmic2_po 247 xbar_dmic2_port: port@1b {
1501 reg = 248 reg = <0x1b>;
1502 249
1503 xbar_ 250 xbar_dmic2_ep: endpoint {
1504 251 remote-endpoint = <&dmic2_cif_ep>;
1505 }; 252 };
1506 }; 253 };
1507 254
1508 xbar_dmic3_po 255 xbar_dmic3_port: port@1c {
1509 reg = 256 reg = <0x1c>;
1510 257
1511 xbar_ 258 xbar_dmic3_ep: endpoint {
1512 259 remote-endpoint = <&dmic3_cif_ep>;
1513 }; 260 };
1514 }; 261 };
1515 262
1516 xbar_dspk1_po 263 xbar_dspk1_port: port@1e {
1517 reg = 264 reg = <0x1e>;
1518 265
1519 xbar_ 266 xbar_dspk1_ep: endpoint {
1520 267 remote-endpoint = <&dspk1_cif_ep>;
1521 }; 268 };
1522 }; 269 };
1523 270
1524 xbar_dspk2_po 271 xbar_dspk2_port: port@1f {
1525 reg = 272 reg = <0x1f>;
1526 273
1527 xbar_ 274 xbar_dspk2_ep: endpoint {
1528 275 remote-endpoint = <&dspk2_cif_ep>;
1529 }; 276 };
1530 }; 277 };
>> 278 };
1531 279
1532 xbar_sfc1_in_ !! 280 admaif@290f000 {
1533 reg = !! 281 status = "okay";
1534 <<
1535 xbar_ <<
1536 <<
1537 }; <<
1538 }; <<
1539 <<
1540 port@21 { <<
1541 reg = <<
1542 <<
1543 xbar_ <<
1544 <<
1545 }; <<
1546 }; <<
1547 <<
1548 xbar_sfc2_in_ <<
1549 reg = <<
1550 <<
1551 xbar_ <<
1552 <<
1553 }; <<
1554 }; <<
1555 <<
1556 port@23 { <<
1557 reg = <<
1558 <<
1559 xbar_ <<
1560 <<
1561 }; <<
1562 }; <<
1563 <<
1564 xbar_sfc3_in_ <<
1565 reg = <<
1566 <<
1567 xbar_ <<
1568 <<
1569 }; <<
1570 }; <<
1571 <<
1572 port@25 { <<
1573 reg = <<
1574 <<
1575 xbar_ <<
1576 <<
1577 }; <<
1578 }; <<
1579 <<
1580 xbar_sfc4_in_ <<
1581 reg = <<
1582 <<
1583 xbar_ <<
1584 <<
1585 }; <<
1586 }; <<
1587 <<
1588 port@27 { <<
1589 reg = <<
1590 <<
1591 xbar_ <<
1592 <<
1593 }; <<
1594 }; <<
1595 <<
1596 xbar_mvc1_in_ <<
1597 reg = <<
1598 <<
1599 xbar_ <<
1600 <<
1601 }; <<
1602 }; <<
1603 <<
1604 port@29 { <<
1605 reg = <<
1606 <<
1607 xbar_ <<
1608 <<
1609 }; <<
1610 }; <<
1611 <<
1612 xbar_mvc2_in_ <<
1613 reg = <<
1614 <<
1615 xbar_ <<
1616 <<
1617 }; <<
1618 }; <<
1619 <<
1620 port@2b { <<
1621 reg = <<
1622 <<
1623 xbar_ <<
1624 <<
1625 }; <<
1626 }; <<
1627 <<
1628 xbar_amx1_in1 <<
1629 reg = <<
1630 <<
1631 xbar_ <<
1632 <<
1633 }; <<
1634 }; <<
1635 <<
1636 xbar_amx1_in2 <<
1637 reg = <<
1638 <<
1639 xbar_ <<
1640 <<
1641 }; <<
1642 }; <<
1643 <<
1644 xbar_amx1_in3 <<
1645 reg = <<
1646 <<
1647 xbar_ <<
1648 <<
1649 }; <<
1650 }; <<
1651 <<
1652 xbar_amx1_in4 <<
1653 reg = <<
1654 <<
1655 xbar_ <<
1656 <<
1657 }; <<
1658 }; <<
1659 <<
1660 port@30 { <<
1661 reg = <<
1662 <<
1663 xbar_ <<
1664 <<
1665 }; <<
1666 }; <<
1667 <<
1668 xbar_amx2_in1 <<
1669 reg = <<
1670 <<
1671 xbar_ <<
1672 <<
1673 }; <<
1674 }; <<
1675 <<
1676 xbar_amx2_in2 <<
1677 reg = <<
1678 <<
1679 xbar_ <<
1680 <<
1681 }; <<
1682 }; <<
1683 <<
1684 xbar_amx2_in3 <<
1685 reg = <<
1686 <<
1687 xbar_ <<
1688 <<
1689 }; <<
1690 }; <<
1691 <<
1692 xbar_amx2_in4 <<
1693 reg = <<
1694 <<
1695 xbar_ <<
1696 <<
1697 }; <<
1698 }; <<
1699 <<
1700 port@35 { <<
1701 reg = <<
1702 <<
1703 xbar_ <<
1704 <<
1705 }; <<
1706 }; <<
1707 <<
1708 xbar_amx3_in1 <<
1709 reg = <<
1710 <<
1711 xbar_ <<
1712 <<
1713 }; <<
1714 }; <<
1715 <<
1716 xbar_amx3_in2 <<
1717 reg = <<
1718 <<
1719 xbar_ <<
1720 <<
1721 }; <<
1722 }; <<
1723 <<
1724 xbar_amx3_in3 <<
1725 reg = <<
1726 <<
1727 xbar_ <<
1728 <<
1729 }; <<
1730 }; <<
1731 <<
1732 xbar_amx3_in4 <<
1733 reg = <<
1734 <<
1735 xbar_ <<
1736 <<
1737 }; <<
1738 }; <<
1739 <<
1740 port@3a { <<
1741 reg = <<
1742 <<
1743 xbar_ <<
1744 <<
1745 }; <<
1746 }; <<
1747 <<
1748 xbar_amx4_in1 <<
1749 reg = <<
1750 <<
1751 xbar_ <<
1752 <<
1753 }; <<
1754 }; <<
1755 <<
1756 xbar_amx4_in2 <<
1757 reg = <<
1758 282
1759 xbar_ !! 283 ports {
1760 !! 284 #address-cells = <1>;
1761 }; !! 285 #size-cells = <0>;
1762 }; <<
1763 286
1764 xbar_amx4_in3 !! 287 admaif0_port: port@0 {
1765 reg = !! 288 reg = <0x0>;
1766 289
1767 xbar_ !! 290 admaif0_ep: endpoint {
1768 !! 291 remote-endpoint = <&xbar_admaif0_ep>;
>> 292 };
1769 }; 293 };
1770 }; <<
1771 294
1772 xbar_amx4_in4 !! 295 admaif1_port: port@1 {
1773 reg = !! 296 reg = <0x1>;
1774 297
1775 xbar_ !! 298 admaif1_ep: endpoint {
1776 !! 299 remote-endpoint = <&xbar_admaif1_ep>;
>> 300 };
1777 }; 301 };
1778 }; <<
1779 302
1780 port@3f { !! 303 admaif2_port: port@2 {
1781 reg = !! 304 reg = <0x2>;
1782 305
1783 xbar_ !! 306 admaif2_ep: endpoint {
1784 !! 307 remote-endpoint = <&xbar_admaif2_ep>;
>> 308 };
1785 }; 309 };
1786 }; <<
1787 310
1788 xbar_adx1_in_ !! 311 admaif3_port: port@3 {
1789 reg = !! 312 reg = <0x3>;
1790 313
1791 xbar_ !! 314 admaif3_ep: endpoint {
1792 !! 315 remote-endpoint = <&xbar_admaif3_ep>;
>> 316 };
1793 }; 317 };
1794 }; <<
1795 318
1796 port@41 { !! 319 admaif4_port: port@4 {
1797 reg = !! 320 reg = <0x4>;
1798 321
1799 xbar_ !! 322 admaif4_ep: endpoint {
1800 !! 323 remote-endpoint = <&xbar_admaif4_ep>;
>> 324 };
1801 }; 325 };
1802 }; <<
1803 326
1804 port@42 { !! 327 admaif5_port: port@5 {
1805 reg = !! 328 reg = <0x5>;
1806 329
1807 xbar_ !! 330 admaif5_ep: endpoint {
1808 !! 331 remote-endpoint = <&xbar_admaif5_ep>;
>> 332 };
1809 }; 333 };
1810 }; <<
1811 334
1812 port@43 { !! 335 admaif6_port: port@6 {
1813 reg = !! 336 reg = <0x6>;
1814 337
1815 xbar_ !! 338 admaif6_ep: endpoint {
1816 !! 339 remote-endpoint = <&xbar_admaif6_ep>;
>> 340 };
1817 }; 341 };
1818 }; <<
1819 342
1820 port@44 { !! 343 admaif7_port: port@7 {
1821 reg = !! 344 reg = <0x7>;
1822 345
1823 xbar_ !! 346 admaif7_ep: endpoint {
1824 !! 347 remote-endpoint = <&xbar_admaif7_ep>;
>> 348 };
1825 }; 349 };
1826 }; <<
1827 350
1828 xbar_adx2_in_ !! 351 admaif8_port: port@8 {
1829 reg = !! 352 reg = <0x8>;
1830 353
1831 xbar_ !! 354 admaif8_ep: endpoint {
1832 !! 355 remote-endpoint = <&xbar_admaif8_ep>;
>> 356 };
1833 }; 357 };
1834 }; <<
1835 358
1836 port@46 { !! 359 admaif9_port: port@9 {
1837 reg = !! 360 reg = <0x9>;
1838 361
1839 xbar_ !! 362 admaif9_ep: endpoint {
1840 !! 363 remote-endpoint = <&xbar_admaif9_ep>;
>> 364 };
1841 }; 365 };
1842 }; <<
1843 366
1844 port@47 { !! 367 admaif10_port: port@a {
1845 reg = !! 368 reg = <0xa>;
1846 369
1847 xbar_ !! 370 admaif10_ep: endpoint {
1848 !! 371 remote-endpoint = <&xbar_admaif10_ep>;
>> 372 };
1849 }; 373 };
1850 }; <<
1851 374
1852 port@48 { !! 375 admaif11_port: port@b {
1853 reg = !! 376 reg = <0xb>;
1854 377
1855 xbar_ !! 378 admaif11_ep: endpoint {
1856 !! 379 remote-endpoint = <&xbar_admaif11_ep>;
>> 380 };
1857 }; 381 };
1858 }; <<
1859 382
1860 port@49 { !! 383 admaif12_port: port@c {
1861 reg = !! 384 reg = <0xc>;
1862 385
1863 xbar_ !! 386 admaif12_ep: endpoint {
1864 !! 387 remote-endpoint = <&xbar_admaif12_ep>;
>> 388 };
1865 }; 389 };
1866 }; <<
1867 390
1868 xbar_adx3_in_ !! 391 admaif13_port: port@d {
1869 reg = !! 392 reg = <0xd>;
1870 393
1871 xbar_ !! 394 admaif13_ep: endpoint {
1872 !! 395 remote-endpoint = <&xbar_admaif13_ep>;
>> 396 };
1873 }; 397 };
1874 }; <<
1875 398
1876 port@4b { !! 399 admaif14_port: port@e {
1877 reg = !! 400 reg = <0xe>;
1878 401
1879 xbar_ !! 402 admaif14_ep: endpoint {
1880 !! 403 remote-endpoint = <&xbar_admaif14_ep>;
>> 404 };
1881 }; 405 };
1882 }; <<
1883 406
1884 port@4c { !! 407 admaif15_port: port@f {
1885 reg = !! 408 reg = <0xf>;
1886 409
1887 xbar_ !! 410 admaif15_ep: endpoint {
1888 !! 411 remote-endpoint = <&xbar_admaif15_ep>;
>> 412 };
1889 }; 413 };
1890 }; <<
1891 414
1892 port@4d { !! 415 admaif16_port: port@10 {
1893 reg = !! 416 reg = <0x10>;
1894 417
1895 xbar_ !! 418 admaif16_ep: endpoint {
1896 !! 419 remote-endpoint = <&xbar_admaif16_ep>;
>> 420 };
1897 }; 421 };
1898 }; <<
1899 422
1900 port@4e { !! 423 admaif17_port: port@11 {
1901 reg = !! 424 reg = <0x11>;
1902 425
1903 xbar_ !! 426 admaif17_ep: endpoint {
1904 !! 427 remote-endpoint = <&xbar_admaif17_ep>;
>> 428 };
1905 }; 429 };
1906 }; <<
1907 430
1908 xbar_adx4_in_ !! 431 admaif18_port: port@12 {
1909 reg = !! 432 reg = <0x12>;
1910 433
1911 xbar_ !! 434 admaif18_ep: endpoint {
1912 !! 435 remote-endpoint = <&xbar_admaif18_ep>;
>> 436 };
1913 }; 437 };
1914 }; <<
1915 438
1916 port@50 { !! 439 admaif19_port: port@13 {
1917 reg = !! 440 reg = <0x13>;
1918 441
1919 xbar_ !! 442 admaif19_ep: endpoint {
1920 !! 443 remote-endpoint = <&xbar_admaif19_ep>;
>> 444 };
1921 }; 445 };
1922 }; 446 };
>> 447 };
1923 448
1924 port@51 { !! 449 i2s@2901000 {
1925 reg = !! 450 status = "okay";
1926 451
1927 xbar_ !! 452 ports {
1928 !! 453 #address-cells = <1>;
1929 }; !! 454 #size-cells = <0>;
1930 }; <<
1931 455
1932 port@52 { !! 456 port@0 {
1933 reg = !! 457 reg = <0>;
1934 458
1935 xbar_ !! 459 i2s1_cif_ep: endpoint {
1936 !! 460 remote-endpoint = <&xbar_i2s1_ep>;
>> 461 };
1937 }; 462 };
1938 }; <<
1939 463
1940 port@53 { !! 464 i2s1_port: port@1 {
1941 reg = !! 465 reg = <1>;
1942 466
1943 xbar_ !! 467 i2s1_dap_ep: endpoint {
1944 !! 468 dai-format = "i2s";
>> 469 /* Placeholder for external Codec */
>> 470 };
1945 }; 471 };
1946 }; 472 };
>> 473 };
1947 474
1948 xbar_mixer_in !! 475 i2s@2901100 {
1949 reg = !! 476 status = "okay";
1950 477
1951 xbar_ !! 478 ports {
1952 !! 479 #address-cells = <1>;
1953 }; !! 480 #size-cells = <0>;
1954 }; <<
1955 481
1956 xbar_mixer_in !! 482 port@0 {
1957 reg = !! 483 reg = <0>;
1958 484
1959 xbar_ !! 485 i2s2_cif_ep: endpoint {
1960 !! 486 remote-endpoint = <&xbar_i2s2_ep>;
>> 487 };
1961 }; 488 };
1962 }; <<
1963 489
1964 xbar_mixer_in !! 490 i2s2_port: port@1 {
1965 reg = !! 491 reg = <1>;
1966 492
1967 xbar_ !! 493 i2s2_dap_ep: endpoint {
1968 !! 494 dai-format = "i2s";
>> 495 /* Placeholder for external Codec */
>> 496 };
1969 }; 497 };
1970 }; 498 };
>> 499 };
1971 500
1972 xbar_mixer_in !! 501 i2s@2901200 {
1973 reg = !! 502 status = "okay";
1974 503
1975 xbar_ !! 504 ports {
1976 !! 505 #address-cells = <1>;
1977 }; !! 506 #size-cells = <0>;
1978 }; <<
1979 507
1980 xbar_mixer_in !! 508 port@0 {
1981 reg = !! 509 reg = <0>;
1982 510
1983 xbar_ !! 511 i2s3_cif_ep: endpoint {
1984 !! 512 remote-endpoint = <&xbar_i2s3_ep>;
>> 513 };
1985 }; 514 };
1986 }; <<
1987 515
1988 xbar_mixer_in !! 516 i2s3_port: port@1 {
1989 reg = !! 517 reg = <1>;
1990 518
1991 xbar_ !! 519 i2s3_dap_ep: endpoint {
1992 !! 520 dai-format = "i2s";
>> 521 /* Placeholder for external Codec */
>> 522 };
1993 }; 523 };
1994 }; 524 };
>> 525 };
1995 526
1996 xbar_mixer_in !! 527 i2s@2901300 {
1997 reg = !! 528 status = "okay";
1998 529
1999 xbar_ !! 530 ports {
2000 !! 531 #address-cells = <1>;
2001 }; !! 532 #size-cells = <0>;
2002 }; <<
2003 533
2004 xbar_mixer_in !! 534 port@0 {
2005 reg = !! 535 reg = <0>;
2006 536
2007 xbar_ !! 537 i2s4_cif_ep: endpoint {
2008 !! 538 remote-endpoint = <&xbar_i2s4_ep>;
>> 539 };
2009 }; 540 };
2010 }; <<
2011 541
2012 xbar_mixer_in !! 542 i2s4_port: port@1 {
2013 reg = !! 543 reg = <1>;
2014 544
2015 xbar_ !! 545 i2s4_dap_ep: endpoint {
2016 !! 546 dai-format = "i2s";
>> 547 /* Placeholder for external Codec */
>> 548 };
2017 }; 549 };
2018 }; 550 };
>> 551 };
2019 552
2020 xbar_mixer_in !! 553 i2s@2901400 {
2021 reg = !! 554 status = "okay";
2022 555
2023 xbar_ !! 556 ports {
2024 !! 557 #address-cells = <1>;
2025 }; !! 558 #size-cells = <0>;
2026 }; <<
2027 559
2028 port@5e { !! 560 port@0 {
2029 reg = !! 561 reg = <0>;
2030 562
2031 xbar_ !! 563 i2s5_cif_ep: endpoint {
2032 !! 564 remote-endpoint = <&xbar_i2s5_ep>;
>> 565 };
2033 }; 566 };
2034 }; <<
2035 567
2036 port@5f { !! 568 i2s5_port: port@1 {
2037 reg = !! 569 reg = <1>;
2038 570
2039 xbar_ !! 571 i2s5_dap_ep: endpoint {
2040 !! 572 dai-format = "i2s";
>> 573 /* Placeholder for external Codec */
>> 574 };
2041 }; 575 };
2042 }; 576 };
>> 577 };
2043 578
2044 port@60 { !! 579 i2s@2901500 {
2045 reg = !! 580 status = "okay";
2046 581
2047 xbar_ !! 582 ports {
2048 !! 583 #address-cells = <1>;
2049 }; !! 584 #size-cells = <0>;
2050 }; <<
2051 585
2052 port@61 { !! 586 port@0 {
2053 reg = !! 587 reg = <0>;
2054 588
2055 xbar_ !! 589 i2s6_cif_ep: endpoint {
2056 !! 590 remote-endpoint = <&xbar_i2s6_ep>;
>> 591 };
2057 }; 592 };
2058 }; <<
2059 593
2060 port@62 { !! 594 i2s6_port: port@1 {
2061 reg = !! 595 reg = <1>;
2062 596
2063 xbar_ !! 597 i2s6_dap_ep: endpoint {
2064 !! 598 dai-format = "i2s";
>> 599 /* Placeholder for external Codec */
>> 600 };
2065 }; 601 };
2066 }; 602 };
>> 603 };
2067 604
2068 xbar_asrc_in1 !! 605 dmic@2904000 {
2069 reg = !! 606 status = "okay";
2070 607
2071 xbar_ !! 608 ports {
2072 !! 609 #address-cells = <1>;
2073 }; !! 610 #size-cells = <0>;
2074 }; <<
2075 611
2076 port@64 { !! 612 port@0 {
2077 reg = !! 613 reg = <0>;
2078 614
2079 xbar_ !! 615 dmic1_cif_ep: endpoint {
2080 !! 616 remote-endpoint = <&xbar_dmic1_ep>;
>> 617 };
2081 }; 618 };
2082 }; <<
2083 619
2084 xbar_asrc_in2 !! 620 dmic1_port: port@1 {
2085 reg = !! 621 reg = <1>;
2086 622
2087 xbar_ !! 623 dmic1_dap_ep: endpoint {
2088 !! 624 /* Place holder for external Codec */
>> 625 };
2089 }; 626 };
2090 }; 627 };
>> 628 };
2091 629
2092 port@66 { !! 630 dmic@2904100 {
2093 reg = !! 631 status = "okay";
2094 632
2095 xbar_ !! 633 ports {
2096 !! 634 #address-cells = <1>;
2097 }; !! 635 #size-cells = <0>;
2098 }; <<
2099 636
2100 xbar_asrc_in3 !! 637 port@0 {
2101 reg = !! 638 reg = <0>;
2102 639
2103 xbar_ !! 640 dmic2_cif_ep: endpoint {
2104 !! 641 remote-endpoint = <&xbar_dmic2_ep>;
>> 642 };
2105 }; 643 };
2106 }; <<
2107 644
2108 port@68 { !! 645 dmic2_port: port@1 {
2109 reg = !! 646 reg = <1>;
2110 647
2111 xbar_ !! 648 dmic2_dap_ep: endpoint {
2112 !! 649 /* Place holder for external Codec */
>> 650 };
2113 }; 651 };
2114 }; 652 };
>> 653 };
2115 654
2116 xbar_asrc_in4 !! 655 dmic@2904200 {
2117 reg = !! 656 status = "okay";
2118 657
2119 xbar_ !! 658 ports {
2120 !! 659 #address-cells = <1>;
2121 }; !! 660 #size-cells = <0>;
2122 }; <<
2123 661
2124 port@6a { !! 662 port@0 {
2125 reg = !! 663 reg = <0>;
2126 664
2127 xbar_ !! 665 dmic3_cif_ep: endpoint {
2128 !! 666 remote-endpoint = <&xbar_dmic3_ep>;
>> 667 };
2129 }; 668 };
2130 }; <<
2131 669
2132 xbar_asrc_in5 !! 670 dmic3_port: port@1 {
2133 reg = !! 671 reg = <1>;
2134 672
2135 xbar_ !! 673 dmic3_dap_ep: endpoint {
2136 !! 674 /* Place holder for external Codec */
>> 675 };
2137 }; 676 };
2138 }; 677 };
>> 678 };
2139 679
2140 port@6c { !! 680 dspk@2905000 {
2141 reg = !! 681 status = "okay";
2142 682
2143 xbar_ !! 683 ports {
2144 !! 684 #address-cells = <1>;
2145 }; !! 685 #size-cells = <0>;
2146 }; <<
2147 686
2148 xbar_asrc_in6 !! 687 port@0 {
2149 reg = !! 688 reg = <0>;
2150 689
2151 xbar_ !! 690 dspk1_cif_ep: endpoint {
2152 !! 691 remote-endpoint = <&xbar_dspk1_ep>;
>> 692 };
2153 }; 693 };
2154 }; <<
2155 694
2156 port@6e { !! 695 dspk1_port: port@1 {
2157 reg = !! 696 reg = <1>;
2158 697
2159 xbar_ !! 698 dspk1_dap_ep: endpoint {
2160 !! 699 /* Place holder for external Codec */
>> 700 };
2161 }; 701 };
2162 }; 702 };
>> 703 };
2163 704
2164 xbar_asrc_in7 !! 705 dspk@2905100 {
2165 reg = !! 706 status = "okay";
2166 707
2167 xbar_ !! 708 ports {
2168 !! 709 #address-cells = <1>;
2169 }; !! 710 #size-cells = <0>;
2170 }; <<
2171 711
2172 xbar_ope1_in_ !! 712 port@0 {
2173 reg = !! 713 reg = <0>;
2174 714
2175 xbar_ !! 715 dspk2_cif_ep: endpoint {
2176 !! 716 remote-endpoint = <&xbar_dspk2_ep>;
>> 717 };
2177 }; 718 };
2178 }; <<
2179 719
2180 port@71 { !! 720 dspk2_port: port@1 {
2181 reg = !! 721 reg = <1>;
2182 722
2183 xbar_ !! 723 dspk2_dap_ep: endpoint {
2184 !! 724 /* Place holder for external Codec */
>> 725 };
2185 }; 726 };
2186 }; 727 };
2187 }; 728 };
2188 }; 729 };
2189 <<
2190 dma-controller@2930000 { <<
2191 status = "okay"; <<
2192 }; <<
2193 <<
2194 interrupt-controller@2a40000 <<
2195 status = "okay"; <<
2196 }; <<
2197 }; 730 };
2198 731
2199 i2c@3160000 { 732 i2c@3160000 {
2200 power-monitor@42 { 733 power-monitor@42 {
2201 compatible = "ti,ina3 734 compatible = "ti,ina3221";
2202 reg = <0x42>; 735 reg = <0x42>;
2203 #address-cells = <1>; 736 #address-cells = <1>;
2204 #size-cells = <0>; 737 #size-cells = <0>;
2205 738
2206 input@0 { !! 739 channel@0 {
2207 reg = <0x0>; 740 reg = <0x0>;
2208 label = "VDD_ 741 label = "VDD_MUX";
2209 shunt-resisto 742 shunt-resistor-micro-ohms = <20000>;
2210 }; 743 };
2211 744
2212 input@1 { !! 745 channel@1 {
2213 reg = <0x1>; 746 reg = <0x1>;
2214 label = "VDD_ 747 label = "VDD_5V0_IO_SYS";
2215 shunt-resisto 748 shunt-resistor-micro-ohms = <5000>;
2216 }; 749 };
2217 750
2218 input@2 { !! 751 channel@2 {
2219 reg = <0x2>; 752 reg = <0x2>;
2220 label = "VDD_ 753 label = "VDD_3V3_SYS";
2221 shunt-resisto 754 shunt-resistor-micro-ohms = <10000>;
2222 }; 755 };
2223 }; 756 };
2224 757
2225 power-monitor@43 { 758 power-monitor@43 {
2226 compatible = "ti,ina3 759 compatible = "ti,ina3221";
2227 reg = <0x43>; 760 reg = <0x43>;
2228 #address-cells = <1>; 761 #address-cells = <1>;
2229 #size-cells = <0>; 762 #size-cells = <0>;
2230 763
2231 input@0 { !! 764 channel@0 {
2232 reg = <0x0>; 765 reg = <0x0>;
2233 label = "VDD_ 766 label = "VDD_3V3_IO_SLP";
2234 shunt-resisto 767 shunt-resistor-micro-ohms = <10000>;
2235 }; 768 };
2236 769
2237 input@1 { !! 770 channel@1 {
2238 reg = <0x1>; 771 reg = <0x1>;
2239 label = "VDD_ 772 label = "VDD_1V8_IO";
2240 shunt-resisto 773 shunt-resistor-micro-ohms = <10000>;
2241 }; 774 };
2242 775
2243 input@2 { !! 776 channel@2 {
2244 reg = <0x2>; 777 reg = <0x2>;
2245 label = "VDD_ 778 label = "VDD_M2_IN";
2246 shunt-resisto 779 shunt-resistor-micro-ohms = <10000>;
2247 }; 780 };
2248 }; 781 };
2249 782
2250 exp1: gpio@74 { 783 exp1: gpio@74 {
2251 compatible = "ti,tca9 784 compatible = "ti,tca9539";
2252 reg = <0x74>; 785 reg = <0x74>;
2253 786
2254 interrupt-parent = <& 787 interrupt-parent = <&gpio>;
2255 interrupts = <TEGRA18 788 interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
2256 GPIO_AC 789 GPIO_ACTIVE_LOW>;
2257 790
2258 #gpio-cells = <2>; 791 #gpio-cells = <2>;
2259 gpio-controller; 792 gpio-controller;
2260 793
2261 vcc-supply = <&vdd_3v 794 vcc-supply = <&vdd_3v3_sys>;
2262 }; 795 };
2263 796
2264 exp2: gpio@77 { 797 exp2: gpio@77 {
2265 compatible = "ti,tca9 798 compatible = "ti,tca9539";
2266 reg = <0x77>; 799 reg = <0x77>;
2267 800
2268 interrupt-parent = <& 801 interrupt-parent = <&gpio>;
2269 interrupts = <TEGRA18 802 interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
2270 GPIO_AC 803 GPIO_ACTIVE_LOW>;
2271 804
2272 #gpio-cells = <2>; 805 #gpio-cells = <2>;
2273 gpio-controller; 806 gpio-controller;
2274 807
2275 vcc-supply = <&vdd_1v 808 vcc-supply = <&vdd_1v8>;
2276 }; 809 };
2277 }; 810 };
2278 811
2279 /* SDMMC1 (SD/MMC) */ 812 /* SDMMC1 (SD/MMC) */
2280 mmc@3400000 { 813 mmc@3400000 {
2281 status = "okay"; 814 status = "okay";
2282 815
2283 vmmc-supply = <&vdd_sd>; 816 vmmc-supply = <&vdd_sd>;
2284 }; 817 };
2285 818
2286 sata@3507000 { <<
2287 status = "okay"; <<
2288 }; <<
2289 <<
2290 hda@3510000 { 819 hda@3510000 {
2291 nvidia,model = "NVIDIA Jetson 820 nvidia,model = "NVIDIA Jetson TX2 HDA";
2292 status = "okay"; 821 status = "okay";
2293 }; 822 };
2294 823
2295 padctl@3520000 { 824 padctl@3520000 {
2296 status = "okay"; 825 status = "okay";
2297 826
2298 avdd-pll-erefeut-supply = <&v 827 avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
2299 avdd-usb-supply = <&vdd_3v3_s 828 avdd-usb-supply = <&vdd_3v3_sys>;
2300 vclamp-usb-supply = <&vdd_1v8 829 vclamp-usb-supply = <&vdd_1v8>;
2301 vddio-hsic-supply = <&gnd>; 830 vddio-hsic-supply = <&gnd>;
2302 831
2303 pads { 832 pads {
2304 usb2 { 833 usb2 {
2305 status = "oka 834 status = "okay";
2306 835
2307 lanes { 836 lanes {
2308 micro 837 micro_b: usb2-0 {
2309 838 nvidia,function = "xusb";
2310 839 status = "okay";
2311 }; 840 };
2312 841
2313 usb2- 842 usb2-1 {
2314 843 nvidia,function = "xusb";
2315 844 status = "okay";
2316 }; 845 };
2317 846
2318 usb2- 847 usb2-2 {
2319 848 nvidia,function = "xusb";
2320 849 status = "okay";
2321 }; 850 };
2322 }; 851 };
2323 }; 852 };
2324 853
2325 usb3 { 854 usb3 {
2326 status = "oka 855 status = "okay";
2327 856
2328 lanes { 857 lanes {
2329 usb3- 858 usb3-0 {
2330 859 nvidia,function = "xusb";
2331 860 status = "okay";
2332 }; 861 };
2333 862
2334 usb3- 863 usb3-1 {
2335 864 nvidia,function = "xusb";
2336 865 status = "okay";
2337 }; 866 };
2338 867
2339 usb3- 868 usb3-2 {
2340 869 nvidia,function = "xusb";
2341 870 status = "okay";
2342 }; 871 };
2343 }; 872 };
2344 }; 873 };
2345 }; 874 };
2346 875
2347 ports { 876 ports {
2348 usb2-0 { 877 usb2-0 {
2349 status = "oka 878 status = "okay";
2350 mode = "otg"; 879 mode = "otg";
2351 vbus-supply = 880 vbus-supply = <&vdd_usb0>;
2352 usb-role-swit 881 usb-role-switch;
2353 882
2354 connector { 883 connector {
2355 compa 884 compatible = "gpio-usb-b-connector",
2356 885 "usb-b-connector";
2357 label 886 label = "micro-USB";
2358 type 887 type = "micro";
2359 vbus- 888 vbus-gpios = <&gpio
2360 889 TEGRA186_MAIN_GPIO(X, 7)
2361 890 GPIO_ACTIVE_LOW>;
2362 id-gp 891 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
2363 }; 892 };
2364 }; 893 };
2365 894
2366 usb2-1 { 895 usb2-1 {
2367 status = "oka 896 status = "okay";
2368 mode = "host" 897 mode = "host";
2369 898
2370 vbus-supply = 899 vbus-supply = <&vdd_usb1>;
2371 }; 900 };
2372 901
2373 usb3-0 { 902 usb3-0 {
2374 nvidia,usb2-c 903 nvidia,usb2-companion = <1>;
2375 vbus-supply = 904 vbus-supply = <&vdd_usb1>;
2376 status = "oka 905 status = "okay";
2377 }; 906 };
2378 }; 907 };
2379 }; 908 };
2380 909
2381 usb@3530000 { 910 usb@3530000 {
2382 status = "okay"; 911 status = "okay";
2383 912
2384 phys = <&{/padctl@3520000/pads 913 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
2385 <&{/padctl@3520000/pads 914 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
2386 <&{/padctl@3520000/pads 915 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
2387 phy-names = "usb2-0", "usb2-1 916 phy-names = "usb2-0", "usb2-1", "usb3-0";
2388 }; 917 };
2389 918
2390 usb@3550000 { 919 usb@3550000 {
2391 status = "okay"; 920 status = "okay";
2392 921
2393 phys = <µ_b>; 922 phys = <µ_b>;
2394 phy-names = "usb2-0"; 923 phy-names = "usb2-0";
2395 }; 924 };
2396 925
2397 i2c@c250000 { 926 i2c@c250000 {
2398 /* carrier board ID EEPROM */ 927 /* carrier board ID EEPROM */
2399 eeprom@57 { 928 eeprom@57 {
2400 compatible = "atmel,2 929 compatible = "atmel,24c02";
2401 reg = <0x57>; 930 reg = <0x57>;
2402 931
2403 label = "system"; 932 label = "system";
2404 vcc-supply = <&vdd_1v 933 vcc-supply = <&vdd_1v8>;
2405 address-width = <8>; 934 address-width = <8>;
2406 pagesize = <8>; 935 pagesize = <8>;
2407 size = <256>; 936 size = <256>;
2408 read-only; 937 read-only;
2409 }; 938 };
2410 }; 939 };
2411 940
2412 pcie@10003000 { 941 pcie@10003000 {
2413 status = "okay"; 942 status = "okay";
2414 943
2415 dvdd-pex-supply = <&vdd_pex>; 944 dvdd-pex-supply = <&vdd_pex>;
2416 hvdd-pex-pll-supply = <&vdd_1 945 hvdd-pex-pll-supply = <&vdd_1v8>;
2417 hvdd-pex-supply = <&vdd_1v8>; 946 hvdd-pex-supply = <&vdd_1v8>;
2418 vddio-pexctl-aud-supply = <&v 947 vddio-pexctl-aud-supply = <&vdd_1v8>;
2419 948
2420 pci@1,0 { 949 pci@1,0 {
2421 nvidia,num-lanes = <4 950 nvidia,num-lanes = <4>;
2422 status = "okay"; 951 status = "okay";
2423 }; 952 };
2424 953
2425 pci@2,0 { 954 pci@2,0 {
2426 nvidia,num-lanes = <0 955 nvidia,num-lanes = <0>;
2427 status = "disabled"; 956 status = "disabled";
2428 }; 957 };
2429 958
2430 pci@3,0 { 959 pci@3,0 {
2431 nvidia,num-lanes = <1 960 nvidia,num-lanes = <1>;
2432 status = "disabled"; 961 status = "disabled";
2433 }; 962 };
2434 }; 963 };
2435 964
2436 host1x@13e00000 { 965 host1x@13e00000 {
2437 status = "okay"; 966 status = "okay";
2438 967
2439 dpaux@15040000 { 968 dpaux@15040000 {
2440 status = "okay"; 969 status = "okay";
2441 }; 970 };
2442 971
2443 display-hub@15200000 { 972 display-hub@15200000 {
2444 status = "okay"; 973 status = "okay";
2445 }; 974 };
2446 975
2447 dsi@15300000 { 976 dsi@15300000 {
2448 status = "disabled"; 977 status = "disabled";
2449 }; 978 };
2450 979
2451 /* DP on E3320 */ 980 /* DP on E3320 */
2452 sor@15540000 { 981 sor@15540000 {
2453 status = "okay"; 982 status = "okay";
2454 983
2455 avdd-io-hdmi-dp-suppl 984 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2456 vdd-hdmi-dp-pll-suppl 985 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2457 986
2458 nvidia,dpaux = <&dpau 987 nvidia,dpaux = <&dpaux>;
2459 }; 988 };
2460 989
2461 sor@15580000 { 990 sor@15580000 {
2462 status = "okay"; 991 status = "okay";
2463 992
2464 avdd-io-hdmi-dp-suppl 993 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2465 vdd-hdmi-dp-pll-suppl 994 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2466 hdmi-supply = <&vdd_h 995 hdmi-supply = <&vdd_hdmi>;
2467 996
2468 nvidia,ddc-i2c-bus = 997 nvidia,ddc-i2c-bus = <&ddc>;
2469 nvidia,hpd-gpio = <&g 998 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
2470 999 GPIO_ACTIVE_LOW>;
2471 }; 1000 };
2472 1001
2473 dpaux@155c0000 { 1002 dpaux@155c0000 {
2474 status = "okay"; 1003 status = "okay";
2475 }; 1004 };
2476 }; 1005 };
2477 1006
>> 1007 sata@3507000 {
>> 1008 status = "okay";
>> 1009 };
>> 1010
2478 gpio-keys { 1011 gpio-keys {
2479 compatible = "gpio-keys"; 1012 compatible = "gpio-keys";
2480 1013
2481 key-power { !! 1014 power {
2482 label = "Power"; 1015 label = "Power";
2483 gpios = <&gpio_aon TE 1016 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
2484 GP 1017 GPIO_ACTIVE_LOW>;
2485 linux,input-type = <E 1018 linux,input-type = <EV_KEY>;
2486 linux,code = <KEY_POW 1019 linux,code = <KEY_POWER>;
2487 debounce-interval = < 1020 debounce-interval = <10>;
2488 wakeup-event-action = 1021 wakeup-event-action = <EV_ACT_ASSERTED>;
2489 wakeup-source; 1022 wakeup-source;
2490 }; 1023 };
2491 1024
2492 key-volume-down { !! 1025 volume-up {
2493 label = "Volume Down" !! 1026 label = "Volume Up";
2494 gpios = <&gpio_aon TE !! 1027 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
2495 GP 1028 GPIO_ACTIVE_LOW>;
2496 linux,input-type = <E 1029 linux,input-type = <EV_KEY>;
2497 linux,code = <KEY_VOL !! 1030 linux,code = <KEY_VOLUMEUP>;
2498 debounce-interval = < 1031 debounce-interval = <10>;
2499 }; 1032 };
2500 1033
2501 key-volume-up { !! 1034 volume-down {
2502 label = "Volume Up"; !! 1035 label = "Volume Down";
2503 gpios = <&gpio_aon TE !! 1036 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
2504 GP 1037 GPIO_ACTIVE_LOW>;
2505 linux,input-type = <E 1038 linux,input-type = <EV_KEY>;
2506 linux,code = <KEY_VOL !! 1039 linux,code = <KEY_VOLUMEDOWN>;
2507 debounce-interval = < 1040 debounce-interval = <10>;
2508 }; 1041 };
2509 }; 1042 };
2510 1043
2511 vdd_sd: regulator-vdd-sd { !! 1044 vdd_sd: regulator@100 {
2512 compatible = "regulator-fixed 1045 compatible = "regulator-fixed";
2513 regulator-name = "SD_CARD_SW_ 1046 regulator-name = "SD_CARD_SW_PWR";
2514 regulator-min-microvolt = <33 1047 regulator-min-microvolt = <3300000>;
2515 regulator-max-microvolt = <33 1048 regulator-max-microvolt = <3300000>;
2516 1049
2517 gpio = <&gpio TEGRA186_MAIN_G 1050 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
2518 enable-active-high; 1051 enable-active-high;
2519 1052
2520 vin-supply = <&vdd_3v3_sys>; 1053 vin-supply = <&vdd_3v3_sys>;
2521 }; 1054 };
2522 1055
2523 vdd_hdmi: regulator-vdd-hdmi { !! 1056 vdd_hdmi: regulator@101 {
2524 compatible = "regulator-fixed 1057 compatible = "regulator-fixed";
2525 regulator-name = "VDD_HDMI_5V 1058 regulator-name = "VDD_HDMI_5V0";
2526 regulator-min-microvolt = <50 1059 regulator-min-microvolt = <5000000>;
2527 regulator-max-microvolt = <50 1060 regulator-max-microvolt = <5000000>;
2528 1061
2529 gpio = <&exp1 14 GPIO_ACTIVE_ 1062 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
2530 enable-active-high; 1063 enable-active-high;
2531 1064
2532 vin-supply = <&vdd_5v0_sys>; 1065 vin-supply = <&vdd_5v0_sys>;
2533 }; 1066 };
2534 1067
2535 vdd_usb0: regulator-vdd-usb0 { !! 1068 vdd_usb0: regulator@102 {
2536 compatible = "regulator-fixed 1069 compatible = "regulator-fixed";
2537 regulator-name = "VDD_USB0"; 1070 regulator-name = "VDD_USB0";
2538 regulator-min-microvolt = <50 1071 regulator-min-microvolt = <5000000>;
2539 regulator-max-microvolt = <50 1072 regulator-max-microvolt = <5000000>;
2540 1073
2541 gpio = <&gpio TEGRA186_MAIN_G 1074 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
2542 enable-active-high; 1075 enable-active-high;
2543 1076
2544 vin-supply = <&vdd_5v0_sys>; 1077 vin-supply = <&vdd_5v0_sys>;
2545 }; 1078 };
2546 1079
2547 vdd_usb1: regulator-vdd-usb1 { !! 1080 vdd_usb1: regulator@103 {
2548 compatible = "regulator-fixed 1081 compatible = "regulator-fixed";
2549 regulator-name = "VDD_USB1"; 1082 regulator-name = "VDD_USB1";
2550 regulator-min-microvolt = <50 1083 regulator-min-microvolt = <5000000>;
2551 regulator-max-microvolt = <50 1084 regulator-max-microvolt = <5000000>;
2552 1085
2553 gpio = <&gpio TEGRA186_MAIN_G 1086 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
2554 enable-active-high; 1087 enable-active-high;
2555 1088
2556 vin-supply = <&vdd_5v0_sys>; 1089 vin-supply = <&vdd_5v0_sys>;
2557 }; 1090 };
2558 1091
2559 sound { 1092 sound {
2560 compatible = "nvidia,tegra186 1093 compatible = "nvidia,tegra186-audio-graph-card";
2561 status = "okay"; 1094 status = "okay";
2562 1095
2563 dais = /* FE */ 1096 dais = /* FE */
2564 <&admaif0_port>, <&adm 1097 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
2565 <&admaif4_port>, <&adm 1098 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
2566 <&admaif8_port>, <&adm 1099 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
2567 <&admaif12_port>, <&ad 1100 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
2568 <&admaif16_port>, <&ad 1101 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
2569 /* Router */ 1102 /* Router */
2570 <&xbar_i2s1_port>, <&x 1103 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
2571 <&xbar_i2s4_port>, <&x 1104 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
2572 <&xbar_dmic1_port>, <& 1105 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
2573 <&xbar_dspk1_port>, <& 1106 <&xbar_dspk1_port>, <&xbar_dspk2_port>,
2574 <&xbar_sfc1_in_port>, <<
2575 <&xbar_sfc3_in_port>, <<
2576 <&xbar_mvc1_in_port>, <<
2577 <&xbar_amx1_in1_port>, <<
2578 <&xbar_amx1_in3_port>, <<
2579 <&xbar_amx2_in1_port>, <<
2580 <&xbar_amx2_in3_port>, <<
2581 <&xbar_amx3_in1_port>, <<
2582 <&xbar_amx3_in3_port>, <<
2583 <&xbar_amx4_in1_port>, <<
2584 <&xbar_amx4_in3_port>, <<
2585 <&xbar_adx1_in_port>, <<
2586 <&xbar_adx3_in_port>, <<
2587 <&xbar_mixer_in1_port> <<
2588 <&xbar_mixer_in3_port> <<
2589 <&xbar_mixer_in5_port> <<
2590 <&xbar_mixer_in7_port> <<
2591 <&xbar_mixer_in9_port> <<
2592 <&xbar_asrc_in1_port>, <<
2593 <&xbar_asrc_in3_port>, <<
2594 <&xbar_asrc_in5_port>, <<
2595 <&xbar_asrc_in7_port>, <<
2596 <&xbar_ope1_in_port>, <<
2597 /* HW accelerators */ <<
2598 <&sfc1_out_port>, <&sf <<
2599 <&sfc3_out_port>, <&sf <<
2600 <&mvc1_out_port>, <&mv <<
2601 <&amx1_out_port>, <&am <<
2602 <&amx3_out_port>, <&am <<
2603 <&adx1_out1_port>, <&a <<
2604 <&adx1_out3_port>, <&a <<
2605 <&adx2_out1_port>, <&a <<
2606 <&adx2_out3_port>, <&a <<
2607 <&adx3_out1_port>, <&a <<
2608 <&adx3_out3_port>, <&a <<
2609 <&adx4_out1_port>, <&a <<
2610 <&adx4_out3_port>, <&a <<
2611 <&mixer_out1_port>, <& <<
2612 <&mixer_out3_port>, <& <<
2613 <&mixer_out5_port>, <<
2614 <&asrc_out1_port>, <&a <<
2615 <&asrc_out4_port>, <&a <<
2616 <&ope1_out_port>, <<
2617 /* I/O */ 1107 /* I/O */
2618 <&i2s1_port>, <&i2s2_p 1108 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
2619 <&i2s5_port>, <&i2s6_p 1109 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
2620 <&dmic3_port>, <&dspk1 1110 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
2621 1111
2622 label = "NVIDIA Jetson TX2 AP 1112 label = "NVIDIA Jetson TX2 APE";
2623 }; 1113 };
2624 }; 1114 };
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