1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/linux-event-codes. 4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/gpio-keys.h>
6 6
7 #include "tegra186-p3310.dtsi" 7 #include "tegra186-p3310.dtsi"
8 8
9 / { 9 / {
10 model = "NVIDIA Jetson TX2 Developer K 10 model = "NVIDIA Jetson TX2 Developer Kit";
11 compatible = "nvidia,p2771-0000", "nvi 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
12 12
13 aconnect@2900000 { 13 aconnect@2900000 {
14 status = "okay"; 14 status = "okay";
15 15
16 ahub@2900800 { !! 16 dma-controller@2930000 {
17 status = "okay"; 17 status = "okay";
>> 18 };
18 19
19 i2s@2901000 { !! 20 interrupt-controller@2a40000 {
20 status = "okay !! 21 status = "okay";
21 !! 22 };
22 ports { <<
23 #addre <<
24 #size- <<
25 23
26 port@0 !! 24 ahub@2900800 {
27 !! 25 status = "okay";
28 26
29 !! 27 ports {
30 !! 28 #address-cells = <1>;
31 !! 29 #size-cells = <0>;
32 }; <<
33 30
34 i2s1_p !! 31 port@0 {
35 !! 32 reg = <0x0>;
36 33
37 !! 34 xbar_admaif0_ep: endpoint {
38 !! 35 remote-endpoint = <&admaif0_ep>;
39 <<
40 <<
41 }; 36 };
42 }; 37 };
43 }; <<
44 <<
45 i2s@2901100 { <<
46 status = "okay <<
47 <<
48 ports { <<
49 #addre <<
50 #size- <<
51 38
52 port@0 !! 39 port@1 {
53 !! 40 reg = <0x1>;
54 41
55 !! 42 xbar_admaif1_ep: endpoint {
56 !! 43 remote-endpoint = <&admaif1_ep>;
57 <<
58 }; 44 };
>> 45 };
59 46
60 i2s2_p !! 47 port@2 {
61 !! 48 reg = <0x2>;
62 49
63 !! 50 xbar_admaif2_ep: endpoint {
64 !! 51 remote-endpoint = <&admaif2_ep>;
65 <<
66 <<
67 }; 52 };
68 }; 53 };
69 }; <<
70 <<
71 i2s@2901200 { <<
72 status = "okay <<
73 54
74 ports { !! 55 port@3 {
75 #addre !! 56 reg = <0x3>;
76 #size- <<
77 <<
78 port@0 <<
79 <<
80 57
81 !! 58 xbar_admaif3_ep: endpoint {
82 !! 59 remote-endpoint = <&admaif3_ep>;
83 <<
84 }; 60 };
>> 61 };
85 62
86 i2s3_p !! 63 port@4 {
87 !! 64 reg = <0x4>;
88 65
89 !! 66 xbar_admaif4_ep: endpoint {
90 !! 67 remote-endpoint = <&admaif4_ep>;
91 <<
92 <<
93 }; 68 };
94 }; 69 };
95 }; <<
96 70
97 i2s@2901300 { !! 71 port@5 {
98 status = "okay !! 72 reg = <0x5>;
99 <<
100 ports { <<
101 #addre <<
102 #size- <<
103 <<
104 port@0 <<
105 <<
106 73
107 !! 74 xbar_admaif5_ep: endpoint {
108 !! 75 remote-endpoint = <&admaif5_ep>;
109 <<
110 }; 76 };
>> 77 };
111 78
112 i2s4_p !! 79 port@6 {
113 !! 80 reg = <0x6>;
114 81
115 !! 82 xbar_admaif6_ep: endpoint {
116 !! 83 remote-endpoint = <&admaif6_ep>;
117 <<
118 <<
119 }; 84 };
120 }; 85 };
121 }; <<
122 86
123 i2s@2901400 { !! 87 port@7 {
124 status = "okay !! 88 reg = <0x7>;
125 89
126 ports { !! 90 xbar_admaif7_ep: endpoint {
127 #addre !! 91 remote-endpoint = <&admaif7_ep>;
128 #size- !! 92 };
>> 93 };
129 94
130 port@0 !! 95 port@8 {
131 !! 96 reg = <0x8>;
132 97
133 !! 98 xbar_admaif8_ep: endpoint {
134 !! 99 remote-endpoint = <&admaif8_ep>;
135 <<
136 }; 100 };
>> 101 };
137 102
138 i2s5_p !! 103 port@9 {
139 !! 104 reg = <0x9>;
140 105
141 !! 106 xbar_admaif9_ep: endpoint {
142 !! 107 remote-endpoint = <&admaif9_ep>;
143 <<
144 <<
145 }; 108 };
146 }; 109 };
147 }; <<
148 110
149 i2s@2901500 { !! 111 port@a {
150 status = "okay !! 112 reg = <0xa>;
151 113
152 ports { !! 114 xbar_admaif10_ep: endpoint {
153 #addre !! 115 remote-endpoint = <&admaif10_ep>;
154 #size- !! 116 };
>> 117 };
155 118
156 port@0 !! 119 port@b {
157 !! 120 reg = <0xb>;
158 121
159 !! 122 xbar_admaif11_ep: endpoint {
160 !! 123 remote-endpoint = <&admaif11_ep>;
161 <<
162 }; 124 };
>> 125 };
163 126
164 i2s6_p !! 127 port@c {
165 !! 128 reg = <0xc>;
166 129
167 !! 130 xbar_admaif12_ep: endpoint {
168 !! 131 remote-endpoint = <&admaif12_ep>;
169 <<
170 <<
171 }; 132 };
172 }; 133 };
173 }; <<
174 134
175 sfc@2902000 { !! 135 port@d {
176 status = "okay !! 136 reg = <0xd>;
177 137
178 ports { !! 138 xbar_admaif13_ep: endpoint {
179 #addre !! 139 remote-endpoint = <&admaif13_ep>;
180 #size- !! 140 };
>> 141 };
181 142
182 port@0 !! 143 port@e {
183 !! 144 reg = <0xe>;
184 145
185 !! 146 xbar_admaif14_ep: endpoint {
186 !! 147 remote-endpoint = <&admaif14_ep>;
187 <<
188 <<
189 }; 148 };
>> 149 };
190 150
191 sfc1_o !! 151 port@f {
192 !! 152 reg = <0xf>;
193 153
194 !! 154 xbar_admaif15_ep: endpoint {
195 !! 155 remote-endpoint = <&admaif15_ep>;
196 <<
197 <<
198 }; 156 };
199 }; 157 };
200 }; <<
201 158
202 sfc@2902200 { !! 159 port@10 {
203 status = "okay !! 160 reg = <0x10>;
204 161
205 ports { !! 162 xbar_admaif16_ep: endpoint {
206 #addre !! 163 remote-endpoint = <&admaif16_ep>;
207 #size- !! 164 };
>> 165 };
208 166
209 port@0 !! 167 port@11 {
210 !! 168 reg = <0x11>;
211 169
212 !! 170 xbar_admaif17_ep: endpoint {
213 !! 171 remote-endpoint = <&admaif17_ep>;
214 <<
215 }; 172 };
>> 173 };
216 174
217 sfc2_o !! 175 port@12 {
218 !! 176 reg = <0x12>;
219 177
220 !! 178 xbar_admaif18_ep: endpoint {
221 !! 179 remote-endpoint = <&admaif18_ep>;
222 <<
223 }; 180 };
224 }; 181 };
225 }; <<
226 182
227 sfc@2902400 { !! 183 port@13 {
228 status = "okay !! 184 reg = <0x13>;
229 185
230 ports { !! 186 xbar_admaif19_ep: endpoint {
231 #addre !! 187 remote-endpoint = <&admaif19_ep>;
232 #size- !! 188 };
>> 189 };
233 190
234 port@0 !! 191 xbar_i2s1_port: port@14 {
235 !! 192 reg = <0x14>;
236 193
237 !! 194 xbar_i2s1_ep: endpoint {
238 !! 195 remote-endpoint = <&i2s1_cif_ep>;
239 <<
240 }; 196 };
>> 197 };
241 198
242 sfc3_o !! 199 xbar_i2s2_port: port@15 {
243 !! 200 reg = <0x15>;
244 201
245 !! 202 xbar_i2s2_ep: endpoint {
246 !! 203 remote-endpoint = <&i2s2_cif_ep>;
247 <<
248 }; 204 };
249 }; 205 };
250 }; <<
251 206
252 sfc@2902600 { !! 207 xbar_i2s3_port: port@16 {
253 status = "okay !! 208 reg = <0x16>;
254 209
255 ports { !! 210 xbar_i2s3_ep: endpoint {
256 #addre !! 211 remote-endpoint = <&i2s3_cif_ep>;
257 #size- !! 212 };
>> 213 };
258 214
259 port@0 !! 215 xbar_i2s4_port: port@17 {
260 !! 216 reg = <0x17>;
261 217
262 !! 218 xbar_i2s4_ep: endpoint {
263 !! 219 remote-endpoint = <&i2s4_cif_ep>;
264 <<
265 }; 220 };
>> 221 };
266 222
267 sfc4_o !! 223 xbar_i2s5_port: port@18 {
268 !! 224 reg = <0x18>;
269 225
270 !! 226 xbar_i2s5_ep: endpoint {
271 !! 227 remote-endpoint = <&i2s5_cif_ep>;
272 <<
273 }; 228 };
274 }; 229 };
275 }; <<
276 230
277 amx@2903000 { !! 231 xbar_i2s6_port: port@19 {
278 status = "okay !! 232 reg = <0x19>;
279 233
280 ports { !! 234 xbar_i2s6_ep: endpoint {
281 #addre !! 235 remote-endpoint = <&i2s6_cif_ep>;
282 #size- !! 236 };
>> 237 };
283 238
284 port@0 !! 239 xbar_dmic1_port: port@1a {
285 !! 240 reg = <0x1a>;
286 241
287 !! 242 xbar_dmic1_ep: endpoint {
288 !! 243 remote-endpoint = <&dmic1_cif_ep>;
289 <<
290 }; 244 };
>> 245 };
291 246
292 port@1 !! 247 xbar_dmic2_port: port@1b {
293 !! 248 reg = <0x1b>;
294 249
295 !! 250 xbar_dmic2_ep: endpoint {
296 !! 251 remote-endpoint = <&dmic2_cif_ep>;
297 <<
298 }; 252 };
>> 253 };
299 254
300 port@2 !! 255 xbar_dmic3_port: port@1c {
301 !! 256 reg = <0x1c>;
302 257
303 !! 258 xbar_dmic3_ep: endpoint {
304 !! 259 remote-endpoint = <&dmic3_cif_ep>;
305 <<
306 }; 260 };
>> 261 };
307 262
308 port@3 !! 263 xbar_dspk1_port: port@1e {
309 !! 264 reg = <0x1e>;
310 265
311 !! 266 xbar_dspk1_ep: endpoint {
312 !! 267 remote-endpoint = <&dspk1_cif_ep>;
313 <<
314 }; 268 };
>> 269 };
315 270
316 amx1_o !! 271 xbar_dspk2_port: port@1f {
317 !! 272 reg = <0x1f>;
318 273
319 !! 274 xbar_dspk2_ep: endpoint {
320 !! 275 remote-endpoint = <&dspk2_cif_ep>;
321 <<
322 }; 276 };
323 }; 277 };
324 }; <<
325 278
326 amx@2903100 { !! 279 xbar_sfc1_in_port: port@20 {
327 status = "okay !! 280 reg = <0x20>;
328 281
329 ports { !! 282 xbar_sfc1_in_ep: endpoint {
330 #addre !! 283 remote-endpoint = <&sfc1_cif_in_ep>;
331 #size- !! 284 };
>> 285 };
332 286
333 port@0 !! 287 port@21 {
334 !! 288 reg = <0x21>;
335 289
336 !! 290 xbar_sfc1_out_ep: endpoint {
337 !! 291 remote-endpoint = <&sfc1_cif_out_ep>;
338 <<
339 }; 292 };
>> 293 };
340 294
341 port@1 !! 295 xbar_sfc2_in_port: port@22 {
342 !! 296 reg = <0x22>;
343 297
344 !! 298 xbar_sfc2_in_ep: endpoint {
345 !! 299 remote-endpoint = <&sfc2_cif_in_ep>;
346 <<
347 }; 300 };
>> 301 };
348 302
349 amx2_i !! 303 port@23 {
350 !! 304 reg = <0x23>;
351 305
352 !! 306 xbar_sfc2_out_ep: endpoint {
353 !! 307 remote-endpoint = <&sfc2_cif_out_ep>;
354 <<
355 }; 308 };
>> 309 };
356 310
357 amx2_i !! 311 xbar_sfc3_in_port: port@24 {
358 !! 312 reg = <0x24>;
359 313
360 !! 314 xbar_sfc3_in_ep: endpoint {
361 !! 315 remote-endpoint = <&sfc3_cif_in_ep>;
362 <<
363 }; 316 };
>> 317 };
364 318
365 amx2_o !! 319 port@25 {
366 !! 320 reg = <0x25>;
367 321
368 !! 322 xbar_sfc3_out_ep: endpoint {
369 !! 323 remote-endpoint = <&sfc3_cif_out_ep>;
370 <<
371 }; 324 };
372 }; 325 };
373 }; <<
374 326
375 amx@2903200 { !! 327 xbar_sfc4_in_port: port@26 {
376 status = "okay !! 328 reg = <0x26>;
377 329
378 ports { !! 330 xbar_sfc4_in_ep: endpoint {
379 #addre !! 331 remote-endpoint = <&sfc4_cif_in_ep>;
380 #size- !! 332 };
>> 333 };
381 334
382 port@0 !! 335 port@27 {
383 !! 336 reg = <0x27>;
384 337
385 !! 338 xbar_sfc4_out_ep: endpoint {
386 !! 339 remote-endpoint = <&sfc4_cif_out_ep>;
387 <<
388 }; 340 };
>> 341 };
389 342
390 port@1 !! 343 xbar_mvc1_in_port: port@28 {
391 !! 344 reg = <0x28>;
392 345
393 !! 346 xbar_mvc1_in_ep: endpoint {
394 !! 347 remote-endpoint = <&mvc1_cif_in_ep>;
395 <<
396 }; 348 };
>> 349 };
397 350
398 port@2 !! 351 port@29 {
399 !! 352 reg = <0x29>;
400 353
401 !! 354 xbar_mvc1_out_ep: endpoint {
402 !! 355 remote-endpoint = <&mvc1_cif_out_ep>;
403 <<
404 }; 356 };
>> 357 };
405 358
406 port@3 !! 359 xbar_mvc2_in_port: port@2a {
407 !! 360 reg = <0x2a>;
408 361
409 !! 362 xbar_mvc2_in_ep: endpoint {
410 !! 363 remote-endpoint = <&mvc2_cif_in_ep>;
411 <<
412 }; 364 };
>> 365 };
413 366
414 amx3_o !! 367 port@2b {
415 !! 368 reg = <0x2b>;
416 369
417 !! 370 xbar_mvc2_out_ep: endpoint {
418 !! 371 remote-endpoint = <&mvc2_cif_out_ep>;
419 <<
420 }; 372 };
421 }; 373 };
422 }; <<
423 374
424 amx@2903300 { !! 375 xbar_amx1_in1_port: port@2c {
425 status = "okay !! 376 reg = <0x2c>;
426 377
427 ports { !! 378 xbar_amx1_in1_ep: endpoint {
428 #addre !! 379 remote-endpoint = <&amx1_in1_ep>;
429 #size- !! 380 };
>> 381 };
430 382
431 port@0 !! 383 xbar_amx1_in2_port: port@2d {
432 !! 384 reg = <0x2d>;
433 385
434 !! 386 xbar_amx1_in2_ep: endpoint {
435 !! 387 remote-endpoint = <&amx1_in2_ep>;
436 <<
437 }; 388 };
>> 389 };
438 390
439 port@1 !! 391 xbar_amx1_in3_port: port@2e {
440 !! 392 reg = <0x2e>;
441 393
442 !! 394 xbar_amx1_in3_ep: endpoint {
443 !! 395 remote-endpoint = <&amx1_in3_ep>;
444 <<
445 }; 396 };
>> 397 };
446 398
447 port@2 !! 399 xbar_amx1_in4_port: port@2f {
448 !! 400 reg = <0x2f>;
449 401
450 !! 402 xbar_amx1_in4_ep: endpoint {
451 !! 403 remote-endpoint = <&amx1_in4_ep>;
452 <<
453 }; 404 };
>> 405 };
454 406
455 port@3 !! 407 port@30 {
456 !! 408 reg = <0x30>;
457 409
458 !! 410 xbar_amx1_out_ep: endpoint {
459 !! 411 remote-endpoint = <&amx1_out_ep>;
460 <<
461 }; 412 };
>> 413 };
462 414
463 amx4_o !! 415 xbar_amx2_in1_port: port@31 {
464 !! 416 reg = <0x31>;
465 417
466 !! 418 xbar_amx2_in1_ep: endpoint {
467 !! 419 remote-endpoint = <&amx2_in1_ep>;
468 <<
469 }; 420 };
470 }; 421 };
471 }; <<
472 422
473 adx@2903800 { !! 423 xbar_amx2_in2_port: port@32 {
474 status = "okay !! 424 reg = <0x32>;
475 425
476 ports { !! 426 xbar_amx2_in2_ep: endpoint {
477 #addre !! 427 remote-endpoint = <&amx2_in2_ep>;
478 #size- !! 428 };
>> 429 };
479 430
480 port@0 !! 431 xbar_amx2_in3_port: port@33 {
481 !! 432 reg = <0x33>;
482 433
483 !! 434 xbar_amx2_in3_ep: endpoint {
484 !! 435 remote-endpoint = <&amx2_in3_ep>;
485 <<
486 }; 436 };
>> 437 };
487 438
488 adx1_o !! 439 xbar_amx2_in4_port: port@34 {
489 !! 440 reg = <0x34>;
490 441
491 !! 442 xbar_amx2_in4_ep: endpoint {
492 !! 443 remote-endpoint = <&amx2_in4_ep>;
493 <<
494 }; 444 };
>> 445 };
495 446
496 adx1_o !! 447 port@35 {
497 !! 448 reg = <0x35>;
498 449
499 !! 450 xbar_amx2_out_ep: endpoint {
500 !! 451 remote-endpoint = <&amx2_out_ep>;
501 <<
502 }; 452 };
>> 453 };
503 454
504 adx1_o !! 455 xbar_amx3_in1_port: port@36 {
505 !! 456 reg = <0x36>;
506 457
507 !! 458 xbar_amx3_in1_ep: endpoint {
508 !! 459 remote-endpoint = <&amx3_in1_ep>;
509 <<
510 }; 460 };
>> 461 };
511 462
512 adx1_o !! 463 xbar_amx3_in2_port: port@37 {
513 !! 464 reg = <0x37>;
514 465
515 !! 466 xbar_amx3_in2_ep: endpoint {
516 !! 467 remote-endpoint = <&amx3_in2_ep>;
517 <<
518 }; 468 };
519 }; 469 };
520 }; <<
521 470
522 adx@2903900 { !! 471 xbar_amx3_in3_port: port@38 {
523 status = "okay !! 472 reg = <0x38>;
524 473
525 ports { !! 474 xbar_amx3_in3_ep: endpoint {
526 #addre !! 475 remote-endpoint = <&amx3_in3_ep>;
527 #size- !! 476 };
>> 477 };
528 478
529 port@0 !! 479 xbar_amx3_in4_port: port@39 {
530 !! 480 reg = <0x39>;
531 481
532 !! 482 xbar_amx3_in4_ep: endpoint {
533 !! 483 remote-endpoint = <&amx3_in4_ep>;
534 <<
535 }; 484 };
>> 485 };
536 486
537 adx2_o !! 487 port@3a {
538 !! 488 reg = <0x3a>;
539 489
540 !! 490 xbar_amx3_out_ep: endpoint {
541 !! 491 remote-endpoint = <&amx3_out_ep>;
542 <<
543 }; 492 };
>> 493 };
544 494
545 adx2_o !! 495 xbar_amx4_in1_port: port@3b {
546 !! 496 reg = <0x3b>;
547 497
548 !! 498 xbar_amx4_in1_ep: endpoint {
549 !! 499 remote-endpoint = <&amx4_in1_ep>;
550 <<
551 }; 500 };
>> 501 };
552 502
553 adx2_o !! 503 xbar_amx4_in2_port: port@3c {
554 !! 504 reg = <0x3c>;
555 505
556 !! 506 xbar_amx4_in2_ep: endpoint {
557 !! 507 remote-endpoint = <&amx4_in2_ep>;
558 <<
559 }; 508 };
>> 509 };
560 510
561 adx2_o !! 511 xbar_amx4_in3_port: port@3d {
562 !! 512 reg = <0x3d>;
563 513
564 !! 514 xbar_amx4_in3_ep: endpoint {
565 !! 515 remote-endpoint = <&amx4_in3_ep>;
566 <<
567 }; 516 };
568 }; 517 };
569 }; <<
570 518
571 adx@2903a00 { !! 519 xbar_amx4_in4_port: port@3e {
572 status = "okay !! 520 reg = <0x3e>;
573 521
574 ports { !! 522 xbar_amx4_in4_ep: endpoint {
575 #addre !! 523 remote-endpoint = <&amx4_in4_ep>;
576 #size- !! 524 };
>> 525 };
577 526
578 port@0 !! 527 port@3f {
579 !! 528 reg = <0x3f>;
580 529
581 !! 530 xbar_amx4_out_ep: endpoint {
582 !! 531 remote-endpoint = <&amx4_out_ep>;
583 <<
584 }; 532 };
>> 533 };
585 534
586 adx3_o !! 535 xbar_adx1_in_port: port@40 {
587 !! 536 reg = <0x40>;
588 537
589 !! 538 xbar_adx1_in_ep: endpoint {
590 !! 539 remote-endpoint = <&adx1_in_ep>;
591 <<
592 }; 540 };
>> 541 };
593 542
594 adx3_o !! 543 port@41 {
595 !! 544 reg = <0x41>;
596 545
597 !! 546 xbar_adx1_out1_ep: endpoint {
598 !! 547 remote-endpoint = <&adx1_out1_ep>;
599 <<
600 }; 548 };
>> 549 };
601 550
602 adx3_o !! 551 port@42 {
603 !! 552 reg = <0x42>;
604 553
605 !! 554 xbar_adx1_out2_ep: endpoint {
606 !! 555 remote-endpoint = <&adx1_out2_ep>;
607 <<
608 }; 556 };
>> 557 };
609 558
610 adx3_o !! 559 port@43 {
611 !! 560 reg = <0x43>;
612 561
613 !! 562 xbar_adx1_out3_ep: endpoint {
614 !! 563 remote-endpoint = <&adx1_out3_ep>;
615 <<
616 }; 564 };
617 }; 565 };
618 }; <<
619 566
620 adx@2903b00 { !! 567 port@44 {
621 status = "okay !! 568 reg = <0x44>;
622 569
623 ports { !! 570 xbar_adx1_out4_ep: endpoint {
624 #addre !! 571 remote-endpoint = <&adx1_out4_ep>;
625 #size- !! 572 };
>> 573 };
626 574
627 port@0 !! 575 xbar_adx2_in_port: port@45 {
628 !! 576 reg = <0x45>;
629 577
630 !! 578 xbar_adx2_in_ep: endpoint {
631 !! 579 remote-endpoint = <&adx2_in_ep>;
632 <<
633 }; 580 };
>> 581 };
634 582
635 adx4_o !! 583 port@46 {
636 !! 584 reg = <0x46>;
637 585
638 !! 586 xbar_adx2_out1_ep: endpoint {
639 !! 587 remote-endpoint = <&adx2_out1_ep>;
640 <<
641 }; 588 };
>> 589 };
642 590
643 adx4_o !! 591 port@47 {
644 !! 592 reg = <0x47>;
645 593
646 !! 594 xbar_adx2_out2_ep: endpoint {
647 !! 595 remote-endpoint = <&adx2_out2_ep>;
648 <<
649 }; 596 };
>> 597 };
650 598
651 adx4_o !! 599 port@48 {
652 !! 600 reg = <0x48>;
653 601
654 !! 602 xbar_adx2_out3_ep: endpoint {
655 !! 603 remote-endpoint = <&adx2_out3_ep>;
656 <<
657 }; 604 };
>> 605 };
658 606
659 adx4_o !! 607 port@49 {
660 !! 608 reg = <0x49>;
661 609
662 !! 610 xbar_adx2_out4_ep: endpoint {
663 !! 611 remote-endpoint = <&adx2_out4_ep>;
664 <<
665 }; 612 };
666 }; 613 };
667 }; <<
668 614
669 dmic@2904000 { !! 615 xbar_adx3_in_port: port@4a {
670 status = "okay !! 616 reg = <0x4a>;
671 617
672 ports { !! 618 xbar_adx3_in_ep: endpoint {
673 #addre !! 619 remote-endpoint = <&adx3_in_ep>;
674 #size- !! 620 };
>> 621 };
675 622
676 port@0 !! 623 port@4b {
677 !! 624 reg = <0x4b>;
678 625
679 !! 626 xbar_adx3_out1_ep: endpoint {
680 !! 627 remote-endpoint = <&adx3_out1_ep>;
681 <<
682 }; 628 };
>> 629 };
683 630
684 dmic1_ !! 631 port@4c {
685 !! 632 reg = <0x4c>;
686 633
687 !! 634 xbar_adx3_out2_ep: endpoint {
688 !! 635 remote-endpoint = <&adx3_out2_ep>;
689 <<
690 }; 636 };
691 }; 637 };
692 }; <<
693 638
694 dmic@2904100 { !! 639 port@4d {
695 status = "okay !! 640 reg = <0x4d>;
696 641
697 ports { !! 642 xbar_adx3_out3_ep: endpoint {
698 #addre !! 643 remote-endpoint = <&adx3_out3_ep>;
699 #size- !! 644 };
>> 645 };
700 646
701 port@0 !! 647 port@4e {
702 !! 648 reg = <0x4e>;
703 649
704 !! 650 xbar_adx3_out4_ep: endpoint {
705 !! 651 remote-endpoint = <&adx3_out4_ep>;
706 <<
707 }; 652 };
>> 653 };
708 654
709 dmic2_ !! 655 xbar_adx4_in_port: port@4f {
710 !! 656 reg = <0x4f>;
711 657
712 !! 658 xbar_adx4_in_ep: endpoint {
713 !! 659 remote-endpoint = <&adx4_in_ep>;
714 <<
715 }; 660 };
716 }; 661 };
717 }; <<
718 662
719 dmic@2904200 { !! 663 port@50 {
720 status = "okay !! 664 reg = <0x50>;
721 665
722 ports { !! 666 xbar_adx4_out1_ep: endpoint {
723 #addre !! 667 remote-endpoint = <&adx4_out1_ep>;
724 #size- !! 668 };
>> 669 };
725 670
726 port@0 !! 671 port@51 {
727 !! 672 reg = <0x51>;
728 673
729 !! 674 xbar_adx4_out2_ep: endpoint {
730 !! 675 remote-endpoint = <&adx4_out2_ep>;
731 <<
732 }; 676 };
>> 677 };
733 678
734 dmic3_ !! 679 port@52 {
735 !! 680 reg = <0x52>;
736 681
737 !! 682 xbar_adx4_out3_ep: endpoint {
738 !! 683 remote-endpoint = <&adx4_out3_ep>;
739 <<
740 }; 684 };
741 }; 685 };
742 }; <<
743 686
744 dspk@2905000 { !! 687 port@53 {
745 status = "okay !! 688 reg = <0x53>;
746 689
747 ports { !! 690 xbar_adx4_out4_ep: endpoint {
748 #addre !! 691 remote-endpoint = <&adx4_out4_ep>;
749 #size- !! 692 };
>> 693 };
750 694
751 port@0 !! 695 xbar_mixer_in1_port: port@54 {
752 !! 696 reg = <0x54>;
753 697
754 !! 698 xbar_mixer_in1_ep: endpoint {
755 !! 699 remote-endpoint = <&mixer_in1_ep>;
756 <<
757 }; 700 };
>> 701 };
758 702
759 dspk1_ !! 703 xbar_mixer_in2_port: port@55 {
760 !! 704 reg = <0x55>;
761 705
762 !! 706 xbar_mixer_in2_ep: endpoint {
763 !! 707 remote-endpoint = <&mixer_in2_ep>;
764 <<
765 }; 708 };
766 }; 709 };
767 }; <<
768 710
769 dspk@2905100 { !! 711 xbar_mixer_in3_port: port@56 {
770 status = "okay !! 712 reg = <0x56>;
771 713
772 ports { !! 714 xbar_mixer_in3_ep: endpoint {
773 #addre !! 715 remote-endpoint = <&mixer_in3_ep>;
774 #size- !! 716 };
>> 717 };
775 718
776 port@0 !! 719 xbar_mixer_in4_port: port@57 {
777 !! 720 reg = <0x57>;
778 721
779 !! 722 xbar_mixer_in4_ep: endpoint {
780 !! 723 remote-endpoint = <&mixer_in4_ep>;
781 <<
782 }; 724 };
>> 725 };
783 726
784 dspk2_ !! 727 xbar_mixer_in5_port: port@58 {
785 !! 728 reg = <0x58>;
786 729
787 !! 730 xbar_mixer_in5_ep: endpoint {
788 !! 731 remote-endpoint = <&mixer_in5_ep>;
789 <<
790 }; 732 };
791 }; 733 };
792 }; <<
793 734
794 processing-engine@2908 !! 735 xbar_mixer_in6_port: port@59 {
795 status = "okay !! 736 reg = <0x59>;
796 737
797 ports { !! 738 xbar_mixer_in6_ep: endpoint {
798 #addre !! 739 remote-endpoint = <&mixer_in6_ep>;
799 #size- !! 740 };
>> 741 };
800 742
801 port@0 !! 743 xbar_mixer_in7_port: port@5a {
802 !! 744 reg = <0x5a>;
803 745
804 !! 746 xbar_mixer_in7_ep: endpoint {
805 !! 747 remote-endpoint = <&mixer_in7_ep>;
806 <<
807 }; 748 };
>> 749 };
808 750
809 ope1_o !! 751 xbar_mixer_in8_port: port@5b {
810 !! 752 reg = <0x5b>;
811 753
812 !! 754 xbar_mixer_in8_ep: endpoint {
813 !! 755 remote-endpoint = <&mixer_in8_ep>;
814 <<
815 }; 756 };
816 }; 757 };
817 }; <<
818 758
819 mvc@290a000 { !! 759 xbar_mixer_in9_port: port@5c {
820 status = "okay !! 760 reg = <0x5c>;
821 761
822 ports { !! 762 xbar_mixer_in9_ep: endpoint {
823 #addre !! 763 remote-endpoint = <&mixer_in9_ep>;
824 #size- !! 764 };
>> 765 };
825 766
826 port@0 !! 767 xbar_mixer_in10_port: port@5d {
827 !! 768 reg = <0x5d>;
828 769
829 !! 770 xbar_mixer_in10_ep: endpoint {
830 !! 771 remote-endpoint = <&mixer_in10_ep>;
831 <<
832 }; 772 };
>> 773 };
833 774
834 mvc1_o !! 775 port@5e {
835 !! 776 reg = <0x5e>;
836 777
837 !! 778 xbar_mixer_out1_ep: endpoint {
838 !! 779 remote-endpoint = <&mixer_out1_ep>;
839 <<
840 }; 780 };
841 }; 781 };
842 }; <<
843 782
844 mvc@290a200 { !! 783 port@5f {
845 status = "okay !! 784 reg = <0x5f>;
846 785
847 ports { !! 786 xbar_mixer_out2_ep: endpoint {
848 #addre !! 787 remote-endpoint = <&mixer_out2_ep>;
849 #size- !! 788 };
>> 789 };
850 790
851 port@0 !! 791 port@60 {
852 !! 792 reg = <0x60>;
853 793
854 !! 794 xbar_mixer_out3_ep: endpoint {
855 !! 795 remote-endpoint = <&mixer_out3_ep>;
856 <<
857 }; 796 };
>> 797 };
858 798
859 mvc2_o !! 799 port@61 {
860 !! 800 reg = <0x61>;
861 801
862 !! 802 xbar_mixer_out4_ep: endpoint {
863 !! 803 remote-endpoint = <&mixer_out4_ep>;
864 <<
865 }; 804 };
866 }; 805 };
867 }; <<
868 806
869 amixer@290bb00 { !! 807 port@62 {
870 status = "okay !! 808 reg = <0x62>;
871 809
872 ports { !! 810 xbar_mixer_out5_ep: endpoint {
873 #addre !! 811 remote-endpoint = <&mixer_out5_ep>;
874 #size- !! 812 };
>> 813 };
875 814
876 port@0 !! 815 xbar_asrc_in1_port: port@63 {
877 !! 816 reg = <0x63>;
878 817
879 !! 818 xbar_asrc_in1_ep: endpoint {
880 !! 819 remote-endpoint = <&asrc_in1_ep>;
881 <<
882 }; 820 };
>> 821 };
883 822
884 port@1 !! 823 port@64 {
885 !! 824 reg = <0x64>;
886 825
887 !! 826 xbar_asrc_out1_ep: endpoint {
888 !! 827 remote-endpoint = <&asrc_out1_ep>;
889 <<
890 }; 828 };
>> 829 };
891 830
892 port@2 !! 831 xbar_asrc_in2_port: port@65 {
893 !! 832 reg = <0x65>;
894 833
895 !! 834 xbar_asrc_in2_ep: endpoint {
896 !! 835 remote-endpoint = <&asrc_in2_ep>;
897 <<
898 }; 836 };
>> 837 };
899 838
900 port@3 !! 839 port@66 {
901 !! 840 reg = <0x66>;
902 841
903 !! 842 xbar_asrc_out2_ep: endpoint {
904 !! 843 remote-endpoint = <&asrc_out2_ep>;
905 <<
906 }; 844 };
>> 845 };
907 846
908 port@4 !! 847 xbar_asrc_in3_port: port@67 {
909 !! 848 reg = <0x67>;
910 849
911 !! 850 xbar_asrc_in3_ep: endpoint {
912 !! 851 remote-endpoint = <&asrc_in3_ep>;
913 <<
914 }; 852 };
>> 853 };
915 854
916 port@5 !! 855 port@68 {
917 !! 856 reg = <0x68>;
918 857
919 !! 858 xbar_asrc_out3_ep: endpoint {
920 !! 859 remote-endpoint = <&asrc_out3_ep>;
921 <<
922 }; 860 };
>> 861 };
923 862
924 port@6 !! 863 xbar_asrc_in4_port: port@69 {
925 !! 864 reg = <0x69>;
926 865
927 !! 866 xbar_asrc_in4_ep: endpoint {
928 !! 867 remote-endpoint = <&asrc_in4_ep>;
929 <<
930 }; 868 };
>> 869 };
931 870
932 port@7 !! 871 port@6a {
933 !! 872 reg = <0x6a>;
934 873
935 !! 874 xbar_asrc_out4_ep: endpoint {
936 !! 875 remote-endpoint = <&asrc_out4_ep>;
937 <<
938 }; 876 };
>> 877 };
939 878
940 port@8 !! 879 xbar_asrc_in5_port: port@6b {
941 !! 880 reg = <0x6b>;
942 881
943 !! 882 xbar_asrc_in5_ep: endpoint {
944 !! 883 remote-endpoint = <&asrc_in5_ep>;
945 <<
946 }; 884 };
>> 885 };
947 886
948 port@9 !! 887 port@6c {
949 !! 888 reg = <0x6c>;
950 889
951 !! 890 xbar_asrc_out5_ep: endpoint {
952 !! 891 remote-endpoint = <&asrc_out5_ep>;
953 <<
954 }; 892 };
>> 893 };
955 894
956 mixer_ !! 895 xbar_asrc_in6_port: port@6d {
957 !! 896 reg = <0x6d>;
958 897
959 !! 898 xbar_asrc_in6_ep: endpoint {
960 !! 899 remote-endpoint = <&asrc_in6_ep>;
961 <<
962 }; 900 };
>> 901 };
963 902
964 mixer_ !! 903 port@6e {
965 !! 904 reg = <0x6e>;
966 905
967 !! 906 xbar_asrc_out6_ep: endpoint {
968 !! 907 remote-endpoint = <&asrc_out6_ep>;
969 <<
970 }; 908 };
>> 909 };
971 910
972 mixer_ !! 911 xbar_asrc_in7_port: port@6f {
973 !! 912 reg = <0x6f>;
974 913
975 !! 914 xbar_asrc_in7_ep: endpoint {
976 !! 915 remote-endpoint = <&asrc_in7_ep>;
977 <<
978 }; 916 };
>> 917 };
979 918
980 mixer_ !! 919 xbar_ope1_in_port: port@70 {
981 !! 920 reg = <0x70>;
982 921
983 !! 922 xbar_ope1_in_ep: endpoint {
984 !! 923 remote-endpoint = <&ope1_cif_in_ep>;
985 <<
986 }; 924 };
>> 925 };
987 926
988 mixer_ !! 927 port@71 {
989 !! 928 reg = <0x71>;
990 929
991 !! 930 xbar_ope1_out_ep: endpoint {
992 !! 931 remote-endpoint = <&ope1_cif_out_ep>;
993 <<
994 }; 932 };
995 }; 933 };
996 }; 934 };
997 935
998 admaif@290f000 { 936 admaif@290f000 {
999 status = "okay 937 status = "okay";
1000 938
1001 ports { 939 ports {
1002 #addr 940 #address-cells = <1>;
1003 #size 941 #size-cells = <0>;
1004 942
1005 admai 943 admaif0_port: port@0 {
1006 944 reg = <0x0>;
1007 945
1008 946 admaif0_ep: endpoint {
1009 947 remote-endpoint = <&xbar_admaif0_ep>;
1010 948 };
1011 }; 949 };
1012 950
1013 admai 951 admaif1_port: port@1 {
1014 952 reg = <0x1>;
1015 953
1016 954 admaif1_ep: endpoint {
1017 955 remote-endpoint = <&xbar_admaif1_ep>;
1018 956 };
1019 }; 957 };
1020 958
1021 admai 959 admaif2_port: port@2 {
1022 960 reg = <0x2>;
1023 961
1024 962 admaif2_ep: endpoint {
1025 963 remote-endpoint = <&xbar_admaif2_ep>;
1026 964 };
1027 }; 965 };
1028 966
1029 admai 967 admaif3_port: port@3 {
1030 968 reg = <0x3>;
1031 969
1032 970 admaif3_ep: endpoint {
1033 971 remote-endpoint = <&xbar_admaif3_ep>;
1034 972 };
1035 }; 973 };
1036 974
1037 admai 975 admaif4_port: port@4 {
1038 976 reg = <0x4>;
1039 977
1040 978 admaif4_ep: endpoint {
1041 979 remote-endpoint = <&xbar_admaif4_ep>;
1042 980 };
1043 }; 981 };
1044 982
1045 admai 983 admaif5_port: port@5 {
1046 984 reg = <0x5>;
1047 985
1048 986 admaif5_ep: endpoint {
1049 987 remote-endpoint = <&xbar_admaif5_ep>;
1050 988 };
1051 }; 989 };
1052 990
1053 admai 991 admaif6_port: port@6 {
1054 992 reg = <0x6>;
1055 993
1056 994 admaif6_ep: endpoint {
1057 995 remote-endpoint = <&xbar_admaif6_ep>;
1058 996 };
1059 }; 997 };
1060 998
1061 admai 999 admaif7_port: port@7 {
1062 1000 reg = <0x7>;
1063 1001
1064 1002 admaif7_ep: endpoint {
1065 1003 remote-endpoint = <&xbar_admaif7_ep>;
1066 1004 };
1067 }; 1005 };
1068 1006
1069 admai 1007 admaif8_port: port@8 {
1070 1008 reg = <0x8>;
1071 1009
1072 1010 admaif8_ep: endpoint {
1073 1011 remote-endpoint = <&xbar_admaif8_ep>;
1074 1012 };
1075 }; 1013 };
1076 1014
1077 admai 1015 admaif9_port: port@9 {
1078 1016 reg = <0x9>;
1079 1017
1080 1018 admaif9_ep: endpoint {
1081 1019 remote-endpoint = <&xbar_admaif9_ep>;
1082 1020 };
1083 }; 1021 };
1084 1022
1085 admai 1023 admaif10_port: port@a {
1086 1024 reg = <0xa>;
1087 1025
1088 1026 admaif10_ep: endpoint {
1089 1027 remote-endpoint = <&xbar_admaif10_ep>;
1090 1028 };
1091 }; 1029 };
1092 1030
1093 admai 1031 admaif11_port: port@b {
1094 1032 reg = <0xb>;
1095 1033
1096 1034 admaif11_ep: endpoint {
1097 1035 remote-endpoint = <&xbar_admaif11_ep>;
1098 1036 };
1099 }; 1037 };
1100 1038
1101 admai 1039 admaif12_port: port@c {
1102 1040 reg = <0xc>;
1103 1041
1104 1042 admaif12_ep: endpoint {
1105 1043 remote-endpoint = <&xbar_admaif12_ep>;
1106 1044 };
1107 }; 1045 };
1108 1046
1109 admai 1047 admaif13_port: port@d {
1110 1048 reg = <0xd>;
1111 1049
1112 1050 admaif13_ep: endpoint {
1113 1051 remote-endpoint = <&xbar_admaif13_ep>;
1114 1052 };
1115 }; 1053 };
1116 1054
1117 admai 1055 admaif14_port: port@e {
1118 1056 reg = <0xe>;
1119 1057
1120 1058 admaif14_ep: endpoint {
1121 1059 remote-endpoint = <&xbar_admaif14_ep>;
1122 1060 };
1123 }; 1061 };
1124 1062
1125 admai 1063 admaif15_port: port@f {
1126 1064 reg = <0xf>;
1127 1065
1128 1066 admaif15_ep: endpoint {
1129 1067 remote-endpoint = <&xbar_admaif15_ep>;
1130 1068 };
1131 }; 1069 };
1132 1070
1133 admai 1071 admaif16_port: port@10 {
1134 1072 reg = <0x10>;
1135 1073
1136 1074 admaif16_ep: endpoint {
1137 1075 remote-endpoint = <&xbar_admaif16_ep>;
1138 1076 };
1139 }; 1077 };
1140 1078
1141 admai 1079 admaif17_port: port@11 {
1142 1080 reg = <0x11>;
1143 1081
1144 1082 admaif17_ep: endpoint {
1145 1083 remote-endpoint = <&xbar_admaif17_ep>;
1146 1084 };
1147 }; 1085 };
1148 1086
1149 admai 1087 admaif18_port: port@12 {
1150 1088 reg = <0x12>;
1151 1089
1152 1090 admaif18_ep: endpoint {
1153 1091 remote-endpoint = <&xbar_admaif18_ep>;
1154 1092 };
1155 }; 1093 };
1156 1094
1157 admai 1095 admaif19_port: port@13 {
1158 1096 reg = <0x13>;
1159 1097
1160 1098 admaif19_ep: endpoint {
1161 1099 remote-endpoint = <&xbar_admaif19_ep>;
1162 1100 };
1163 }; 1101 };
1164 }; 1102 };
1165 }; 1103 };
1166 1104
1167 asrc@2910000 { !! 1105 i2s@2901000 {
1168 status = "oka 1106 status = "okay";
1169 1107
1170 ports { 1108 ports {
1171 #addr 1109 #address-cells = <1>;
1172 #size 1110 #size-cells = <0>;
1173 1111
1174 port@ 1112 port@0 {
1175 !! 1113 reg = <0>;
1176 1114
1177 !! 1115 i2s1_cif_ep: endpoint {
1178 !! 1116 remote-endpoint = <&xbar_i2s1_ep>;
1179 1117 };
1180 }; 1118 };
1181 1119
1182 port@ !! 1120 i2s1_port: port@1 {
1183 !! 1121 reg = <1>;
1184 1122
1185 !! 1123 i2s1_dap_ep: endpoint {
1186 !! 1124 dai-format = "i2s";
>> 1125 /* Placeholder for external Codec */
1187 1126 };
1188 }; 1127 };
>> 1128 };
>> 1129 };
1189 1130
1190 port@ !! 1131 i2s@2901100 {
1191 !! 1132 status = "okay";
1192 1133
1193 !! 1134 ports {
1194 !! 1135 #address-cells = <1>;
1195 !! 1136 #size-cells = <0>;
1196 }; <<
1197 1137
1198 port@ !! 1138 port@0 {
1199 !! 1139 reg = <0>;
1200 1140
1201 !! 1141 i2s2_cif_ep: endpoint {
1202 !! 1142 remote-endpoint = <&xbar_i2s2_ep>;
1203 1143 };
1204 }; 1144 };
1205 1145
1206 port@ !! 1146 i2s2_port: port@1 {
1207 !! 1147 reg = <1>;
1208 1148
1209 !! 1149 i2s2_dap_ep: endpoint {
1210 !! 1150 dai-format = "i2s";
>> 1151 /* Placeholder for external Codec */
1211 1152 };
1212 }; 1153 };
>> 1154 };
>> 1155 };
1213 1156
1214 port@ !! 1157 i2s@2901200 {
1215 !! 1158 status = "okay";
1216 1159
1217 !! 1160 ports {
1218 !! 1161 #address-cells = <1>;
>> 1162 #size-cells = <0>;
>> 1163
>> 1164 port@0 {
>> 1165 reg = <0>;
>> 1166
>> 1167 i2s3_cif_ep: endpoint {
>> 1168 remote-endpoint = <&xbar_i2s3_ep>;
1219 1169 };
1220 }; 1170 };
1221 1171
1222 port@ !! 1172 i2s3_port: port@1 {
1223 !! 1173 reg = <1>;
1224 1174
1225 !! 1175 i2s3_dap_ep: endpoint {
1226 !! 1176 dai-format = "i2s";
>> 1177 /* Placeholder for external Codec */
1227 1178 };
1228 }; 1179 };
>> 1180 };
>> 1181 };
1229 1182
1230 asrc_ !! 1183 i2s@2901300 {
1231 !! 1184 status = "okay";
1232 1185
1233 !! 1186 ports {
1234 !! 1187 #address-cells = <1>;
>> 1188 #size-cells = <0>;
>> 1189
>> 1190 port@0 {
>> 1191 reg = <0>;
>> 1192
>> 1193 i2s4_cif_ep: endpoint {
>> 1194 remote-endpoint = <&xbar_i2s4_ep>;
1235 1195 };
1236 }; 1196 };
1237 1197
1238 asrc_ !! 1198 i2s4_port: port@1 {
1239 !! 1199 reg = <1>;
1240 1200
1241 !! 1201 i2s4_dap_ep: endpoint {
1242 !! 1202 dai-format = "i2s";
>> 1203 /* Placeholder for external Codec */
1243 1204 };
1244 }; 1205 };
>> 1206 };
>> 1207 };
1245 1208
1246 asrc_ !! 1209 i2s@2901400 {
1247 !! 1210 status = "okay";
1248 1211
1249 !! 1212 ports {
1250 !! 1213 #address-cells = <1>;
>> 1214 #size-cells = <0>;
>> 1215
>> 1216 port@0 {
>> 1217 reg = <0>;
>> 1218
>> 1219 i2s5_cif_ep: endpoint {
>> 1220 remote-endpoint = <&xbar_i2s5_ep>;
1251 1221 };
1252 }; 1222 };
1253 1223
1254 asrc_ !! 1224 i2s5_port: port@1 {
1255 !! 1225 reg = <1>;
1256 1226
1257 !! 1227 i2s5_dap_ep: endpoint {
1258 !! 1228 dai-format = "i2s";
>> 1229 /* Placeholder for external Codec */
1259 1230 };
1260 }; 1231 };
>> 1232 };
>> 1233 };
1261 1234
1262 asrc_ !! 1235 i2s@2901500 {
1263 !! 1236 status = "okay";
1264 1237
1265 !! 1238 ports {
1266 !! 1239 #address-cells = <1>;
>> 1240 #size-cells = <0>;
>> 1241
>> 1242 port@0 {
>> 1243 reg = <0>;
>> 1244
>> 1245 i2s6_cif_ep: endpoint {
>> 1246 remote-endpoint = <&xbar_i2s6_ep>;
1267 1247 };
1268 }; 1248 };
1269 1249
1270 asrc_ !! 1250 i2s6_port: port@1 {
1271 !! 1251 reg = <1>;
1272 1252
1273 !! 1253 i2s6_dap_ep: endpoint {
1274 !! 1254 dai-format = "i2s";
>> 1255 /* Placeholder for external Codec */
1275 1256 };
1276 }; 1257 };
1277 }; 1258 };
1278 }; 1259 };
1279 1260
1280 ports { !! 1261 dmic@2904000 {
1281 #address-cell !! 1262 status = "okay";
1282 #size-cells = <<
1283 1263
1284 port@0 { !! 1264 ports {
1285 reg = !! 1265 #address-cells = <1>;
>> 1266 #size-cells = <0>;
1286 1267
1287 xbar_ !! 1268 port@0 {
1288 !! 1269 reg = <0>;
>> 1270
>> 1271 dmic1_cif_ep: endpoint {
>> 1272 remote-endpoint = <&xbar_dmic1_ep>;
>> 1273 };
1289 }; 1274 };
1290 }; <<
1291 1275
1292 port@1 { !! 1276 dmic1_port: port@1 {
1293 reg = !! 1277 reg = <1>;
1294 1278
1295 xbar_ !! 1279 dmic1_dap_ep: endpoint {
1296 !! 1280 /* Place holder for external Codec */
>> 1281 };
1297 }; 1282 };
1298 }; 1283 };
>> 1284 };
1299 1285
1300 port@2 { !! 1286 dmic@2904100 {
1301 reg = !! 1287 status = "okay";
1302 1288
1303 xbar_ !! 1289 ports {
1304 !! 1290 #address-cells = <1>;
1305 }; !! 1291 #size-cells = <0>;
1306 }; <<
1307 1292
1308 port@3 { !! 1293 port@0 {
1309 reg = !! 1294 reg = <0>;
1310 1295
1311 xbar_ !! 1296 dmic2_cif_ep: endpoint {
1312 !! 1297 remote-endpoint = <&xbar_dmic2_ep>;
>> 1298 };
1313 }; 1299 };
1314 }; <<
1315 1300
1316 port@4 { !! 1301 dmic2_port: port@1 {
1317 reg = !! 1302 reg = <1>;
1318 1303
1319 xbar_ !! 1304 dmic2_dap_ep: endpoint {
1320 !! 1305 /* Place holder for external Codec */
>> 1306 };
1321 }; 1307 };
1322 }; 1308 };
>> 1309 };
1323 1310
1324 port@5 { !! 1311 dmic@2904200 {
1325 reg = !! 1312 status = "okay";
1326 1313
1327 xbar_ !! 1314 ports {
1328 !! 1315 #address-cells = <1>;
1329 }; !! 1316 #size-cells = <0>;
1330 }; <<
1331 1317
1332 port@6 { !! 1318 port@0 {
1333 reg = !! 1319 reg = <0>;
1334 1320
1335 xbar_ !! 1321 dmic3_cif_ep: endpoint {
1336 !! 1322 remote-endpoint = <&xbar_dmic3_ep>;
>> 1323 };
1337 }; 1324 };
1338 }; <<
1339 1325
1340 port@7 { !! 1326 dmic3_port: port@1 {
1341 reg = !! 1327 reg = <1>;
1342 1328
1343 xbar_ !! 1329 dmic3_dap_ep: endpoint {
1344 !! 1330 /* Place holder for external Codec */
>> 1331 };
1345 }; 1332 };
1346 }; 1333 };
>> 1334 };
1347 1335
1348 port@8 { !! 1336 dspk@2905000 {
1349 reg = !! 1337 status = "okay";
1350 1338
1351 xbar_ !! 1339 ports {
1352 !! 1340 #address-cells = <1>;
1353 }; !! 1341 #size-cells = <0>;
1354 }; <<
1355 1342
1356 port@9 { !! 1343 port@0 {
1357 reg = !! 1344 reg = <0>;
1358 1345
1359 xbar_ !! 1346 dspk1_cif_ep: endpoint {
1360 !! 1347 remote-endpoint = <&xbar_dspk1_ep>;
>> 1348 };
1361 }; 1349 };
1362 }; <<
1363 1350
1364 port@a { !! 1351 dspk1_port: port@1 {
1365 reg = !! 1352 reg = <1>;
1366 1353
1367 xbar_ !! 1354 dspk1_dap_ep: endpoint {
1368 !! 1355 /* Place holder for external Codec */
>> 1356 };
1369 }; 1357 };
1370 }; 1358 };
>> 1359 };
1371 1360
1372 port@b { !! 1361 dspk@2905100 {
1373 reg = !! 1362 status = "okay";
1374 1363
1375 xbar_ !! 1364 ports {
1376 !! 1365 #address-cells = <1>;
1377 }; !! 1366 #size-cells = <0>;
1378 }; <<
1379 1367
1380 port@c { !! 1368 port@0 {
1381 reg = !! 1369 reg = <0>;
1382 1370
1383 xbar_ !! 1371 dspk2_cif_ep: endpoint {
1384 !! 1372 remote-endpoint = <&xbar_dspk2_ep>;
>> 1373 };
1385 }; 1374 };
1386 }; <<
1387 1375
1388 port@d { !! 1376 dspk2_port: port@1 {
1389 reg = !! 1377 reg = <1>;
1390 1378
1391 xbar_ !! 1379 dspk2_dap_ep: endpoint {
1392 !! 1380 /* Place holder for external Codec */
>> 1381 };
1393 }; 1382 };
1394 }; 1383 };
>> 1384 };
1395 1385
1396 port@e { !! 1386 sfc@2902000 {
1397 reg = !! 1387 status = "okay";
1398 1388
1399 xbar_ !! 1389 ports {
1400 !! 1390 #address-cells = <1>;
1401 }; !! 1391 #size-cells = <0>;
1402 }; <<
1403 1392
1404 port@f { !! 1393 port@0 {
1405 reg = !! 1394 reg = <0>;
1406 1395
1407 xbar_ !! 1396 sfc1_cif_in_ep: endpoint {
1408 !! 1397 remote-endpoint = <&xbar_sfc1_in_ep>;
>> 1398 convert-rate = <44100>;
>> 1399 };
1409 }; 1400 };
1410 }; <<
1411 1401
1412 port@10 { !! 1402 sfc1_out_port: port@1 {
1413 reg = !! 1403 reg = <1>;
1414 1404
1415 xbar_ !! 1405 sfc1_cif_out_ep: endpoint {
1416 !! 1406 remote-endpoint = <&xbar_sfc1_out_ep>;
>> 1407 convert-rate = <48000>;
>> 1408 };
1417 }; 1409 };
1418 }; 1410 };
>> 1411 };
1419 1412
1420 port@11 { !! 1413 sfc@2902200 {
1421 reg = !! 1414 status = "okay";
1422 1415
1423 xbar_ !! 1416 ports {
1424 !! 1417 #address-cells = <1>;
1425 }; !! 1418 #size-cells = <0>;
1426 }; <<
1427 1419
1428 port@12 { !! 1420 port@0 {
1429 reg = !! 1421 reg = <0>;
1430 1422
1431 xbar_ !! 1423 sfc2_cif_in_ep: endpoint {
1432 !! 1424 remote-endpoint = <&xbar_sfc2_in_ep>;
>> 1425 };
1433 }; 1426 };
1434 }; <<
1435 1427
1436 port@13 { !! 1428 sfc2_out_port: port@1 {
1437 reg = !! 1429 reg = <1>;
1438 1430
1439 xbar_ !! 1431 sfc2_cif_out_ep: endpoint {
1440 !! 1432 remote-endpoint = <&xbar_sfc2_out_ep>;
>> 1433 };
1441 }; 1434 };
1442 }; 1435 };
>> 1436 };
1443 1437
1444 xbar_i2s1_por !! 1438 sfc@2902400 {
1445 reg = !! 1439 status = "okay";
1446 1440
1447 xbar_ !! 1441 ports {
1448 !! 1442 #address-cells = <1>;
1449 }; !! 1443 #size-cells = <0>;
1450 }; <<
1451 1444
1452 xbar_i2s2_por !! 1445 port@0 {
1453 reg = !! 1446 reg = <0>;
1454 1447
1455 xbar_ !! 1448 sfc3_cif_in_ep: endpoint {
1456 !! 1449 remote-endpoint = <&xbar_sfc3_in_ep>;
>> 1450 };
1457 }; 1451 };
1458 }; <<
1459 1452
1460 xbar_i2s3_por !! 1453 sfc3_out_port: port@1 {
1461 reg = !! 1454 reg = <1>;
1462 1455
1463 xbar_ !! 1456 sfc3_cif_out_ep: endpoint {
1464 !! 1457 remote-endpoint = <&xbar_sfc3_out_ep>;
>> 1458 };
1465 }; 1459 };
1466 }; 1460 };
>> 1461 };
1467 1462
1468 xbar_i2s4_por !! 1463 sfc@2902600 {
1469 reg = !! 1464 status = "okay";
1470 1465
1471 xbar_ !! 1466 ports {
1472 !! 1467 #address-cells = <1>;
1473 }; !! 1468 #size-cells = <0>;
1474 }; <<
1475 1469
1476 xbar_i2s5_por !! 1470 port@0 {
1477 reg = !! 1471 reg = <0>;
1478 1472
1479 xbar_ !! 1473 sfc4_cif_in_ep: endpoint {
1480 !! 1474 remote-endpoint = <&xbar_sfc4_in_ep>;
>> 1475 };
1481 }; 1476 };
1482 }; <<
1483 1477
1484 xbar_i2s6_por !! 1478 sfc4_out_port: port@1 {
1485 reg = !! 1479 reg = <1>;
1486 1480
1487 xbar_ !! 1481 sfc4_cif_out_ep: endpoint {
1488 !! 1482 remote-endpoint = <&xbar_sfc4_out_ep>;
>> 1483 };
1489 }; 1484 };
1490 }; 1485 };
>> 1486 };
1491 1487
1492 xbar_dmic1_po !! 1488 mvc@290a000 {
1493 reg = !! 1489 status = "okay";
1494 1490
1495 xbar_ !! 1491 ports {
1496 !! 1492 #address-cells = <1>;
1497 }; !! 1493 #size-cells = <0>;
1498 }; <<
1499 1494
1500 xbar_dmic2_po !! 1495 port@0 {
1501 reg = !! 1496 reg = <0>;
1502 1497
1503 xbar_ !! 1498 mvc1_cif_in_ep: endpoint {
1504 !! 1499 remote-endpoint = <&xbar_mvc1_in_ep>;
>> 1500 };
1505 }; 1501 };
1506 }; <<
1507 1502
1508 xbar_dmic3_po !! 1503 mvc1_out_port: port@1 {
1509 reg = !! 1504 reg = <1>;
1510 1505
1511 xbar_ !! 1506 mvc1_cif_out_ep: endpoint {
1512 !! 1507 remote-endpoint = <&xbar_mvc1_out_ep>;
>> 1508 };
1513 }; 1509 };
1514 }; 1510 };
>> 1511 };
1515 1512
1516 xbar_dspk1_po !! 1513 mvc@290a200 {
1517 reg = !! 1514 status = "okay";
1518 1515
1519 xbar_ !! 1516 ports {
1520 !! 1517 #address-cells = <1>;
1521 }; !! 1518 #size-cells = <0>;
1522 }; <<
1523 1519
1524 xbar_dspk2_po !! 1520 port@0 {
1525 reg = !! 1521 reg = <0>;
1526 1522
1527 xbar_ !! 1523 mvc2_cif_in_ep: endpoint {
1528 !! 1524 remote-endpoint = <&xbar_mvc2_in_ep>;
>> 1525 };
1529 }; 1526 };
1530 }; <<
1531 1527
1532 xbar_sfc1_in_ !! 1528 mvc2_out_port: port@1 {
1533 reg = !! 1529 reg = <1>;
1534 1530
1535 xbar_ !! 1531 mvc2_cif_out_ep: endpoint {
1536 !! 1532 remote-endpoint = <&xbar_mvc2_out_ep>;
>> 1533 };
1537 }; 1534 };
1538 }; 1535 };
>> 1536 };
1539 1537
1540 port@21 { !! 1538 amx@2903000 {
1541 reg = !! 1539 status = "okay";
1542 1540
1543 xbar_ !! 1541 ports {
1544 !! 1542 #address-cells = <1>;
1545 }; !! 1543 #size-cells = <0>;
1546 }; <<
1547 1544
1548 xbar_sfc2_in_ !! 1545 port@0 {
1549 reg = !! 1546 reg = <0>;
1550 1547
1551 xbar_ !! 1548 amx1_in1_ep: endpoint {
1552 !! 1549 remote-endpoint = <&xbar_amx1_in1_ep>;
>> 1550 };
1553 }; 1551 };
1554 }; <<
1555 1552
1556 port@23 { !! 1553 port@1 {
1557 reg = !! 1554 reg = <1>;
1558 1555
1559 xbar_ !! 1556 amx1_in2_ep: endpoint {
1560 !! 1557 remote-endpoint = <&xbar_amx1_in2_ep>;
>> 1558 };
1561 }; 1559 };
1562 }; <<
1563 1560
1564 xbar_sfc3_in_ !! 1561 port@2 {
1565 reg = !! 1562 reg = <2>;
1566 1563
1567 xbar_ !! 1564 amx1_in3_ep: endpoint {
1568 !! 1565 remote-endpoint = <&xbar_amx1_in3_ep>;
>> 1566 };
1569 }; 1567 };
1570 }; <<
1571 1568
1572 port@25 { !! 1569 port@3 {
1573 reg = !! 1570 reg = <3>;
1574 1571
1575 xbar_ !! 1572 amx1_in4_ep: endpoint {
1576 !! 1573 remote-endpoint = <&xbar_amx1_in4_ep>;
>> 1574 };
1577 }; 1575 };
1578 }; <<
1579 1576
1580 xbar_sfc4_in_ !! 1577 amx1_out_port: port@4 {
1581 reg = !! 1578 reg = <4>;
1582 1579
1583 xbar_ !! 1580 amx1_out_ep: endpoint {
1584 !! 1581 remote-endpoint = <&xbar_amx1_out_ep>;
>> 1582 };
1585 }; 1583 };
1586 }; 1584 };
>> 1585 };
1587 1586
1588 port@27 { !! 1587 amx@2903100 {
1589 reg = !! 1588 status = "okay";
1590 1589
1591 xbar_ !! 1590 ports {
1592 !! 1591 #address-cells = <1>;
1593 }; !! 1592 #size-cells = <0>;
1594 }; <<
1595 1593
1596 xbar_mvc1_in_ !! 1594 port@0 {
1597 reg = !! 1595 reg = <0>;
1598 1596
1599 xbar_ !! 1597 amx2_in1_ep: endpoint {
1600 !! 1598 remote-endpoint = <&xbar_amx2_in1_ep>;
>> 1599 };
1601 }; 1600 };
1602 }; <<
1603 1601
1604 port@29 { !! 1602 port@1 {
1605 reg = !! 1603 reg = <1>;
1606 1604
1607 xbar_ !! 1605 amx2_in2_ep: endpoint {
1608 !! 1606 remote-endpoint = <&xbar_amx2_in2_ep>;
>> 1607 };
1609 }; 1608 };
1610 }; <<
1611 1609
1612 xbar_mvc2_in_ !! 1610 amx2_in3_port: port@2 {
1613 reg = !! 1611 reg = <2>;
1614 1612
1615 xbar_ !! 1613 amx2_in3_ep: endpoint {
1616 !! 1614 remote-endpoint = <&xbar_amx2_in3_ep>;
>> 1615 };
1617 }; 1616 };
1618 }; <<
1619 1617
1620 port@2b { !! 1618 amx2_in4_port: port@3 {
1621 reg = !! 1619 reg = <3>;
1622 1620
1623 xbar_ !! 1621 amx2_in4_ep: endpoint {
1624 !! 1622 remote-endpoint = <&xbar_amx2_in4_ep>;
>> 1623 };
1625 }; 1624 };
1626 }; <<
1627 1625
1628 xbar_amx1_in1 !! 1626 amx2_out_port: port@4 {
1629 reg = !! 1627 reg = <4>;
1630 1628
1631 xbar_ !! 1629 amx2_out_ep: endpoint {
1632 !! 1630 remote-endpoint = <&xbar_amx2_out_ep>;
>> 1631 };
1633 }; 1632 };
1634 }; 1633 };
>> 1634 };
1635 1635
1636 xbar_amx1_in2 !! 1636 amx@2903200 {
1637 reg = !! 1637 status = "okay";
1638 1638
1639 xbar_ !! 1639 ports {
1640 !! 1640 #address-cells = <1>;
1641 }; !! 1641 #size-cells = <0>;
1642 }; <<
1643 1642
1644 xbar_amx1_in3 !! 1643 port@0 {
1645 reg = !! 1644 reg = <0>;
1646 1645
1647 xbar_ !! 1646 amx3_in1_ep: endpoint {
1648 !! 1647 remote-endpoint = <&xbar_amx3_in1_ep>;
>> 1648 };
1649 }; 1649 };
1650 }; <<
1651 1650
1652 xbar_amx1_in4 !! 1651 port@1 {
1653 reg = !! 1652 reg = <1>;
1654 1653
1655 xbar_ !! 1654 amx3_in2_ep: endpoint {
1656 !! 1655 remote-endpoint = <&xbar_amx3_in2_ep>;
>> 1656 };
1657 }; 1657 };
1658 }; <<
1659 1658
1660 port@30 { !! 1659 port@2 {
1661 reg = !! 1660 reg = <2>;
1662 1661
1663 xbar_ !! 1662 amx3_in3_ep: endpoint {
1664 !! 1663 remote-endpoint = <&xbar_amx3_in3_ep>;
>> 1664 };
1665 }; 1665 };
1666 }; <<
1667 1666
1668 xbar_amx2_in1 !! 1667 port@3 {
1669 reg = !! 1668 reg = <3>;
1670 1669
1671 xbar_ !! 1670 amx3_in4_ep: endpoint {
1672 !! 1671 remote-endpoint = <&xbar_amx3_in4_ep>;
>> 1672 };
1673 }; 1673 };
1674 }; <<
1675 1674
1676 xbar_amx2_in2 !! 1675 amx3_out_port: port@4 {
1677 reg = !! 1676 reg = <4>;
1678 1677
1679 xbar_ !! 1678 amx3_out_ep: endpoint {
1680 !! 1679 remote-endpoint = <&xbar_amx3_out_ep>;
>> 1680 };
1681 }; 1681 };
1682 }; 1682 };
>> 1683 };
1683 1684
1684 xbar_amx2_in3 !! 1685 amx@2903300 {
1685 reg = !! 1686 status = "okay";
1686 1687
1687 xbar_ !! 1688 ports {
1688 !! 1689 #address-cells = <1>;
1689 }; !! 1690 #size-cells = <0>;
1690 }; <<
1691 1691
1692 xbar_amx2_in4 !! 1692 port@0 {
1693 reg = !! 1693 reg = <0>;
1694 1694
1695 xbar_ !! 1695 amx4_in1_ep: endpoint {
1696 !! 1696 remote-endpoint = <&xbar_amx4_in1_ep>;
>> 1697 };
1697 }; 1698 };
1698 }; <<
1699 1699
1700 port@35 { !! 1700 port@1 {
1701 reg = !! 1701 reg = <1>;
1702 1702
1703 xbar_ !! 1703 amx4_in2_ep: endpoint {
1704 !! 1704 remote-endpoint = <&xbar_amx4_in2_ep>;
>> 1705 };
1705 }; 1706 };
1706 }; <<
1707 1707
1708 xbar_amx3_in1 !! 1708 port@2 {
1709 reg = !! 1709 reg = <2>;
1710 1710
1711 xbar_ !! 1711 amx4_in3_ep: endpoint {
1712 !! 1712 remote-endpoint = <&xbar_amx4_in3_ep>;
>> 1713 };
1713 }; 1714 };
1714 }; <<
1715 1715
1716 xbar_amx3_in2 !! 1716 port@3 {
1717 reg = !! 1717 reg = <3>;
1718 1718
1719 xbar_ !! 1719 amx4_in4_ep: endpoint {
1720 !! 1720 remote-endpoint = <&xbar_amx4_in4_ep>;
>> 1721 };
1721 }; 1722 };
1722 }; <<
1723 1723
1724 xbar_amx3_in3 !! 1724 amx4_out_port: port@4 {
1725 reg = !! 1725 reg = <4>;
1726 1726
1727 xbar_ !! 1727 amx4_out_ep: endpoint {
1728 !! 1728 remote-endpoint = <&xbar_amx4_out_ep>;
>> 1729 };
1729 }; 1730 };
1730 }; 1731 };
>> 1732 };
1731 1733
1732 xbar_amx3_in4 !! 1734 adx@2903800 {
1733 reg = !! 1735 status = "okay";
1734 1736
1735 xbar_ !! 1737 ports {
1736 !! 1738 #address-cells = <1>;
1737 }; !! 1739 #size-cells = <0>;
1738 }; <<
1739 1740
1740 port@3a { !! 1741 port@0 {
1741 reg = !! 1742 reg = <0>;
1742 1743
1743 xbar_ !! 1744 adx1_in_ep: endpoint {
1744 !! 1745 remote-endpoint = <&xbar_adx1_in_ep>;
>> 1746 };
1745 }; 1747 };
1746 }; <<
1747 1748
1748 xbar_amx4_in1 !! 1749 adx1_out1_port: port@1 {
1749 reg = !! 1750 reg = <1>;
1750 1751
1751 xbar_ !! 1752 adx1_out1_ep: endpoint {
1752 !! 1753 remote-endpoint = <&xbar_adx1_out1_ep>;
>> 1754 };
1753 }; 1755 };
1754 }; <<
1755 1756
1756 xbar_amx4_in2 !! 1757 adx1_out2_port: port@2 {
1757 reg = !! 1758 reg = <2>;
1758 1759
1759 xbar_ !! 1760 adx1_out2_ep: endpoint {
1760 !! 1761 remote-endpoint = <&xbar_adx1_out2_ep>;
>> 1762 };
1761 }; 1763 };
1762 }; <<
1763 1764
1764 xbar_amx4_in3 !! 1765 adx1_out3_port: port@3 {
1765 reg = !! 1766 reg = <3>;
1766 1767
1767 xbar_ !! 1768 adx1_out3_ep: endpoint {
1768 !! 1769 remote-endpoint = <&xbar_adx1_out3_ep>;
>> 1770 };
1769 }; 1771 };
1770 }; <<
1771 1772
1772 xbar_amx4_in4 !! 1773 adx1_out4_port: port@4 {
1773 reg = !! 1774 reg = <4>;
1774 1775
1775 xbar_ !! 1776 adx1_out4_ep: endpoint {
1776 !! 1777 remote-endpoint = <&xbar_adx1_out4_ep>;
>> 1778 };
1777 }; 1779 };
1778 }; 1780 };
>> 1781 };
1779 1782
1780 port@3f { !! 1783 adx@2903900 {
1781 reg = !! 1784 status = "okay";
1782 1785
1783 xbar_ !! 1786 ports {
1784 !! 1787 #address-cells = <1>;
1785 }; !! 1788 #size-cells = <0>;
1786 }; <<
1787 1789
1788 xbar_adx1_in_ !! 1790 port@0 {
1789 reg = !! 1791 reg = <0>;
1790 1792
1791 xbar_ !! 1793 adx2_in_ep: endpoint {
1792 !! 1794 remote-endpoint = <&xbar_adx2_in_ep>;
>> 1795 };
1793 }; 1796 };
1794 }; <<
1795 1797
1796 port@41 { !! 1798 adx2_out1_port: port@1 {
1797 reg = !! 1799 reg = <1>;
1798 1800
1799 xbar_ !! 1801 adx2_out1_ep: endpoint {
1800 !! 1802 remote-endpoint = <&xbar_adx2_out1_ep>;
>> 1803 };
1801 }; 1804 };
1802 }; <<
1803 1805
1804 port@42 { !! 1806 adx2_out2_port: port@2 {
1805 reg = !! 1807 reg = <2>;
1806 1808
1807 xbar_ !! 1809 adx2_out2_ep: endpoint {
1808 !! 1810 remote-endpoint = <&xbar_adx2_out2_ep>;
>> 1811 };
1809 }; 1812 };
1810 }; <<
1811 1813
1812 port@43 { !! 1814 adx2_out3_port: port@3 {
1813 reg = !! 1815 reg = <3>;
1814 1816
1815 xbar_ !! 1817 adx2_out3_ep: endpoint {
1816 !! 1818 remote-endpoint = <&xbar_adx2_out3_ep>;
>> 1819 };
1817 }; 1820 };
1818 }; <<
1819 1821
1820 port@44 { !! 1822 adx2_out4_port: port@4 {
1821 reg = !! 1823 reg = <4>;
1822 1824
1823 xbar_ !! 1825 adx2_out4_ep: endpoint {
1824 !! 1826 remote-endpoint = <&xbar_adx2_out4_ep>;
>> 1827 };
1825 }; 1828 };
1826 }; 1829 };
>> 1830 };
1827 1831
1828 xbar_adx2_in_ !! 1832 adx@2903a00 {
1829 reg = !! 1833 status = "okay";
1830 1834
1831 xbar_ !! 1835 ports {
1832 !! 1836 #address-cells = <1>;
1833 }; !! 1837 #size-cells = <0>;
1834 }; <<
1835 1838
1836 port@46 { !! 1839 port@0 {
1837 reg = !! 1840 reg = <0>;
1838 1841
1839 xbar_ !! 1842 adx3_in_ep: endpoint {
1840 !! 1843 remote-endpoint = <&xbar_adx3_in_ep>;
>> 1844 };
1841 }; 1845 };
1842 }; <<
1843 1846
1844 port@47 { !! 1847 adx3_out1_port: port@1 {
1845 reg = !! 1848 reg = <1>;
1846 1849
1847 xbar_ !! 1850 adx3_out1_ep: endpoint {
1848 !! 1851 remote-endpoint = <&xbar_adx3_out1_ep>;
>> 1852 };
1849 }; 1853 };
1850 }; <<
1851 1854
1852 port@48 { !! 1855 adx3_out2_port: port@2 {
1853 reg = !! 1856 reg = <2>;
1854 1857
1855 xbar_ !! 1858 adx3_out2_ep: endpoint {
1856 !! 1859 remote-endpoint = <&xbar_adx3_out2_ep>;
>> 1860 };
1857 }; 1861 };
1858 }; <<
1859 1862
1860 port@49 { !! 1863 adx3_out3_port: port@3 {
1861 reg = !! 1864 reg = <3>;
1862 1865
1863 xbar_ !! 1866 adx3_out3_ep: endpoint {
1864 !! 1867 remote-endpoint = <&xbar_adx3_out3_ep>;
>> 1868 };
1865 }; 1869 };
1866 }; <<
1867 1870
1868 xbar_adx3_in_ !! 1871 adx3_out4_port: port@4 {
1869 reg = !! 1872 reg = <4>;
1870 1873
1871 xbar_ !! 1874 adx3_out4_ep: endpoint {
1872 !! 1875 remote-endpoint = <&xbar_adx3_out4_ep>;
>> 1876 };
1873 }; 1877 };
1874 }; 1878 };
>> 1879 };
1875 1880
1876 port@4b { !! 1881 adx@2903b00 {
1877 reg = !! 1882 status = "okay";
1878 1883
1879 xbar_ !! 1884 ports {
1880 !! 1885 #address-cells = <1>;
1881 }; !! 1886 #size-cells = <0>;
1882 }; <<
1883 1887
1884 port@4c { !! 1888 port@0 {
1885 reg = !! 1889 reg = <0>;
1886 1890
1887 xbar_ !! 1891 adx4_in_ep: endpoint {
1888 !! 1892 remote-endpoint = <&xbar_adx4_in_ep>;
>> 1893 };
1889 }; 1894 };
1890 }; <<
1891 1895
1892 port@4d { !! 1896 adx4_out1_port: port@1 {
1893 reg = !! 1897 reg = <1>;
1894 1898
1895 xbar_ !! 1899 adx4_out1_ep: endpoint {
1896 !! 1900 remote-endpoint = <&xbar_adx4_out1_ep>;
>> 1901 };
1897 }; 1902 };
1898 }; <<
1899 1903
1900 port@4e { !! 1904 adx4_out2_port: port@2 {
1901 reg = !! 1905 reg = <2>;
1902 1906
1903 xbar_ !! 1907 adx4_out2_ep: endpoint {
1904 !! 1908 remote-endpoint = <&xbar_adx4_out2_ep>;
>> 1909 };
1905 }; 1910 };
1906 }; <<
1907 1911
1908 xbar_adx4_in_ !! 1912 adx4_out3_port: port@3 {
1909 reg = !! 1913 reg = <3>;
1910 1914
1911 xbar_ !! 1915 adx4_out3_ep: endpoint {
1912 !! 1916 remote-endpoint = <&xbar_adx4_out3_ep>;
>> 1917 };
1913 }; 1918 };
1914 }; <<
1915 1919
1916 port@50 { !! 1920 adx4_out4_port: port@4 {
1917 reg = !! 1921 reg = <4>;
1918 1922
1919 xbar_ !! 1923 adx4_out4_ep: endpoint {
1920 !! 1924 remote-endpoint = <&xbar_adx4_out4_ep>;
>> 1925 };
1921 }; 1926 };
1922 }; 1927 };
>> 1928 };
1923 1929
1924 port@51 { !! 1930 processing-engine@2908000 {
1925 reg = !! 1931 status = "okay";
1926 1932
1927 xbar_ !! 1933 ports {
1928 !! 1934 #address-cells = <1>;
1929 }; !! 1935 #size-cells = <0>;
1930 }; <<
1931 1936
1932 port@52 { !! 1937 port@0 {
1933 reg = !! 1938 reg = <0x0>;
1934 1939
1935 xbar_ !! 1940 ope1_cif_in_ep: endpoint {
1936 !! 1941 remote-endpoint = <&xbar_ope1_in_ep>;
>> 1942 };
1937 }; 1943 };
1938 }; <<
1939 1944
1940 port@53 { !! 1945 ope1_out_port: port@1 {
1941 reg = !! 1946 reg = <0x1>;
1942 1947
1943 xbar_ !! 1948 ope1_cif_out_ep: endpoint {
1944 !! 1949 remote-endpoint = <&xbar_ope1_out_ep>;
>> 1950 };
1945 }; 1951 };
1946 }; 1952 };
>> 1953 };
1947 1954
1948 xbar_mixer_in !! 1955 amixer@290bb00 {
1949 reg = !! 1956 status = "okay";
1950 1957
1951 xbar_ !! 1958 ports {
1952 !! 1959 #address-cells = <1>;
1953 }; !! 1960 #size-cells = <0>;
1954 }; <<
1955 1961
1956 xbar_mixer_in !! 1962 port@0 {
1957 reg = !! 1963 reg = <0x0>;
1958 1964
1959 xbar_ !! 1965 mixer_in1_ep: endpoint {
1960 !! 1966 remote-endpoint = <&xbar_mixer_in1_ep>;
>> 1967 };
1961 }; 1968 };
1962 }; <<
1963 1969
1964 xbar_mixer_in !! 1970 port@1 {
1965 reg = !! 1971 reg = <0x1>;
1966 1972
1967 xbar_ !! 1973 mixer_in2_ep: endpoint {
1968 !! 1974 remote-endpoint = <&xbar_mixer_in2_ep>;
>> 1975 };
1969 }; 1976 };
1970 }; <<
1971 1977
1972 xbar_mixer_in !! 1978 port@2 {
1973 reg = !! 1979 reg = <0x2>;
1974 1980
1975 xbar_ !! 1981 mixer_in3_ep: endpoint {
1976 !! 1982 remote-endpoint = <&xbar_mixer_in3_ep>;
>> 1983 };
1977 }; 1984 };
1978 }; <<
1979 1985
1980 xbar_mixer_in !! 1986 port@3 {
1981 reg = !! 1987 reg = <0x3>;
1982 1988
1983 xbar_ !! 1989 mixer_in4_ep: endpoint {
1984 !! 1990 remote-endpoint = <&xbar_mixer_in4_ep>;
>> 1991 };
1985 }; 1992 };
1986 }; <<
1987 1993
1988 xbar_mixer_in !! 1994 port@4 {
1989 reg = !! 1995 reg = <0x4>;
1990 1996
1991 xbar_ !! 1997 mixer_in5_ep: endpoint {
1992 !! 1998 remote-endpoint = <&xbar_mixer_in5_ep>;
>> 1999 };
1993 }; 2000 };
1994 }; <<
1995 2001
1996 xbar_mixer_in !! 2002 port@5 {
1997 reg = !! 2003 reg = <0x5>;
1998 2004
1999 xbar_ !! 2005 mixer_in6_ep: endpoint {
2000 !! 2006 remote-endpoint = <&xbar_mixer_in6_ep>;
>> 2007 };
2001 }; 2008 };
2002 }; <<
2003 2009
2004 xbar_mixer_in !! 2010 port@6 {
2005 reg = !! 2011 reg = <0x6>;
2006 2012
2007 xbar_ !! 2013 mixer_in7_ep: endpoint {
2008 !! 2014 remote-endpoint = <&xbar_mixer_in7_ep>;
>> 2015 };
2009 }; 2016 };
2010 }; <<
2011 2017
2012 xbar_mixer_in !! 2018 port@7 {
2013 reg = !! 2019 reg = <0x7>;
2014 2020
2015 xbar_ !! 2021 mixer_in8_ep: endpoint {
2016 !! 2022 remote-endpoint = <&xbar_mixer_in8_ep>;
>> 2023 };
2017 }; 2024 };
2018 }; <<
2019 2025
2020 xbar_mixer_in !! 2026 port@8 {
2021 reg = !! 2027 reg = <0x8>;
2022 2028
2023 xbar_ !! 2029 mixer_in9_ep: endpoint {
2024 !! 2030 remote-endpoint = <&xbar_mixer_in9_ep>;
>> 2031 };
2025 }; 2032 };
2026 }; <<
2027 2033
2028 port@5e { !! 2034 port@9 {
2029 reg = !! 2035 reg = <0x9>;
2030 2036
2031 xbar_ !! 2037 mixer_in10_ep: endpoint {
2032 !! 2038 remote-endpoint = <&xbar_mixer_in10_ep>;
>> 2039 };
2033 }; 2040 };
2034 }; <<
2035 2041
2036 port@5f { !! 2042 mixer_out1_port: port@a {
2037 reg = !! 2043 reg = <0xa>;
2038 2044
2039 xbar_ !! 2045 mixer_out1_ep: endpoint {
2040 !! 2046 remote-endpoint = <&xbar_mixer_out1_ep>;
>> 2047 };
2041 }; 2048 };
2042 }; <<
2043 2049
2044 port@60 { !! 2050 mixer_out2_port: port@b {
2045 reg = !! 2051 reg = <0xb>;
2046 2052
2047 xbar_ !! 2053 mixer_out2_ep: endpoint {
2048 !! 2054 remote-endpoint = <&xbar_mixer_out2_ep>;
>> 2055 };
2049 }; 2056 };
2050 }; <<
2051 2057
2052 port@61 { !! 2058 mixer_out3_port: port@c {
2053 reg = !! 2059 reg = <0xc>;
2054 2060
2055 xbar_ !! 2061 mixer_out3_ep: endpoint {
2056 !! 2062 remote-endpoint = <&xbar_mixer_out3_ep>;
>> 2063 };
2057 }; 2064 };
2058 }; <<
2059 2065
2060 port@62 { !! 2066 mixer_out4_port: port@d {
2061 reg = !! 2067 reg = <0xd>;
2062 2068
2063 xbar_ !! 2069 mixer_out4_ep: endpoint {
2064 !! 2070 remote-endpoint = <&xbar_mixer_out4_ep>;
>> 2071 };
2065 }; 2072 };
2066 }; <<
2067 2073
2068 xbar_asrc_in1 !! 2074 mixer_out5_port: port@e {
2069 reg = !! 2075 reg = <0xe>;
2070 2076
2071 xbar_ !! 2077 mixer_out5_ep: endpoint {
2072 !! 2078 remote-endpoint = <&xbar_mixer_out5_ep>;
>> 2079 };
2073 }; 2080 };
2074 }; 2081 };
>> 2082 };
2075 2083
2076 port@64 { !! 2084 asrc@2910000 {
2077 reg = !! 2085 status = "okay";
2078 2086
2079 xbar_ !! 2087 ports {
2080 !! 2088 #address-cells = <1>;
2081 }; !! 2089 #size-cells = <0>;
2082 }; <<
2083 2090
2084 xbar_asrc_in2 !! 2091 port@0 {
2085 reg = !! 2092 reg = <0x0>;
2086 2093
2087 xbar_ !! 2094 asrc_in1_ep: endpoint {
2088 !! 2095 remote-endpoint = <&xbar_asrc_in1_ep>;
>> 2096 };
2089 }; 2097 };
2090 }; <<
2091 2098
2092 port@66 { !! 2099 port@1 {
2093 reg = !! 2100 reg = <0x1>;
2094 2101
2095 xbar_ !! 2102 asrc_in2_ep: endpoint {
2096 !! 2103 remote-endpoint = <&xbar_asrc_in2_ep>;
>> 2104 };
2097 }; 2105 };
2098 }; <<
2099 2106
2100 xbar_asrc_in3 !! 2107 port@2 {
2101 reg = !! 2108 reg = <0x2>;
2102 2109
2103 xbar_ !! 2110 asrc_in3_ep: endpoint {
2104 !! 2111 remote-endpoint = <&xbar_asrc_in3_ep>;
>> 2112 };
2105 }; 2113 };
2106 }; <<
2107 2114
2108 port@68 { !! 2115 port@3 {
2109 reg = !! 2116 reg = <0x3>;
2110 2117
2111 xbar_ !! 2118 asrc_in4_ep: endpoint {
2112 !! 2119 remote-endpoint = <&xbar_asrc_in4_ep>;
>> 2120 };
2113 }; 2121 };
2114 }; <<
2115 2122
2116 xbar_asrc_in4 !! 2123 port@4 {
2117 reg = !! 2124 reg = <0x4>;
2118 2125
2119 xbar_ !! 2126 asrc_in5_ep: endpoint {
2120 !! 2127 remote-endpoint = <&xbar_asrc_in5_ep>;
>> 2128 };
2121 }; 2129 };
2122 }; <<
2123 2130
2124 port@6a { !! 2131 port@5 {
2125 reg = !! 2132 reg = <0x5>;
2126 2133
2127 xbar_ !! 2134 asrc_in6_ep: endpoint {
2128 !! 2135 remote-endpoint = <&xbar_asrc_in6_ep>;
>> 2136 };
2129 }; 2137 };
2130 }; <<
2131 2138
2132 xbar_asrc_in5 !! 2139 port@6 {
2133 reg = !! 2140 reg = <0x6>;
2134 2141
2135 xbar_ !! 2142 asrc_in7_ep: endpoint {
2136 !! 2143 remote-endpoint = <&xbar_asrc_in7_ep>;
>> 2144 };
2137 }; 2145 };
2138 }; <<
2139 2146
2140 port@6c { !! 2147 asrc_out1_port: port@7 {
2141 reg = !! 2148 reg = <0x7>;
2142 2149
2143 xbar_ !! 2150 asrc_out1_ep: endpoint {
2144 !! 2151 remote-endpoint = <&xbar_asrc_out1_ep>;
>> 2152 };
2145 }; 2153 };
2146 }; <<
2147 2154
2148 xbar_asrc_in6 !! 2155 asrc_out2_port: port@8 {
2149 reg = !! 2156 reg = <0x8>;
2150 2157
2151 xbar_ !! 2158 asrc_out2_ep: endpoint {
2152 !! 2159 remote-endpoint = <&xbar_asrc_out2_ep>;
>> 2160 };
2153 }; 2161 };
2154 }; <<
2155 2162
2156 port@6e { !! 2163 asrc_out3_port: port@9 {
2157 reg = !! 2164 reg = <0x9>;
2158 2165
2159 xbar_ !! 2166 asrc_out3_ep: endpoint {
2160 !! 2167 remote-endpoint = <&xbar_asrc_out3_ep>;
>> 2168 };
2161 }; 2169 };
2162 }; <<
2163 2170
2164 xbar_asrc_in7 !! 2171 asrc_out4_port: port@a {
2165 reg = !! 2172 reg = <0xa>;
2166 2173
2167 xbar_ !! 2174 asrc_out4_ep: endpoint {
2168 !! 2175 remote-endpoint = <&xbar_asrc_out4_ep>;
>> 2176 };
2169 }; 2177 };
2170 }; <<
2171 2178
2172 xbar_ope1_in_ !! 2179 asrc_out5_port: port@b {
2173 reg = !! 2180 reg = <0xb>;
2174 2181
2175 xbar_ !! 2182 asrc_out5_ep: endpoint {
2176 !! 2183 remote-endpoint = <&xbar_asrc_out5_ep>;
>> 2184 };
2177 }; 2185 };
2178 }; <<
2179 2186
2180 port@71 { !! 2187 asrc_out6_port: port@c {
2181 reg = !! 2188 reg = <0xc>;
2182 2189
2183 xbar_ !! 2190 asrc_out6_ep: endpoint {
2184 !! 2191 remote-endpoint = <&xbar_asrc_out6_ep>;
>> 2192 };
2185 }; 2193 };
2186 }; 2194 };
2187 }; 2195 };
2188 }; 2196 };
2189 <<
2190 dma-controller@2930000 { <<
2191 status = "okay"; <<
2192 }; <<
2193 <<
2194 interrupt-controller@2a40000 <<
2195 status = "okay"; <<
2196 }; <<
2197 }; 2197 };
2198 2198
2199 i2c@3160000 { 2199 i2c@3160000 {
2200 power-monitor@42 { 2200 power-monitor@42 {
2201 compatible = "ti,ina3 2201 compatible = "ti,ina3221";
2202 reg = <0x42>; 2202 reg = <0x42>;
2203 #address-cells = <1>; 2203 #address-cells = <1>;
2204 #size-cells = <0>; 2204 #size-cells = <0>;
2205 2205
2206 input@0 { 2206 input@0 {
2207 reg = <0x0>; 2207 reg = <0x0>;
2208 label = "VDD_ 2208 label = "VDD_MUX";
2209 shunt-resisto 2209 shunt-resistor-micro-ohms = <20000>;
2210 }; 2210 };
2211 2211
2212 input@1 { 2212 input@1 {
2213 reg = <0x1>; 2213 reg = <0x1>;
2214 label = "VDD_ 2214 label = "VDD_5V0_IO_SYS";
2215 shunt-resisto 2215 shunt-resistor-micro-ohms = <5000>;
2216 }; 2216 };
2217 2217
2218 input@2 { 2218 input@2 {
2219 reg = <0x2>; 2219 reg = <0x2>;
2220 label = "VDD_ 2220 label = "VDD_3V3_SYS";
2221 shunt-resisto 2221 shunt-resistor-micro-ohms = <10000>;
2222 }; 2222 };
2223 }; 2223 };
2224 2224
2225 power-monitor@43 { 2225 power-monitor@43 {
2226 compatible = "ti,ina3 2226 compatible = "ti,ina3221";
2227 reg = <0x43>; 2227 reg = <0x43>;
2228 #address-cells = <1>; 2228 #address-cells = <1>;
2229 #size-cells = <0>; 2229 #size-cells = <0>;
2230 2230
2231 input@0 { 2231 input@0 {
2232 reg = <0x0>; 2232 reg = <0x0>;
2233 label = "VDD_ 2233 label = "VDD_3V3_IO_SLP";
2234 shunt-resisto 2234 shunt-resistor-micro-ohms = <10000>;
2235 }; 2235 };
2236 2236
2237 input@1 { 2237 input@1 {
2238 reg = <0x1>; 2238 reg = <0x1>;
2239 label = "VDD_ 2239 label = "VDD_1V8_IO";
2240 shunt-resisto 2240 shunt-resistor-micro-ohms = <10000>;
2241 }; 2241 };
2242 2242
2243 input@2 { 2243 input@2 {
2244 reg = <0x2>; 2244 reg = <0x2>;
2245 label = "VDD_ 2245 label = "VDD_M2_IN";
2246 shunt-resisto 2246 shunt-resistor-micro-ohms = <10000>;
2247 }; 2247 };
2248 }; 2248 };
2249 2249
2250 exp1: gpio@74 { 2250 exp1: gpio@74 {
2251 compatible = "ti,tca9 2251 compatible = "ti,tca9539";
2252 reg = <0x74>; 2252 reg = <0x74>;
2253 2253
2254 interrupt-parent = <& 2254 interrupt-parent = <&gpio>;
2255 interrupts = <TEGRA18 2255 interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
2256 GPIO_AC 2256 GPIO_ACTIVE_LOW>;
2257 2257
2258 #gpio-cells = <2>; 2258 #gpio-cells = <2>;
2259 gpio-controller; 2259 gpio-controller;
2260 2260
2261 vcc-supply = <&vdd_3v 2261 vcc-supply = <&vdd_3v3_sys>;
2262 }; 2262 };
2263 2263
2264 exp2: gpio@77 { 2264 exp2: gpio@77 {
2265 compatible = "ti,tca9 2265 compatible = "ti,tca9539";
2266 reg = <0x77>; 2266 reg = <0x77>;
2267 2267
2268 interrupt-parent = <& 2268 interrupt-parent = <&gpio>;
2269 interrupts = <TEGRA18 2269 interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
2270 GPIO_AC 2270 GPIO_ACTIVE_LOW>;
2271 2271
2272 #gpio-cells = <2>; 2272 #gpio-cells = <2>;
2273 gpio-controller; 2273 gpio-controller;
2274 2274
2275 vcc-supply = <&vdd_1v 2275 vcc-supply = <&vdd_1v8>;
2276 }; 2276 };
2277 }; 2277 };
2278 2278
2279 /* SDMMC1 (SD/MMC) */ 2279 /* SDMMC1 (SD/MMC) */
2280 mmc@3400000 { 2280 mmc@3400000 {
2281 status = "okay"; 2281 status = "okay";
2282 2282
2283 vmmc-supply = <&vdd_sd>; 2283 vmmc-supply = <&vdd_sd>;
2284 }; 2284 };
2285 2285
2286 sata@3507000 { <<
2287 status = "okay"; <<
2288 }; <<
2289 <<
2290 hda@3510000 { 2286 hda@3510000 {
2291 nvidia,model = "NVIDIA Jetson 2287 nvidia,model = "NVIDIA Jetson TX2 HDA";
2292 status = "okay"; 2288 status = "okay";
2293 }; 2289 };
2294 2290
2295 padctl@3520000 { 2291 padctl@3520000 {
2296 status = "okay"; 2292 status = "okay";
2297 2293
2298 avdd-pll-erefeut-supply = <&v 2294 avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
2299 avdd-usb-supply = <&vdd_3v3_s 2295 avdd-usb-supply = <&vdd_3v3_sys>;
2300 vclamp-usb-supply = <&vdd_1v8 2296 vclamp-usb-supply = <&vdd_1v8>;
2301 vddio-hsic-supply = <&gnd>; 2297 vddio-hsic-supply = <&gnd>;
2302 2298
2303 pads { 2299 pads {
2304 usb2 { 2300 usb2 {
2305 status = "oka 2301 status = "okay";
2306 2302
2307 lanes { 2303 lanes {
2308 micro 2304 micro_b: usb2-0 {
2309 2305 nvidia,function = "xusb";
2310 2306 status = "okay";
2311 }; 2307 };
2312 2308
2313 usb2- 2309 usb2-1 {
2314 2310 nvidia,function = "xusb";
2315 2311 status = "okay";
2316 }; 2312 };
2317 2313
2318 usb2- 2314 usb2-2 {
2319 2315 nvidia,function = "xusb";
2320 2316 status = "okay";
2321 }; 2317 };
2322 }; 2318 };
2323 }; 2319 };
2324 2320
2325 usb3 { 2321 usb3 {
2326 status = "oka 2322 status = "okay";
2327 2323
2328 lanes { 2324 lanes {
2329 usb3- 2325 usb3-0 {
2330 2326 nvidia,function = "xusb";
2331 2327 status = "okay";
2332 }; 2328 };
2333 2329
2334 usb3- 2330 usb3-1 {
2335 2331 nvidia,function = "xusb";
2336 2332 status = "okay";
2337 }; 2333 };
2338 2334
2339 usb3- 2335 usb3-2 {
2340 2336 nvidia,function = "xusb";
2341 2337 status = "okay";
2342 }; 2338 };
2343 }; 2339 };
2344 }; 2340 };
2345 }; 2341 };
2346 2342
2347 ports { 2343 ports {
2348 usb2-0 { 2344 usb2-0 {
2349 status = "oka 2345 status = "okay";
2350 mode = "otg"; 2346 mode = "otg";
2351 vbus-supply = 2347 vbus-supply = <&vdd_usb0>;
2352 usb-role-swit 2348 usb-role-switch;
2353 2349
2354 connector { 2350 connector {
2355 compa 2351 compatible = "gpio-usb-b-connector",
2356 2352 "usb-b-connector";
2357 label 2353 label = "micro-USB";
2358 type 2354 type = "micro";
2359 vbus- 2355 vbus-gpios = <&gpio
2360 2356 TEGRA186_MAIN_GPIO(X, 7)
2361 2357 GPIO_ACTIVE_LOW>;
2362 id-gp 2358 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
2363 }; 2359 };
2364 }; 2360 };
2365 2361
2366 usb2-1 { 2362 usb2-1 {
2367 status = "oka 2363 status = "okay";
2368 mode = "host" 2364 mode = "host";
2369 2365
2370 vbus-supply = 2366 vbus-supply = <&vdd_usb1>;
2371 }; 2367 };
2372 2368
2373 usb3-0 { 2369 usb3-0 {
2374 nvidia,usb2-c 2370 nvidia,usb2-companion = <1>;
2375 vbus-supply = 2371 vbus-supply = <&vdd_usb1>;
2376 status = "oka 2372 status = "okay";
2377 }; 2373 };
2378 }; 2374 };
2379 }; 2375 };
2380 2376
2381 usb@3530000 { 2377 usb@3530000 {
2382 status = "okay"; 2378 status = "okay";
2383 2379
2384 phys = <&{/padctl@3520000/pads 2380 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
2385 <&{/padctl@3520000/pads 2381 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
2386 <&{/padctl@3520000/pads 2382 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
2387 phy-names = "usb2-0", "usb2-1 2383 phy-names = "usb2-0", "usb2-1", "usb3-0";
2388 }; 2384 };
2389 2385
2390 usb@3550000 { 2386 usb@3550000 {
2391 status = "okay"; 2387 status = "okay";
2392 2388
2393 phys = <µ_b>; 2389 phys = <µ_b>;
2394 phy-names = "usb2-0"; 2390 phy-names = "usb2-0";
2395 }; 2391 };
2396 2392
2397 i2c@c250000 { 2393 i2c@c250000 {
2398 /* carrier board ID EEPROM */ 2394 /* carrier board ID EEPROM */
2399 eeprom@57 { 2395 eeprom@57 {
2400 compatible = "atmel,2 2396 compatible = "atmel,24c02";
2401 reg = <0x57>; 2397 reg = <0x57>;
2402 2398
2403 label = "system"; 2399 label = "system";
2404 vcc-supply = <&vdd_1v 2400 vcc-supply = <&vdd_1v8>;
2405 address-width = <8>; 2401 address-width = <8>;
2406 pagesize = <8>; 2402 pagesize = <8>;
2407 size = <256>; 2403 size = <256>;
2408 read-only; 2404 read-only;
2409 }; 2405 };
2410 }; 2406 };
2411 2407
2412 pcie@10003000 { 2408 pcie@10003000 {
2413 status = "okay"; 2409 status = "okay";
2414 2410
2415 dvdd-pex-supply = <&vdd_pex>; 2411 dvdd-pex-supply = <&vdd_pex>;
2416 hvdd-pex-pll-supply = <&vdd_1 2412 hvdd-pex-pll-supply = <&vdd_1v8>;
2417 hvdd-pex-supply = <&vdd_1v8>; 2413 hvdd-pex-supply = <&vdd_1v8>;
2418 vddio-pexctl-aud-supply = <&v 2414 vddio-pexctl-aud-supply = <&vdd_1v8>;
2419 2415
2420 pci@1,0 { 2416 pci@1,0 {
2421 nvidia,num-lanes = <4 2417 nvidia,num-lanes = <4>;
2422 status = "okay"; 2418 status = "okay";
2423 }; 2419 };
2424 2420
2425 pci@2,0 { 2421 pci@2,0 {
2426 nvidia,num-lanes = <0 2422 nvidia,num-lanes = <0>;
2427 status = "disabled"; 2423 status = "disabled";
2428 }; 2424 };
2429 2425
2430 pci@3,0 { 2426 pci@3,0 {
2431 nvidia,num-lanes = <1 2427 nvidia,num-lanes = <1>;
2432 status = "disabled"; 2428 status = "disabled";
2433 }; 2429 };
2434 }; 2430 };
2435 2431
2436 host1x@13e00000 { 2432 host1x@13e00000 {
2437 status = "okay"; 2433 status = "okay";
2438 2434
2439 dpaux@15040000 { 2435 dpaux@15040000 {
2440 status = "okay"; 2436 status = "okay";
2441 }; 2437 };
2442 2438
2443 display-hub@15200000 { 2439 display-hub@15200000 {
2444 status = "okay"; 2440 status = "okay";
2445 }; 2441 };
2446 2442
2447 dsi@15300000 { 2443 dsi@15300000 {
2448 status = "disabled"; 2444 status = "disabled";
2449 }; 2445 };
2450 2446
2451 /* DP on E3320 */ 2447 /* DP on E3320 */
2452 sor@15540000 { 2448 sor@15540000 {
2453 status = "okay"; 2449 status = "okay";
2454 2450
2455 avdd-io-hdmi-dp-suppl 2451 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2456 vdd-hdmi-dp-pll-suppl 2452 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2457 2453
2458 nvidia,dpaux = <&dpau 2454 nvidia,dpaux = <&dpaux>;
2459 }; 2455 };
2460 2456
2461 sor@15580000 { 2457 sor@15580000 {
2462 status = "okay"; 2458 status = "okay";
2463 2459
2464 avdd-io-hdmi-dp-suppl 2460 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2465 vdd-hdmi-dp-pll-suppl 2461 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2466 hdmi-supply = <&vdd_h 2462 hdmi-supply = <&vdd_hdmi>;
2467 2463
2468 nvidia,ddc-i2c-bus = 2464 nvidia,ddc-i2c-bus = <&ddc>;
2469 nvidia,hpd-gpio = <&g 2465 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
2470 2466 GPIO_ACTIVE_LOW>;
2471 }; 2467 };
2472 2468
2473 dpaux@155c0000 { 2469 dpaux@155c0000 {
2474 status = "okay"; 2470 status = "okay";
2475 }; 2471 };
2476 }; 2472 };
2477 2473
>> 2474 sata@3507000 {
>> 2475 status = "okay";
>> 2476 };
>> 2477
2478 gpio-keys { 2478 gpio-keys {
2479 compatible = "gpio-keys"; 2479 compatible = "gpio-keys";
2480 2480
2481 key-power { 2481 key-power {
2482 label = "Power"; 2482 label = "Power";
2483 gpios = <&gpio_aon TE 2483 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
2484 GP 2484 GPIO_ACTIVE_LOW>;
2485 linux,input-type = <E 2485 linux,input-type = <EV_KEY>;
2486 linux,code = <KEY_POW 2486 linux,code = <KEY_POWER>;
2487 debounce-interval = < 2487 debounce-interval = <10>;
2488 wakeup-event-action = 2488 wakeup-event-action = <EV_ACT_ASSERTED>;
2489 wakeup-source; 2489 wakeup-source;
2490 }; 2490 };
2491 2491
2492 key-volume-down { !! 2492 key-volume-up {
2493 label = "Volume Down" !! 2493 label = "Volume Up";
2494 gpios = <&gpio_aon TE !! 2494 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
2495 GP 2495 GPIO_ACTIVE_LOW>;
2496 linux,input-type = <E 2496 linux,input-type = <EV_KEY>;
2497 linux,code = <KEY_VOL !! 2497 linux,code = <KEY_VOLUMEUP>;
2498 debounce-interval = < 2498 debounce-interval = <10>;
2499 }; 2499 };
2500 2500
2501 key-volume-up { !! 2501 key-volume-down {
2502 label = "Volume Up"; !! 2502 label = "Volume Down";
2503 gpios = <&gpio_aon TE !! 2503 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
2504 GP 2504 GPIO_ACTIVE_LOW>;
2505 linux,input-type = <E 2505 linux,input-type = <EV_KEY>;
2506 linux,code = <KEY_VOL !! 2506 linux,code = <KEY_VOLUMEDOWN>;
2507 debounce-interval = < 2507 debounce-interval = <10>;
2508 }; 2508 };
2509 }; 2509 };
2510 2510
2511 vdd_sd: regulator-vdd-sd { 2511 vdd_sd: regulator-vdd-sd {
2512 compatible = "regulator-fixed 2512 compatible = "regulator-fixed";
2513 regulator-name = "SD_CARD_SW_ 2513 regulator-name = "SD_CARD_SW_PWR";
2514 regulator-min-microvolt = <33 2514 regulator-min-microvolt = <3300000>;
2515 regulator-max-microvolt = <33 2515 regulator-max-microvolt = <3300000>;
2516 2516
2517 gpio = <&gpio TEGRA186_MAIN_G 2517 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
2518 enable-active-high; 2518 enable-active-high;
2519 2519
2520 vin-supply = <&vdd_3v3_sys>; 2520 vin-supply = <&vdd_3v3_sys>;
2521 }; 2521 };
2522 2522
2523 vdd_hdmi: regulator-vdd-hdmi { 2523 vdd_hdmi: regulator-vdd-hdmi {
2524 compatible = "regulator-fixed 2524 compatible = "regulator-fixed";
2525 regulator-name = "VDD_HDMI_5V 2525 regulator-name = "VDD_HDMI_5V0";
2526 regulator-min-microvolt = <50 2526 regulator-min-microvolt = <5000000>;
2527 regulator-max-microvolt = <50 2527 regulator-max-microvolt = <5000000>;
2528 2528
2529 gpio = <&exp1 14 GPIO_ACTIVE_ 2529 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
2530 enable-active-high; 2530 enable-active-high;
2531 2531
2532 vin-supply = <&vdd_5v0_sys>; 2532 vin-supply = <&vdd_5v0_sys>;
2533 }; 2533 };
2534 2534
2535 vdd_usb0: regulator-vdd-usb0 { 2535 vdd_usb0: regulator-vdd-usb0 {
2536 compatible = "regulator-fixed 2536 compatible = "regulator-fixed";
2537 regulator-name = "VDD_USB0"; 2537 regulator-name = "VDD_USB0";
2538 regulator-min-microvolt = <50 2538 regulator-min-microvolt = <5000000>;
2539 regulator-max-microvolt = <50 2539 regulator-max-microvolt = <5000000>;
2540 2540
2541 gpio = <&gpio TEGRA186_MAIN_G 2541 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
2542 enable-active-high; 2542 enable-active-high;
2543 2543
2544 vin-supply = <&vdd_5v0_sys>; 2544 vin-supply = <&vdd_5v0_sys>;
2545 }; 2545 };
2546 2546
2547 vdd_usb1: regulator-vdd-usb1 { 2547 vdd_usb1: regulator-vdd-usb1 {
2548 compatible = "regulator-fixed 2548 compatible = "regulator-fixed";
2549 regulator-name = "VDD_USB1"; 2549 regulator-name = "VDD_USB1";
2550 regulator-min-microvolt = <50 2550 regulator-min-microvolt = <5000000>;
2551 regulator-max-microvolt = <50 2551 regulator-max-microvolt = <5000000>;
2552 2552
2553 gpio = <&gpio TEGRA186_MAIN_G 2553 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
2554 enable-active-high; 2554 enable-active-high;
2555 2555
2556 vin-supply = <&vdd_5v0_sys>; 2556 vin-supply = <&vdd_5v0_sys>;
2557 }; 2557 };
2558 2558
2559 sound { 2559 sound {
2560 compatible = "nvidia,tegra186 2560 compatible = "nvidia,tegra186-audio-graph-card";
2561 status = "okay"; 2561 status = "okay";
2562 2562
2563 dais = /* FE */ 2563 dais = /* FE */
2564 <&admaif0_port>, <&adm 2564 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
2565 <&admaif4_port>, <&adm 2565 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
2566 <&admaif8_port>, <&adm 2566 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
2567 <&admaif12_port>, <&ad 2567 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
2568 <&admaif16_port>, <&ad 2568 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
2569 /* Router */ 2569 /* Router */
2570 <&xbar_i2s1_port>, <&x 2570 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
2571 <&xbar_i2s4_port>, <&x 2571 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
2572 <&xbar_dmic1_port>, <& 2572 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
2573 <&xbar_dspk1_port>, <& 2573 <&xbar_dspk1_port>, <&xbar_dspk2_port>,
2574 <&xbar_sfc1_in_port>, 2574 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
2575 <&xbar_sfc3_in_port>, 2575 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
2576 <&xbar_mvc1_in_port>, 2576 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
2577 <&xbar_amx1_in1_port>, 2577 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
2578 <&xbar_amx1_in3_port>, 2578 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
2579 <&xbar_amx2_in1_port>, 2579 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
2580 <&xbar_amx2_in3_port>, 2580 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
2581 <&xbar_amx3_in1_port>, 2581 <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
2582 <&xbar_amx3_in3_port>, 2582 <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
2583 <&xbar_amx4_in1_port>, 2583 <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
2584 <&xbar_amx4_in3_port>, 2584 <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
2585 <&xbar_adx1_in_port>, 2585 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
2586 <&xbar_adx3_in_port>, 2586 <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
2587 <&xbar_mixer_in1_port> 2587 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
2588 <&xbar_mixer_in3_port> 2588 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
2589 <&xbar_mixer_in5_port> 2589 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
2590 <&xbar_mixer_in7_port> 2590 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
2591 <&xbar_mixer_in9_port> 2591 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
2592 <&xbar_asrc_in1_port>, 2592 <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
2593 <&xbar_asrc_in3_port>, 2593 <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
2594 <&xbar_asrc_in5_port>, 2594 <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
2595 <&xbar_asrc_in7_port>, 2595 <&xbar_asrc_in7_port>,
2596 <&xbar_ope1_in_port>, 2596 <&xbar_ope1_in_port>,
2597 /* HW accelerators */ 2597 /* HW accelerators */
2598 <&sfc1_out_port>, <&sf 2598 <&sfc1_out_port>, <&sfc2_out_port>,
2599 <&sfc3_out_port>, <&sf 2599 <&sfc3_out_port>, <&sfc4_out_port>,
2600 <&mvc1_out_port>, <&mv 2600 <&mvc1_out_port>, <&mvc2_out_port>,
2601 <&amx1_out_port>, <&am 2601 <&amx1_out_port>, <&amx2_out_port>,
2602 <&amx3_out_port>, <&am 2602 <&amx3_out_port>, <&amx4_out_port>,
2603 <&adx1_out1_port>, <&a 2603 <&adx1_out1_port>, <&adx1_out2_port>,
2604 <&adx1_out3_port>, <&a 2604 <&adx1_out3_port>, <&adx1_out4_port>,
2605 <&adx2_out1_port>, <&a 2605 <&adx2_out1_port>, <&adx2_out2_port>,
2606 <&adx2_out3_port>, <&a 2606 <&adx2_out3_port>, <&adx2_out4_port>,
2607 <&adx3_out1_port>, <&a 2607 <&adx3_out1_port>, <&adx3_out2_port>,
2608 <&adx3_out3_port>, <&a 2608 <&adx3_out3_port>, <&adx3_out4_port>,
2609 <&adx4_out1_port>, <&a 2609 <&adx4_out1_port>, <&adx4_out2_port>,
2610 <&adx4_out3_port>, <&a 2610 <&adx4_out3_port>, <&adx4_out4_port>,
2611 <&mixer_out1_port>, <& 2611 <&mixer_out1_port>, <&mixer_out2_port>,
2612 <&mixer_out3_port>, <& 2612 <&mixer_out3_port>, <&mixer_out4_port>,
2613 <&mixer_out5_port>, 2613 <&mixer_out5_port>,
2614 <&asrc_out1_port>, <&a 2614 <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
2615 <&asrc_out4_port>, <&a 2615 <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
2616 <&ope1_out_port>, 2616 <&ope1_out_port>,
2617 /* I/O */ 2617 /* I/O */
2618 <&i2s1_port>, <&i2s2_p 2618 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
2619 <&i2s5_port>, <&i2s6_p 2619 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
2620 <&dmic3_port>, <&dspk1 2620 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
2621 2621
2622 label = "NVIDIA Jetson TX2 AP 2622 label = "NVIDIA Jetson TX2 APE";
2623 }; 2623 };
2624 }; 2624 };
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