1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io
8 #include <dt-bindings/power/tegra186-powergate
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-th
11
12 / {
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 misc@100000 {
19 compatible = "nvidia,tegra186-
20 reg = <0x0 0x00100000 0x0 0xf0
21 <0x0 0x0010f000 0x0 0x10
22 };
23
24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186-
26 reg-names = "security", "gpio"
27 reg = <0x0 0x2200000 0x0 0x100
28 <0x0 0x2210000 0x0 0x100
29 interrupts = <GIC_SPI 47 IRQ_
30 <GIC_SPI 50 IRQ_
31 <GIC_SPI 53 IRQ_
32 <GIC_SPI 56 IRQ_
33 <GIC_SPI 59 IRQ_
34 <GIC_SPI 180 IRQ_
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
39 };
40
41 ethernet@2490000 {
42 compatible = "nvidia,tegra186-
43 "snps,dwc-qos-eth
44 reg = <0x0 0x02490000 0x0 0x10
45 interrupts = <GIC_SPI 194 IRQ_
46 <GIC_SPI 195 IRQ_
47 <GIC_SPI 190 IRQ_
48 <GIC_SPI 186 IRQ_
49 <GIC_SPI 191 IRQ_
50 <GIC_SPI 187 IRQ_
51 <GIC_SPI 192 IRQ_
52 <GIC_SPI 188 IRQ_
53 <GIC_SPI 193 IRQ_
54 <GIC_SPI 189 IRQ_
55 clocks = <&bpmp TEGRA186_CLK_A
56 <&bpmp TEGRA186_CLK_E
57 <&bpmp TEGRA186_CLK_E
58 <&bpmp TEGRA186_CLK_E
59 <&bpmp TEGRA186_CLK_E
60 clock-names = "master_bus", "s
61 resets = <&bpmp TEGRA186_RESET
62 reset-names = "eqos";
63 interconnects = <&mc TEGRA186_
64 <&mc TEGRA186_
65 interconnect-names = "dma-mem"
66 iommus = <&smmu TEGRA186_SID_E
67 status = "disabled";
68
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
72 snps,txpbl = <32>;
73 snps,rxpbl = <8>;
74 };
75
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-
78 reg = <0x0 0x2600000 0x0 0x210
79 resets = <&bpmp TEGRA186_RESET
80 reset-names = "gpcdma";
81 interrupts = <GIC_SPI 75 IRQ_T
82 <GIC_SPI 76 IRQ_T
83 <GIC_SPI 77 IRQ_T
84 <GIC_SPI 78 IRQ_T
85 <GIC_SPI 79 IRQ_T
86 <GIC_SPI 80 IRQ_T
87 <GIC_SPI 81 IRQ_T
88 <GIC_SPI 82 IRQ_T
89 <GIC_SPI 83 IRQ_T
90 <GIC_SPI 84 IRQ_T
91 <GIC_SPI 85 IRQ_T
92 <GIC_SPI 86 IRQ_T
93 <GIC_SPI 87 IRQ_T
94 <GIC_SPI 88 IRQ_T
95 <GIC_SPI 89 IRQ_T
96 <GIC_SPI 90 IRQ_T
97 <GIC_SPI 91 IRQ_T
98 <GIC_SPI 92 IRQ_T
99 <GIC_SPI 93 IRQ_T
100 <GIC_SPI 94 IRQ_T
101 <GIC_SPI 95 IRQ_T
102 <GIC_SPI 96 IRQ_T
103 <GIC_SPI 97 IRQ_T
104 <GIC_SPI 98 IRQ_T
105 <GIC_SPI 99 IRQ_T
106 <GIC_SPI 100 IRQ_
107 <GIC_SPI 101 IRQ_
108 <GIC_SPI 102 IRQ_
109 <GIC_SPI 103 IRQ_
110 <GIC_SPI 104 IRQ_
111 <GIC_SPI 105 IRQ_
112 <GIC_SPI 106 IRQ_
113 #dma-cells = <1>;
114 iommus = <&smmu TEGRA186_SID_G
115 dma-coherent;
116 dma-channel-mask = <0xfffffffe
117 status = "okay";
118 };
119
120 aconnect@2900000 {
121 compatible = "nvidia,tegra186-
122 "nvidia,tegra210-
123 clocks = <&bpmp TEGRA186_CLK_A
124 <&bpmp TEGRA186_CLK_A
125 clock-names = "ape", "apb2ape"
126 power-domains = <&bpmp TEGRA18
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0x02900000 0x0 0x029
130 status = "disabled";
131
132 tegra_ahub: ahub@2900800 {
133 compatible = "nvidia,t
134 reg = <0x02900800 0x80
135 clocks = <&bpmp TEGRA1
136 clock-names = "ahub";
137 assigned-clocks = <&bp
138 assigned-clock-parents
139 assigned-clock-rates =
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x02900800 0
143 status = "disabled";
144
145 tegra_i2s1: i2s@290100
146 compatible = "
147 "
148 reg = <0x29010
149 clocks = <&bpm
150 <&bpm
151 clock-names =
152 assigned-clock
153 assigned-clock
154 assigned-clock
155 sound-name-pre
156 status = "disa
157 };
158
159 tegra_i2s2: i2s@290110
160 compatible = "
161 "
162 reg = <0x29011
163 clocks = <&bpm
164 <&bpm
165 clock-names =
166 assigned-clock
167 assigned-clock
168 assigned-clock
169 sound-name-pre
170 status = "disa
171 };
172
173 tegra_i2s3: i2s@290120
174 compatible = "
175 "
176 reg = <0x29012
177 clocks = <&bpm
178 <&bpm
179 clock-names =
180 assigned-clock
181 assigned-clock
182 assigned-clock
183 sound-name-pre
184 status = "disa
185 };
186
187 tegra_i2s4: i2s@290130
188 compatible = "
189 "
190 reg = <0x29013
191 clocks = <&bpm
192 <&bpm
193 clock-names =
194 assigned-clock
195 assigned-clock
196 assigned-clock
197 sound-name-pre
198 status = "disa
199 };
200
201 tegra_i2s5: i2s@290140
202 compatible = "
203 "
204 reg = <0x29014
205 clocks = <&bpm
206 <&bpm
207 clock-names =
208 assigned-clock
209 assigned-clock
210 assigned-clock
211 sound-name-pre
212 status = "disa
213 };
214
215 tegra_i2s6: i2s@290150
216 compatible = "
217 "
218 reg = <0x29015
219 clocks = <&bpm
220 <&bpm
221 clock-names =
222 assigned-clock
223 assigned-clock
224 assigned-clock
225 sound-name-pre
226 status = "disa
227 };
228
229 tegra_sfc1: sfc@290200
230 compatible = "
231 "
232 reg = <0x29020
233 sound-name-pre
234 status = "disa
235 };
236
237 tegra_sfc2: sfc@290220
238 compatible = "
239 "
240 reg = <0x29022
241 sound-name-pre
242 status = "disa
243 };
244
245 tegra_sfc3: sfc@290240
246 compatible = "
247 "
248 reg = <0x29024
249 sound-name-pre
250 status = "disa
251 };
252
253 tegra_sfc4: sfc@290260
254 compatible = "
255 "
256 reg = <0x29026
257 sound-name-pre
258 status = "disa
259 };
260
261 tegra_amx1: amx@290300
262 compatible = "
263 "
264 reg = <0x29030
265 sound-name-pre
266 status = "disa
267 };
268
269 tegra_amx2: amx@290310
270 compatible = "
271 "
272 reg = <0x29031
273 sound-name-pre
274 status = "disa
275 };
276
277 tegra_amx3: amx@290320
278 compatible = "
279 "
280 reg = <0x29032
281 sound-name-pre
282 status = "disa
283 };
284
285 tegra_amx4: amx@290330
286 compatible = "
287 "
288 reg = <0x29033
289 sound-name-pre
290 status = "disa
291 };
292
293 tegra_adx1: adx@290380
294 compatible = "
295 "
296 reg = <0x29038
297 sound-name-pre
298 status = "disa
299 };
300
301 tegra_adx2: adx@290390
302 compatible = "
303 "
304 reg = <0x29039
305 sound-name-pre
306 status = "disa
307 };
308
309 tegra_adx3: adx@2903a0
310 compatible = "
311 "
312 reg = <0x2903a
313 sound-name-pre
314 status = "disa
315 };
316
317 tegra_adx4: adx@2903b0
318 compatible = "
319 "
320 reg = <0x2903b
321 sound-name-pre
322 status = "disa
323 };
324
325 tegra_dmic1: dmic@2904
326 compatible = "
327 reg = <0x29040
328 clocks = <&bpm
329 clock-names =
330 assigned-clock
331 assigned-clock
332 assigned-clock
333 sound-name-pre
334 status = "disa
335 };
336
337 tegra_dmic2: dmic@2904
338 compatible = "
339 reg = <0x29041
340 clocks = <&bpm
341 clock-names =
342 assigned-clock
343 assigned-clock
344 assigned-clock
345 sound-name-pre
346 status = "disa
347 };
348
349 tegra_dmic3: dmic@2904
350 compatible = "
351 reg = <0x29042
352 clocks = <&bpm
353 clock-names =
354 assigned-clock
355 assigned-clock
356 assigned-clock
357 sound-name-pre
358 status = "disa
359 };
360
361 tegra_dmic4: dmic@2904
362 compatible = "
363 reg = <0x29043
364 clocks = <&bpm
365 clock-names =
366 assigned-clock
367 assigned-clock
368 assigned-clock
369 sound-name-pre
370 status = "disa
371 };
372
373 tegra_dspk1: dspk@2905
374 compatible = "
375 reg = <0x29050
376 clocks = <&bpm
377 clock-names =
378 assigned-clock
379 assigned-clock
380 assigned-clock
381 sound-name-pre
382 status = "disa
383 };
384
385 tegra_dspk2: dspk@2905
386 compatible = "
387 reg = <0x29051
388 clocks = <&bpm
389 clock-names =
390 assigned-clock
391 assigned-clock
392 assigned-clock
393 sound-name-pre
394 status = "disa
395 };
396
397 tegra_ope1: processing
398 compatible = "
399 "
400 reg = <0x29080
401 #address-cells
402 #size-cells =
403 ranges;
404 sound-name-pre
405 status = "disa
406
407 equalizer@2908
408 compat
409
410 reg =
411 };
412
413 dynamic-range-
414 compat
415
416 reg =
417 };
418 };
419
420 tegra_mvc1: mvc@290a00
421 compatible = "
422 "
423 reg = <0x290a0
424 sound-name-pre
425 status = "disa
426 };
427
428 tegra_mvc2: mvc@290a20
429 compatible = "
430 "
431 reg = <0x290a2
432 sound-name-pre
433 status = "disa
434 };
435
436 tegra_amixer: amixer@2
437 compatible = "
438 "
439 reg = <0x290bb
440 sound-name-pre
441 status = "disa
442 };
443
444 tegra_admaif: admaif@2
445 compatible = "
446 reg = <0x0290f
447 dmas = <&adma
448 <&adma
449 <&adma
450 <&adma
451 <&adma
452 <&adma
453 <&adma
454 <&adma
455 <&adma
456 <&adma
457 <&adma
458 <&adma
459 <&adma
460 <&adma
461 <&adma
462 <&adma
463 <&adma
464 <&adma
465 <&adma
466 <&adma
467 dma-names = "r
468 "r
469 "r
470 "r
471 "r
472 "r
473 "r
474 "r
475 "r
476 "r
477 "r
478 "r
479 "r
480 "r
481 "r
482 "r
483 "r
484 "r
485 "r
486 "r
487 status = "disa
488 };
489
490 tegra_asrc: asrc@29100
491 compatible = "
492 reg = <0x29100
493 sound-name-pre
494 status = "disa
495 };
496 };
497
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,t
500 reg = <0x02930000 0x20
501 interrupt-parent = <&a
502 interrupts = <GIC_SPI
503 <GIC_SPI
504 <GIC_SPI
505 <GIC_SPI
506 <GIC_SPI
507 <GIC_SPI
508 <GIC_SPI
509 <GIC_SPI
510 <GIC_SPI
511 <GIC_SPI
512 <GIC_SPI
513 <GIC_SPI
514 <GIC_SPI
515 <GIC_SPI
516 <GIC_SPI
517 <GIC_SPI
518 <GIC_SPI
519 <GIC_SPI
520 <GIC_SPI
521 <GIC_SPI
522 <GIC_SPI
523 <GIC_SPI
524 <GIC_SPI
525 <GIC_SPI
526 <GIC_SPI
527 <GIC_SPI
528 <GIC_SPI
529 <GIC_SPI
530 <GIC_SPI
531 <GIC_SPI
532 <GIC_SPI
533 <GIC_SPI
534 #dma-cells = <1>;
535 clocks = <&bpmp TEGRA1
536 clock-names = "d_audio
537 status = "disabled";
538 };
539
540 agic: interrupt-controller@2a4
541 compatible = "nvidia,t
542 "nvidia,t
543 #interrupt-cells = <3>
544 interrupt-controller;
545 reg = <0x02a41000 0x10
546 <0x02a42000 0x20
547 interrupts = <GIC_SPI
548 (GIC_CPU_MASK_
549 clocks = <&bpmp TEGRA1
550 clock-names = "clk";
551 status = "disabled";
552 };
553 };
554
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-
557 reg = <0x0 0x02c00000 0x0 0x10
558 <0x0 0x02c10000 0x0 0x10
559 <0x0 0x02c20000 0x0 0x10
560 <0x0 0x02c30000 0x0 0x10
561 <0x0 0x02c40000 0x0 0x10
562 <0x0 0x02c50000 0x0 0x10
563 reg-names = "sid", "broadcast"
564 interrupts = <GIC_SPI 223 IRQ_
565 status = "disabled";
566
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
569 #size-cells = <2>;
570
571 ranges = <0x0 0x02c00000 0x0 0
572
573 /*
574 * Memory clients have access
575 * controller can address.
576 */
577 dma-ranges = <0x0 0x0 0x0 0x0
578
579 emc: external-memory-controlle
580 compatible = "nvidia,t
581 reg = <0x0 0x02c60000
582 interrupts = <GIC_SPI
583 clocks = <&bpmp TEGRA1
584 clock-names = "emc";
585
586 #interconnect-cells =
587
588 nvidia,bpmp = <&bpmp>;
589 };
590 };
591
592 timer@3010000 {
593 compatible = "nvidia,tegra186-
594 reg = <0x0 0x03010000 0x0 0x00
595 interrupts = <GIC_SPI 0 IRQ_TY
596 <GIC_SPI 1 IRQ_TY
597 <GIC_SPI 2 IRQ_TY
598 <GIC_SPI 3 IRQ_TY
599 <GIC_SPI 4 IRQ_TY
600 <GIC_SPI 5 IRQ_TY
601 <GIC_SPI 6 IRQ_TY
602 <GIC_SPI 7 IRQ_TY
603 <GIC_SPI 8 IRQ_TY
604 <GIC_SPI 9 IRQ_TY
605 status = "okay";
606 };
607
608 uarta: serial@3100000 {
609 compatible = "nvidia,tegra186-
610 reg = <0x0 0x03100000 0x0 0x40
611 reg-shift = <2>;
612 interrupts = <GIC_SPI 112 IRQ_
613 clocks = <&bpmp TEGRA186_CLK_U
614 resets = <&bpmp TEGRA186_RESET
615 status = "disabled";
616 };
617
618 uartb: serial@3110000 {
619 compatible = "nvidia,tegra186-
620 reg = <0x0 0x03110000 0x0 0x40
621 reg-shift = <2>;
622 interrupts = <GIC_SPI 113 IRQ_
623 clocks = <&bpmp TEGRA186_CLK_U
624 clock-names = "serial";
625 resets = <&bpmp TEGRA186_RESET
626 reset-names = "serial";
627 status = "disabled";
628 };
629
630 uartd: serial@3130000 {
631 compatible = "nvidia,tegra186-
632 reg = <0x0 0x03130000 0x0 0x40
633 reg-shift = <2>;
634 interrupts = <GIC_SPI 115 IRQ_
635 clocks = <&bpmp TEGRA186_CLK_U
636 clock-names = "serial";
637 resets = <&bpmp TEGRA186_RESET
638 reset-names = "serial";
639 status = "disabled";
640 };
641
642 uarte: serial@3140000 {
643 compatible = "nvidia,tegra186-
644 reg = <0x0 0x03140000 0x0 0x40
645 reg-shift = <2>;
646 interrupts = <GIC_SPI 116 IRQ_
647 clocks = <&bpmp TEGRA186_CLK_U
648 clock-names = "serial";
649 resets = <&bpmp TEGRA186_RESET
650 reset-names = "serial";
651 status = "disabled";
652 };
653
654 uartf: serial@3150000 {
655 compatible = "nvidia,tegra186-
656 reg = <0x0 0x03150000 0x0 0x40
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 117 IRQ_
659 clocks = <&bpmp TEGRA186_CLK_U
660 clock-names = "serial";
661 resets = <&bpmp TEGRA186_RESET
662 reset-names = "serial";
663 status = "disabled";
664 };
665
666 gen1_i2c: i2c@3160000 {
667 compatible = "nvidia,tegra186-
668 reg = <0x0 0x03160000 0x0 0x10
669 interrupts = <GIC_SPI 25 IRQ_T
670 #address-cells = <1>;
671 #size-cells = <0>;
672 clocks = <&bpmp TEGRA186_CLK_I
673 clock-names = "div-clk";
674 resets = <&bpmp TEGRA186_RESET
675 reset-names = "i2c";
676 dmas = <&gpcdma 21>, <&gpcdma
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 cam_i2c: i2c@3180000 {
682 compatible = "nvidia,tegra186-
683 reg = <0x0 0x03180000 0x0 0x10
684 interrupts = <GIC_SPI 27 IRQ_T
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clocks = <&bpmp TEGRA186_CLK_I
688 clock-names = "div-clk";
689 resets = <&bpmp TEGRA186_RESET
690 reset-names = "i2c";
691 dmas = <&gpcdma 23>, <&gpcdma
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
695
696 /* shares pads with dpaux1 */
697 dp_aux_ch1_i2c: i2c@3190000 {
698 compatible = "nvidia,tegra186-
699 reg = <0x0 0x03190000 0x0 0x10
700 interrupts = <GIC_SPI 28 IRQ_T
701 #address-cells = <1>;
702 #size-cells = <0>;
703 clocks = <&bpmp TEGRA186_CLK_I
704 clock-names = "div-clk";
705 resets = <&bpmp TEGRA186_RESET
706 reset-names = "i2c";
707 pinctrl-names = "default", "id
708 pinctrl-0 = <&state_dpaux1_i2c
709 pinctrl-1 = <&state_dpaux1_off
710 dmas = <&gpcdma 26>, <&gpcdma
711 dma-names = "rx", "tx";
712 status = "disabled";
713 };
714
715 /* controlled by BPMP, should not be e
716 pwr_i2c: i2c@31a0000 {
717 compatible = "nvidia,tegra186-
718 reg = <0x0 0x031a0000 0x0 0x10
719 interrupts = <GIC_SPI 29 IRQ_T
720 #address-cells = <1>;
721 #size-cells = <0>;
722 clocks = <&bpmp TEGRA186_CLK_I
723 clock-names = "div-clk";
724 resets = <&bpmp TEGRA186_RESET
725 reset-names = "i2c";
726 status = "disabled";
727 };
728
729 /* shares pads with dpaux0 */
730 dp_aux_ch0_i2c: i2c@31b0000 {
731 compatible = "nvidia,tegra186-
732 reg = <0x0 0x031b0000 0x0 0x10
733 interrupts = <GIC_SPI 30 IRQ_T
734 #address-cells = <1>;
735 #size-cells = <0>;
736 clocks = <&bpmp TEGRA186_CLK_I
737 clock-names = "div-clk";
738 resets = <&bpmp TEGRA186_RESET
739 reset-names = "i2c";
740 pinctrl-names = "default", "id
741 pinctrl-0 = <&state_dpaux_i2c>
742 pinctrl-1 = <&state_dpaux_off>
743 dmas = <&gpcdma 30>, <&gpcdma
744 dma-names = "rx", "tx";
745 status = "disabled";
746 };
747
748 gen7_i2c: i2c@31c0000 {
749 compatible = "nvidia,tegra186-
750 reg = <0x0 0x031c0000 0x0 0x10
751 interrupts = <GIC_SPI 31 IRQ_T
752 #address-cells = <1>;
753 #size-cells = <0>;
754 clocks = <&bpmp TEGRA186_CLK_I
755 clock-names = "div-clk";
756 resets = <&bpmp TEGRA186_RESET
757 reset-names = "i2c";
758 dmas = <&gpcdma 27>, <&gpcdma
759 dma-names = "rx", "tx";
760 status = "disabled";
761 };
762
763 gen9_i2c: i2c@31e0000 {
764 compatible = "nvidia,tegra186-
765 reg = <0x0 0x031e0000 0x0 0x10
766 interrupts = <GIC_SPI 33 IRQ_T
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&bpmp TEGRA186_CLK_I
770 clock-names = "div-clk";
771 resets = <&bpmp TEGRA186_RESET
772 reset-names = "i2c";
773 dmas = <&gpcdma 31>, <&gpcdma
774 dma-names = "rx", "tx";
775 status = "disabled";
776 };
777
778 pwm1: pwm@3280000 {
779 compatible = "nvidia,tegra186-
780 reg = <0x0 0x3280000 0x0 0x100
781 clocks = <&bpmp TEGRA186_CLK_P
782 resets = <&bpmp TEGRA186_RESET
783 reset-names = "pwm";
784 status = "disabled";
785 #pwm-cells = <2>;
786 };
787
788 pwm2: pwm@3290000 {
789 compatible = "nvidia,tegra186-
790 reg = <0x0 0x3290000 0x0 0x100
791 clocks = <&bpmp TEGRA186_CLK_P
792 resets = <&bpmp TEGRA186_RESET
793 reset-names = "pwm";
794 status = "disabled";
795 #pwm-cells = <2>;
796 };
797
798 pwm3: pwm@32a0000 {
799 compatible = "nvidia,tegra186-
800 reg = <0x0 0x32a0000 0x0 0x100
801 clocks = <&bpmp TEGRA186_CLK_P
802 resets = <&bpmp TEGRA186_RESET
803 reset-names = "pwm";
804 status = "disabled";
805 #pwm-cells = <2>;
806 };
807
808 pwm5: pwm@32c0000 {
809 compatible = "nvidia,tegra186-
810 reg = <0x0 0x32c0000 0x0 0x100
811 clocks = <&bpmp TEGRA186_CLK_P
812 resets = <&bpmp TEGRA186_RESET
813 reset-names = "pwm";
814 status = "disabled";
815 #pwm-cells = <2>;
816 };
817
818 pwm6: pwm@32d0000 {
819 compatible = "nvidia,tegra186-
820 reg = <0x0 0x32d0000 0x0 0x100
821 clocks = <&bpmp TEGRA186_CLK_P
822 resets = <&bpmp TEGRA186_RESET
823 reset-names = "pwm";
824 status = "disabled";
825 #pwm-cells = <2>;
826 };
827
828 pwm7: pwm@32e0000 {
829 compatible = "nvidia,tegra186-
830 reg = <0x0 0x32e0000 0x0 0x100
831 clocks = <&bpmp TEGRA186_CLK_P
832 resets = <&bpmp TEGRA186_RESET
833 reset-names = "pwm";
834 status = "disabled";
835 #pwm-cells = <2>;
836 };
837
838 pwm8: pwm@32f0000 {
839 compatible = "nvidia,tegra186-
840 reg = <0x0 0x32f0000 0x0 0x100
841 clocks = <&bpmp TEGRA186_CLK_P
842 resets = <&bpmp TEGRA186_RESET
843 reset-names = "pwm";
844 status = "disabled";
845 #pwm-cells = <2>;
846 };
847
848 sdmmc1: mmc@3400000 {
849 compatible = "nvidia,tegra186-
850 reg = <0x0 0x03400000 0x0 0x10
851 interrupts = <GIC_SPI 62 IRQ_T
852 clocks = <&bpmp TEGRA186_CLK_S
853 <&bpmp TEGRA186_CLK_S
854 clock-names = "sdhci", "tmclk"
855 resets = <&bpmp TEGRA186_RESET
856 reset-names = "sdhci";
857 interconnects = <&mc TEGRA186_
858 <&mc TEGRA186_
859 interconnect-names = "dma-mem"
860 iommus = <&smmu TEGRA186_SID_S
861 pinctrl-names = "sdmmc-3v3", "
862 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-off
865 nvidia,pad-autocal-pull-down-o
866 nvidia,pad-autocal-pull-up-off
867 nvidia,pad-autocal-pull-down-o
868 nvidia,pad-autocal-pull-up-off
869 nvidia,pad-autocal-pull-down-o
870 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA
873 <&bpmp TEGRA
874 assigned-clock-parents = <&bpm
875 status = "disabled";
876 };
877
878 sdmmc2: mmc@3420000 {
879 compatible = "nvidia,tegra186-
880 reg = <0x0 0x03420000 0x0 0x10
881 interrupts = <GIC_SPI 63 IRQ_T
882 clocks = <&bpmp TEGRA186_CLK_S
883 <&bpmp TEGRA186_CLK_S
884 clock-names = "sdhci", "tmclk"
885 resets = <&bpmp TEGRA186_RESET
886 reset-names = "sdhci";
887 interconnects = <&mc TEGRA186_
888 <&mc TEGRA186_
889 interconnect-names = "dma-mem"
890 iommus = <&smmu TEGRA186_SID_S
891 pinctrl-names = "sdmmc-3v3", "
892 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-off
895 nvidia,pad-autocal-pull-down-o
896 nvidia,pad-autocal-pull-up-off
897 nvidia,pad-autocal-pull-down-o
898 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>;
900 status = "disabled";
901 };
902
903 sdmmc3: mmc@3440000 {
904 compatible = "nvidia,tegra186-
905 reg = <0x0 0x03440000 0x0 0x10
906 interrupts = <GIC_SPI 64 IRQ_T
907 clocks = <&bpmp TEGRA186_CLK_S
908 <&bpmp TEGRA186_CLK_S
909 clock-names = "sdhci", "tmclk"
910 resets = <&bpmp TEGRA186_RESET
911 reset-names = "sdhci";
912 interconnects = <&mc TEGRA186_
913 <&mc TEGRA186_
914 interconnect-names = "dma-mem"
915 iommus = <&smmu TEGRA186_SID_S
916 pinctrl-names = "sdmmc-3v3", "
917 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-off
920 nvidia,pad-autocal-pull-down-o
921 nvidia,pad-autocal-pull-up-off
922 nvidia,pad-autocal-pull-down-o
923 nvidia,pad-autocal-pull-up-off
924 nvidia,pad-autocal-pull-down-o
925 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>;
927 status = "disabled";
928 };
929
930 sdmmc4: mmc@3460000 {
931 compatible = "nvidia,tegra186-
932 reg = <0x0 0x03460000 0x0 0x10
933 interrupts = <GIC_SPI 65 IRQ_T
934 clocks = <&bpmp TEGRA186_CLK_S
935 <&bpmp TEGRA186_CLK_S
936 clock-names = "sdhci", "tmclk"
937 assigned-clocks = <&bpmp TEGRA
938 <&bpmp TEGRA
939 assigned-clock-parents = <&bpm
940 resets = <&bpmp TEGRA186_RESET
941 reset-names = "sdhci";
942 interconnects = <&mc TEGRA186_
943 <&mc TEGRA186_
944 interconnect-names = "dma-mem"
945 iommus = <&smmu TEGRA186_SID_S
946 nvidia,pad-autocal-pull-up-off
947 nvidia,pad-autocal-pull-down-o
948 nvidia,pad-autocal-pull-up-off
949 nvidia,pad-autocal-pull-down-o
950 nvidia,pad-autocal-pull-up-off
951 nvidia,pad-autocal-pull-down-o
952 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>;
955 mmc-hs400-1_8v;
956 supports-cqe;
957 status = "disabled";
958 };
959
960 sata@3507000 {
961 compatible = "nvidia,tegra186-
962 reg = <0x0 0x03507000 0x0 0x00
963 <0x0 0x03500000 0x0 0x00
964 <0x0 0x03A90000 0x0 0x00
965 interrupts = <GIC_SPI 197 IRQ_
966
967 power-domains = <&bpmp TEGRA18
968 interconnects = <&mc TEGRA186_
969 <&mc TEGRA186_
970 interconnect-names = "dma-mem"
971 iommus = <&smmu TEGRA186_SID_S
972
973 clocks = <&bpmp TEGRA186_CLK_S
974 <&bpmp TEGRA186_CLK_S
975 clock-names = "sata", "sata-oo
976 assigned-clocks = <&bpmp TEGRA
977 <&bpmp TEGRA
978 assigned-clock-parents = <&bpm
979 <&bpm
980 assigned-clock-rates = <102000
981 <204000
982 resets = <&bpmp TEGRA186_RESET
983 <&bpmp TEGRA186_RESET_
984 reset-names = "sata", "sata-co
985 status = "disabled";
986 };
987
988 hda@3510000 {
989 compatible = "nvidia,tegra186-
990 reg = <0x0 0x03510000 0x0 0x10
991 interrupts = <GIC_SPI 161 IRQ_
992 clocks = <&bpmp TEGRA186_CLK_H
993 <&bpmp TEGRA186_CLK_H
994 <&bpmp TEGRA186_CLK_H
995 clock-names = "hda", "hda2hdmi
996 resets = <&bpmp TEGRA186_RESET
997 <&bpmp TEGRA186_RESET
998 <&bpmp TEGRA186_RESET
999 reset-names = "hda", "hda2hdmi
1000 power-domains = <&bpmp TEGRA1
1001 interconnects = <&mc TEGRA186
1002 <&mc TEGRA186
1003 interconnect-names = "dma-mem
1004 iommus = <&smmu TEGRA186_SID_
1005 status = "disabled";
1006 };
1007
1008 padctl: padctl@3520000 {
1009 compatible = "nvidia,tegra186
1010 reg = <0x0 0x03520000 0x0 0x1
1011 <0x0 0x03540000 0x0 0x1
1012 reg-names = "padctl", "ao";
1013 interrupts = <GIC_SPI 167 IRQ
1014
1015 resets = <&bpmp TEGRA186_RESE
1016 reset-names = "padctl";
1017
1018 status = "disabled";
1019
1020 pads {
1021 usb2 {
1022 clocks = <&bp
1023 clock-names =
1024 status = "dis
1025
1026 lanes {
1027 usb2-
1028
1029
1030 };
1031
1032 usb2-
1033
1034
1035 };
1036
1037 usb2-
1038
1039
1040 };
1041 };
1042 };
1043
1044 hsic {
1045 clocks = <&bp
1046 clock-names =
1047 status = "dis
1048
1049 lanes {
1050 hsic-
1051
1052
1053 };
1054 };
1055 };
1056
1057 usb3 {
1058 status = "dis
1059
1060 lanes {
1061 usb3-
1062
1063
1064 };
1065
1066 usb3-
1067
1068
1069 };
1070
1071 usb3-
1072
1073
1074 };
1075 };
1076 };
1077 };
1078
1079 ports {
1080 usb2-0 {
1081 status = "dis
1082 };
1083
1084 usb2-1 {
1085 status = "dis
1086 };
1087
1088 usb2-2 {
1089 status = "dis
1090 };
1091
1092 hsic-0 {
1093 status = "dis
1094 };
1095
1096 usb3-0 {
1097 status = "dis
1098 };
1099
1100 usb3-1 {
1101 status = "dis
1102 };
1103
1104 usb3-2 {
1105 status = "dis
1106 };
1107 };
1108 };
1109
1110 usb@3530000 {
1111 compatible = "nvidia,tegra186
1112 reg = <0x0 0x03530000 0x0 0x8
1113 <0x0 0x03538000 0x0 0x1
1114 reg-names = "hcd", "fpci";
1115 interrupts = <GIC_SPI 163 IRQ
1116 <GIC_SPI 164 IRQ
1117 clocks = <&bpmp TEGRA186_CLK_
1118 <&bpmp TEGRA186_CLK_
1119 <&bpmp TEGRA186_CLK_
1120 <&bpmp TEGRA186_CLK_
1121 <&bpmp TEGRA186_CLK_
1122 <&bpmp TEGRA186_CLK_
1123 <&bpmp TEGRA186_CLK_
1124 <&bpmp TEGRA186_CLK_
1125 <&bpmp TEGRA186_CLK_
1126 clock-names = "xusb_host", "x
1127 "xusb_ss_src",
1128 "pll_u_480m", "
1129 power-domains = <&bpmp TEGRA1
1130 <&bpmp TEGRA1
1131 power-domain-names = "xusb_ho
1132 interconnects = <&mc TEGRA186
1133 <&mc TEGRA186
1134 interconnect-names = "dma-mem
1135 iommus = <&smmu TEGRA186_SID_
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 status = "disabled";
1139
1140 nvidia,xusb-padctl = <&padctl
1141 };
1142
1143 usb@3550000 {
1144 compatible = "nvidia,tegra186
1145 reg = <0x0 0x03550000 0x0 0x8
1146 <0x0 0x03558000 0x0 0x1
1147 reg-names = "base", "fpci";
1148 interrupts = <GIC_SPI 166 IRQ
1149 clocks = <&bpmp TEGRA186_CLK_
1150 <&bpmp TEGRA186_CLK_
1151 <&bpmp TEGRA186_CLK_
1152 <&bpmp TEGRA186_CLK_
1153 clock-names = "dev", "ss", "s
1154 interconnects = <&mc TEGRA186
1155 <&mc TEGRA186
1156 interconnect-names = "dma-mem
1157 iommus = <&smmu TEGRA186_SID_
1158 power-domains = <&bpmp TEGRA1
1159 <&bpmp TEGRA1
1160 power-domain-names = "dev", "
1161 nvidia,xusb-padctl = <&padctl
1162 status = "disabled";
1163 };
1164
1165 fuse@3820000 {
1166 compatible = "nvidia,tegra186
1167 reg = <0x0 0x03820000 0x0 0x1
1168 clocks = <&bpmp TEGRA186_CLK_
1169 clock-names = "fuse";
1170 };
1171
1172 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>;
1175 interrupt-controller;
1176 reg = <0x0 0x03881000 0x0 0x1
1177 <0x0 0x03882000 0x0 0x2
1178 <0x0 0x03884000 0x0 0x2
1179 <0x0 0x03886000 0x0 0x2
1180 interrupts = <GIC_PPI 9
1181 (GIC_CPU_MASK_SIMPLE(
1182 interrupt-parent = <&gic>;
1183 };
1184
1185 cec@3960000 {
1186 compatible = "nvidia,tegra186
1187 reg = <0x0 0x03960000 0x0 0x1
1188 interrupts = <GIC_SPI 162 IRQ
1189 clocks = <&bpmp TEGRA186_CLK_
1190 clock-names = "cec";
1191 status = "disabled";
1192 };
1193
1194 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186
1196 reg = <0x0 0x03c00000 0x0 0xa
1197 interrupts = <GIC_SPI 176 IRQ
1198 interrupt-names = "doorbell";
1199 #mbox-cells = <2>;
1200 status = "disabled";
1201 };
1202
1203 gen2_i2c: i2c@c240000 {
1204 compatible = "nvidia,tegra186
1205 reg = <0x0 0x0c240000 0x0 0x1
1206 interrupts = <GIC_SPI 26 IRQ_
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 clocks = <&bpmp TEGRA186_CLK_
1210 clock-names = "div-clk";
1211 resets = <&bpmp TEGRA186_RESE
1212 reset-names = "i2c";
1213 dmas = <&gpcdma 22>, <&gpcdma
1214 dma-names = "rx", "tx";
1215 status = "disabled";
1216 };
1217
1218 gen8_i2c: i2c@c250000 {
1219 compatible = "nvidia,tegra186
1220 reg = <0x0 0x0c250000 0x0 0x1
1221 interrupts = <GIC_SPI 32 IRQ_
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 clocks = <&bpmp TEGRA186_CLK_
1225 clock-names = "div-clk";
1226 resets = <&bpmp TEGRA186_RESE
1227 reset-names = "i2c";
1228 dmas = <&gpcdma 0>, <&gpcdma
1229 dma-names = "rx", "tx";
1230 status = "disabled";
1231 };
1232
1233 uartc: serial@c280000 {
1234 compatible = "nvidia,tegra186
1235 reg = <0x0 0x0c280000 0x0 0x4
1236 reg-shift = <2>;
1237 interrupts = <GIC_SPI 114 IRQ
1238 clocks = <&bpmp TEGRA186_CLK_
1239 clock-names = "serial";
1240 resets = <&bpmp TEGRA186_RESE
1241 reset-names = "serial";
1242 status = "disabled";
1243 };
1244
1245 uartg: serial@c290000 {
1246 compatible = "nvidia,tegra186
1247 reg = <0x0 0x0c290000 0x0 0x4
1248 reg-shift = <2>;
1249 interrupts = <GIC_SPI 118 IRQ
1250 clocks = <&bpmp TEGRA186_CLK_
1251 clock-names = "serial";
1252 resets = <&bpmp TEGRA186_RESE
1253 reset-names = "serial";
1254 status = "disabled";
1255 };
1256
1257 rtc: rtc@c2a0000 {
1258 compatible = "nvidia,tegra186
1259 reg = <0 0x0c2a0000 0 0x10000
1260 interrupt-parent = <&pmc>;
1261 interrupts = <73 IRQ_TYPE_LEV
1262 clocks = <&bpmp TEGRA186_CLK_
1263 clock-names = "rtc";
1264 status = "disabled";
1265 };
1266
1267 gpio_aon: gpio@c2f0000 {
1268 compatible = "nvidia,tegra186
1269 reg-names = "security", "gpio
1270 reg = <0x0 0xc2f0000 0x0 0x10
1271 <0x0 0xc2f1000 0x0 0x10
1272 interrupts = <GIC_SPI 60 IRQ_
1273 gpio-controller;
1274 #gpio-cells = <2>;
1275 interrupt-controller;
1276 #interrupt-cells = <2>;
1277 };
1278
1279 pwm4: pwm@c340000 {
1280 compatible = "nvidia,tegra186
1281 reg = <0x0 0xc340000 0x0 0x10
1282 clocks = <&bpmp TEGRA186_CLK_
1283 resets = <&bpmp TEGRA186_RESE
1284 reset-names = "pwm";
1285 status = "disabled";
1286 #pwm-cells = <2>;
1287 };
1288
1289 pmc: pmc@c360000 {
1290 compatible = "nvidia,tegra186
1291 reg = <0 0x0c360000 0 0x10000
1292 <0 0x0c370000 0 0x10000
1293 <0 0x0c380000 0 0x10000
1294 <0 0x0c390000 0 0x10000
1295 reg-names = "pmc", "wake", "a
1296
1297 #interrupt-cells = <2>;
1298 interrupt-controller;
1299
1300 sdmmc1_1v8: sdmmc1-1v8 {
1301 pins = "sdmmc1-hv";
1302 power-source = <TEGRA
1303 };
1304
1305 sdmmc1_3v3: sdmmc1-3v3 {
1306 pins = "sdmmc1-hv";
1307 power-source = <TEGRA
1308 };
1309
1310 sdmmc2_1v8: sdmmc2-1v8 {
1311 pins = "sdmmc2-hv";
1312 power-source = <TEGRA
1313 };
1314
1315 sdmmc2_3v3: sdmmc2-3v3 {
1316 pins = "sdmmc2-hv";
1317 power-source = <TEGRA
1318 };
1319
1320 sdmmc3_1v8: sdmmc3-1v8 {
1321 pins = "sdmmc3-hv";
1322 power-source = <TEGRA
1323 };
1324
1325 sdmmc3_3v3: sdmmc3-3v3 {
1326 pins = "sdmmc3-hv";
1327 power-source = <TEGRA
1328 };
1329 };
1330
1331 ccplex@e000000 {
1332 compatible = "nvidia,tegra186
1333 reg = <0x0 0x0e000000 0x0 0x4
1334
1335 nvidia,bpmp = <&bpmp>;
1336 };
1337
1338 pcie@10003000 {
1339 compatible = "nvidia,tegra186
1340 power-domains = <&bpmp TEGRA1
1341 device_type = "pci";
1342 reg = <0x0 0x10003000 0x0 0x0
1343 <0x0 0x10003800 0x0 0x0
1344 <0x0 0x40000000 0x0 0x1
1345 reg-names = "pads", "afi", "c
1346
1347 interrupts = <GIC_SPI 72 IRQ_
1348 <GIC_SPI 73 IRQ_
1349 interrupt-names = "intr", "ms
1350
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0
1353 interrupt-map = <0 0 0 0 &gic
1354
1355 bus-range = <0x00 0xff>;
1356 #address-cells = <3>;
1357 #size-cells = <2>;
1358
1359 ranges = <0x02000000 0 0x1000
1360 <0x02000000 0 0x1000
1361 <0x02000000 0 0x1000
1362 <0x01000000 0 0x0
1363 <0x02000000 0 0x5010
1364 <0x42000000 0 0x5800
1365
1366 clocks = <&bpmp TEGRA186_CLK_
1367 <&bpmp TEGRA186_CLK_
1368 <&bpmp TEGRA186_CLK_
1369 clock-names = "pex", "afi", "
1370
1371 resets = <&bpmp TEGRA186_RESE
1372 <&bpmp TEGRA186_RESE
1373 <&bpmp TEGRA186_RESE
1374 reset-names = "pex", "afi", "
1375
1376 interconnects = <&mc TEGRA186
1377 <&mc TEGRA186
1378 interconnect-names = "dma-mem
1379
1380 iommus = <&smmu TEGRA186_SID_
1381 iommu-map = <0x0 &smmu TEGRA1
1382 iommu-map-mask = <0x0>;
1383
1384 status = "disabled";
1385
1386 pci@1,0 {
1387 device_type = "pci";
1388 assigned-addresses =
1389 reg = <0x000800 0 0 0
1390 status = "disabled";
1391
1392 #address-cells = <3>;
1393 #size-cells = <2>;
1394 ranges;
1395
1396 nvidia,num-lanes = <2
1397 };
1398
1399 pci@2,0 {
1400 device_type = "pci";
1401 assigned-addresses =
1402 reg = <0x001000 0 0 0
1403 status = "disabled";
1404
1405 #address-cells = <3>;
1406 #size-cells = <2>;
1407 ranges;
1408
1409 nvidia,num-lanes = <1
1410 };
1411
1412 pci@3,0 {
1413 device_type = "pci";
1414 assigned-addresses =
1415 reg = <0x001800 0 0 0
1416 status = "disabled";
1417
1418 #address-cells = <3>;
1419 #size-cells = <2>;
1420 ranges;
1421
1422 nvidia,num-lanes = <1
1423 };
1424 };
1425
1426 smmu: iommu@12000000 {
1427 compatible = "nvidia,tegra186
1428 reg = <0 0x12000000 0 0x80000
1429 interrupts = <GIC_SPI 170 IRQ
1430 <GIC_SPI 170 IRQ
1431 <GIC_SPI 170 IRQ
1432 <GIC_SPI 170 IRQ
1433 <GIC_SPI 170 IRQ
1434 <GIC_SPI 170 IRQ
1435 <GIC_SPI 170 IRQ
1436 <GIC_SPI 170 IRQ
1437 <GIC_SPI 170 IRQ
1438 <GIC_SPI 170 IRQ
1439 <GIC_SPI 170 IRQ
1440 <GIC_SPI 170 IRQ
1441 <GIC_SPI 170 IRQ
1442 <GIC_SPI 170 IRQ
1443 <GIC_SPI 170 IRQ
1444 <GIC_SPI 170 IRQ
1445 <GIC_SPI 170 IRQ
1446 <GIC_SPI 170 IRQ
1447 <GIC_SPI 170 IRQ
1448 <GIC_SPI 170 IRQ
1449 <GIC_SPI 170 IRQ
1450 <GIC_SPI 170 IRQ
1451 <GIC_SPI 170 IRQ
1452 <GIC_SPI 170 IRQ
1453 <GIC_SPI 170 IRQ
1454 <GIC_SPI 170 IRQ
1455 <GIC_SPI 170 IRQ
1456 <GIC_SPI 170 IRQ
1457 <GIC_SPI 170 IRQ
1458 <GIC_SPI 170 IRQ
1459 <GIC_SPI 170 IRQ
1460 <GIC_SPI 170 IRQ
1461 <GIC_SPI 170 IRQ
1462 <GIC_SPI 170 IRQ
1463 <GIC_SPI 170 IRQ
1464 <GIC_SPI 170 IRQ
1465 <GIC_SPI 170 IRQ
1466 <GIC_SPI 170 IRQ
1467 <GIC_SPI 170 IRQ
1468 <GIC_SPI 170 IRQ
1469 <GIC_SPI 170 IRQ
1470 <GIC_SPI 170 IRQ
1471 <GIC_SPI 170 IRQ
1472 <GIC_SPI 170 IRQ
1473 <GIC_SPI 170 IRQ
1474 <GIC_SPI 170 IRQ
1475 <GIC_SPI 170 IRQ
1476 <GIC_SPI 170 IRQ
1477 <GIC_SPI 170 IRQ
1478 <GIC_SPI 170 IRQ
1479 <GIC_SPI 170 IRQ
1480 <GIC_SPI 170 IRQ
1481 <GIC_SPI 170 IRQ
1482 <GIC_SPI 170 IRQ
1483 <GIC_SPI 170 IRQ
1484 <GIC_SPI 170 IRQ
1485 <GIC_SPI 170 IRQ
1486 <GIC_SPI 170 IRQ
1487 <GIC_SPI 170 IRQ
1488 <GIC_SPI 170 IRQ
1489 <GIC_SPI 170 IRQ
1490 <GIC_SPI 170 IRQ
1491 <GIC_SPI 170 IRQ
1492 <GIC_SPI 170 IRQ
1493 <GIC_SPI 170 IRQ
1494 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>;
1496 #iommu-cells = <1>;
1497
1498 nvidia,memory-controller = <&
1499 };
1500
1501 host1x@13e00000 {
1502 compatible = "nvidia,tegra186
1503 reg = <0x0 0x13e00000 0x0 0x1
1504 <0x0 0x13e10000 0x0 0x1
1505 reg-names = "hypervisor", "vm
1506 interrupts = <GIC_SPI 265 IRQ
1507 <GIC_SPI 263 IRQ
1508 interrupt-names = "syncpt", "
1509 clocks = <&bpmp TEGRA186_CLK_
1510 clock-names = "host1x";
1511 resets = <&bpmp TEGRA186_RESE
1512 reset-names = "host1x";
1513
1514 #address-cells = <1>;
1515 #size-cells = <1>;
1516
1517 ranges = <0x15000000 0x0 0x15
1518
1519 interconnects = <&mc TEGRA186
1520 interconnect-names = "dma-mem
1521
1522 iommus = <&smmu TEGRA186_SID_
1523
1524 /* Context isolation domains
1525 iommu-map = <0 &smmu TEGRA186
1526 <1 &smmu TEGRA186
1527 <2 &smmu TEGRA186
1528 <3 &smmu TEGRA186
1529 <4 &smmu TEGRA186
1530 <5 &smmu TEGRA186
1531 <6 &smmu TEGRA186
1532 <7 &smmu TEGRA186
1533
1534 dpaux1: dpaux@15040000 {
1535 compatible = "nvidia,
1536 reg = <0x15040000 0x1
1537 interrupts = <GIC_SPI
1538 clocks = <&bpmp TEGRA
1539 <&bpmp TEGRA
1540 clock-names = "dpaux"
1541 resets = <&bpmp TEGRA
1542 reset-names = "dpaux"
1543 status = "disabled";
1544
1545 power-domains = <&bpm
1546
1547 state_dpaux1_aux: pin
1548 groups = "dpa
1549 function = "a
1550 };
1551
1552 state_dpaux1_i2c: pin
1553 groups = "dpa
1554 function = "i
1555 };
1556
1557 state_dpaux1_off: pin
1558 groups = "dpa
1559 function = "o
1560 };
1561
1562 i2c-bus {
1563 #address-cell
1564 #size-cells =
1565 };
1566 };
1567
1568 display-hub@15200000 {
1569 compatible = "nvidia,
1570 reg = <0x15200000 0x0
1571 resets = <&bpmp TEGRA
1572 <&bpmp TEGRA
1573 <&bpmp TEGRA
1574 <&bpmp TEGRA
1575 <&bpmp TEGRA
1576 <&bpmp TEGRA
1577 <&bpmp TEGRA
1578 reset-names = "misc",
1579 "wgrp3"
1580 clocks = <&bpmp TEGRA
1581 <&bpmp TEGRA
1582 <&bpmp TEGRA
1583 clock-names = "disp",
1584 status = "disabled";
1585
1586 power-domains = <&bpm
1587
1588 #address-cells = <1>;
1589 #size-cells = <1>;
1590
1591 ranges = <0x15200000
1592
1593 display@15200000 {
1594 compatible =
1595 reg = <0x1520
1596 interrupts =
1597 clocks = <&bp
1598 clock-names =
1599 resets = <&bp
1600 reset-names =
1601
1602 power-domains
1603 interconnects
1604
1605 interconnect-
1606 iommus = <&sm
1607
1608 nvidia,output
1609 nvidia,head =
1610 };
1611
1612 display@15210000 {
1613 compatible =
1614 reg = <0x1521
1615 interrupts =
1616 clocks = <&bp
1617 clock-names =
1618 resets = <&bp
1619 reset-names =
1620
1621 power-domains
1622 interconnects
1623
1624 interconnect-
1625 iommus = <&sm
1626
1627 nvidia,output
1628 nvidia,head =
1629 };
1630
1631 display@15220000 {
1632 compatible =
1633 reg = <0x1522
1634 interrupts =
1635 clocks = <&bp
1636 clock-names =
1637 resets = <&bp
1638 reset-names =
1639
1640 power-domains
1641 interconnects
1642
1643 interconnect-
1644 iommus = <&sm
1645
1646 nvidia,output
1647 nvidia,head =
1648 };
1649 };
1650
1651 dsia: dsi@15300000 {
1652 compatible = "nvidia,
1653 reg = <0x15300000 0x1
1654 interrupts = <GIC_SPI
1655 clocks = <&bpmp TEGRA
1656 <&bpmp TEGRA
1657 <&bpmp TEGRA
1658 clock-names = "dsi",
1659 resets = <&bpmp TEGRA
1660 reset-names = "dsi";
1661 status = "disabled";
1662
1663 power-domains = <&bpm
1664 };
1665
1666 vic@15340000 {
1667 compatible = "nvidia,
1668 reg = <0x15340000 0x4
1669 interrupts = <GIC_SPI
1670 clocks = <&bpmp TEGRA
1671 clock-names = "vic";
1672 resets = <&bpmp TEGRA
1673 reset-names = "vic";
1674
1675 power-domains = <&bpm
1676 interconnects = <&mc
1677 <&mc
1678 interconnect-names =
1679 iommus = <&smmu TEGRA
1680 };
1681
1682 nvjpg@15380000 {
1683 compatible = "nvidia,
1684 reg = <0x15380000 0x4
1685 clocks = <&bpmp TEGRA
1686 clock-names = "nvjpg"
1687 resets = <&bpmp TEGRA
1688 reset-names = "nvjpg"
1689
1690 power-domains = <&bpm
1691 interconnects = <&mc
1692 <&mc
1693 interconnect-names =
1694 iommus = <&smmu TEGRA
1695 };
1696
1697 dsib: dsi@15400000 {
1698 compatible = "nvidia,
1699 reg = <0x15400000 0x1
1700 interrupts = <GIC_SPI
1701 clocks = <&bpmp TEGRA
1702 <&bpmp TEGRA
1703 <&bpmp TEGRA
1704 clock-names = "dsi",
1705 resets = <&bpmp TEGRA
1706 reset-names = "dsi";
1707 status = "disabled";
1708
1709 power-domains = <&bpm
1710 };
1711
1712 nvdec@15480000 {
1713 compatible = "nvidia,
1714 reg = <0x15480000 0x4
1715 clocks = <&bpmp TEGRA
1716 clock-names = "nvdec"
1717 resets = <&bpmp TEGRA
1718 reset-names = "nvdec"
1719
1720 power-domains = <&bpm
1721 interconnects = <&mc
1722 <&mc
1723 <&mc
1724 interconnect-names =
1725 iommus = <&smmu TEGRA
1726 };
1727
1728 nvenc@154c0000 {
1729 compatible = "nvidia,
1730 reg = <0x154c0000 0x4
1731 clocks = <&bpmp TEGRA
1732 clock-names = "nvenc"
1733 resets = <&bpmp TEGRA
1734 reset-names = "nvenc"
1735
1736 power-domains = <&bpm
1737 interconnects = <&mc
1738 <&mc
1739 interconnect-names =
1740 iommus = <&smmu TEGRA
1741 };
1742
1743 sor0: sor@15540000 {
1744 compatible = "nvidia,
1745 reg = <0x15540000 0x1
1746 interrupts = <GIC_SPI
1747 clocks = <&bpmp TEGRA
1748 <&bpmp TEGRA
1749 <&bpmp TEGRA
1750 <&bpmp TEGRA
1751 <&bpmp TEGRA
1752 <&bpmp TEGRA
1753 clock-names = "sor",
1754 "pad";
1755 resets = <&bpmp TEGRA
1756 reset-names = "sor";
1757 pinctrl-0 = <&state_d
1758 pinctrl-1 = <&state_d
1759 pinctrl-2 = <&state_d
1760 pinctrl-names = "aux"
1761 status = "disabled";
1762
1763 power-domains = <&bpm
1764 nvidia,interface = <0
1765 };
1766
1767 sor1: sor@15580000 {
1768 compatible = "nvidia,
1769 reg = <0x15580000 0x1
1770 interrupts = <GIC_SPI
1771 clocks = <&bpmp TEGRA
1772 <&bpmp TEGRA
1773 <&bpmp TEGRA
1774 <&bpmp TEGRA
1775 <&bpmp TEGRA
1776 <&bpmp TEGRA
1777 clock-names = "sor",
1778 "pad";
1779 resets = <&bpmp TEGRA
1780 reset-names = "sor";
1781 pinctrl-0 = <&state_d
1782 pinctrl-1 = <&state_d
1783 pinctrl-2 = <&state_d
1784 pinctrl-names = "aux"
1785 status = "disabled";
1786
1787 power-domains = <&bpm
1788 nvidia,interface = <1
1789 };
1790
1791 dpaux: dpaux@155c0000 {
1792 compatible = "nvidia,
1793 reg = <0x155c0000 0x1
1794 interrupts = <GIC_SPI
1795 clocks = <&bpmp TEGRA
1796 <&bpmp TEGRA
1797 clock-names = "dpaux"
1798 resets = <&bpmp TEGRA
1799 reset-names = "dpaux"
1800 status = "disabled";
1801
1802 power-domains = <&bpm
1803
1804 state_dpaux_aux: pinm
1805 groups = "dpa
1806 function = "a
1807 };
1808
1809 state_dpaux_i2c: pinm
1810 groups = "dpa
1811 function = "i
1812 };
1813
1814 state_dpaux_off: pinm
1815 groups = "dpa
1816 function = "o
1817 };
1818
1819 i2c-bus {
1820 #address-cell
1821 #size-cells =
1822 };
1823 };
1824
1825 padctl@15880000 {
1826 compatible = "nvidia,
1827 reg = <0x15880000 0x1
1828 resets = <&bpmp TEGRA
1829 reset-names = "dsi";
1830 status = "disabled";
1831 };
1832
1833 dsic: dsi@15900000 {
1834 compatible = "nvidia,
1835 reg = <0x15900000 0x1
1836 interrupts = <GIC_SPI
1837 clocks = <&bpmp TEGRA
1838 <&bpmp TEGRA
1839 <&bpmp TEGRA
1840 clock-names = "dsi",
1841 resets = <&bpmp TEGRA
1842 reset-names = "dsi";
1843 status = "disabled";
1844
1845 power-domains = <&bpm
1846 };
1847
1848 dsid: dsi@15940000 {
1849 compatible = "nvidia,
1850 reg = <0x15940000 0x1
1851 interrupts = <GIC_SPI
1852 clocks = <&bpmp TEGRA
1853 <&bpmp TEGRA
1854 <&bpmp TEGRA
1855 clock-names = "dsi",
1856 resets = <&bpmp TEGRA
1857 reset-names = "dsi";
1858 status = "disabled";
1859
1860 power-domains = <&bpm
1861 };
1862 };
1863
1864 gpu@17000000 {
1865 compatible = "nvidia,gp10b";
1866 reg = <0x0 0x17000000 0x0 0x1
1867 <0x0 0x18000000 0x0 0x1
1868 interrupts = <GIC_SPI 70 IRQ_
1869 <GIC_SPI 71 IRQ_
1870 interrupt-names = "stall", "n
1871
1872 clocks = <&bpmp TEGRA186_CLK_
1873 <&bpmp TEGRA186_CLK_
1874 clock-names = "gpu", "pwr";
1875 resets = <&bpmp TEGRA186_RESE
1876 reset-names = "gpu";
1877 status = "disabled";
1878
1879 power-domains = <&bpmp TEGRA1
1880 interconnects = <&mc TEGRA186
1881 <&mc TEGRA186
1882 <&mc TEGRA186
1883 <&mc TEGRA186
1884 interconnect-names = "dma-mem
1885 };
1886
1887 sram@30000000 {
1888 compatible = "nvidia,tegra186
1889 reg = <0x0 0x30000000 0x0 0x5
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1892 ranges = <0x0 0x0 0x30000000
1893 no-memory-wc;
1894
1895 cpu_bpmp_tx: sram@4e000 {
1896 reg = <0x4e000 0x1000
1897 label = "cpu-bpmp-tx"
1898 pool;
1899 };
1900
1901 cpu_bpmp_rx: sram@4f000 {
1902 reg = <0x4f000 0x1000
1903 label = "cpu-bpmp-rx"
1904 pool;
1905 };
1906 };
1907
1908 bpmp: bpmp {
1909 compatible = "nvidia,tegra186
1910 interconnects = <&mc TEGRA186
1911 <&mc TEGRA186
1912 <&mc TEGRA186
1913 <&mc TEGRA186
1914 interconnect-names = "read",
1915 iommus = <&smmu TEGRA186_SID_
1916 mboxes = <&hsp_top0 TEGRA_HSP
1917 TEGRA_HSP
1918 shmem = <&cpu_bpmp_tx>, <&cpu
1919 #clock-cells = <1>;
1920 #reset-cells = <1>;
1921 #power-domain-cells = <1>;
1922
1923 bpmp_i2c: i2c {
1924 compatible = "nvidia,
1925 nvidia,bpmp-bus-id =
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1928 status = "disabled";
1929 };
1930
1931 bpmp_thermal: thermal {
1932 compatible = "nvidia,
1933 #thermal-sensor-cells
1934 };
1935 };
1936
1937 cpus {
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1940
1941 denver_0: cpu@0 {
1942 compatible = "nvidia,
1943 device_type = "cpu";
1944 i-cache-size = <0x200
1945 i-cache-line-size = <
1946 i-cache-sets = <512>;
1947 d-cache-size = <0x100
1948 d-cache-line-size = <
1949 d-cache-sets = <256>;
1950 next-level-cache = <&
1951 reg = <0x000>;
1952 };
1953
1954 denver_1: cpu@1 {
1955 compatible = "nvidia,
1956 device_type = "cpu";
1957 i-cache-size = <0x200
1958 i-cache-line-size = <
1959 i-cache-sets = <512>;
1960 d-cache-size = <0x100
1961 d-cache-line-size = <
1962 d-cache-sets = <256>;
1963 next-level-cache = <&
1964 reg = <0x001>;
1965 };
1966
1967 ca57_0: cpu@2 {
1968 compatible = "arm,cor
1969 device_type = "cpu";
1970 i-cache-size = <0xC00
1971 i-cache-line-size = <
1972 i-cache-sets = <256>;
1973 d-cache-size = <0x800
1974 d-cache-line-size = <
1975 d-cache-sets = <256>;
1976 next-level-cache = <&
1977 reg = <0x100>;
1978 };
1979
1980 ca57_1: cpu@3 {
1981 compatible = "arm,cor
1982 device_type = "cpu";
1983 i-cache-size = <0xC00
1984 i-cache-line-size = <
1985 i-cache-sets = <256>;
1986 d-cache-size = <0x800
1987 d-cache-line-size = <
1988 d-cache-sets = <256>;
1989 next-level-cache = <&
1990 reg = <0x101>;
1991 };
1992
1993 ca57_2: cpu@4 {
1994 compatible = "arm,cor
1995 device_type = "cpu";
1996 i-cache-size = <0xC00
1997 i-cache-line-size = <
1998 i-cache-sets = <256>;
1999 d-cache-size = <0x800
2000 d-cache-line-size = <
2001 d-cache-sets = <256>;
2002 next-level-cache = <&
2003 reg = <0x102>;
2004 };
2005
2006 ca57_3: cpu@5 {
2007 compatible = "arm,cor
2008 device_type = "cpu";
2009 i-cache-size = <0xC00
2010 i-cache-line-size = <
2011 i-cache-sets = <256>;
2012 d-cache-size = <0x800
2013 d-cache-line-size = <
2014 d-cache-sets = <256>;
2015 next-level-cache = <&
2016 reg = <0x103>;
2017 };
2018
2019 L2_DENVER: l2-cache0 {
2020 compatible = "cache";
2021 cache-unified;
2022 cache-level = <2>;
2023 cache-size = <0x20000
2024 cache-line-size = <64
2025 cache-sets = <2048>;
2026 };
2027
2028 L2_A57: l2-cache1 {
2029 compatible = "cache";
2030 cache-unified;
2031 cache-level = <2>;
2032 cache-size = <0x20000
2033 cache-line-size = <64
2034 cache-sets = <2048>;
2035 };
2036 };
2037
2038 pmu-a57 {
2039 compatible = "arm,cortex-a57-
2040 interrupts = <GIC_SPI 296 IRQ
2041 <GIC_SPI 297 IRQ
2042 <GIC_SPI 298 IRQ
2043 <GIC_SPI 299 IRQ
2044 interrupt-affinity = <&ca57_0
2045 };
2046
2047 pmu-denver {
2048 compatible = "nvidia,denver-p
2049 interrupts = <GIC_SPI 320 IRQ
2050 <GIC_SPI 321 IRQ
2051 interrupt-affinity = <&denver
2052 };
2053
2054 sound {
2055 status = "disabled";
2056
2057 clocks = <&bpmp TEGRA186_CLK_
2058 <&bpmp TEGRA186_CLK_
2059 clock-names = "pll_a", "plla_
2060 assigned-clocks = <&bpmp TEGR
2061 <&bpmp TEGR
2062 <&bpmp TEGR
2063 assigned-clock-parents = <0>,
2064 <&bp
2065 <&bp
2066 /*
2067 * PLLA supports dynamic ramp
2068 * for this to work and oscil
2069 * for 8x and 11.025x sample
2070 */
2071 assigned-clock-rates = <25800
2072
2073 iommus = <&smmu TEGRA186_SID_
2074 };
2075
2076 thermal-zones {
2077 /* Cortex-A57 cluster */
2078 cpu-thermal {
2079 polling-delay = <0>;
2080 polling-delay-passive
2081
2082 thermal-sensors = <&b
2083
2084 trips {
2085 critical {
2086 tempe
2087 hyste
2088 type
2089 };
2090 };
2091
2092 cooling-maps {
2093 };
2094 };
2095
2096 /* Denver cluster */
2097 aux-thermal {
2098 polling-delay = <0>;
2099 polling-delay-passive
2100
2101 thermal-sensors = <&b
2102
2103 trips {
2104 critical {
2105 tempe
2106 hyste
2107 type
2108 };
2109 };
2110
2111 cooling-maps {
2112 };
2113 };
2114
2115 gpu-thermal {
2116 polling-delay = <0>;
2117 polling-delay-passive
2118
2119 thermal-sensors = <&b
2120
2121 trips {
2122 critical {
2123 tempe
2124 hyste
2125 type
2126 };
2127 };
2128
2129 cooling-maps {
2130 };
2131 };
2132
2133 pll-thermal {
2134 polling-delay = <0>;
2135 polling-delay-passive
2136
2137 thermal-sensors = <&b
2138
2139 trips {
2140 critical {
2141 tempe
2142 hyste
2143 type
2144 };
2145 };
2146
2147 cooling-maps {
2148 };
2149 };
2150
2151 ao-thermal {
2152 polling-delay = <0>;
2153 polling-delay-passive
2154
2155 thermal-sensors = <&b
2156
2157 trips {
2158 critical {
2159 tempe
2160 hyste
2161 type
2162 };
2163 };
2164
2165 cooling-maps {
2166 };
2167 };
2168 };
2169
2170 timer {
2171 compatible = "arm,armv8-timer
2172 interrupts = <GIC_PPI 13
2173 (GIC_CPU_MASK
2174 <GIC_PPI 14
2175 (GIC_CPU_MASK
2176 <GIC_PPI 11
2177 (GIC_CPU_MASK
2178 <GIC_PPI 10
2179 (GIC_CPU_MASK
2180 interrupt-parent = <&gic>;
2181 always-on;
2182 };
2183 };
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