1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h> 2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h> 3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h> 6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io 7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate 8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h> 9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-th 10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11 11
12 / { 12 / {
13 compatible = "nvidia,tegra186"; 13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 misc@100000 { 18 misc@100000 {
19 compatible = "nvidia,tegra186- 19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf0 20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x10 21 <0x0 0x0010f000 0x0 0x1000>;
22 }; 22 };
23 23
24 gpio: gpio@2200000 { 24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186- 25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio" 26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x100 27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x100 28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_ 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_ 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_ 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_ 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_ 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_ 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>; 35 #interrupt-cells = <2>;
36 interrupt-controller; 36 interrupt-controller;
37 #gpio-cells = <2>; 37 #gpio-cells = <2>;
38 gpio-controller; 38 gpio-controller;
39 }; 39 };
40 40
41 ethernet@2490000 { 41 ethernet@2490000 {
42 compatible = "nvidia,tegra186- 42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-eth 43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10 44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_ 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_A 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_E 56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_E 57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_E 58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_E 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "s 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET 61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos"; 62 reset-names = "eqos";
63 interconnects = <&mc TEGRA186_ 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64 <&mc TEGRA186_ 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65 interconnect-names = "dma-mem" 65 interconnect-names = "dma-mem", "write";
66 iommus = <&smmu TEGRA186_SID_E 66 iommus = <&smmu TEGRA186_SID_EQOS>;
67 status = "disabled"; 67 status = "disabled";
68 68
69 snps,write-requests = <1>; 69 snps,write-requests = <1>;
70 snps,read-requests = <3>; 70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>; 71 snps,burst-map = <0x7>;
72 snps,txpbl = <32>; 72 snps,txpbl = <32>;
73 snps,rxpbl = <8>; 73 snps,rxpbl = <8>;
74 }; 74 };
75 75
76 gpcdma: dma-controller@2600000 { <<
77 compatible = "nvidia,tegra186- <<
78 reg = <0x0 0x2600000 0x0 0x210 <<
79 resets = <&bpmp TEGRA186_RESET <<
80 reset-names = "gpcdma"; <<
81 interrupts = <GIC_SPI 75 IRQ_T <<
82 <GIC_SPI 76 IRQ_T <<
83 <GIC_SPI 77 IRQ_T <<
84 <GIC_SPI 78 IRQ_T <<
85 <GIC_SPI 79 IRQ_T <<
86 <GIC_SPI 80 IRQ_T <<
87 <GIC_SPI 81 IRQ_T <<
88 <GIC_SPI 82 IRQ_T <<
89 <GIC_SPI 83 IRQ_T <<
90 <GIC_SPI 84 IRQ_T <<
91 <GIC_SPI 85 IRQ_T <<
92 <GIC_SPI 86 IRQ_T <<
93 <GIC_SPI 87 IRQ_T <<
94 <GIC_SPI 88 IRQ_T <<
95 <GIC_SPI 89 IRQ_T <<
96 <GIC_SPI 90 IRQ_T <<
97 <GIC_SPI 91 IRQ_T <<
98 <GIC_SPI 92 IRQ_T <<
99 <GIC_SPI 93 IRQ_T <<
100 <GIC_SPI 94 IRQ_T <<
101 <GIC_SPI 95 IRQ_T <<
102 <GIC_SPI 96 IRQ_T <<
103 <GIC_SPI 97 IRQ_T <<
104 <GIC_SPI 98 IRQ_T <<
105 <GIC_SPI 99 IRQ_T <<
106 <GIC_SPI 100 IRQ_ <<
107 <GIC_SPI 101 IRQ_ <<
108 <GIC_SPI 102 IRQ_ <<
109 <GIC_SPI 103 IRQ_ <<
110 <GIC_SPI 104 IRQ_ <<
111 <GIC_SPI 105 IRQ_ <<
112 <GIC_SPI 106 IRQ_ <<
113 #dma-cells = <1>; <<
114 iommus = <&smmu TEGRA186_SID_G <<
115 dma-coherent; <<
116 dma-channel-mask = <0xfffffffe <<
117 status = "okay"; <<
118 }; <<
119 <<
120 aconnect@2900000 { 76 aconnect@2900000 {
121 compatible = "nvidia,tegra186- 77 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210- 78 "nvidia,tegra210-aconnect";
123 clocks = <&bpmp TEGRA186_CLK_A 79 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_A 80 <&bpmp TEGRA186_CLK_APB2APE>;
125 clock-names = "ape", "apb2ape" 81 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA18 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>; 83 #address-cells = <1>;
128 #size-cells = <1>; 84 #size-cells = <1>;
129 ranges = <0x02900000 0x0 0x029 85 ranges = <0x02900000 0x0 0x02900000 0x200000>;
130 status = "disabled"; 86 status = "disabled";
131 87
>> 88 adma: dma-controller@2930000 {
>> 89 compatible = "nvidia,tegra186-adma";
>> 90 reg = <0x02930000 0x20000>;
>> 91 interrupt-parent = <&agic>;
>> 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 124 #dma-cells = <1>;
>> 125 clocks = <&bpmp TEGRA186_CLK_AHUB>;
>> 126 clock-names = "d_audio";
>> 127 status = "disabled";
>> 128 };
>> 129
>> 130 agic: interrupt-controller@2a40000 {
>> 131 compatible = "nvidia,tegra186-agic",
>> 132 "nvidia,tegra210-agic";
>> 133 #interrupt-cells = <3>;
>> 134 interrupt-controller;
>> 135 reg = <0x02a41000 0x1000>,
>> 136 <0x02a42000 0x2000>;
>> 137 interrupts = <GIC_SPI 145
>> 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> 139 clocks = <&bpmp TEGRA186_CLK_APE>;
>> 140 clock-names = "clk";
>> 141 status = "disabled";
>> 142 };
>> 143
132 tegra_ahub: ahub@2900800 { 144 tegra_ahub: ahub@2900800 {
133 compatible = "nvidia,t 145 compatible = "nvidia,tegra186-ahub";
134 reg = <0x02900800 0x80 146 reg = <0x02900800 0x800>;
135 clocks = <&bpmp TEGRA1 147 clocks = <&bpmp TEGRA186_CLK_AHUB>;
136 clock-names = "ahub"; 148 clock-names = "ahub";
137 assigned-clocks = <&bp 149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents !! 150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
139 assigned-clock-rates = <<
140 #address-cells = <1>; 151 #address-cells = <1>;
141 #size-cells = <1>; 152 #size-cells = <1>;
142 ranges = <0x02900800 0 153 ranges = <0x02900800 0x02900800 0x11800>;
143 status = "disabled"; 154 status = "disabled";
144 155
>> 156 tegra_admaif: admaif@290f000 {
>> 157 compatible = "nvidia,tegra186-admaif";
>> 158 reg = <0x0290f000 0x1000>;
>> 159 dmas = <&adma 1>, <&adma 1>,
>> 160 <&adma 2>, <&adma 2>,
>> 161 <&adma 3>, <&adma 3>,
>> 162 <&adma 4>, <&adma 4>,
>> 163 <&adma 5>, <&adma 5>,
>> 164 <&adma 6>, <&adma 6>,
>> 165 <&adma 7>, <&adma 7>,
>> 166 <&adma 8>, <&adma 8>,
>> 167 <&adma 9>, <&adma 9>,
>> 168 <&adma 10>, <&adma 10>,
>> 169 <&adma 11>, <&adma 11>,
>> 170 <&adma 12>, <&adma 12>,
>> 171 <&adma 13>, <&adma 13>,
>> 172 <&adma 14>, <&adma 14>,
>> 173 <&adma 15>, <&adma 15>,
>> 174 <&adma 16>, <&adma 16>,
>> 175 <&adma 17>, <&adma 17>,
>> 176 <&adma 18>, <&adma 18>,
>> 177 <&adma 19>, <&adma 19>,
>> 178 <&adma 20>, <&adma 20>;
>> 179 dma-names = "rx1", "tx1",
>> 180 "rx2", "tx2",
>> 181 "rx3", "tx3",
>> 182 "rx4", "tx4",
>> 183 "rx5", "tx5",
>> 184 "rx6", "tx6",
>> 185 "rx7", "tx7",
>> 186 "rx8", "tx8",
>> 187 "rx9", "tx9",
>> 188 "rx10", "tx10",
>> 189 "rx11", "tx11",
>> 190 "rx12", "tx12",
>> 191 "rx13", "tx13",
>> 192 "rx14", "tx14",
>> 193 "rx15", "tx15",
>> 194 "rx16", "tx16",
>> 195 "rx17", "tx17",
>> 196 "rx18", "tx18",
>> 197 "rx19", "tx19",
>> 198 "rx20", "tx20";
>> 199 status = "disabled";
>> 200 };
>> 201
145 tegra_i2s1: i2s@290100 202 tegra_i2s1: i2s@2901000 {
146 compatible = " 203 compatible = "nvidia,tegra186-i2s",
147 " 204 "nvidia,tegra210-i2s";
148 reg = <0x29010 205 reg = <0x2901000 0x100>;
149 clocks = <&bpm 206 clocks = <&bpmp TEGRA186_CLK_I2S1>,
150 <&bpm 207 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
151 clock-names = 208 clock-names = "i2s", "sync_input";
152 assigned-clock 209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock 210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock 211 assigned-clock-rates = <1536000>;
155 sound-name-pre 212 sound-name-prefix = "I2S1";
156 status = "disa 213 status = "disabled";
157 }; 214 };
158 215
159 tegra_i2s2: i2s@290110 216 tegra_i2s2: i2s@2901100 {
160 compatible = " 217 compatible = "nvidia,tegra186-i2s",
161 " 218 "nvidia,tegra210-i2s";
162 reg = <0x29011 219 reg = <0x2901100 0x100>;
163 clocks = <&bpm 220 clocks = <&bpmp TEGRA186_CLK_I2S2>,
164 <&bpm 221 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
165 clock-names = 222 clock-names = "i2s", "sync_input";
166 assigned-clock 223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock 224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock 225 assigned-clock-rates = <1536000>;
169 sound-name-pre 226 sound-name-prefix = "I2S2";
170 status = "disa 227 status = "disabled";
171 }; 228 };
172 229
173 tegra_i2s3: i2s@290120 230 tegra_i2s3: i2s@2901200 {
174 compatible = " 231 compatible = "nvidia,tegra186-i2s",
175 " 232 "nvidia,tegra210-i2s";
176 reg = <0x29012 233 reg = <0x2901200 0x100>;
177 clocks = <&bpm 234 clocks = <&bpmp TEGRA186_CLK_I2S3>,
178 <&bpm 235 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
179 clock-names = 236 clock-names = "i2s", "sync_input";
180 assigned-clock 237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock 238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock 239 assigned-clock-rates = <1536000>;
183 sound-name-pre 240 sound-name-prefix = "I2S3";
184 status = "disa 241 status = "disabled";
185 }; 242 };
186 243
187 tegra_i2s4: i2s@290130 244 tegra_i2s4: i2s@2901300 {
188 compatible = " 245 compatible = "nvidia,tegra186-i2s",
189 " 246 "nvidia,tegra210-i2s";
190 reg = <0x29013 247 reg = <0x2901300 0x100>;
191 clocks = <&bpm 248 clocks = <&bpmp TEGRA186_CLK_I2S4>,
192 <&bpm 249 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
193 clock-names = 250 clock-names = "i2s", "sync_input";
194 assigned-clock 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock 253 assigned-clock-rates = <1536000>;
197 sound-name-pre 254 sound-name-prefix = "I2S4";
198 status = "disa 255 status = "disabled";
199 }; 256 };
200 257
201 tegra_i2s5: i2s@290140 258 tegra_i2s5: i2s@2901400 {
202 compatible = " 259 compatible = "nvidia,tegra186-i2s",
203 " 260 "nvidia,tegra210-i2s";
204 reg = <0x29014 261 reg = <0x2901400 0x100>;
205 clocks = <&bpm 262 clocks = <&bpmp TEGRA186_CLK_I2S5>,
206 <&bpm 263 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
207 clock-names = 264 clock-names = "i2s", "sync_input";
208 assigned-clock 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock 267 assigned-clock-rates = <1536000>;
211 sound-name-pre 268 sound-name-prefix = "I2S5";
212 status = "disa 269 status = "disabled";
213 }; 270 };
214 271
215 tegra_i2s6: i2s@290150 272 tegra_i2s6: i2s@2901500 {
216 compatible = " 273 compatible = "nvidia,tegra186-i2s",
217 " 274 "nvidia,tegra210-i2s";
218 reg = <0x29015 275 reg = <0x2901500 0x100>;
219 clocks = <&bpm 276 clocks = <&bpmp TEGRA186_CLK_I2S6>,
220 <&bpm 277 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
221 clock-names = 278 clock-names = "i2s", "sync_input";
222 assigned-clock 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock 281 assigned-clock-rates = <1536000>;
225 sound-name-pre 282 sound-name-prefix = "I2S6";
226 status = "disa 283 status = "disabled";
227 }; 284 };
228 285
229 tegra_sfc1: sfc@290200 <<
230 compatible = " <<
231 " <<
232 reg = <0x29020 <<
233 sound-name-pre <<
234 status = "disa <<
235 }; <<
236 <<
237 tegra_sfc2: sfc@290220 <<
238 compatible = " <<
239 " <<
240 reg = <0x29022 <<
241 sound-name-pre <<
242 status = "disa <<
243 }; <<
244 <<
245 tegra_sfc3: sfc@290240 <<
246 compatible = " <<
247 " <<
248 reg = <0x29024 <<
249 sound-name-pre <<
250 status = "disa <<
251 }; <<
252 <<
253 tegra_sfc4: sfc@290260 <<
254 compatible = " <<
255 " <<
256 reg = <0x29026 <<
257 sound-name-pre <<
258 status = "disa <<
259 }; <<
260 <<
261 tegra_amx1: amx@290300 <<
262 compatible = " <<
263 " <<
264 reg = <0x29030 <<
265 sound-name-pre <<
266 status = "disa <<
267 }; <<
268 <<
269 tegra_amx2: amx@290310 <<
270 compatible = " <<
271 " <<
272 reg = <0x29031 <<
273 sound-name-pre <<
274 status = "disa <<
275 }; <<
276 <<
277 tegra_amx3: amx@290320 <<
278 compatible = " <<
279 " <<
280 reg = <0x29032 <<
281 sound-name-pre <<
282 status = "disa <<
283 }; <<
284 <<
285 tegra_amx4: amx@290330 <<
286 compatible = " <<
287 " <<
288 reg = <0x29033 <<
289 sound-name-pre <<
290 status = "disa <<
291 }; <<
292 <<
293 tegra_adx1: adx@290380 <<
294 compatible = " <<
295 " <<
296 reg = <0x29038 <<
297 sound-name-pre <<
298 status = "disa <<
299 }; <<
300 <<
301 tegra_adx2: adx@290390 <<
302 compatible = " <<
303 " <<
304 reg = <0x29039 <<
305 sound-name-pre <<
306 status = "disa <<
307 }; <<
308 <<
309 tegra_adx3: adx@2903a0 <<
310 compatible = " <<
311 " <<
312 reg = <0x2903a <<
313 sound-name-pre <<
314 status = "disa <<
315 }; <<
316 <<
317 tegra_adx4: adx@2903b0 <<
318 compatible = " <<
319 " <<
320 reg = <0x2903b <<
321 sound-name-pre <<
322 status = "disa <<
323 }; <<
324 <<
325 tegra_dmic1: dmic@2904 286 tegra_dmic1: dmic@2904000 {
326 compatible = " 287 compatible = "nvidia,tegra210-dmic";
327 reg = <0x29040 288 reg = <0x2904000 0x100>;
328 clocks = <&bpm 289 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
329 clock-names = 290 clock-names = "dmic";
330 assigned-clock 291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock 292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock 293 assigned-clock-rates = <3072000>;
333 sound-name-pre 294 sound-name-prefix = "DMIC1";
334 status = "disa 295 status = "disabled";
335 }; 296 };
336 297
337 tegra_dmic2: dmic@2904 298 tegra_dmic2: dmic@2904100 {
338 compatible = " 299 compatible = "nvidia,tegra210-dmic";
339 reg = <0x29041 300 reg = <0x2904100 0x100>;
340 clocks = <&bpm 301 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
341 clock-names = 302 clock-names = "dmic";
342 assigned-clock 303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock 304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock 305 assigned-clock-rates = <3072000>;
345 sound-name-pre 306 sound-name-prefix = "DMIC2";
346 status = "disa 307 status = "disabled";
347 }; 308 };
348 309
349 tegra_dmic3: dmic@2904 310 tegra_dmic3: dmic@2904200 {
350 compatible = " 311 compatible = "nvidia,tegra210-dmic";
351 reg = <0x29042 312 reg = <0x2904200 0x100>;
352 clocks = <&bpm 313 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
353 clock-names = 314 clock-names = "dmic";
354 assigned-clock 315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock 316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock 317 assigned-clock-rates = <3072000>;
357 sound-name-pre 318 sound-name-prefix = "DMIC3";
358 status = "disa 319 status = "disabled";
359 }; 320 };
360 321
361 tegra_dmic4: dmic@2904 322 tegra_dmic4: dmic@2904300 {
362 compatible = " 323 compatible = "nvidia,tegra210-dmic";
363 reg = <0x29043 324 reg = <0x2904300 0x100>;
364 clocks = <&bpm 325 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
365 clock-names = 326 clock-names = "dmic";
366 assigned-clock 327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock 328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock 329 assigned-clock-rates = <3072000>;
369 sound-name-pre 330 sound-name-prefix = "DMIC4";
370 status = "disa 331 status = "disabled";
371 }; 332 };
372 333
373 tegra_dspk1: dspk@2905 334 tegra_dspk1: dspk@2905000 {
374 compatible = " 335 compatible = "nvidia,tegra186-dspk";
375 reg = <0x29050 336 reg = <0x2905000 0x100>;
376 clocks = <&bpm 337 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
377 clock-names = 338 clock-names = "dspk";
378 assigned-clock 339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock 340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock 341 assigned-clock-rates = <12288000>;
381 sound-name-pre 342 sound-name-prefix = "DSPK1";
382 status = "disa 343 status = "disabled";
383 }; 344 };
384 345
385 tegra_dspk2: dspk@2905 346 tegra_dspk2: dspk@2905100 {
386 compatible = " 347 compatible = "nvidia,tegra186-dspk";
387 reg = <0x29051 348 reg = <0x2905100 0x100>;
388 clocks = <&bpm 349 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
389 clock-names = 350 clock-names = "dspk";
390 assigned-clock 351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock 353 assigned-clock-rates = <12288000>;
393 sound-name-pre 354 sound-name-prefix = "DSPK2";
394 status = "disa 355 status = "disabled";
395 }; 356 };
396 <<
397 tegra_ope1: processing <<
398 compatible = " <<
399 " <<
400 reg = <0x29080 <<
401 #address-cells <<
402 #size-cells = <<
403 ranges; <<
404 sound-name-pre <<
405 status = "disa <<
406 <<
407 equalizer@2908 <<
408 compat <<
409 <<
410 reg = <<
411 }; <<
412 <<
413 dynamic-range- <<
414 compat <<
415 <<
416 reg = <<
417 }; <<
418 }; <<
419 <<
420 tegra_mvc1: mvc@290a00 <<
421 compatible = " <<
422 " <<
423 reg = <0x290a0 <<
424 sound-name-pre <<
425 status = "disa <<
426 }; <<
427 <<
428 tegra_mvc2: mvc@290a20 <<
429 compatible = " <<
430 " <<
431 reg = <0x290a2 <<
432 sound-name-pre <<
433 status = "disa <<
434 }; <<
435 <<
436 tegra_amixer: amixer@2 <<
437 compatible = " <<
438 " <<
439 reg = <0x290bb <<
440 sound-name-pre <<
441 status = "disa <<
442 }; <<
443 <<
444 tegra_admaif: admaif@2 <<
445 compatible = " <<
446 reg = <0x0290f <<
447 dmas = <&adma <<
448 <&adma <<
449 <&adma <<
450 <&adma <<
451 <&adma <<
452 <&adma <<
453 <&adma <<
454 <&adma <<
455 <&adma <<
456 <&adma <<
457 <&adma <<
458 <&adma <<
459 <&adma <<
460 <&adma <<
461 <&adma <<
462 <&adma <<
463 <&adma <<
464 <&adma <<
465 <&adma <<
466 <&adma <<
467 dma-names = "r <<
468 "r <<
469 "r <<
470 "r <<
471 "r <<
472 "r <<
473 "r <<
474 "r <<
475 "r <<
476 "r <<
477 "r <<
478 "r <<
479 "r <<
480 "r <<
481 "r <<
482 "r <<
483 "r <<
484 "r <<
485 "r <<
486 "r <<
487 status = "disa <<
488 }; <<
489 <<
490 tegra_asrc: asrc@29100 <<
491 compatible = " <<
492 reg = <0x29100 <<
493 sound-name-pre <<
494 status = "disa <<
495 }; <<
496 }; <<
497 <<
498 adma: dma-controller@2930000 { <<
499 compatible = "nvidia,t <<
500 reg = <0x02930000 0x20 <<
501 interrupt-parent = <&a <<
502 interrupts = <GIC_SPI <<
503 <GIC_SPI <<
504 <GIC_SPI <<
505 <GIC_SPI <<
506 <GIC_SPI <<
507 <GIC_SPI <<
508 <GIC_SPI <<
509 <GIC_SPI <<
510 <GIC_SPI <<
511 <GIC_SPI <<
512 <GIC_SPI <<
513 <GIC_SPI <<
514 <GIC_SPI <<
515 <GIC_SPI <<
516 <GIC_SPI <<
517 <GIC_SPI <<
518 <GIC_SPI <<
519 <GIC_SPI <<
520 <GIC_SPI <<
521 <GIC_SPI <<
522 <GIC_SPI <<
523 <GIC_SPI <<
524 <GIC_SPI <<
525 <GIC_SPI <<
526 <GIC_SPI <<
527 <GIC_SPI <<
528 <GIC_SPI <<
529 <GIC_SPI <<
530 <GIC_SPI <<
531 <GIC_SPI <<
532 <GIC_SPI <<
533 <GIC_SPI <<
534 #dma-cells = <1>; <<
535 clocks = <&bpmp TEGRA1 <<
536 clock-names = "d_audio <<
537 status = "disabled"; <<
538 }; <<
539 <<
540 agic: interrupt-controller@2a4 <<
541 compatible = "nvidia,t <<
542 "nvidia,t <<
543 #interrupt-cells = <3> <<
544 interrupt-controller; <<
545 reg = <0x02a41000 0x10 <<
546 <0x02a42000 0x20 <<
547 interrupts = <GIC_SPI <<
548 (GIC_CPU_MASK_ <<
549 clocks = <&bpmp TEGRA1 <<
550 clock-names = "clk"; <<
551 status = "disabled"; <<
552 }; 357 };
553 }; 358 };
554 359
555 mc: memory-controller@2c00000 { 360 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186- 361 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10 !! 362 reg = <0x0 0x02c00000 0x0 0xb0000>;
558 <0x0 0x02c10000 0x0 0x10 <<
559 <0x0 0x02c20000 0x0 0x10 <<
560 <0x0 0x02c30000 0x0 0x10 <<
561 <0x0 0x02c40000 0x0 0x10 <<
562 <0x0 0x02c50000 0x0 0x10 <<
563 reg-names = "sid", "broadcast" <<
564 interrupts = <GIC_SPI 223 IRQ_ 363 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
565 status = "disabled"; 364 status = "disabled";
566 365
567 #interconnect-cells = <1>; 366 #interconnect-cells = <1>;
568 #address-cells = <2>; 367 #address-cells = <2>;
569 #size-cells = <2>; 368 #size-cells = <2>;
570 369
571 ranges = <0x0 0x02c00000 0x0 0 370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
572 371
573 /* 372 /*
574 * Memory clients have access 373 * Memory clients have access to all 40 bits that the memory
575 * controller can address. 374 * controller can address.
576 */ 375 */
577 dma-ranges = <0x0 0x0 0x0 0x0 376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
578 377
579 emc: external-memory-controlle 378 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,t 379 compatible = "nvidia,tegra186-emc";
581 reg = <0x0 0x02c60000 380 reg = <0x0 0x02c60000 0x0 0x50000>;
582 interrupts = <GIC_SPI 381 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&bpmp TEGRA1 382 clocks = <&bpmp TEGRA186_CLK_EMC>;
584 clock-names = "emc"; 383 clock-names = "emc";
585 384
586 #interconnect-cells = 385 #interconnect-cells = <0>;
587 386
588 nvidia,bpmp = <&bpmp>; 387 nvidia,bpmp = <&bpmp>;
589 }; 388 };
590 }; 389 };
591 390
592 timer@3010000 { <<
593 compatible = "nvidia,tegra186- <<
594 reg = <0x0 0x03010000 0x0 0x00 <<
595 interrupts = <GIC_SPI 0 IRQ_TY <<
596 <GIC_SPI 1 IRQ_TY <<
597 <GIC_SPI 2 IRQ_TY <<
598 <GIC_SPI 3 IRQ_TY <<
599 <GIC_SPI 4 IRQ_TY <<
600 <GIC_SPI 5 IRQ_TY <<
601 <GIC_SPI 6 IRQ_TY <<
602 <GIC_SPI 7 IRQ_TY <<
603 <GIC_SPI 8 IRQ_TY <<
604 <GIC_SPI 9 IRQ_TY <<
605 status = "okay"; <<
606 }; <<
607 <<
608 uarta: serial@3100000 { 391 uarta: serial@3100000 {
609 compatible = "nvidia,tegra186- 392 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
610 reg = <0x0 0x03100000 0x0 0x40 393 reg = <0x0 0x03100000 0x0 0x40>;
611 reg-shift = <2>; 394 reg-shift = <2>;
612 interrupts = <GIC_SPI 112 IRQ_ 395 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&bpmp TEGRA186_CLK_U 396 clocks = <&bpmp TEGRA186_CLK_UARTA>;
>> 397 clock-names = "serial";
614 resets = <&bpmp TEGRA186_RESET 398 resets = <&bpmp TEGRA186_RESET_UARTA>;
>> 399 reset-names = "serial";
615 status = "disabled"; 400 status = "disabled";
616 }; 401 };
617 402
618 uartb: serial@3110000 { 403 uartb: serial@3110000 {
619 compatible = "nvidia,tegra186- 404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620 reg = <0x0 0x03110000 0x0 0x40 405 reg = <0x0 0x03110000 0x0 0x40>;
621 reg-shift = <2>; 406 reg-shift = <2>;
622 interrupts = <GIC_SPI 113 IRQ_ 407 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&bpmp TEGRA186_CLK_U 408 clocks = <&bpmp TEGRA186_CLK_UARTB>;
624 clock-names = "serial"; 409 clock-names = "serial";
625 resets = <&bpmp TEGRA186_RESET 410 resets = <&bpmp TEGRA186_RESET_UARTB>;
626 reset-names = "serial"; 411 reset-names = "serial";
627 status = "disabled"; 412 status = "disabled";
628 }; 413 };
629 414
630 uartd: serial@3130000 { 415 uartd: serial@3130000 {
631 compatible = "nvidia,tegra186- 416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632 reg = <0x0 0x03130000 0x0 0x40 417 reg = <0x0 0x03130000 0x0 0x40>;
633 reg-shift = <2>; 418 reg-shift = <2>;
634 interrupts = <GIC_SPI 115 IRQ_ 419 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&bpmp TEGRA186_CLK_U 420 clocks = <&bpmp TEGRA186_CLK_UARTD>;
636 clock-names = "serial"; 421 clock-names = "serial";
637 resets = <&bpmp TEGRA186_RESET 422 resets = <&bpmp TEGRA186_RESET_UARTD>;
638 reset-names = "serial"; 423 reset-names = "serial";
639 status = "disabled"; 424 status = "disabled";
640 }; 425 };
641 426
642 uarte: serial@3140000 { 427 uarte: serial@3140000 {
643 compatible = "nvidia,tegra186- 428 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
644 reg = <0x0 0x03140000 0x0 0x40 429 reg = <0x0 0x03140000 0x0 0x40>;
645 reg-shift = <2>; 430 reg-shift = <2>;
646 interrupts = <GIC_SPI 116 IRQ_ 431 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&bpmp TEGRA186_CLK_U 432 clocks = <&bpmp TEGRA186_CLK_UARTE>;
648 clock-names = "serial"; 433 clock-names = "serial";
649 resets = <&bpmp TEGRA186_RESET 434 resets = <&bpmp TEGRA186_RESET_UARTE>;
650 reset-names = "serial"; 435 reset-names = "serial";
651 status = "disabled"; 436 status = "disabled";
652 }; 437 };
653 438
654 uartf: serial@3150000 { 439 uartf: serial@3150000 {
655 compatible = "nvidia,tegra186- 440 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
656 reg = <0x0 0x03150000 0x0 0x40 441 reg = <0x0 0x03150000 0x0 0x40>;
657 reg-shift = <2>; 442 reg-shift = <2>;
658 interrupts = <GIC_SPI 117 IRQ_ 443 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&bpmp TEGRA186_CLK_U 444 clocks = <&bpmp TEGRA186_CLK_UARTF>;
660 clock-names = "serial"; 445 clock-names = "serial";
661 resets = <&bpmp TEGRA186_RESET 446 resets = <&bpmp TEGRA186_RESET_UARTF>;
662 reset-names = "serial"; 447 reset-names = "serial";
663 status = "disabled"; 448 status = "disabled";
664 }; 449 };
665 450
666 gen1_i2c: i2c@3160000 { 451 gen1_i2c: i2c@3160000 {
667 compatible = "nvidia,tegra186- !! 452 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
668 reg = <0x0 0x03160000 0x0 0x10 453 reg = <0x0 0x03160000 0x0 0x10000>;
669 interrupts = <GIC_SPI 25 IRQ_T 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>; 455 #address-cells = <1>;
671 #size-cells = <0>; 456 #size-cells = <0>;
672 clocks = <&bpmp TEGRA186_CLK_I 457 clocks = <&bpmp TEGRA186_CLK_I2C1>;
673 clock-names = "div-clk"; 458 clock-names = "div-clk";
674 resets = <&bpmp TEGRA186_RESET 459 resets = <&bpmp TEGRA186_RESET_I2C1>;
675 reset-names = "i2c"; 460 reset-names = "i2c";
676 dmas = <&gpcdma 21>, <&gpcdma <<
677 dma-names = "rx", "tx"; <<
678 status = "disabled"; 461 status = "disabled";
679 }; 462 };
680 463
681 cam_i2c: i2c@3180000 { 464 cam_i2c: i2c@3180000 {
682 compatible = "nvidia,tegra186- !! 465 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
683 reg = <0x0 0x03180000 0x0 0x10 466 reg = <0x0 0x03180000 0x0 0x10000>;
684 interrupts = <GIC_SPI 27 IRQ_T 467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>; 468 #address-cells = <1>;
686 #size-cells = <0>; 469 #size-cells = <0>;
687 clocks = <&bpmp TEGRA186_CLK_I 470 clocks = <&bpmp TEGRA186_CLK_I2C3>;
688 clock-names = "div-clk"; 471 clock-names = "div-clk";
689 resets = <&bpmp TEGRA186_RESET 472 resets = <&bpmp TEGRA186_RESET_I2C3>;
690 reset-names = "i2c"; 473 reset-names = "i2c";
691 dmas = <&gpcdma 23>, <&gpcdma <<
692 dma-names = "rx", "tx"; <<
693 status = "disabled"; 474 status = "disabled";
694 }; 475 };
695 476
696 /* shares pads with dpaux1 */ 477 /* shares pads with dpaux1 */
697 dp_aux_ch1_i2c: i2c@3190000 { 478 dp_aux_ch1_i2c: i2c@3190000 {
698 compatible = "nvidia,tegra186- !! 479 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
699 reg = <0x0 0x03190000 0x0 0x10 480 reg = <0x0 0x03190000 0x0 0x10000>;
700 interrupts = <GIC_SPI 28 IRQ_T 481 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>; 482 #address-cells = <1>;
702 #size-cells = <0>; 483 #size-cells = <0>;
703 clocks = <&bpmp TEGRA186_CLK_I 484 clocks = <&bpmp TEGRA186_CLK_I2C4>;
704 clock-names = "div-clk"; 485 clock-names = "div-clk";
705 resets = <&bpmp TEGRA186_RESET 486 resets = <&bpmp TEGRA186_RESET_I2C4>;
706 reset-names = "i2c"; 487 reset-names = "i2c";
707 pinctrl-names = "default", "id 488 pinctrl-names = "default", "idle";
708 pinctrl-0 = <&state_dpaux1_i2c 489 pinctrl-0 = <&state_dpaux1_i2c>;
709 pinctrl-1 = <&state_dpaux1_off 490 pinctrl-1 = <&state_dpaux1_off>;
710 dmas = <&gpcdma 26>, <&gpcdma <<
711 dma-names = "rx", "tx"; <<
712 status = "disabled"; 491 status = "disabled";
713 }; 492 };
714 493
715 /* controlled by BPMP, should not be e 494 /* controlled by BPMP, should not be enabled */
716 pwr_i2c: i2c@31a0000 { 495 pwr_i2c: i2c@31a0000 {
717 compatible = "nvidia,tegra186- !! 496 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
718 reg = <0x0 0x031a0000 0x0 0x10 497 reg = <0x0 0x031a0000 0x0 0x10000>;
719 interrupts = <GIC_SPI 29 IRQ_T 498 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>; 499 #address-cells = <1>;
721 #size-cells = <0>; 500 #size-cells = <0>;
722 clocks = <&bpmp TEGRA186_CLK_I 501 clocks = <&bpmp TEGRA186_CLK_I2C5>;
723 clock-names = "div-clk"; 502 clock-names = "div-clk";
724 resets = <&bpmp TEGRA186_RESET 503 resets = <&bpmp TEGRA186_RESET_I2C5>;
725 reset-names = "i2c"; 504 reset-names = "i2c";
726 status = "disabled"; 505 status = "disabled";
727 }; 506 };
728 507
729 /* shares pads with dpaux0 */ 508 /* shares pads with dpaux0 */
730 dp_aux_ch0_i2c: i2c@31b0000 { 509 dp_aux_ch0_i2c: i2c@31b0000 {
731 compatible = "nvidia,tegra186- !! 510 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
732 reg = <0x0 0x031b0000 0x0 0x10 511 reg = <0x0 0x031b0000 0x0 0x10000>;
733 interrupts = <GIC_SPI 30 IRQ_T 512 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
734 #address-cells = <1>; 513 #address-cells = <1>;
735 #size-cells = <0>; 514 #size-cells = <0>;
736 clocks = <&bpmp TEGRA186_CLK_I 515 clocks = <&bpmp TEGRA186_CLK_I2C6>;
737 clock-names = "div-clk"; 516 clock-names = "div-clk";
738 resets = <&bpmp TEGRA186_RESET 517 resets = <&bpmp TEGRA186_RESET_I2C6>;
739 reset-names = "i2c"; 518 reset-names = "i2c";
740 pinctrl-names = "default", "id 519 pinctrl-names = "default", "idle";
741 pinctrl-0 = <&state_dpaux_i2c> 520 pinctrl-0 = <&state_dpaux_i2c>;
742 pinctrl-1 = <&state_dpaux_off> 521 pinctrl-1 = <&state_dpaux_off>;
743 dmas = <&gpcdma 30>, <&gpcdma <<
744 dma-names = "rx", "tx"; <<
745 status = "disabled"; 522 status = "disabled";
746 }; 523 };
747 524
748 gen7_i2c: i2c@31c0000 { 525 gen7_i2c: i2c@31c0000 {
749 compatible = "nvidia,tegra186- !! 526 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
750 reg = <0x0 0x031c0000 0x0 0x10 527 reg = <0x0 0x031c0000 0x0 0x10000>;
751 interrupts = <GIC_SPI 31 IRQ_T 528 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
752 #address-cells = <1>; 529 #address-cells = <1>;
753 #size-cells = <0>; 530 #size-cells = <0>;
754 clocks = <&bpmp TEGRA186_CLK_I 531 clocks = <&bpmp TEGRA186_CLK_I2C7>;
755 clock-names = "div-clk"; 532 clock-names = "div-clk";
756 resets = <&bpmp TEGRA186_RESET 533 resets = <&bpmp TEGRA186_RESET_I2C7>;
757 reset-names = "i2c"; 534 reset-names = "i2c";
758 dmas = <&gpcdma 27>, <&gpcdma <<
759 dma-names = "rx", "tx"; <<
760 status = "disabled"; 535 status = "disabled";
761 }; 536 };
762 537
763 gen9_i2c: i2c@31e0000 { 538 gen9_i2c: i2c@31e0000 {
764 compatible = "nvidia,tegra186- !! 539 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
765 reg = <0x0 0x031e0000 0x0 0x10 540 reg = <0x0 0x031e0000 0x0 0x10000>;
766 interrupts = <GIC_SPI 33 IRQ_T 541 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>; 542 #address-cells = <1>;
768 #size-cells = <0>; 543 #size-cells = <0>;
769 clocks = <&bpmp TEGRA186_CLK_I 544 clocks = <&bpmp TEGRA186_CLK_I2C9>;
770 clock-names = "div-clk"; 545 clock-names = "div-clk";
771 resets = <&bpmp TEGRA186_RESET 546 resets = <&bpmp TEGRA186_RESET_I2C9>;
772 reset-names = "i2c"; 547 reset-names = "i2c";
773 dmas = <&gpcdma 31>, <&gpcdma <<
774 dma-names = "rx", "tx"; <<
775 status = "disabled"; <<
776 }; <<
777 <<
778 pwm1: pwm@3280000 { <<
779 compatible = "nvidia,tegra186- <<
780 reg = <0x0 0x3280000 0x0 0x100 <<
781 clocks = <&bpmp TEGRA186_CLK_P <<
782 resets = <&bpmp TEGRA186_RESET <<
783 reset-names = "pwm"; <<
784 status = "disabled"; <<
785 #pwm-cells = <2>; <<
786 }; <<
787 <<
788 pwm2: pwm@3290000 { <<
789 compatible = "nvidia,tegra186- <<
790 reg = <0x0 0x3290000 0x0 0x100 <<
791 clocks = <&bpmp TEGRA186_CLK_P <<
792 resets = <&bpmp TEGRA186_RESET <<
793 reset-names = "pwm"; <<
794 status = "disabled"; <<
795 #pwm-cells = <2>; <<
796 }; <<
797 <<
798 pwm3: pwm@32a0000 { <<
799 compatible = "nvidia,tegra186- <<
800 reg = <0x0 0x32a0000 0x0 0x100 <<
801 clocks = <&bpmp TEGRA186_CLK_P <<
802 resets = <&bpmp TEGRA186_RESET <<
803 reset-names = "pwm"; <<
804 status = "disabled"; <<
805 #pwm-cells = <2>; <<
806 }; <<
807 <<
808 pwm5: pwm@32c0000 { <<
809 compatible = "nvidia,tegra186- <<
810 reg = <0x0 0x32c0000 0x0 0x100 <<
811 clocks = <&bpmp TEGRA186_CLK_P <<
812 resets = <&bpmp TEGRA186_RESET <<
813 reset-names = "pwm"; <<
814 status = "disabled"; <<
815 #pwm-cells = <2>; <<
816 }; <<
817 <<
818 pwm6: pwm@32d0000 { <<
819 compatible = "nvidia,tegra186- <<
820 reg = <0x0 0x32d0000 0x0 0x100 <<
821 clocks = <&bpmp TEGRA186_CLK_P <<
822 resets = <&bpmp TEGRA186_RESET <<
823 reset-names = "pwm"; <<
824 status = "disabled"; <<
825 #pwm-cells = <2>; <<
826 }; <<
827 <<
828 pwm7: pwm@32e0000 { <<
829 compatible = "nvidia,tegra186- <<
830 reg = <0x0 0x32e0000 0x0 0x100 <<
831 clocks = <&bpmp TEGRA186_CLK_P <<
832 resets = <&bpmp TEGRA186_RESET <<
833 reset-names = "pwm"; <<
834 status = "disabled"; <<
835 #pwm-cells = <2>; <<
836 }; <<
837 <<
838 pwm8: pwm@32f0000 { <<
839 compatible = "nvidia,tegra186- <<
840 reg = <0x0 0x32f0000 0x0 0x100 <<
841 clocks = <&bpmp TEGRA186_CLK_P <<
842 resets = <&bpmp TEGRA186_RESET <<
843 reset-names = "pwm"; <<
844 status = "disabled"; 548 status = "disabled";
845 #pwm-cells = <2>; <<
846 }; 549 };
847 550
848 sdmmc1: mmc@3400000 { 551 sdmmc1: mmc@3400000 {
849 compatible = "nvidia,tegra186- 552 compatible = "nvidia,tegra186-sdhci";
850 reg = <0x0 0x03400000 0x0 0x10 553 reg = <0x0 0x03400000 0x0 0x10000>;
851 interrupts = <GIC_SPI 62 IRQ_T 554 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&bpmp TEGRA186_CLK_S 555 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
853 <&bpmp TEGRA186_CLK_S 556 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
854 clock-names = "sdhci", "tmclk" 557 clock-names = "sdhci", "tmclk";
855 resets = <&bpmp TEGRA186_RESET 558 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
856 reset-names = "sdhci"; 559 reset-names = "sdhci";
857 interconnects = <&mc TEGRA186_ 560 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
858 <&mc TEGRA186_ 561 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
859 interconnect-names = "dma-mem" 562 interconnect-names = "dma-mem", "write";
860 iommus = <&smmu TEGRA186_SID_S 563 iommus = <&smmu TEGRA186_SID_SDMMC1>;
861 pinctrl-names = "sdmmc-3v3", " 564 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
862 pinctrl-0 = <&sdmmc1_3v3>; 565 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>; 566 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-off 567 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-o 568 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-off 569 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-o 570 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-off 571 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-o 572 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>; 573 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>; 574 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA 575 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
873 <&bpmp TEGRA 576 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 assigned-clock-parents = <&bpm 577 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
875 status = "disabled"; 578 status = "disabled";
876 }; 579 };
877 580
878 sdmmc2: mmc@3420000 { 581 sdmmc2: mmc@3420000 {
879 compatible = "nvidia,tegra186- 582 compatible = "nvidia,tegra186-sdhci";
880 reg = <0x0 0x03420000 0x0 0x10 583 reg = <0x0 0x03420000 0x0 0x10000>;
881 interrupts = <GIC_SPI 63 IRQ_T 584 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&bpmp TEGRA186_CLK_S 585 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
883 <&bpmp TEGRA186_CLK_S 586 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
884 clock-names = "sdhci", "tmclk" 587 clock-names = "sdhci", "tmclk";
885 resets = <&bpmp TEGRA186_RESET 588 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
886 reset-names = "sdhci"; 589 reset-names = "sdhci";
887 interconnects = <&mc TEGRA186_ 590 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
888 <&mc TEGRA186_ 591 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
889 interconnect-names = "dma-mem" 592 interconnect-names = "dma-mem", "write";
890 iommus = <&smmu TEGRA186_SID_S 593 iommus = <&smmu TEGRA186_SID_SDMMC2>;
891 pinctrl-names = "sdmmc-3v3", " 594 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
892 pinctrl-0 = <&sdmmc2_3v3>; 595 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>; 596 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-off 597 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-o 598 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-off 599 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-o 600 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>; 601 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>; 602 nvidia,default-trim = <0xb>;
900 status = "disabled"; 603 status = "disabled";
901 }; 604 };
902 605
903 sdmmc3: mmc@3440000 { 606 sdmmc3: mmc@3440000 {
904 compatible = "nvidia,tegra186- 607 compatible = "nvidia,tegra186-sdhci";
905 reg = <0x0 0x03440000 0x0 0x10 608 reg = <0x0 0x03440000 0x0 0x10000>;
906 interrupts = <GIC_SPI 64 IRQ_T 609 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&bpmp TEGRA186_CLK_S 610 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
908 <&bpmp TEGRA186_CLK_S 611 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
909 clock-names = "sdhci", "tmclk" 612 clock-names = "sdhci", "tmclk";
910 resets = <&bpmp TEGRA186_RESET 613 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
911 reset-names = "sdhci"; 614 reset-names = "sdhci";
912 interconnects = <&mc TEGRA186_ 615 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
913 <&mc TEGRA186_ 616 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
914 interconnect-names = "dma-mem" 617 interconnect-names = "dma-mem", "write";
915 iommus = <&smmu TEGRA186_SID_S 618 iommus = <&smmu TEGRA186_SID_SDMMC3>;
916 pinctrl-names = "sdmmc-3v3", " 619 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
917 pinctrl-0 = <&sdmmc3_3v3>; 620 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>; 621 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-off 622 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-o 623 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-off 624 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-o 625 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-off 626 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-o 627 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>; 628 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>; 629 nvidia,default-trim = <0xb>;
927 status = "disabled"; 630 status = "disabled";
928 }; 631 };
929 632
930 sdmmc4: mmc@3460000 { 633 sdmmc4: mmc@3460000 {
931 compatible = "nvidia,tegra186- 634 compatible = "nvidia,tegra186-sdhci";
932 reg = <0x0 0x03460000 0x0 0x10 635 reg = <0x0 0x03460000 0x0 0x10000>;
933 interrupts = <GIC_SPI 65 IRQ_T 636 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&bpmp TEGRA186_CLK_S 637 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
935 <&bpmp TEGRA186_CLK_S 638 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
936 clock-names = "sdhci", "tmclk" 639 clock-names = "sdhci", "tmclk";
937 assigned-clocks = <&bpmp TEGRA 640 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
938 <&bpmp TEGRA 641 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
939 assigned-clock-parents = <&bpm 642 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 resets = <&bpmp TEGRA186_RESET 643 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
941 reset-names = "sdhci"; 644 reset-names = "sdhci";
942 interconnects = <&mc TEGRA186_ 645 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
943 <&mc TEGRA186_ 646 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
944 interconnect-names = "dma-mem" 647 interconnect-names = "dma-mem", "write";
945 iommus = <&smmu TEGRA186_SID_S 648 iommus = <&smmu TEGRA186_SID_SDMMC4>;
946 nvidia,pad-autocal-pull-up-off 649 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-o 650 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-off 651 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-o 652 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-off 653 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-o 654 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>; 655 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>; 656 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>; 657 nvidia,dqs-trim = <63>;
955 mmc-hs400-1_8v; 658 mmc-hs400-1_8v;
956 supports-cqe; 659 supports-cqe;
957 status = "disabled"; 660 status = "disabled";
958 }; 661 };
959 662
960 sata@3507000 { <<
961 compatible = "nvidia,tegra186- <<
962 reg = <0x0 0x03507000 0x0 0x00 <<
963 <0x0 0x03500000 0x0 0x00 <<
964 <0x0 0x03A90000 0x0 0x00 <<
965 interrupts = <GIC_SPI 197 IRQ_ <<
966 <<
967 power-domains = <&bpmp TEGRA18 <<
968 interconnects = <&mc TEGRA186_ <<
969 <&mc TEGRA186_ <<
970 interconnect-names = "dma-mem" <<
971 iommus = <&smmu TEGRA186_SID_S <<
972 <<
973 clocks = <&bpmp TEGRA186_CLK_S <<
974 <&bpmp TEGRA186_CLK_S <<
975 clock-names = "sata", "sata-oo <<
976 assigned-clocks = <&bpmp TEGRA <<
977 <&bpmp TEGRA <<
978 assigned-clock-parents = <&bpm <<
979 <&bpm <<
980 assigned-clock-rates = <102000 <<
981 <204000 <<
982 resets = <&bpmp TEGRA186_RESET <<
983 <&bpmp TEGRA186_RESET_ <<
984 reset-names = "sata", "sata-co <<
985 status = "disabled"; <<
986 }; <<
987 <<
988 hda@3510000 { 663 hda@3510000 {
989 compatible = "nvidia,tegra186- 664 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
990 reg = <0x0 0x03510000 0x0 0x10 665 reg = <0x0 0x03510000 0x0 0x10000>;
991 interrupts = <GIC_SPI 161 IRQ_ 666 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&bpmp TEGRA186_CLK_H 667 clocks = <&bpmp TEGRA186_CLK_HDA>,
993 <&bpmp TEGRA186_CLK_H 668 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
994 <&bpmp TEGRA186_CLK_H 669 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
995 clock-names = "hda", "hda2hdmi 670 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
996 resets = <&bpmp TEGRA186_RESET 671 resets = <&bpmp TEGRA186_RESET_HDA>,
997 <&bpmp TEGRA186_RESET 672 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
998 <&bpmp TEGRA186_RESET 673 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
999 reset-names = "hda", "hda2hdmi 674 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 power-domains = <&bpmp TEGRA1 675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1001 interconnects = <&mc TEGRA186 676 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
1002 <&mc TEGRA186 677 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
1003 interconnect-names = "dma-mem 678 interconnect-names = "dma-mem", "write";
1004 iommus = <&smmu TEGRA186_SID_ 679 iommus = <&smmu TEGRA186_SID_HDA>;
1005 status = "disabled"; 680 status = "disabled";
1006 }; 681 };
1007 682
1008 padctl: padctl@3520000 { 683 padctl: padctl@3520000 {
1009 compatible = "nvidia,tegra186 684 compatible = "nvidia,tegra186-xusb-padctl";
1010 reg = <0x0 0x03520000 0x0 0x1 685 reg = <0x0 0x03520000 0x0 0x1000>,
1011 <0x0 0x03540000 0x0 0x1 686 <0x0 0x03540000 0x0 0x1000>;
1012 reg-names = "padctl", "ao"; 687 reg-names = "padctl", "ao";
1013 interrupts = <GIC_SPI 167 IRQ 688 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1014 689
1015 resets = <&bpmp TEGRA186_RESE 690 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1016 reset-names = "padctl"; 691 reset-names = "padctl";
1017 692
1018 status = "disabled"; 693 status = "disabled";
1019 694
1020 pads { 695 pads {
1021 usb2 { 696 usb2 {
1022 clocks = <&bp 697 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1023 clock-names = 698 clock-names = "trk";
1024 status = "dis 699 status = "disabled";
1025 700
1026 lanes { 701 lanes {
1027 usb2- 702 usb2-0 {
1028 703 status = "disabled";
1029 704 #phy-cells = <0>;
1030 }; 705 };
1031 706
1032 usb2- 707 usb2-1 {
1033 708 status = "disabled";
1034 709 #phy-cells = <0>;
1035 }; 710 };
1036 711
1037 usb2- 712 usb2-2 {
1038 713 status = "disabled";
1039 714 #phy-cells = <0>;
1040 }; 715 };
1041 }; 716 };
1042 }; 717 };
1043 718
1044 hsic { 719 hsic {
1045 clocks = <&bp 720 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1046 clock-names = 721 clock-names = "trk";
1047 status = "dis 722 status = "disabled";
1048 723
1049 lanes { 724 lanes {
1050 hsic- 725 hsic-0 {
1051 726 status = "disabled";
1052 727 #phy-cells = <0>;
1053 }; 728 };
1054 }; 729 };
1055 }; 730 };
1056 731
1057 usb3 { 732 usb3 {
1058 status = "dis 733 status = "disabled";
1059 734
1060 lanes { 735 lanes {
1061 usb3- 736 usb3-0 {
1062 737 status = "disabled";
1063 738 #phy-cells = <0>;
1064 }; 739 };
1065 740
1066 usb3- 741 usb3-1 {
1067 742 status = "disabled";
1068 743 #phy-cells = <0>;
1069 }; 744 };
1070 745
1071 usb3- 746 usb3-2 {
1072 747 status = "disabled";
1073 748 #phy-cells = <0>;
1074 }; 749 };
1075 }; 750 };
1076 }; 751 };
1077 }; 752 };
1078 753
1079 ports { 754 ports {
1080 usb2-0 { 755 usb2-0 {
1081 status = "dis 756 status = "disabled";
1082 }; 757 };
1083 758
1084 usb2-1 { 759 usb2-1 {
1085 status = "dis 760 status = "disabled";
1086 }; 761 };
1087 762
1088 usb2-2 { 763 usb2-2 {
1089 status = "dis 764 status = "disabled";
1090 }; 765 };
1091 766
1092 hsic-0 { 767 hsic-0 {
1093 status = "dis 768 status = "disabled";
1094 }; 769 };
1095 770
1096 usb3-0 { 771 usb3-0 {
1097 status = "dis 772 status = "disabled";
1098 }; 773 };
1099 774
1100 usb3-1 { 775 usb3-1 {
1101 status = "dis 776 status = "disabled";
1102 }; 777 };
1103 778
1104 usb3-2 { 779 usb3-2 {
1105 status = "dis 780 status = "disabled";
1106 }; 781 };
1107 }; 782 };
1108 }; 783 };
1109 784
1110 usb@3530000 { 785 usb@3530000 {
1111 compatible = "nvidia,tegra186 786 compatible = "nvidia,tegra186-xusb";
1112 reg = <0x0 0x03530000 0x0 0x8 787 reg = <0x0 0x03530000 0x0 0x8000>,
1113 <0x0 0x03538000 0x0 0x1 788 <0x0 0x03538000 0x0 0x1000>;
1114 reg-names = "hcd", "fpci"; 789 reg-names = "hcd", "fpci";
1115 interrupts = <GIC_SPI 163 IRQ 790 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 164 IRQ 791 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&bpmp TEGRA186_CLK_ 792 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1118 <&bpmp TEGRA186_CLK_ 793 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1119 <&bpmp TEGRA186_CLK_ 794 <&bpmp TEGRA186_CLK_XUSB_SS>,
1120 <&bpmp TEGRA186_CLK_ 795 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1121 <&bpmp TEGRA186_CLK_ 796 <&bpmp TEGRA186_CLK_CLK_M>,
1122 <&bpmp TEGRA186_CLK_ 797 <&bpmp TEGRA186_CLK_XUSB_FS>,
1123 <&bpmp TEGRA186_CLK_ 798 <&bpmp TEGRA186_CLK_PLLU>,
1124 <&bpmp TEGRA186_CLK_ 799 <&bpmp TEGRA186_CLK_CLK_M>,
1125 <&bpmp TEGRA186_CLK_ 800 <&bpmp TEGRA186_CLK_PLLE>;
1126 clock-names = "xusb_host", "x 801 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1127 "xusb_ss_src", 802 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1128 "pll_u_480m", " 803 "pll_u_480m", "clk_m", "pll_e";
1129 power-domains = <&bpmp TEGRA1 804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1130 <&bpmp TEGRA1 805 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1131 power-domain-names = "xusb_ho 806 power-domain-names = "xusb_host", "xusb_ss";
1132 interconnects = <&mc TEGRA186 807 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1133 <&mc TEGRA186 808 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1134 interconnect-names = "dma-mem 809 interconnect-names = "dma-mem", "write";
1135 iommus = <&smmu TEGRA186_SID_ 810 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1136 #address-cells = <1>; 811 #address-cells = <1>;
1137 #size-cells = <0>; 812 #size-cells = <0>;
1138 status = "disabled"; 813 status = "disabled";
1139 814
1140 nvidia,xusb-padctl = <&padctl 815 nvidia,xusb-padctl = <&padctl>;
1141 }; 816 };
1142 817
1143 usb@3550000 { 818 usb@3550000 {
1144 compatible = "nvidia,tegra186 819 compatible = "nvidia,tegra186-xudc";
1145 reg = <0x0 0x03550000 0x0 0x8 820 reg = <0x0 0x03550000 0x0 0x8000>,
1146 <0x0 0x03558000 0x0 0x1 821 <0x0 0x03558000 0x0 0x1000>;
1147 reg-names = "base", "fpci"; 822 reg-names = "base", "fpci";
1148 interrupts = <GIC_SPI 166 IRQ 823 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&bpmp TEGRA186_CLK_ 824 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1150 <&bpmp TEGRA186_CLK_ 825 <&bpmp TEGRA186_CLK_XUSB_SS>,
1151 <&bpmp TEGRA186_CLK_ 826 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1152 <&bpmp TEGRA186_CLK_ 827 <&bpmp TEGRA186_CLK_XUSB_FS>;
1153 clock-names = "dev", "ss", "s 828 clock-names = "dev", "ss", "ss_src", "fs_src";
1154 interconnects = <&mc TEGRA186 <<
1155 <&mc TEGRA186 <<
1156 interconnect-names = "dma-mem <<
1157 iommus = <&smmu TEGRA186_SID_ 829 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1158 power-domains = <&bpmp TEGRA1 830 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1159 <&bpmp TEGRA1 831 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1160 power-domain-names = "dev", " 832 power-domain-names = "dev", "ss";
1161 nvidia,xusb-padctl = <&padctl 833 nvidia,xusb-padctl = <&padctl>;
1162 status = "disabled"; 834 status = "disabled";
1163 }; 835 };
1164 836
1165 fuse@3820000 { 837 fuse@3820000 {
1166 compatible = "nvidia,tegra186 838 compatible = "nvidia,tegra186-efuse";
1167 reg = <0x0 0x03820000 0x0 0x1 839 reg = <0x0 0x03820000 0x0 0x10000>;
1168 clocks = <&bpmp TEGRA186_CLK_ 840 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1169 clock-names = "fuse"; 841 clock-names = "fuse";
1170 }; 842 };
1171 843
1172 gic: interrupt-controller@3881000 { 844 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400"; 845 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>; 846 #interrupt-cells = <3>;
1175 interrupt-controller; 847 interrupt-controller;
1176 reg = <0x0 0x03881000 0x0 0x1 848 reg = <0x0 0x03881000 0x0 0x1000>,
1177 <0x0 0x03882000 0x0 0x2 849 <0x0 0x03882000 0x0 0x2000>,
1178 <0x0 0x03884000 0x0 0x2 850 <0x0 0x03884000 0x0 0x2000>,
1179 <0x0 0x03886000 0x0 0x2 851 <0x0 0x03886000 0x0 0x2000>;
1180 interrupts = <GIC_PPI 9 852 interrupts = <GIC_PPI 9
1181 (GIC_CPU_MASK_SIMPLE( 853 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1182 interrupt-parent = <&gic>; 854 interrupt-parent = <&gic>;
1183 }; 855 };
1184 856
1185 cec@3960000 { 857 cec@3960000 {
1186 compatible = "nvidia,tegra186 858 compatible = "nvidia,tegra186-cec";
1187 reg = <0x0 0x03960000 0x0 0x1 859 reg = <0x0 0x03960000 0x0 0x10000>;
1188 interrupts = <GIC_SPI 162 IRQ 860 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&bpmp TEGRA186_CLK_ 861 clocks = <&bpmp TEGRA186_CLK_CEC>;
1190 clock-names = "cec"; 862 clock-names = "cec";
1191 status = "disabled"; 863 status = "disabled";
1192 }; 864 };
1193 865
1194 hsp_top0: hsp@3c00000 { 866 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186 867 compatible = "nvidia,tegra186-hsp";
1196 reg = <0x0 0x03c00000 0x0 0xa 868 reg = <0x0 0x03c00000 0x0 0xa0000>;
1197 interrupts = <GIC_SPI 176 IRQ 869 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "doorbell"; 870 interrupt-names = "doorbell";
1199 #mbox-cells = <2>; 871 #mbox-cells = <2>;
1200 status = "disabled"; 872 status = "disabled";
1201 }; 873 };
1202 874
1203 gen2_i2c: i2c@c240000 { 875 gen2_i2c: i2c@c240000 {
1204 compatible = "nvidia,tegra186 !! 876 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1205 reg = <0x0 0x0c240000 0x0 0x1 877 reg = <0x0 0x0c240000 0x0 0x10000>;
1206 interrupts = <GIC_SPI 26 IRQ_ 878 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>; 879 #address-cells = <1>;
1208 #size-cells = <0>; 880 #size-cells = <0>;
1209 clocks = <&bpmp TEGRA186_CLK_ 881 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1210 clock-names = "div-clk"; 882 clock-names = "div-clk";
1211 resets = <&bpmp TEGRA186_RESE 883 resets = <&bpmp TEGRA186_RESET_I2C2>;
1212 reset-names = "i2c"; 884 reset-names = "i2c";
1213 dmas = <&gpcdma 22>, <&gpcdma <<
1214 dma-names = "rx", "tx"; <<
1215 status = "disabled"; 885 status = "disabled";
1216 }; 886 };
1217 887
1218 gen8_i2c: i2c@c250000 { 888 gen8_i2c: i2c@c250000 {
1219 compatible = "nvidia,tegra186 !! 889 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1220 reg = <0x0 0x0c250000 0x0 0x1 890 reg = <0x0 0x0c250000 0x0 0x10000>;
1221 interrupts = <GIC_SPI 32 IRQ_ 891 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>; 892 #address-cells = <1>;
1223 #size-cells = <0>; 893 #size-cells = <0>;
1224 clocks = <&bpmp TEGRA186_CLK_ 894 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1225 clock-names = "div-clk"; 895 clock-names = "div-clk";
1226 resets = <&bpmp TEGRA186_RESE 896 resets = <&bpmp TEGRA186_RESET_I2C8>;
1227 reset-names = "i2c"; 897 reset-names = "i2c";
1228 dmas = <&gpcdma 0>, <&gpcdma <<
1229 dma-names = "rx", "tx"; <<
1230 status = "disabled"; 898 status = "disabled";
1231 }; 899 };
1232 900
1233 uartc: serial@c280000 { 901 uartc: serial@c280000 {
1234 compatible = "nvidia,tegra186 902 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1235 reg = <0x0 0x0c280000 0x0 0x4 903 reg = <0x0 0x0c280000 0x0 0x40>;
1236 reg-shift = <2>; 904 reg-shift = <2>;
1237 interrupts = <GIC_SPI 114 IRQ 905 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&bpmp TEGRA186_CLK_ 906 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1239 clock-names = "serial"; 907 clock-names = "serial";
1240 resets = <&bpmp TEGRA186_RESE 908 resets = <&bpmp TEGRA186_RESET_UARTC>;
1241 reset-names = "serial"; 909 reset-names = "serial";
1242 status = "disabled"; 910 status = "disabled";
1243 }; 911 };
1244 912
1245 uartg: serial@c290000 { 913 uartg: serial@c290000 {
1246 compatible = "nvidia,tegra186 914 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1247 reg = <0x0 0x0c290000 0x0 0x4 915 reg = <0x0 0x0c290000 0x0 0x40>;
1248 reg-shift = <2>; 916 reg-shift = <2>;
1249 interrupts = <GIC_SPI 118 IRQ 917 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&bpmp TEGRA186_CLK_ 918 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1251 clock-names = "serial"; 919 clock-names = "serial";
1252 resets = <&bpmp TEGRA186_RESE 920 resets = <&bpmp TEGRA186_RESET_UARTG>;
1253 reset-names = "serial"; 921 reset-names = "serial";
1254 status = "disabled"; 922 status = "disabled";
1255 }; 923 };
1256 924
1257 rtc: rtc@c2a0000 { 925 rtc: rtc@c2a0000 {
1258 compatible = "nvidia,tegra186 926 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1259 reg = <0 0x0c2a0000 0 0x10000 927 reg = <0 0x0c2a0000 0 0x10000>;
1260 interrupt-parent = <&pmc>; 928 interrupt-parent = <&pmc>;
1261 interrupts = <73 IRQ_TYPE_LEV 929 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&bpmp TEGRA186_CLK_ 930 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1263 clock-names = "rtc"; 931 clock-names = "rtc";
1264 status = "disabled"; 932 status = "disabled";
1265 }; 933 };
1266 934
1267 gpio_aon: gpio@c2f0000 { 935 gpio_aon: gpio@c2f0000 {
1268 compatible = "nvidia,tegra186 936 compatible = "nvidia,tegra186-gpio-aon";
1269 reg-names = "security", "gpio 937 reg-names = "security", "gpio";
1270 reg = <0x0 0xc2f0000 0x0 0x10 938 reg = <0x0 0xc2f0000 0x0 0x1000>,
1271 <0x0 0xc2f1000 0x0 0x10 939 <0x0 0xc2f1000 0x0 0x1000>;
1272 interrupts = <GIC_SPI 60 IRQ_ 940 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1273 gpio-controller; 941 gpio-controller;
1274 #gpio-cells = <2>; 942 #gpio-cells = <2>;
1275 interrupt-controller; 943 interrupt-controller;
1276 #interrupt-cells = <2>; 944 #interrupt-cells = <2>;
1277 }; 945 };
1278 946
1279 pwm4: pwm@c340000 { <<
1280 compatible = "nvidia,tegra186 <<
1281 reg = <0x0 0xc340000 0x0 0x10 <<
1282 clocks = <&bpmp TEGRA186_CLK_ <<
1283 resets = <&bpmp TEGRA186_RESE <<
1284 reset-names = "pwm"; <<
1285 status = "disabled"; <<
1286 #pwm-cells = <2>; <<
1287 }; <<
1288 <<
1289 pmc: pmc@c360000 { 947 pmc: pmc@c360000 {
1290 compatible = "nvidia,tegra186 948 compatible = "nvidia,tegra186-pmc";
1291 reg = <0 0x0c360000 0 0x10000 949 reg = <0 0x0c360000 0 0x10000>,
1292 <0 0x0c370000 0 0x10000 950 <0 0x0c370000 0 0x10000>,
1293 <0 0x0c380000 0 0x10000 951 <0 0x0c380000 0 0x10000>,
1294 <0 0x0c390000 0 0x10000 952 <0 0x0c390000 0 0x10000>;
1295 reg-names = "pmc", "wake", "a 953 reg-names = "pmc", "wake", "aotag", "scratch";
1296 954
1297 #interrupt-cells = <2>; 955 #interrupt-cells = <2>;
1298 interrupt-controller; 956 interrupt-controller;
1299 957
1300 sdmmc1_1v8: sdmmc1-1v8 { <<
1301 pins = "sdmmc1-hv"; <<
1302 power-source = <TEGRA <<
1303 }; <<
1304 <<
1305 sdmmc1_3v3: sdmmc1-3v3 { 958 sdmmc1_3v3: sdmmc1-3v3 {
1306 pins = "sdmmc1-hv"; 959 pins = "sdmmc1-hv";
1307 power-source = <TEGRA 960 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1308 }; 961 };
1309 962
1310 sdmmc2_1v8: sdmmc2-1v8 { !! 963 sdmmc1_1v8: sdmmc1-1v8 {
1311 pins = "sdmmc2-hv"; !! 964 pins = "sdmmc1-hv";
1312 power-source = <TEGRA 965 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1313 }; 966 };
1314 967
1315 sdmmc2_3v3: sdmmc2-3v3 { 968 sdmmc2_3v3: sdmmc2-3v3 {
1316 pins = "sdmmc2-hv"; 969 pins = "sdmmc2-hv";
1317 power-source = <TEGRA 970 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1318 }; 971 };
1319 972
1320 sdmmc3_1v8: sdmmc3-1v8 { !! 973 sdmmc2_1v8: sdmmc2-1v8 {
1321 pins = "sdmmc3-hv"; !! 974 pins = "sdmmc2-hv";
1322 power-source = <TEGRA 975 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1323 }; 976 };
1324 977
1325 sdmmc3_3v3: sdmmc3-3v3 { 978 sdmmc3_3v3: sdmmc3-3v3 {
1326 pins = "sdmmc3-hv"; 979 pins = "sdmmc3-hv";
1327 power-source = <TEGRA 980 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1328 }; 981 };
>> 982
>> 983 sdmmc3_1v8: sdmmc3-1v8 {
>> 984 pins = "sdmmc3-hv";
>> 985 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 986 };
1329 }; 987 };
1330 988
1331 ccplex@e000000 { 989 ccplex@e000000 {
1332 compatible = "nvidia,tegra186 990 compatible = "nvidia,tegra186-ccplex-cluster";
1333 reg = <0x0 0x0e000000 0x0 0x4 !! 991 reg = <0x0 0x0e000000 0x0 0x3fffff>;
1334 992
1335 nvidia,bpmp = <&bpmp>; 993 nvidia,bpmp = <&bpmp>;
1336 }; 994 };
1337 995
1338 pcie@10003000 { 996 pcie@10003000 {
1339 compatible = "nvidia,tegra186 997 compatible = "nvidia,tegra186-pcie";
1340 power-domains = <&bpmp TEGRA1 998 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1341 device_type = "pci"; 999 device_type = "pci";
1342 reg = <0x0 0x10003000 0x0 0x0 1000 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1343 <0x0 0x10003800 0x0 0x0 1001 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1344 <0x0 0x40000000 0x0 0x1 1002 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1345 reg-names = "pads", "afi", "c 1003 reg-names = "pads", "afi", "cs";
1346 1004
1347 interrupts = <GIC_SPI 72 IRQ_ 1005 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1348 <GIC_SPI 73 IRQ_ 1006 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1349 interrupt-names = "intr", "ms 1007 interrupt-names = "intr", "msi";
1350 1008
1351 #interrupt-cells = <1>; 1009 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0 1010 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic 1011 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1354 1012
1355 bus-range = <0x00 0xff>; 1013 bus-range = <0x00 0xff>;
1356 #address-cells = <3>; 1014 #address-cells = <3>;
1357 #size-cells = <2>; 1015 #size-cells = <2>;
1358 1016
1359 ranges = <0x02000000 0 0x1000 1017 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1360 <0x02000000 0 0x1000 1018 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1361 <0x02000000 0 0x1000 1019 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1362 <0x01000000 0 0x0 1020 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1363 <0x02000000 0 0x5010 1021 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1364 <0x42000000 0 0x5800 1022 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1365 1023
1366 clocks = <&bpmp TEGRA186_CLK_ 1024 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1367 <&bpmp TEGRA186_CLK_ 1025 <&bpmp TEGRA186_CLK_AFI>,
1368 <&bpmp TEGRA186_CLK_ 1026 <&bpmp TEGRA186_CLK_PLLE>;
1369 clock-names = "pex", "afi", " 1027 clock-names = "pex", "afi", "pll_e";
1370 1028
1371 resets = <&bpmp TEGRA186_RESE 1029 resets = <&bpmp TEGRA186_RESET_PCIE>,
1372 <&bpmp TEGRA186_RESE 1030 <&bpmp TEGRA186_RESET_AFI>,
1373 <&bpmp TEGRA186_RESE 1031 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1374 reset-names = "pex", "afi", " 1032 reset-names = "pex", "afi", "pcie_x";
1375 1033
1376 interconnects = <&mc TEGRA186 1034 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1377 <&mc TEGRA186 1035 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1378 interconnect-names = "dma-mem 1036 interconnect-names = "dma-mem", "write";
1379 1037
1380 iommus = <&smmu TEGRA186_SID_ 1038 iommus = <&smmu TEGRA186_SID_AFI>;
1381 iommu-map = <0x0 &smmu TEGRA1 1039 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>; 1040 iommu-map-mask = <0x0>;
1383 1041
1384 status = "disabled"; 1042 status = "disabled";
1385 1043
1386 pci@1,0 { 1044 pci@1,0 {
1387 device_type = "pci"; 1045 device_type = "pci";
1388 assigned-addresses = 1046 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1389 reg = <0x000800 0 0 0 1047 reg = <0x000800 0 0 0 0>;
1390 status = "disabled"; 1048 status = "disabled";
1391 1049
1392 #address-cells = <3>; 1050 #address-cells = <3>;
1393 #size-cells = <2>; 1051 #size-cells = <2>;
1394 ranges; 1052 ranges;
1395 1053
1396 nvidia,num-lanes = <2 1054 nvidia,num-lanes = <2>;
1397 }; 1055 };
1398 1056
1399 pci@2,0 { 1057 pci@2,0 {
1400 device_type = "pci"; 1058 device_type = "pci";
1401 assigned-addresses = 1059 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1402 reg = <0x001000 0 0 0 1060 reg = <0x001000 0 0 0 0>;
1403 status = "disabled"; 1061 status = "disabled";
1404 1062
1405 #address-cells = <3>; 1063 #address-cells = <3>;
1406 #size-cells = <2>; 1064 #size-cells = <2>;
1407 ranges; 1065 ranges;
1408 1066
1409 nvidia,num-lanes = <1 1067 nvidia,num-lanes = <1>;
1410 }; 1068 };
1411 1069
1412 pci@3,0 { 1070 pci@3,0 {
1413 device_type = "pci"; 1071 device_type = "pci";
1414 assigned-addresses = 1072 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1415 reg = <0x001800 0 0 0 1073 reg = <0x001800 0 0 0 0>;
1416 status = "disabled"; 1074 status = "disabled";
1417 1075
1418 #address-cells = <3>; 1076 #address-cells = <3>;
1419 #size-cells = <2>; 1077 #size-cells = <2>;
1420 ranges; 1078 ranges;
1421 1079
1422 nvidia,num-lanes = <1 1080 nvidia,num-lanes = <1>;
1423 }; 1081 };
1424 }; 1082 };
1425 1083
1426 smmu: iommu@12000000 { 1084 smmu: iommu@12000000 {
1427 compatible = "nvidia,tegra186 !! 1085 compatible = "arm,mmu-500";
1428 reg = <0 0x12000000 0 0x80000 1086 reg = <0 0x12000000 0 0x800000>;
1429 interrupts = <GIC_SPI 170 IRQ 1087 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 170 IRQ 1088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 170 IRQ 1089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 170 IRQ 1090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 170 IRQ 1091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 170 IRQ 1092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 170 IRQ 1093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 170 IRQ 1094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 170 IRQ 1095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 170 IRQ 1096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 170 IRQ 1097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 170 IRQ 1098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 170 IRQ 1099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 170 IRQ 1100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 170 IRQ 1101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 170 IRQ 1102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ 1103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 170 IRQ 1104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 170 IRQ 1105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 170 IRQ 1106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 170 IRQ 1107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 170 IRQ 1108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 170 IRQ 1109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 170 IRQ 1110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 170 IRQ 1111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 170 IRQ 1112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 170 IRQ 1113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 170 IRQ 1114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 170 IRQ 1115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 170 IRQ 1116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 170 IRQ 1117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 170 IRQ 1118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 170 IRQ 1119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 170 IRQ 1120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 170 IRQ 1121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 170 IRQ 1122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 170 IRQ 1123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 170 IRQ 1124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 170 IRQ 1125 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 170 IRQ 1126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 170 IRQ 1127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 170 IRQ 1128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 170 IRQ 1129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 170 IRQ 1130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 170 IRQ 1131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 170 IRQ 1132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 170 IRQ 1133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 170 IRQ 1134 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 170 IRQ 1135 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 170 IRQ 1136 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 170 IRQ 1137 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 170 IRQ 1138 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 170 IRQ 1139 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 170 IRQ 1140 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 170 IRQ 1141 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 170 IRQ 1142 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 170 IRQ 1143 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 170 IRQ 1144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 170 IRQ 1145 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 170 IRQ 1146 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 170 IRQ 1147 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 170 IRQ 1148 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 170 IRQ 1149 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 170 IRQ 1150 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 170 IRQ 1151 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1494 stream-match-mask = <0x7f80>; 1152 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>; 1153 #global-interrupts = <1>;
1496 #iommu-cells = <1>; 1154 #iommu-cells = <1>;
1497 <<
1498 nvidia,memory-controller = <& <<
1499 }; 1155 };
1500 1156
1501 host1x@13e00000 { 1157 host1x@13e00000 {
1502 compatible = "nvidia,tegra186 1158 compatible = "nvidia,tegra186-host1x";
1503 reg = <0x0 0x13e00000 0x0 0x1 1159 reg = <0x0 0x13e00000 0x0 0x10000>,
1504 <0x0 0x13e10000 0x0 0x1 1160 <0x0 0x13e10000 0x0 0x10000>;
1505 reg-names = "hypervisor", "vm 1161 reg-names = "hypervisor", "vm";
1506 interrupts = <GIC_SPI 265 IRQ 1162 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 263 IRQ 1163 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-names = "syncpt", " 1164 interrupt-names = "syncpt", "host1x";
1509 clocks = <&bpmp TEGRA186_CLK_ 1165 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1510 clock-names = "host1x"; 1166 clock-names = "host1x";
1511 resets = <&bpmp TEGRA186_RESE 1167 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1512 reset-names = "host1x"; 1168 reset-names = "host1x";
1513 1169
1514 #address-cells = <1>; 1170 #address-cells = <1>;
1515 #size-cells = <1>; 1171 #size-cells = <1>;
1516 1172
1517 ranges = <0x15000000 0x0 0x15 1173 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1518 1174
1519 interconnects = <&mc TEGRA186 1175 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1520 interconnect-names = "dma-mem 1176 interconnect-names = "dma-mem";
1521 1177
1522 iommus = <&smmu TEGRA186_SID_ 1178 iommus = <&smmu TEGRA186_SID_HOST1X>;
1523 1179
1524 /* Context isolation domains <<
1525 iommu-map = <0 &smmu TEGRA186 <<
1526 <1 &smmu TEGRA186 <<
1527 <2 &smmu TEGRA186 <<
1528 <3 &smmu TEGRA186 <<
1529 <4 &smmu TEGRA186 <<
1530 <5 &smmu TEGRA186 <<
1531 <6 &smmu TEGRA186 <<
1532 <7 &smmu TEGRA186 <<
1533 <<
1534 dpaux1: dpaux@15040000 { 1180 dpaux1: dpaux@15040000 {
1535 compatible = "nvidia, 1181 compatible = "nvidia,tegra186-dpaux";
1536 reg = <0x15040000 0x1 1182 reg = <0x15040000 0x10000>;
1537 interrupts = <GIC_SPI 1183 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1538 clocks = <&bpmp TEGRA 1184 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1539 <&bpmp TEGRA 1185 <&bpmp TEGRA186_CLK_PLLDP>;
1540 clock-names = "dpaux" 1186 clock-names = "dpaux", "parent";
1541 resets = <&bpmp TEGRA 1187 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1542 reset-names = "dpaux" 1188 reset-names = "dpaux";
1543 status = "disabled"; 1189 status = "disabled";
1544 1190
1545 power-domains = <&bpm 1191 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1546 1192
1547 state_dpaux1_aux: pin 1193 state_dpaux1_aux: pinmux-aux {
1548 groups = "dpa 1194 groups = "dpaux-io";
1549 function = "a 1195 function = "aux";
1550 }; 1196 };
1551 1197
1552 state_dpaux1_i2c: pin 1198 state_dpaux1_i2c: pinmux-i2c {
1553 groups = "dpa 1199 groups = "dpaux-io";
1554 function = "i 1200 function = "i2c";
1555 }; 1201 };
1556 1202
1557 state_dpaux1_off: pin 1203 state_dpaux1_off: pinmux-off {
1558 groups = "dpa 1204 groups = "dpaux-io";
1559 function = "o 1205 function = "off";
1560 }; 1206 };
1561 1207
1562 i2c-bus { 1208 i2c-bus {
1563 #address-cell 1209 #address-cells = <1>;
1564 #size-cells = 1210 #size-cells = <0>;
1565 }; 1211 };
1566 }; 1212 };
1567 1213
1568 display-hub@15200000 { 1214 display-hub@15200000 {
1569 compatible = "nvidia, 1215 compatible = "nvidia,tegra186-display";
1570 reg = <0x15200000 0x0 1216 reg = <0x15200000 0x00040000>;
1571 resets = <&bpmp TEGRA 1217 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1572 <&bpmp TEGRA 1218 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1573 <&bpmp TEGRA 1219 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1574 <&bpmp TEGRA 1220 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1575 <&bpmp TEGRA 1221 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1576 <&bpmp TEGRA 1222 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1577 <&bpmp TEGRA 1223 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1578 reset-names = "misc", 1224 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1579 "wgrp3" 1225 "wgrp3", "wgrp4", "wgrp5";
1580 clocks = <&bpmp TEGRA 1226 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1581 <&bpmp TEGRA 1227 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1582 <&bpmp TEGRA 1228 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1583 clock-names = "disp", 1229 clock-names = "disp", "dsc", "hub";
1584 status = "disabled"; 1230 status = "disabled";
1585 1231
1586 power-domains = <&bpm 1232 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1587 1233
1588 #address-cells = <1>; 1234 #address-cells = <1>;
1589 #size-cells = <1>; 1235 #size-cells = <1>;
1590 1236
1591 ranges = <0x15200000 1237 ranges = <0x15200000 0x15200000 0x40000>;
1592 1238
1593 display@15200000 { 1239 display@15200000 {
1594 compatible = 1240 compatible = "nvidia,tegra186-dc";
1595 reg = <0x1520 1241 reg = <0x15200000 0x10000>;
1596 interrupts = 1242 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&bp 1243 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1598 clock-names = 1244 clock-names = "dc";
1599 resets = <&bp 1245 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1600 reset-names = 1246 reset-names = "dc";
1601 1247
1602 power-domains 1248 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1603 interconnects 1249 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1604 1250 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1605 interconnect- 1251 interconnect-names = "dma-mem", "read-1";
1606 iommus = <&sm 1252 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1607 1253
1608 nvidia,output 1254 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1609 nvidia,head = 1255 nvidia,head = <0>;
1610 }; 1256 };
1611 1257
1612 display@15210000 { 1258 display@15210000 {
1613 compatible = 1259 compatible = "nvidia,tegra186-dc";
1614 reg = <0x1521 1260 reg = <0x15210000 0x10000>;
1615 interrupts = 1261 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&bp 1262 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1617 clock-names = 1263 clock-names = "dc";
1618 resets = <&bp 1264 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1619 reset-names = 1265 reset-names = "dc";
1620 1266
1621 power-domains 1267 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1622 interconnects 1268 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1623 1269 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1624 interconnect- 1270 interconnect-names = "dma-mem", "read-1";
1625 iommus = <&sm 1271 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1626 1272
1627 nvidia,output 1273 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1628 nvidia,head = 1274 nvidia,head = <1>;
1629 }; 1275 };
1630 1276
1631 display@15220000 { 1277 display@15220000 {
1632 compatible = 1278 compatible = "nvidia,tegra186-dc";
1633 reg = <0x1522 1279 reg = <0x15220000 0x10000>;
1634 interrupts = 1280 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&bp 1281 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1636 clock-names = 1282 clock-names = "dc";
1637 resets = <&bp 1283 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1638 reset-names = 1284 reset-names = "dc";
1639 1285
1640 power-domains 1286 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1641 interconnects 1287 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1642 1288 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1643 interconnect- 1289 interconnect-names = "dma-mem", "read-1";
1644 iommus = <&sm 1290 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1645 1291
1646 nvidia,output 1292 nvidia,outputs = <&sor0 &sor1>;
1647 nvidia,head = 1293 nvidia,head = <2>;
1648 }; 1294 };
1649 }; 1295 };
1650 1296
1651 dsia: dsi@15300000 { 1297 dsia: dsi@15300000 {
1652 compatible = "nvidia, 1298 compatible = "nvidia,tegra186-dsi";
1653 reg = <0x15300000 0x1 1299 reg = <0x15300000 0x10000>;
1654 interrupts = <GIC_SPI 1300 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&bpmp TEGRA 1301 clocks = <&bpmp TEGRA186_CLK_DSI>,
1656 <&bpmp TEGRA 1302 <&bpmp TEGRA186_CLK_DSIA_LP>,
1657 <&bpmp TEGRA 1303 <&bpmp TEGRA186_CLK_PLLD>;
1658 clock-names = "dsi", 1304 clock-names = "dsi", "lp", "parent";
1659 resets = <&bpmp TEGRA 1305 resets = <&bpmp TEGRA186_RESET_DSI>;
1660 reset-names = "dsi"; 1306 reset-names = "dsi";
1661 status = "disabled"; 1307 status = "disabled";
1662 1308
1663 power-domains = <&bpm 1309 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1664 }; 1310 };
1665 1311
1666 vic@15340000 { 1312 vic@15340000 {
1667 compatible = "nvidia, 1313 compatible = "nvidia,tegra186-vic";
1668 reg = <0x15340000 0x4 1314 reg = <0x15340000 0x40000>;
1669 interrupts = <GIC_SPI 1315 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1670 clocks = <&bpmp TEGRA 1316 clocks = <&bpmp TEGRA186_CLK_VIC>;
1671 clock-names = "vic"; 1317 clock-names = "vic";
1672 resets = <&bpmp TEGRA 1318 resets = <&bpmp TEGRA186_RESET_VIC>;
1673 reset-names = "vic"; 1319 reset-names = "vic";
1674 1320
1675 power-domains = <&bpm 1321 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1676 interconnects = <&mc 1322 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1677 <&mc 1323 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1678 interconnect-names = 1324 interconnect-names = "dma-mem", "write";
1679 iommus = <&smmu TEGRA 1325 iommus = <&smmu TEGRA186_SID_VIC>;
1680 }; 1326 };
1681 1327
1682 nvjpg@15380000 { <<
1683 compatible = "nvidia, <<
1684 reg = <0x15380000 0x4 <<
1685 clocks = <&bpmp TEGRA <<
1686 clock-names = "nvjpg" <<
1687 resets = <&bpmp TEGRA <<
1688 reset-names = "nvjpg" <<
1689 <<
1690 power-domains = <&bpm <<
1691 interconnects = <&mc <<
1692 <&mc <<
1693 interconnect-names = <<
1694 iommus = <&smmu TEGRA <<
1695 }; <<
1696 <<
1697 dsib: dsi@15400000 { 1328 dsib: dsi@15400000 {
1698 compatible = "nvidia, 1329 compatible = "nvidia,tegra186-dsi";
1699 reg = <0x15400000 0x1 1330 reg = <0x15400000 0x10000>;
1700 interrupts = <GIC_SPI 1331 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&bpmp TEGRA 1332 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1702 <&bpmp TEGRA 1333 <&bpmp TEGRA186_CLK_DSIB_LP>,
1703 <&bpmp TEGRA 1334 <&bpmp TEGRA186_CLK_PLLD>;
1704 clock-names = "dsi", 1335 clock-names = "dsi", "lp", "parent";
1705 resets = <&bpmp TEGRA 1336 resets = <&bpmp TEGRA186_RESET_DSIB>;
1706 reset-names = "dsi"; 1337 reset-names = "dsi";
1707 status = "disabled"; 1338 status = "disabled";
1708 1339
1709 power-domains = <&bpm 1340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1710 }; 1341 };
1711 1342
1712 nvdec@15480000 { <<
1713 compatible = "nvidia, <<
1714 reg = <0x15480000 0x4 <<
1715 clocks = <&bpmp TEGRA <<
1716 clock-names = "nvdec" <<
1717 resets = <&bpmp TEGRA <<
1718 reset-names = "nvdec" <<
1719 <<
1720 power-domains = <&bpm <<
1721 interconnects = <&mc <<
1722 <&mc <<
1723 <&mc <<
1724 interconnect-names = <<
1725 iommus = <&smmu TEGRA <<
1726 }; <<
1727 <<
1728 nvenc@154c0000 { <<
1729 compatible = "nvidia, <<
1730 reg = <0x154c0000 0x4 <<
1731 clocks = <&bpmp TEGRA <<
1732 clock-names = "nvenc" <<
1733 resets = <&bpmp TEGRA <<
1734 reset-names = "nvenc" <<
1735 <<
1736 power-domains = <&bpm <<
1737 interconnects = <&mc <<
1738 <&mc <<
1739 interconnect-names = <<
1740 iommus = <&smmu TEGRA <<
1741 }; <<
1742 <<
1743 sor0: sor@15540000 { 1343 sor0: sor@15540000 {
1744 compatible = "nvidia, 1344 compatible = "nvidia,tegra186-sor";
1745 reg = <0x15540000 0x1 1345 reg = <0x15540000 0x10000>;
1746 interrupts = <GIC_SPI 1346 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1747 clocks = <&bpmp TEGRA 1347 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1748 <&bpmp TEGRA 1348 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1749 <&bpmp TEGRA 1349 <&bpmp TEGRA186_CLK_PLLD2>,
1750 <&bpmp TEGRA 1350 <&bpmp TEGRA186_CLK_PLLDP>,
1751 <&bpmp TEGRA 1351 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1752 <&bpmp TEGRA 1352 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1753 clock-names = "sor", 1353 clock-names = "sor", "out", "parent", "dp", "safe",
1754 "pad"; 1354 "pad";
1755 resets = <&bpmp TEGRA 1355 resets = <&bpmp TEGRA186_RESET_SOR0>;
1756 reset-names = "sor"; 1356 reset-names = "sor";
1757 pinctrl-0 = <&state_d 1357 pinctrl-0 = <&state_dpaux_aux>;
1758 pinctrl-1 = <&state_d 1358 pinctrl-1 = <&state_dpaux_i2c>;
1759 pinctrl-2 = <&state_d 1359 pinctrl-2 = <&state_dpaux_off>;
1760 pinctrl-names = "aux" 1360 pinctrl-names = "aux", "i2c", "off";
1761 status = "disabled"; 1361 status = "disabled";
1762 1362
1763 power-domains = <&bpm 1363 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1764 nvidia,interface = <0 1364 nvidia,interface = <0>;
1765 }; 1365 };
1766 1366
1767 sor1: sor@15580000 { 1367 sor1: sor@15580000 {
1768 compatible = "nvidia, 1368 compatible = "nvidia,tegra186-sor";
1769 reg = <0x15580000 0x1 1369 reg = <0x15580000 0x10000>;
1770 interrupts = <GIC_SPI 1370 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1771 clocks = <&bpmp TEGRA 1371 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1772 <&bpmp TEGRA 1372 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1773 <&bpmp TEGRA 1373 <&bpmp TEGRA186_CLK_PLLD3>,
1774 <&bpmp TEGRA 1374 <&bpmp TEGRA186_CLK_PLLDP>,
1775 <&bpmp TEGRA 1375 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1776 <&bpmp TEGRA 1376 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1777 clock-names = "sor", 1377 clock-names = "sor", "out", "parent", "dp", "safe",
1778 "pad"; 1378 "pad";
1779 resets = <&bpmp TEGRA 1379 resets = <&bpmp TEGRA186_RESET_SOR1>;
1780 reset-names = "sor"; 1380 reset-names = "sor";
1781 pinctrl-0 = <&state_d 1381 pinctrl-0 = <&state_dpaux1_aux>;
1782 pinctrl-1 = <&state_d 1382 pinctrl-1 = <&state_dpaux1_i2c>;
1783 pinctrl-2 = <&state_d 1383 pinctrl-2 = <&state_dpaux1_off>;
1784 pinctrl-names = "aux" 1384 pinctrl-names = "aux", "i2c", "off";
1785 status = "disabled"; 1385 status = "disabled";
1786 1386
1787 power-domains = <&bpm 1387 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1788 nvidia,interface = <1 1388 nvidia,interface = <1>;
1789 }; 1389 };
1790 1390
1791 dpaux: dpaux@155c0000 { 1391 dpaux: dpaux@155c0000 {
1792 compatible = "nvidia, 1392 compatible = "nvidia,tegra186-dpaux";
1793 reg = <0x155c0000 0x1 1393 reg = <0x155c0000 0x10000>;
1794 interrupts = <GIC_SPI 1394 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&bpmp TEGRA 1395 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1796 <&bpmp TEGRA 1396 <&bpmp TEGRA186_CLK_PLLDP>;
1797 clock-names = "dpaux" 1397 clock-names = "dpaux", "parent";
1798 resets = <&bpmp TEGRA 1398 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1799 reset-names = "dpaux" 1399 reset-names = "dpaux";
1800 status = "disabled"; 1400 status = "disabled";
1801 1401
1802 power-domains = <&bpm 1402 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1803 1403
1804 state_dpaux_aux: pinm 1404 state_dpaux_aux: pinmux-aux {
1805 groups = "dpa 1405 groups = "dpaux-io";
1806 function = "a 1406 function = "aux";
1807 }; 1407 };
1808 1408
1809 state_dpaux_i2c: pinm 1409 state_dpaux_i2c: pinmux-i2c {
1810 groups = "dpa 1410 groups = "dpaux-io";
1811 function = "i 1411 function = "i2c";
1812 }; 1412 };
1813 1413
1814 state_dpaux_off: pinm 1414 state_dpaux_off: pinmux-off {
1815 groups = "dpa 1415 groups = "dpaux-io";
1816 function = "o 1416 function = "off";
1817 }; 1417 };
1818 1418
1819 i2c-bus { 1419 i2c-bus {
1820 #address-cell 1420 #address-cells = <1>;
1821 #size-cells = 1421 #size-cells = <0>;
1822 }; 1422 };
1823 }; 1423 };
1824 1424
1825 padctl@15880000 { 1425 padctl@15880000 {
1826 compatible = "nvidia, 1426 compatible = "nvidia,tegra186-dsi-padctl";
1827 reg = <0x15880000 0x1 1427 reg = <0x15880000 0x10000>;
1828 resets = <&bpmp TEGRA 1428 resets = <&bpmp TEGRA186_RESET_DSI>;
1829 reset-names = "dsi"; 1429 reset-names = "dsi";
1830 status = "disabled"; 1430 status = "disabled";
1831 }; 1431 };
1832 1432
1833 dsic: dsi@15900000 { 1433 dsic: dsi@15900000 {
1834 compatible = "nvidia, 1434 compatible = "nvidia,tegra186-dsi";
1835 reg = <0x15900000 0x1 1435 reg = <0x15900000 0x10000>;
1836 interrupts = <GIC_SPI 1436 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&bpmp TEGRA 1437 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1838 <&bpmp TEGRA 1438 <&bpmp TEGRA186_CLK_DSIC_LP>,
1839 <&bpmp TEGRA 1439 <&bpmp TEGRA186_CLK_PLLD>;
1840 clock-names = "dsi", 1440 clock-names = "dsi", "lp", "parent";
1841 resets = <&bpmp TEGRA 1441 resets = <&bpmp TEGRA186_RESET_DSIC>;
1842 reset-names = "dsi"; 1442 reset-names = "dsi";
1843 status = "disabled"; 1443 status = "disabled";
1844 1444
1845 power-domains = <&bpm 1445 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1846 }; 1446 };
1847 1447
1848 dsid: dsi@15940000 { 1448 dsid: dsi@15940000 {
1849 compatible = "nvidia, 1449 compatible = "nvidia,tegra186-dsi";
1850 reg = <0x15940000 0x1 1450 reg = <0x15940000 0x10000>;
1851 interrupts = <GIC_SPI 1451 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&bpmp TEGRA 1452 clocks = <&bpmp TEGRA186_CLK_DSID>,
1853 <&bpmp TEGRA 1453 <&bpmp TEGRA186_CLK_DSID_LP>,
1854 <&bpmp TEGRA 1454 <&bpmp TEGRA186_CLK_PLLD>;
1855 clock-names = "dsi", 1455 clock-names = "dsi", "lp", "parent";
1856 resets = <&bpmp TEGRA 1456 resets = <&bpmp TEGRA186_RESET_DSID>;
1857 reset-names = "dsi"; 1457 reset-names = "dsi";
1858 status = "disabled"; 1458 status = "disabled";
1859 1459
1860 power-domains = <&bpm 1460 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1861 }; 1461 };
1862 }; 1462 };
1863 1463
1864 gpu@17000000 { 1464 gpu@17000000 {
1865 compatible = "nvidia,gp10b"; 1465 compatible = "nvidia,gp10b";
1866 reg = <0x0 0x17000000 0x0 0x1 1466 reg = <0x0 0x17000000 0x0 0x1000000>,
1867 <0x0 0x18000000 0x0 0x1 1467 <0x0 0x18000000 0x0 0x1000000>;
1868 interrupts = <GIC_SPI 70 IRQ_ 1468 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 71 IRQ_ 1469 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1870 interrupt-names = "stall", "n 1470 interrupt-names = "stall", "nonstall";
1871 1471
1872 clocks = <&bpmp TEGRA186_CLK_ 1472 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1873 <&bpmp TEGRA186_CLK_ 1473 <&bpmp TEGRA186_CLK_GPU>;
1874 clock-names = "gpu", "pwr"; 1474 clock-names = "gpu", "pwr";
1875 resets = <&bpmp TEGRA186_RESE 1475 resets = <&bpmp TEGRA186_RESET_GPU>;
1876 reset-names = "gpu"; 1476 reset-names = "gpu";
1877 status = "disabled"; 1477 status = "disabled";
1878 1478
1879 power-domains = <&bpmp TEGRA1 1479 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1880 interconnects = <&mc TEGRA186 1480 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1881 <&mc TEGRA186 1481 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1882 <&mc TEGRA186 1482 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1883 <&mc TEGRA186 1483 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1884 interconnect-names = "dma-mem 1484 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1885 }; 1485 };
1886 1486
1887 sram@30000000 { 1487 sram@30000000 {
1888 compatible = "nvidia,tegra186 1488 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1889 reg = <0x0 0x30000000 0x0 0x5 1489 reg = <0x0 0x30000000 0x0 0x50000>;
1890 #address-cells = <1>; 1490 #address-cells = <1>;
1891 #size-cells = <1>; 1491 #size-cells = <1>;
1892 ranges = <0x0 0x0 0x30000000 1492 ranges = <0x0 0x0 0x30000000 0x50000>;
1893 no-memory-wc; <<
1894 1493
1895 cpu_bpmp_tx: sram@4e000 { 1494 cpu_bpmp_tx: sram@4e000 {
1896 reg = <0x4e000 0x1000 1495 reg = <0x4e000 0x1000>;
1897 label = "cpu-bpmp-tx" 1496 label = "cpu-bpmp-tx";
1898 pool; 1497 pool;
1899 }; 1498 };
1900 1499
1901 cpu_bpmp_rx: sram@4f000 { 1500 cpu_bpmp_rx: sram@4f000 {
1902 reg = <0x4f000 0x1000 1501 reg = <0x4f000 0x1000>;
1903 label = "cpu-bpmp-rx" 1502 label = "cpu-bpmp-rx";
1904 pool; 1503 pool;
1905 }; 1504 };
1906 }; 1505 };
1907 1506
>> 1507 sata@3507000 {
>> 1508 compatible = "nvidia,tegra186-ahci";
>> 1509 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
>> 1510 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
>> 1511 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
>> 1512 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
>> 1513
>> 1514 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
>> 1515 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
>> 1516 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
>> 1517 interconnect-names = "dma-mem", "write";
>> 1518 iommus = <&smmu TEGRA186_SID_SATA>;
>> 1519
>> 1520 clocks = <&bpmp TEGRA186_CLK_SATA>,
>> 1521 <&bpmp TEGRA186_CLK_SATA_OOB>;
>> 1522 clock-names = "sata", "sata-oob";
>> 1523 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
>> 1524 <&bpmp TEGRA186_CLK_SATA_OOB>;
>> 1525 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
>> 1526 <&bpmp TEGRA186_CLK_PLLP>;
>> 1527 assigned-clock-rates = <102000000>,
>> 1528 <204000000>;
>> 1529 resets = <&bpmp TEGRA186_RESET_SATA>,
>> 1530 <&bpmp TEGRA186_RESET_SATACOLD>;
>> 1531 reset-names = "sata", "sata-cold";
>> 1532 status = "disabled";
>> 1533 };
>> 1534
1908 bpmp: bpmp { 1535 bpmp: bpmp {
1909 compatible = "nvidia,tegra186 1536 compatible = "nvidia,tegra186-bpmp";
1910 interconnects = <&mc TEGRA186 1537 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1911 <&mc TEGRA186 1538 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1912 <&mc TEGRA186 1539 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1913 <&mc TEGRA186 1540 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1914 interconnect-names = "read", 1541 interconnect-names = "read", "write", "dma-mem", "dma-write";
1915 iommus = <&smmu TEGRA186_SID_ 1542 iommus = <&smmu TEGRA186_SID_BPMP>;
1916 mboxes = <&hsp_top0 TEGRA_HSP 1543 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1917 TEGRA_HSP 1544 TEGRA_HSP_DB_MASTER_BPMP>;
1918 shmem = <&cpu_bpmp_tx>, <&cpu !! 1545 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1919 #clock-cells = <1>; 1546 #clock-cells = <1>;
1920 #reset-cells = <1>; 1547 #reset-cells = <1>;
1921 #power-domain-cells = <1>; 1548 #power-domain-cells = <1>;
1922 1549
1923 bpmp_i2c: i2c { 1550 bpmp_i2c: i2c {
1924 compatible = "nvidia, 1551 compatible = "nvidia,tegra186-bpmp-i2c";
1925 nvidia,bpmp-bus-id = 1552 nvidia,bpmp-bus-id = <5>;
1926 #address-cells = <1>; 1553 #address-cells = <1>;
1927 #size-cells = <0>; 1554 #size-cells = <0>;
1928 status = "disabled"; 1555 status = "disabled";
1929 }; 1556 };
1930 1557
1931 bpmp_thermal: thermal { 1558 bpmp_thermal: thermal {
1932 compatible = "nvidia, 1559 compatible = "nvidia,tegra186-bpmp-thermal";
1933 #thermal-sensor-cells 1560 #thermal-sensor-cells = <1>;
1934 }; 1561 };
1935 }; 1562 };
1936 1563
1937 cpus { 1564 cpus {
1938 #address-cells = <1>; 1565 #address-cells = <1>;
1939 #size-cells = <0>; 1566 #size-cells = <0>;
1940 1567
1941 denver_0: cpu@0 { 1568 denver_0: cpu@0 {
1942 compatible = "nvidia, 1569 compatible = "nvidia,tegra186-denver";
1943 device_type = "cpu"; 1570 device_type = "cpu";
1944 i-cache-size = <0x200 1571 i-cache-size = <0x20000>;
1945 i-cache-line-size = < 1572 i-cache-line-size = <64>;
1946 i-cache-sets = <512>; 1573 i-cache-sets = <512>;
1947 d-cache-size = <0x100 1574 d-cache-size = <0x10000>;
1948 d-cache-line-size = < 1575 d-cache-line-size = <64>;
1949 d-cache-sets = <256>; 1576 d-cache-sets = <256>;
1950 next-level-cache = <& 1577 next-level-cache = <&L2_DENVER>;
1951 reg = <0x000>; 1578 reg = <0x000>;
1952 }; 1579 };
1953 1580
1954 denver_1: cpu@1 { 1581 denver_1: cpu@1 {
1955 compatible = "nvidia, 1582 compatible = "nvidia,tegra186-denver";
1956 device_type = "cpu"; 1583 device_type = "cpu";
1957 i-cache-size = <0x200 1584 i-cache-size = <0x20000>;
1958 i-cache-line-size = < 1585 i-cache-line-size = <64>;
1959 i-cache-sets = <512>; 1586 i-cache-sets = <512>;
1960 d-cache-size = <0x100 1587 d-cache-size = <0x10000>;
1961 d-cache-line-size = < 1588 d-cache-line-size = <64>;
1962 d-cache-sets = <256>; 1589 d-cache-sets = <256>;
1963 next-level-cache = <& 1590 next-level-cache = <&L2_DENVER>;
1964 reg = <0x001>; 1591 reg = <0x001>;
1965 }; 1592 };
1966 1593
1967 ca57_0: cpu@2 { 1594 ca57_0: cpu@2 {
1968 compatible = "arm,cor 1595 compatible = "arm,cortex-a57";
1969 device_type = "cpu"; 1596 device_type = "cpu";
1970 i-cache-size = <0xC00 1597 i-cache-size = <0xC000>;
1971 i-cache-line-size = < 1598 i-cache-line-size = <64>;
1972 i-cache-sets = <256>; 1599 i-cache-sets = <256>;
1973 d-cache-size = <0x800 1600 d-cache-size = <0x8000>;
1974 d-cache-line-size = < 1601 d-cache-line-size = <64>;
1975 d-cache-sets = <256>; 1602 d-cache-sets = <256>;
1976 next-level-cache = <& 1603 next-level-cache = <&L2_A57>;
1977 reg = <0x100>; 1604 reg = <0x100>;
1978 }; 1605 };
1979 1606
1980 ca57_1: cpu@3 { 1607 ca57_1: cpu@3 {
1981 compatible = "arm,cor 1608 compatible = "arm,cortex-a57";
1982 device_type = "cpu"; 1609 device_type = "cpu";
1983 i-cache-size = <0xC00 1610 i-cache-size = <0xC000>;
1984 i-cache-line-size = < 1611 i-cache-line-size = <64>;
1985 i-cache-sets = <256>; 1612 i-cache-sets = <256>;
1986 d-cache-size = <0x800 1613 d-cache-size = <0x8000>;
1987 d-cache-line-size = < 1614 d-cache-line-size = <64>;
1988 d-cache-sets = <256>; 1615 d-cache-sets = <256>;
1989 next-level-cache = <& 1616 next-level-cache = <&L2_A57>;
1990 reg = <0x101>; 1617 reg = <0x101>;
1991 }; 1618 };
1992 1619
1993 ca57_2: cpu@4 { 1620 ca57_2: cpu@4 {
1994 compatible = "arm,cor 1621 compatible = "arm,cortex-a57";
1995 device_type = "cpu"; 1622 device_type = "cpu";
1996 i-cache-size = <0xC00 1623 i-cache-size = <0xC000>;
1997 i-cache-line-size = < 1624 i-cache-line-size = <64>;
1998 i-cache-sets = <256>; 1625 i-cache-sets = <256>;
1999 d-cache-size = <0x800 1626 d-cache-size = <0x8000>;
2000 d-cache-line-size = < 1627 d-cache-line-size = <64>;
2001 d-cache-sets = <256>; 1628 d-cache-sets = <256>;
2002 next-level-cache = <& 1629 next-level-cache = <&L2_A57>;
2003 reg = <0x102>; 1630 reg = <0x102>;
2004 }; 1631 };
2005 1632
2006 ca57_3: cpu@5 { 1633 ca57_3: cpu@5 {
2007 compatible = "arm,cor 1634 compatible = "arm,cortex-a57";
2008 device_type = "cpu"; 1635 device_type = "cpu";
2009 i-cache-size = <0xC00 1636 i-cache-size = <0xC000>;
2010 i-cache-line-size = < 1637 i-cache-line-size = <64>;
2011 i-cache-sets = <256>; 1638 i-cache-sets = <256>;
2012 d-cache-size = <0x800 1639 d-cache-size = <0x8000>;
2013 d-cache-line-size = < 1640 d-cache-line-size = <64>;
2014 d-cache-sets = <256>; 1641 d-cache-sets = <256>;
2015 next-level-cache = <& 1642 next-level-cache = <&L2_A57>;
2016 reg = <0x103>; 1643 reg = <0x103>;
2017 }; 1644 };
2018 1645
2019 L2_DENVER: l2-cache0 { 1646 L2_DENVER: l2-cache0 {
2020 compatible = "cache"; 1647 compatible = "cache";
2021 cache-unified; 1648 cache-unified;
2022 cache-level = <2>; 1649 cache-level = <2>;
2023 cache-size = <0x20000 1650 cache-size = <0x200000>;
2024 cache-line-size = <64 1651 cache-line-size = <64>;
2025 cache-sets = <2048>; 1652 cache-sets = <2048>;
2026 }; 1653 };
2027 1654
2028 L2_A57: l2-cache1 { 1655 L2_A57: l2-cache1 {
2029 compatible = "cache"; 1656 compatible = "cache";
2030 cache-unified; 1657 cache-unified;
2031 cache-level = <2>; 1658 cache-level = <2>;
2032 cache-size = <0x20000 1659 cache-size = <0x200000>;
2033 cache-line-size = <64 1660 cache-line-size = <64>;
2034 cache-sets = <2048>; 1661 cache-sets = <2048>;
2035 }; 1662 };
2036 }; 1663 };
2037 1664
2038 pmu-a57 { !! 1665 pmu_denver {
2039 compatible = "arm,cortex-a57- !! 1666 compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
>> 1667 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>> 1668 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
>> 1669 interrupt-affinity = <&denver_0 &denver_1>;
>> 1670 };
>> 1671
>> 1672 pmu_a57 {
>> 1673 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
2040 interrupts = <GIC_SPI 296 IRQ 1674 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 297 IRQ 1675 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 298 IRQ 1676 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 299 IRQ 1677 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2044 interrupt-affinity = <&ca57_0 1678 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2045 }; 1679 };
2046 1680
2047 pmu-denver { <<
2048 compatible = "nvidia,denver-p <<
2049 interrupts = <GIC_SPI 320 IRQ <<
2050 <GIC_SPI 321 IRQ <<
2051 interrupt-affinity = <&denver <<
2052 }; <<
2053 <<
2054 sound { 1681 sound {
2055 status = "disabled"; 1682 status = "disabled";
2056 1683
2057 clocks = <&bpmp TEGRA186_CLK_ 1684 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2058 <&bpmp TEGRA186_CLK_ 1685 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2059 clock-names = "pll_a", "plla_ 1686 clock-names = "pll_a", "plla_out0";
2060 assigned-clocks = <&bpmp TEGR 1687 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2061 <&bpmp TEGR 1688 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2062 <&bpmp TEGR 1689 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2063 assigned-clock-parents = <0>, 1690 assigned-clock-parents = <0>,
2064 <&bp 1691 <&bpmp TEGRA186_CLK_PLLA>,
2065 <&bp 1692 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2066 /* 1693 /*
2067 * PLLA supports dynamic ramp 1694 * PLLA supports dynamic ramp. Below initial rate is chosen
2068 * for this to work and oscil 1695 * for this to work and oscillate between base rates required
2069 * for 8x and 11.025x sample 1696 * for 8x and 11.025x sample rate streams.
2070 */ 1697 */
2071 assigned-clock-rates = <25800 1698 assigned-clock-rates = <258000000>;
2072 1699
2073 iommus = <&smmu TEGRA186_SID_ 1700 iommus = <&smmu TEGRA186_SID_APE>;
2074 }; 1701 };
2075 1702
2076 thermal-zones { 1703 thermal-zones {
2077 /* Cortex-A57 cluster */ !! 1704 a57 {
2078 cpu-thermal { <<
2079 polling-delay = <0>; 1705 polling-delay = <0>;
2080 polling-delay-passive 1706 polling-delay-passive = <1000>;
2081 1707
2082 thermal-sensors = <&b !! 1708 thermal-sensors =
>> 1709 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2083 1710
2084 trips { 1711 trips {
2085 critical { 1712 critical {
2086 tempe 1713 temperature = <101000>;
2087 hyste 1714 hysteresis = <0>;
2088 type 1715 type = "critical";
2089 }; 1716 };
2090 }; 1717 };
2091 1718
2092 cooling-maps { 1719 cooling-maps {
2093 }; 1720 };
2094 }; 1721 };
2095 1722
2096 /* Denver cluster */ !! 1723 denver {
2097 aux-thermal { <<
2098 polling-delay = <0>; 1724 polling-delay = <0>;
2099 polling-delay-passive 1725 polling-delay-passive = <1000>;
2100 1726
2101 thermal-sensors = <&b !! 1727 thermal-sensors =
>> 1728 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2102 1729
2103 trips { 1730 trips {
2104 critical { 1731 critical {
2105 tempe 1732 temperature = <101000>;
2106 hyste 1733 hysteresis = <0>;
2107 type 1734 type = "critical";
2108 }; 1735 };
2109 }; 1736 };
2110 1737
2111 cooling-maps { 1738 cooling-maps {
2112 }; 1739 };
2113 }; 1740 };
2114 1741
2115 gpu-thermal { !! 1742 gpu {
2116 polling-delay = <0>; 1743 polling-delay = <0>;
2117 polling-delay-passive 1744 polling-delay-passive = <1000>;
2118 1745
2119 thermal-sensors = <&b !! 1746 thermal-sensors =
>> 1747 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2120 1748
2121 trips { 1749 trips {
2122 critical { 1750 critical {
2123 tempe 1751 temperature = <101000>;
2124 hyste 1752 hysteresis = <0>;
2125 type 1753 type = "critical";
2126 }; 1754 };
2127 }; 1755 };
2128 1756
2129 cooling-maps { 1757 cooling-maps {
2130 }; 1758 };
2131 }; 1759 };
2132 1760
2133 pll-thermal { !! 1761 pll {
2134 polling-delay = <0>; 1762 polling-delay = <0>;
2135 polling-delay-passive 1763 polling-delay-passive = <1000>;
2136 1764
2137 thermal-sensors = <&b !! 1765 thermal-sensors =
>> 1766 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2138 1767
2139 trips { 1768 trips {
2140 critical { 1769 critical {
2141 tempe 1770 temperature = <101000>;
2142 hyste 1771 hysteresis = <0>;
2143 type 1772 type = "critical";
2144 }; 1773 };
2145 }; 1774 };
2146 1775
2147 cooling-maps { 1776 cooling-maps {
2148 }; 1777 };
2149 }; 1778 };
2150 1779
2151 ao-thermal { !! 1780 always_on {
2152 polling-delay = <0>; 1781 polling-delay = <0>;
2153 polling-delay-passive 1782 polling-delay-passive = <1000>;
2154 1783
2155 thermal-sensors = <&b !! 1784 thermal-sensors =
>> 1785 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2156 1786
2157 trips { 1787 trips {
2158 critical { 1788 critical {
2159 tempe 1789 temperature = <101000>;
2160 hyste 1790 hysteresis = <0>;
2161 type 1791 type = "critical";
2162 }; 1792 };
2163 }; 1793 };
2164 1794
2165 cooling-maps { 1795 cooling-maps {
2166 }; 1796 };
2167 }; 1797 };
2168 }; 1798 };
2169 1799
2170 timer { 1800 timer {
2171 compatible = "arm,armv8-timer 1801 compatible = "arm,armv8-timer";
2172 interrupts = <GIC_PPI 13 1802 interrupts = <GIC_PPI 13
2173 (GIC_CPU_MASK 1803 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2174 <GIC_PPI 14 1804 <GIC_PPI 14
2175 (GIC_CPU_MASK 1805 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2176 <GIC_PPI 11 1806 <GIC_PPI 11
2177 (GIC_CPU_MASK 1807 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2178 <GIC_PPI 10 1808 <GIC_PPI 10
2179 (GIC_CPU_MASK 1809 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2180 interrupt-parent = <&gic>; 1810 interrupt-parent = <&gic>;
2181 always-on; 1811 always-on;
2182 }; 1812 };
2183 }; 1813 };
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