1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h> 2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h> 3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h> 6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io 7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate 8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h> 9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-th 10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11 11
12 / { 12 / {
13 compatible = "nvidia,tegra186"; 13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 misc@100000 { 18 misc@100000 {
19 compatible = "nvidia,tegra186- 19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf0 20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x10 21 <0x0 0x0010f000 0x0 0x1000>;
22 }; 22 };
23 23
24 gpio: gpio@2200000 { 24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186- 25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio" 26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x100 27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x100 28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_ 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_ 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_ 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_ 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_ 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_ 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>; 35 #interrupt-cells = <2>;
36 interrupt-controller; 36 interrupt-controller;
37 #gpio-cells = <2>; 37 #gpio-cells = <2>;
38 gpio-controller; 38 gpio-controller;
39 }; 39 };
40 40
41 ethernet@2490000 { 41 ethernet@2490000 {
42 compatible = "nvidia,tegra186- 42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-eth 43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10 44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_ 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_A 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_E 56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_E 57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_E 58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_E 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "s 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET 61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos"; 62 reset-names = "eqos";
63 interconnects = <&mc TEGRA186_ <<
64 <&mc TEGRA186_ <<
65 interconnect-names = "dma-mem" <<
66 iommus = <&smmu TEGRA186_SID_E 63 iommus = <&smmu TEGRA186_SID_EQOS>;
67 status = "disabled"; 64 status = "disabled";
68 65
69 snps,write-requests = <1>; 66 snps,write-requests = <1>;
70 snps,read-requests = <3>; 67 snps,read-requests = <3>;
71 snps,burst-map = <0x7>; 68 snps,burst-map = <0x7>;
72 snps,txpbl = <32>; 69 snps,txpbl = <32>;
73 snps,rxpbl = <8>; 70 snps,rxpbl = <8>;
74 }; 71 };
75 72
76 gpcdma: dma-controller@2600000 { !! 73 aconnect {
77 compatible = "nvidia,tegra186- <<
78 reg = <0x0 0x2600000 0x0 0x210 <<
79 resets = <&bpmp TEGRA186_RESET <<
80 reset-names = "gpcdma"; <<
81 interrupts = <GIC_SPI 75 IRQ_T <<
82 <GIC_SPI 76 IRQ_T <<
83 <GIC_SPI 77 IRQ_T <<
84 <GIC_SPI 78 IRQ_T <<
85 <GIC_SPI 79 IRQ_T <<
86 <GIC_SPI 80 IRQ_T <<
87 <GIC_SPI 81 IRQ_T <<
88 <GIC_SPI 82 IRQ_T <<
89 <GIC_SPI 83 IRQ_T <<
90 <GIC_SPI 84 IRQ_T <<
91 <GIC_SPI 85 IRQ_T <<
92 <GIC_SPI 86 IRQ_T <<
93 <GIC_SPI 87 IRQ_T <<
94 <GIC_SPI 88 IRQ_T <<
95 <GIC_SPI 89 IRQ_T <<
96 <GIC_SPI 90 IRQ_T <<
97 <GIC_SPI 91 IRQ_T <<
98 <GIC_SPI 92 IRQ_T <<
99 <GIC_SPI 93 IRQ_T <<
100 <GIC_SPI 94 IRQ_T <<
101 <GIC_SPI 95 IRQ_T <<
102 <GIC_SPI 96 IRQ_T <<
103 <GIC_SPI 97 IRQ_T <<
104 <GIC_SPI 98 IRQ_T <<
105 <GIC_SPI 99 IRQ_T <<
106 <GIC_SPI 100 IRQ_ <<
107 <GIC_SPI 101 IRQ_ <<
108 <GIC_SPI 102 IRQ_ <<
109 <GIC_SPI 103 IRQ_ <<
110 <GIC_SPI 104 IRQ_ <<
111 <GIC_SPI 105 IRQ_ <<
112 <GIC_SPI 106 IRQ_ <<
113 #dma-cells = <1>; <<
114 iommus = <&smmu TEGRA186_SID_G <<
115 dma-coherent; <<
116 dma-channel-mask = <0xfffffffe <<
117 status = "okay"; <<
118 }; <<
119 <<
120 aconnect@2900000 { <<
121 compatible = "nvidia,tegra186- 74 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210- 75 "nvidia,tegra210-aconnect";
123 clocks = <&bpmp TEGRA186_CLK_A 76 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_A 77 <&bpmp TEGRA186_CLK_APB2APE>;
125 clock-names = "ape", "apb2ape" 78 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA18 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>; 80 #address-cells = <1>;
128 #size-cells = <1>; 81 #size-cells = <1>;
129 ranges = <0x02900000 0x0 0x029 82 ranges = <0x02900000 0x0 0x02900000 0x200000>;
130 status = "disabled"; 83 status = "disabled";
131 84
132 tegra_ahub: ahub@2900800 { !! 85 dma-controller@2930000 {
133 compatible = "nvidia,t <<
134 reg = <0x02900800 0x80 <<
135 clocks = <&bpmp TEGRA1 <<
136 clock-names = "ahub"; <<
137 assigned-clocks = <&bp <<
138 assigned-clock-parents <<
139 assigned-clock-rates = <<
140 #address-cells = <1>; <<
141 #size-cells = <1>; <<
142 ranges = <0x02900800 0 <<
143 status = "disabled"; <<
144 <<
145 tegra_i2s1: i2s@290100 <<
146 compatible = " <<
147 " <<
148 reg = <0x29010 <<
149 clocks = <&bpm <<
150 <&bpm <<
151 clock-names = <<
152 assigned-clock <<
153 assigned-clock <<
154 assigned-clock <<
155 sound-name-pre <<
156 status = "disa <<
157 }; <<
158 <<
159 tegra_i2s2: i2s@290110 <<
160 compatible = " <<
161 " <<
162 reg = <0x29011 <<
163 clocks = <&bpm <<
164 <&bpm <<
165 clock-names = <<
166 assigned-clock <<
167 assigned-clock <<
168 assigned-clock <<
169 sound-name-pre <<
170 status = "disa <<
171 }; <<
172 <<
173 tegra_i2s3: i2s@290120 <<
174 compatible = " <<
175 " <<
176 reg = <0x29012 <<
177 clocks = <&bpm <<
178 <&bpm <<
179 clock-names = <<
180 assigned-clock <<
181 assigned-clock <<
182 assigned-clock <<
183 sound-name-pre <<
184 status = "disa <<
185 }; <<
186 <<
187 tegra_i2s4: i2s@290130 <<
188 compatible = " <<
189 " <<
190 reg = <0x29013 <<
191 clocks = <&bpm <<
192 <&bpm <<
193 clock-names = <<
194 assigned-clock <<
195 assigned-clock <<
196 assigned-clock <<
197 sound-name-pre <<
198 status = "disa <<
199 }; <<
200 <<
201 tegra_i2s5: i2s@290140 <<
202 compatible = " <<
203 " <<
204 reg = <0x29014 <<
205 clocks = <&bpm <<
206 <&bpm <<
207 clock-names = <<
208 assigned-clock <<
209 assigned-clock <<
210 assigned-clock <<
211 sound-name-pre <<
212 status = "disa <<
213 }; <<
214 <<
215 tegra_i2s6: i2s@290150 <<
216 compatible = " <<
217 " <<
218 reg = <0x29015 <<
219 clocks = <&bpm <<
220 <&bpm <<
221 clock-names = <<
222 assigned-clock <<
223 assigned-clock <<
224 assigned-clock <<
225 sound-name-pre <<
226 status = "disa <<
227 }; <<
228 <<
229 tegra_sfc1: sfc@290200 <<
230 compatible = " <<
231 " <<
232 reg = <0x29020 <<
233 sound-name-pre <<
234 status = "disa <<
235 }; <<
236 <<
237 tegra_sfc2: sfc@290220 <<
238 compatible = " <<
239 " <<
240 reg = <0x29022 <<
241 sound-name-pre <<
242 status = "disa <<
243 }; <<
244 <<
245 tegra_sfc3: sfc@290240 <<
246 compatible = " <<
247 " <<
248 reg = <0x29024 <<
249 sound-name-pre <<
250 status = "disa <<
251 }; <<
252 <<
253 tegra_sfc4: sfc@290260 <<
254 compatible = " <<
255 " <<
256 reg = <0x29026 <<
257 sound-name-pre <<
258 status = "disa <<
259 }; <<
260 <<
261 tegra_amx1: amx@290300 <<
262 compatible = " <<
263 " <<
264 reg = <0x29030 <<
265 sound-name-pre <<
266 status = "disa <<
267 }; <<
268 <<
269 tegra_amx2: amx@290310 <<
270 compatible = " <<
271 " <<
272 reg = <0x29031 <<
273 sound-name-pre <<
274 status = "disa <<
275 }; <<
276 <<
277 tegra_amx3: amx@290320 <<
278 compatible = " <<
279 " <<
280 reg = <0x29032 <<
281 sound-name-pre <<
282 status = "disa <<
283 }; <<
284 <<
285 tegra_amx4: amx@290330 <<
286 compatible = " <<
287 " <<
288 reg = <0x29033 <<
289 sound-name-pre <<
290 status = "disa <<
291 }; <<
292 <<
293 tegra_adx1: adx@290380 <<
294 compatible = " <<
295 " <<
296 reg = <0x29038 <<
297 sound-name-pre <<
298 status = "disa <<
299 }; <<
300 <<
301 tegra_adx2: adx@290390 <<
302 compatible = " <<
303 " <<
304 reg = <0x29039 <<
305 sound-name-pre <<
306 status = "disa <<
307 }; <<
308 <<
309 tegra_adx3: adx@2903a0 <<
310 compatible = " <<
311 " <<
312 reg = <0x2903a <<
313 sound-name-pre <<
314 status = "disa <<
315 }; <<
316 <<
317 tegra_adx4: adx@2903b0 <<
318 compatible = " <<
319 " <<
320 reg = <0x2903b <<
321 sound-name-pre <<
322 status = "disa <<
323 }; <<
324 <<
325 tegra_dmic1: dmic@2904 <<
326 compatible = " <<
327 reg = <0x29040 <<
328 clocks = <&bpm <<
329 clock-names = <<
330 assigned-clock <<
331 assigned-clock <<
332 assigned-clock <<
333 sound-name-pre <<
334 status = "disa <<
335 }; <<
336 <<
337 tegra_dmic2: dmic@2904 <<
338 compatible = " <<
339 reg = <0x29041 <<
340 clocks = <&bpm <<
341 clock-names = <<
342 assigned-clock <<
343 assigned-clock <<
344 assigned-clock <<
345 sound-name-pre <<
346 status = "disa <<
347 }; <<
348 <<
349 tegra_dmic3: dmic@2904 <<
350 compatible = " <<
351 reg = <0x29042 <<
352 clocks = <&bpm <<
353 clock-names = <<
354 assigned-clock <<
355 assigned-clock <<
356 assigned-clock <<
357 sound-name-pre <<
358 status = "disa <<
359 }; <<
360 <<
361 tegra_dmic4: dmic@2904 <<
362 compatible = " <<
363 reg = <0x29043 <<
364 clocks = <&bpm <<
365 clock-names = <<
366 assigned-clock <<
367 assigned-clock <<
368 assigned-clock <<
369 sound-name-pre <<
370 status = "disa <<
371 }; <<
372 <<
373 tegra_dspk1: dspk@2905 <<
374 compatible = " <<
375 reg = <0x29050 <<
376 clocks = <&bpm <<
377 clock-names = <<
378 assigned-clock <<
379 assigned-clock <<
380 assigned-clock <<
381 sound-name-pre <<
382 status = "disa <<
383 }; <<
384 <<
385 tegra_dspk2: dspk@2905 <<
386 compatible = " <<
387 reg = <0x29051 <<
388 clocks = <&bpm <<
389 clock-names = <<
390 assigned-clock <<
391 assigned-clock <<
392 assigned-clock <<
393 sound-name-pre <<
394 status = "disa <<
395 }; <<
396 <<
397 tegra_ope1: processing <<
398 compatible = " <<
399 " <<
400 reg = <0x29080 <<
401 #address-cells <<
402 #size-cells = <<
403 ranges; <<
404 sound-name-pre <<
405 status = "disa <<
406 <<
407 equalizer@2908 <<
408 compat <<
409 <<
410 reg = <<
411 }; <<
412 <<
413 dynamic-range- <<
414 compat <<
415 <<
416 reg = <<
417 }; <<
418 }; <<
419 <<
420 tegra_mvc1: mvc@290a00 <<
421 compatible = " <<
422 " <<
423 reg = <0x290a0 <<
424 sound-name-pre <<
425 status = "disa <<
426 }; <<
427 <<
428 tegra_mvc2: mvc@290a20 <<
429 compatible = " <<
430 " <<
431 reg = <0x290a2 <<
432 sound-name-pre <<
433 status = "disa <<
434 }; <<
435 <<
436 tegra_amixer: amixer@2 <<
437 compatible = " <<
438 " <<
439 reg = <0x290bb <<
440 sound-name-pre <<
441 status = "disa <<
442 }; <<
443 <<
444 tegra_admaif: admaif@2 <<
445 compatible = " <<
446 reg = <0x0290f <<
447 dmas = <&adma <<
448 <&adma <<
449 <&adma <<
450 <&adma <<
451 <&adma <<
452 <&adma <<
453 <&adma <<
454 <&adma <<
455 <&adma <<
456 <&adma <<
457 <&adma <<
458 <&adma <<
459 <&adma <<
460 <&adma <<
461 <&adma <<
462 <&adma <<
463 <&adma <<
464 <&adma <<
465 <&adma <<
466 <&adma <<
467 dma-names = "r <<
468 "r <<
469 "r <<
470 "r <<
471 "r <<
472 "r <<
473 "r <<
474 "r <<
475 "r <<
476 "r <<
477 "r <<
478 "r <<
479 "r <<
480 "r <<
481 "r <<
482 "r <<
483 "r <<
484 "r <<
485 "r <<
486 "r <<
487 status = "disa <<
488 }; <<
489 <<
490 tegra_asrc: asrc@29100 <<
491 compatible = " <<
492 reg = <0x29100 <<
493 sound-name-pre <<
494 status = "disa <<
495 }; <<
496 }; <<
497 <<
498 adma: dma-controller@2930000 { <<
499 compatible = "nvidia,t 86 compatible = "nvidia,tegra186-adma";
500 reg = <0x02930000 0x20 87 reg = <0x02930000 0x20000>;
501 interrupt-parent = <&a 88 interrupt-parent = <&agic>;
502 interrupts = <GIC_SPI 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
534 #dma-cells = <1>; 121 #dma-cells = <1>;
535 clocks = <&bpmp TEGRA1 122 clocks = <&bpmp TEGRA186_CLK_AHUB>;
536 clock-names = "d_audio 123 clock-names = "d_audio";
537 status = "disabled"; 124 status = "disabled";
538 }; 125 };
539 126
540 agic: interrupt-controller@2a4 127 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,t 128 compatible = "nvidia,tegra186-agic",
542 "nvidia,t 129 "nvidia,tegra210-agic";
543 #interrupt-cells = <3> 130 #interrupt-cells = <3>;
544 interrupt-controller; 131 interrupt-controller;
545 reg = <0x02a41000 0x10 132 reg = <0x02a41000 0x1000>,
546 <0x02a42000 0x20 133 <0x02a42000 0x2000>;
547 interrupts = <GIC_SPI 134 interrupts = <GIC_SPI 145
548 (GIC_CPU_MASK_ 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
549 clocks = <&bpmp TEGRA1 136 clocks = <&bpmp TEGRA186_CLK_APE>;
550 clock-names = "clk"; 137 clock-names = "clk";
551 status = "disabled"; 138 status = "disabled";
552 }; 139 };
553 }; 140 };
554 141
555 mc: memory-controller@2c00000 { !! 142 memory-controller@2c00000 {
556 compatible = "nvidia,tegra186- 143 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10 !! 144 reg = <0x0 0x02c00000 0x0 0xb0000>;
558 <0x0 0x02c10000 0x0 0x10 <<
559 <0x0 0x02c20000 0x0 0x10 <<
560 <0x0 0x02c30000 0x0 0x10 <<
561 <0x0 0x02c40000 0x0 0x10 <<
562 <0x0 0x02c50000 0x0 0x10 <<
563 reg-names = "sid", "broadcast" <<
564 interrupts = <GIC_SPI 223 IRQ_ <<
565 status = "disabled"; 145 status = "disabled";
566 <<
567 #interconnect-cells = <1>; <<
568 #address-cells = <2>; <<
569 #size-cells = <2>; <<
570 <<
571 ranges = <0x0 0x02c00000 0x0 0 <<
572 <<
573 /* <<
574 * Memory clients have access <<
575 * controller can address. <<
576 */ <<
577 dma-ranges = <0x0 0x0 0x0 0x0 <<
578 <<
579 emc: external-memory-controlle <<
580 compatible = "nvidia,t <<
581 reg = <0x0 0x02c60000 <<
582 interrupts = <GIC_SPI <<
583 clocks = <&bpmp TEGRA1 <<
584 clock-names = "emc"; <<
585 <<
586 #interconnect-cells = <<
587 <<
588 nvidia,bpmp = <&bpmp>; <<
589 }; <<
590 }; <<
591 <<
592 timer@3010000 { <<
593 compatible = "nvidia,tegra186- <<
594 reg = <0x0 0x03010000 0x0 0x00 <<
595 interrupts = <GIC_SPI 0 IRQ_TY <<
596 <GIC_SPI 1 IRQ_TY <<
597 <GIC_SPI 2 IRQ_TY <<
598 <GIC_SPI 3 IRQ_TY <<
599 <GIC_SPI 4 IRQ_TY <<
600 <GIC_SPI 5 IRQ_TY <<
601 <GIC_SPI 6 IRQ_TY <<
602 <GIC_SPI 7 IRQ_TY <<
603 <GIC_SPI 8 IRQ_TY <<
604 <GIC_SPI 9 IRQ_TY <<
605 status = "okay"; <<
606 }; 146 };
607 147
608 uarta: serial@3100000 { 148 uarta: serial@3100000 {
609 compatible = "nvidia,tegra186- 149 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
610 reg = <0x0 0x03100000 0x0 0x40 150 reg = <0x0 0x03100000 0x0 0x40>;
611 reg-shift = <2>; 151 reg-shift = <2>;
612 interrupts = <GIC_SPI 112 IRQ_ 152 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&bpmp TEGRA186_CLK_U 153 clocks = <&bpmp TEGRA186_CLK_UARTA>;
>> 154 clock-names = "serial";
614 resets = <&bpmp TEGRA186_RESET 155 resets = <&bpmp TEGRA186_RESET_UARTA>;
>> 156 reset-names = "serial";
615 status = "disabled"; 157 status = "disabled";
616 }; 158 };
617 159
618 uartb: serial@3110000 { 160 uartb: serial@3110000 {
619 compatible = "nvidia,tegra186- 161 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620 reg = <0x0 0x03110000 0x0 0x40 162 reg = <0x0 0x03110000 0x0 0x40>;
621 reg-shift = <2>; 163 reg-shift = <2>;
622 interrupts = <GIC_SPI 113 IRQ_ 164 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&bpmp TEGRA186_CLK_U 165 clocks = <&bpmp TEGRA186_CLK_UARTB>;
624 clock-names = "serial"; 166 clock-names = "serial";
625 resets = <&bpmp TEGRA186_RESET 167 resets = <&bpmp TEGRA186_RESET_UARTB>;
626 reset-names = "serial"; 168 reset-names = "serial";
627 status = "disabled"; 169 status = "disabled";
628 }; 170 };
629 171
630 uartd: serial@3130000 { 172 uartd: serial@3130000 {
631 compatible = "nvidia,tegra186- 173 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632 reg = <0x0 0x03130000 0x0 0x40 174 reg = <0x0 0x03130000 0x0 0x40>;
633 reg-shift = <2>; 175 reg-shift = <2>;
634 interrupts = <GIC_SPI 115 IRQ_ 176 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&bpmp TEGRA186_CLK_U 177 clocks = <&bpmp TEGRA186_CLK_UARTD>;
636 clock-names = "serial"; 178 clock-names = "serial";
637 resets = <&bpmp TEGRA186_RESET 179 resets = <&bpmp TEGRA186_RESET_UARTD>;
638 reset-names = "serial"; 180 reset-names = "serial";
639 status = "disabled"; 181 status = "disabled";
640 }; 182 };
641 183
642 uarte: serial@3140000 { 184 uarte: serial@3140000 {
643 compatible = "nvidia,tegra186- 185 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
644 reg = <0x0 0x03140000 0x0 0x40 186 reg = <0x0 0x03140000 0x0 0x40>;
645 reg-shift = <2>; 187 reg-shift = <2>;
646 interrupts = <GIC_SPI 116 IRQ_ 188 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&bpmp TEGRA186_CLK_U 189 clocks = <&bpmp TEGRA186_CLK_UARTE>;
648 clock-names = "serial"; 190 clock-names = "serial";
649 resets = <&bpmp TEGRA186_RESET 191 resets = <&bpmp TEGRA186_RESET_UARTE>;
650 reset-names = "serial"; 192 reset-names = "serial";
651 status = "disabled"; 193 status = "disabled";
652 }; 194 };
653 195
654 uartf: serial@3150000 { 196 uartf: serial@3150000 {
655 compatible = "nvidia,tegra186- 197 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
656 reg = <0x0 0x03150000 0x0 0x40 198 reg = <0x0 0x03150000 0x0 0x40>;
657 reg-shift = <2>; 199 reg-shift = <2>;
658 interrupts = <GIC_SPI 117 IRQ_ 200 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&bpmp TEGRA186_CLK_U 201 clocks = <&bpmp TEGRA186_CLK_UARTF>;
660 clock-names = "serial"; 202 clock-names = "serial";
661 resets = <&bpmp TEGRA186_RESET 203 resets = <&bpmp TEGRA186_RESET_UARTF>;
662 reset-names = "serial"; 204 reset-names = "serial";
663 status = "disabled"; 205 status = "disabled";
664 }; 206 };
665 207
666 gen1_i2c: i2c@3160000 { 208 gen1_i2c: i2c@3160000 {
667 compatible = "nvidia,tegra186- !! 209 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
668 reg = <0x0 0x03160000 0x0 0x10 210 reg = <0x0 0x03160000 0x0 0x10000>;
669 interrupts = <GIC_SPI 25 IRQ_T 211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>; 212 #address-cells = <1>;
671 #size-cells = <0>; 213 #size-cells = <0>;
672 clocks = <&bpmp TEGRA186_CLK_I 214 clocks = <&bpmp TEGRA186_CLK_I2C1>;
673 clock-names = "div-clk"; 215 clock-names = "div-clk";
674 resets = <&bpmp TEGRA186_RESET 216 resets = <&bpmp TEGRA186_RESET_I2C1>;
675 reset-names = "i2c"; 217 reset-names = "i2c";
676 dmas = <&gpcdma 21>, <&gpcdma <<
677 dma-names = "rx", "tx"; <<
678 status = "disabled"; 218 status = "disabled";
679 }; 219 };
680 220
681 cam_i2c: i2c@3180000 { 221 cam_i2c: i2c@3180000 {
682 compatible = "nvidia,tegra186- !! 222 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
683 reg = <0x0 0x03180000 0x0 0x10 223 reg = <0x0 0x03180000 0x0 0x10000>;
684 interrupts = <GIC_SPI 27 IRQ_T 224 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>; 225 #address-cells = <1>;
686 #size-cells = <0>; 226 #size-cells = <0>;
687 clocks = <&bpmp TEGRA186_CLK_I 227 clocks = <&bpmp TEGRA186_CLK_I2C3>;
688 clock-names = "div-clk"; 228 clock-names = "div-clk";
689 resets = <&bpmp TEGRA186_RESET 229 resets = <&bpmp TEGRA186_RESET_I2C3>;
690 reset-names = "i2c"; 230 reset-names = "i2c";
691 dmas = <&gpcdma 23>, <&gpcdma <<
692 dma-names = "rx", "tx"; <<
693 status = "disabled"; 231 status = "disabled";
694 }; 232 };
695 233
696 /* shares pads with dpaux1 */ 234 /* shares pads with dpaux1 */
697 dp_aux_ch1_i2c: i2c@3190000 { 235 dp_aux_ch1_i2c: i2c@3190000 {
698 compatible = "nvidia,tegra186- !! 236 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
699 reg = <0x0 0x03190000 0x0 0x10 237 reg = <0x0 0x03190000 0x0 0x10000>;
700 interrupts = <GIC_SPI 28 IRQ_T 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>; 239 #address-cells = <1>;
702 #size-cells = <0>; 240 #size-cells = <0>;
703 clocks = <&bpmp TEGRA186_CLK_I 241 clocks = <&bpmp TEGRA186_CLK_I2C4>;
704 clock-names = "div-clk"; 242 clock-names = "div-clk";
705 resets = <&bpmp TEGRA186_RESET 243 resets = <&bpmp TEGRA186_RESET_I2C4>;
706 reset-names = "i2c"; 244 reset-names = "i2c";
707 pinctrl-names = "default", "id 245 pinctrl-names = "default", "idle";
708 pinctrl-0 = <&state_dpaux1_i2c 246 pinctrl-0 = <&state_dpaux1_i2c>;
709 pinctrl-1 = <&state_dpaux1_off 247 pinctrl-1 = <&state_dpaux1_off>;
710 dmas = <&gpcdma 26>, <&gpcdma <<
711 dma-names = "rx", "tx"; <<
712 status = "disabled"; 248 status = "disabled";
713 }; 249 };
714 250
715 /* controlled by BPMP, should not be e 251 /* controlled by BPMP, should not be enabled */
716 pwr_i2c: i2c@31a0000 { 252 pwr_i2c: i2c@31a0000 {
717 compatible = "nvidia,tegra186- !! 253 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
718 reg = <0x0 0x031a0000 0x0 0x10 254 reg = <0x0 0x031a0000 0x0 0x10000>;
719 interrupts = <GIC_SPI 29 IRQ_T 255 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>; 256 #address-cells = <1>;
721 #size-cells = <0>; 257 #size-cells = <0>;
722 clocks = <&bpmp TEGRA186_CLK_I 258 clocks = <&bpmp TEGRA186_CLK_I2C5>;
723 clock-names = "div-clk"; 259 clock-names = "div-clk";
724 resets = <&bpmp TEGRA186_RESET 260 resets = <&bpmp TEGRA186_RESET_I2C5>;
725 reset-names = "i2c"; 261 reset-names = "i2c";
726 status = "disabled"; 262 status = "disabled";
727 }; 263 };
728 264
729 /* shares pads with dpaux0 */ 265 /* shares pads with dpaux0 */
730 dp_aux_ch0_i2c: i2c@31b0000 { 266 dp_aux_ch0_i2c: i2c@31b0000 {
731 compatible = "nvidia,tegra186- !! 267 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
732 reg = <0x0 0x031b0000 0x0 0x10 268 reg = <0x0 0x031b0000 0x0 0x10000>;
733 interrupts = <GIC_SPI 30 IRQ_T 269 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
734 #address-cells = <1>; 270 #address-cells = <1>;
735 #size-cells = <0>; 271 #size-cells = <0>;
736 clocks = <&bpmp TEGRA186_CLK_I 272 clocks = <&bpmp TEGRA186_CLK_I2C6>;
737 clock-names = "div-clk"; 273 clock-names = "div-clk";
738 resets = <&bpmp TEGRA186_RESET 274 resets = <&bpmp TEGRA186_RESET_I2C6>;
739 reset-names = "i2c"; 275 reset-names = "i2c";
740 pinctrl-names = "default", "id 276 pinctrl-names = "default", "idle";
741 pinctrl-0 = <&state_dpaux_i2c> 277 pinctrl-0 = <&state_dpaux_i2c>;
742 pinctrl-1 = <&state_dpaux_off> 278 pinctrl-1 = <&state_dpaux_off>;
743 dmas = <&gpcdma 30>, <&gpcdma <<
744 dma-names = "rx", "tx"; <<
745 status = "disabled"; 279 status = "disabled";
746 }; 280 };
747 281
748 gen7_i2c: i2c@31c0000 { 282 gen7_i2c: i2c@31c0000 {
749 compatible = "nvidia,tegra186- !! 283 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
750 reg = <0x0 0x031c0000 0x0 0x10 284 reg = <0x0 0x031c0000 0x0 0x10000>;
751 interrupts = <GIC_SPI 31 IRQ_T 285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
752 #address-cells = <1>; 286 #address-cells = <1>;
753 #size-cells = <0>; 287 #size-cells = <0>;
754 clocks = <&bpmp TEGRA186_CLK_I 288 clocks = <&bpmp TEGRA186_CLK_I2C7>;
755 clock-names = "div-clk"; 289 clock-names = "div-clk";
756 resets = <&bpmp TEGRA186_RESET 290 resets = <&bpmp TEGRA186_RESET_I2C7>;
757 reset-names = "i2c"; 291 reset-names = "i2c";
758 dmas = <&gpcdma 27>, <&gpcdma <<
759 dma-names = "rx", "tx"; <<
760 status = "disabled"; 292 status = "disabled";
761 }; 293 };
762 294
763 gen9_i2c: i2c@31e0000 { 295 gen9_i2c: i2c@31e0000 {
764 compatible = "nvidia,tegra186- !! 296 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
765 reg = <0x0 0x031e0000 0x0 0x10 297 reg = <0x0 0x031e0000 0x0 0x10000>;
766 interrupts = <GIC_SPI 33 IRQ_T 298 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>; 299 #address-cells = <1>;
768 #size-cells = <0>; 300 #size-cells = <0>;
769 clocks = <&bpmp TEGRA186_CLK_I 301 clocks = <&bpmp TEGRA186_CLK_I2C9>;
770 clock-names = "div-clk"; 302 clock-names = "div-clk";
771 resets = <&bpmp TEGRA186_RESET 303 resets = <&bpmp TEGRA186_RESET_I2C9>;
772 reset-names = "i2c"; 304 reset-names = "i2c";
773 dmas = <&gpcdma 31>, <&gpcdma <<
774 dma-names = "rx", "tx"; <<
775 status = "disabled"; <<
776 }; <<
777 <<
778 pwm1: pwm@3280000 { <<
779 compatible = "nvidia,tegra186- <<
780 reg = <0x0 0x3280000 0x0 0x100 <<
781 clocks = <&bpmp TEGRA186_CLK_P <<
782 resets = <&bpmp TEGRA186_RESET <<
783 reset-names = "pwm"; <<
784 status = "disabled"; 305 status = "disabled";
785 #pwm-cells = <2>; <<
786 }; 306 };
787 307
788 pwm2: pwm@3290000 { !! 308 sdmmc1: sdhci@3400000 {
789 compatible = "nvidia,tegra186- <<
790 reg = <0x0 0x3290000 0x0 0x100 <<
791 clocks = <&bpmp TEGRA186_CLK_P <<
792 resets = <&bpmp TEGRA186_RESET <<
793 reset-names = "pwm"; <<
794 status = "disabled"; <<
795 #pwm-cells = <2>; <<
796 }; <<
797 <<
798 pwm3: pwm@32a0000 { <<
799 compatible = "nvidia,tegra186- <<
800 reg = <0x0 0x32a0000 0x0 0x100 <<
801 clocks = <&bpmp TEGRA186_CLK_P <<
802 resets = <&bpmp TEGRA186_RESET <<
803 reset-names = "pwm"; <<
804 status = "disabled"; <<
805 #pwm-cells = <2>; <<
806 }; <<
807 <<
808 pwm5: pwm@32c0000 { <<
809 compatible = "nvidia,tegra186- <<
810 reg = <0x0 0x32c0000 0x0 0x100 <<
811 clocks = <&bpmp TEGRA186_CLK_P <<
812 resets = <&bpmp TEGRA186_RESET <<
813 reset-names = "pwm"; <<
814 status = "disabled"; <<
815 #pwm-cells = <2>; <<
816 }; <<
817 <<
818 pwm6: pwm@32d0000 { <<
819 compatible = "nvidia,tegra186- <<
820 reg = <0x0 0x32d0000 0x0 0x100 <<
821 clocks = <&bpmp TEGRA186_CLK_P <<
822 resets = <&bpmp TEGRA186_RESET <<
823 reset-names = "pwm"; <<
824 status = "disabled"; <<
825 #pwm-cells = <2>; <<
826 }; <<
827 <<
828 pwm7: pwm@32e0000 { <<
829 compatible = "nvidia,tegra186- <<
830 reg = <0x0 0x32e0000 0x0 0x100 <<
831 clocks = <&bpmp TEGRA186_CLK_P <<
832 resets = <&bpmp TEGRA186_RESET <<
833 reset-names = "pwm"; <<
834 status = "disabled"; <<
835 #pwm-cells = <2>; <<
836 }; <<
837 <<
838 pwm8: pwm@32f0000 { <<
839 compatible = "nvidia,tegra186- <<
840 reg = <0x0 0x32f0000 0x0 0x100 <<
841 clocks = <&bpmp TEGRA186_CLK_P <<
842 resets = <&bpmp TEGRA186_RESET <<
843 reset-names = "pwm"; <<
844 status = "disabled"; <<
845 #pwm-cells = <2>; <<
846 }; <<
847 <<
848 sdmmc1: mmc@3400000 { <<
849 compatible = "nvidia,tegra186- 309 compatible = "nvidia,tegra186-sdhci";
850 reg = <0x0 0x03400000 0x0 0x10 310 reg = <0x0 0x03400000 0x0 0x10000>;
851 interrupts = <GIC_SPI 62 IRQ_T 311 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&bpmp TEGRA186_CLK_S !! 312 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
853 <&bpmp TEGRA186_CLK_S !! 313 clock-names = "sdhci";
854 clock-names = "sdhci", "tmclk" <<
855 resets = <&bpmp TEGRA186_RESET 314 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
856 reset-names = "sdhci"; 315 reset-names = "sdhci";
857 interconnects = <&mc TEGRA186_ <<
858 <&mc TEGRA186_ <<
859 interconnect-names = "dma-mem" <<
860 iommus = <&smmu TEGRA186_SID_S 316 iommus = <&smmu TEGRA186_SID_SDMMC1>;
861 pinctrl-names = "sdmmc-3v3", " 317 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
862 pinctrl-0 = <&sdmmc1_3v3>; 318 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>; 319 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-off 320 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-o 321 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-off 322 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-o 323 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-off 324 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-o 325 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>; 326 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>; 327 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA 328 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
873 <&bpmp TEGRA 329 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 assigned-clock-parents = <&bpm 330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
875 status = "disabled"; 331 status = "disabled";
876 }; 332 };
877 333
878 sdmmc2: mmc@3420000 { !! 334 sdmmc2: sdhci@3420000 {
879 compatible = "nvidia,tegra186- 335 compatible = "nvidia,tegra186-sdhci";
880 reg = <0x0 0x03420000 0x0 0x10 336 reg = <0x0 0x03420000 0x0 0x10000>;
881 interrupts = <GIC_SPI 63 IRQ_T 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&bpmp TEGRA186_CLK_S !! 338 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
883 <&bpmp TEGRA186_CLK_S !! 339 clock-names = "sdhci";
884 clock-names = "sdhci", "tmclk" <<
885 resets = <&bpmp TEGRA186_RESET 340 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
886 reset-names = "sdhci"; 341 reset-names = "sdhci";
887 interconnects = <&mc TEGRA186_ <<
888 <&mc TEGRA186_ <<
889 interconnect-names = "dma-mem" <<
890 iommus = <&smmu TEGRA186_SID_S 342 iommus = <&smmu TEGRA186_SID_SDMMC2>;
891 pinctrl-names = "sdmmc-3v3", " 343 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
892 pinctrl-0 = <&sdmmc2_3v3>; 344 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>; 345 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-off 346 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-o 347 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-off 348 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-o 349 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>; 350 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>; 351 nvidia,default-trim = <0xb>;
900 status = "disabled"; 352 status = "disabled";
901 }; 353 };
902 354
903 sdmmc3: mmc@3440000 { !! 355 sdmmc3: sdhci@3440000 {
904 compatible = "nvidia,tegra186- 356 compatible = "nvidia,tegra186-sdhci";
905 reg = <0x0 0x03440000 0x0 0x10 357 reg = <0x0 0x03440000 0x0 0x10000>;
906 interrupts = <GIC_SPI 64 IRQ_T 358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&bpmp TEGRA186_CLK_S !! 359 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
908 <&bpmp TEGRA186_CLK_S !! 360 clock-names = "sdhci";
909 clock-names = "sdhci", "tmclk" <<
910 resets = <&bpmp TEGRA186_RESET 361 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
911 reset-names = "sdhci"; 362 reset-names = "sdhci";
912 interconnects = <&mc TEGRA186_ <<
913 <&mc TEGRA186_ <<
914 interconnect-names = "dma-mem" <<
915 iommus = <&smmu TEGRA186_SID_S 363 iommus = <&smmu TEGRA186_SID_SDMMC3>;
916 pinctrl-names = "sdmmc-3v3", " 364 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
917 pinctrl-0 = <&sdmmc3_3v3>; 365 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>; 366 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-off 367 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-o 368 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-off 369 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-o 370 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-off 371 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-o 372 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>; 373 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>; 374 nvidia,default-trim = <0xb>;
927 status = "disabled"; 375 status = "disabled";
928 }; 376 };
929 377
930 sdmmc4: mmc@3460000 { !! 378 sdmmc4: sdhci@3460000 {
931 compatible = "nvidia,tegra186- 379 compatible = "nvidia,tegra186-sdhci";
932 reg = <0x0 0x03460000 0x0 0x10 380 reg = <0x0 0x03460000 0x0 0x10000>;
933 interrupts = <GIC_SPI 65 IRQ_T 381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&bpmp TEGRA186_CLK_S !! 382 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
935 <&bpmp TEGRA186_CLK_S !! 383 clock-names = "sdhci";
936 clock-names = "sdhci", "tmclk" <<
937 assigned-clocks = <&bpmp TEGRA 384 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
938 <&bpmp TEGRA 385 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
939 assigned-clock-parents = <&bpm 386 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 resets = <&bpmp TEGRA186_RESET 387 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
941 reset-names = "sdhci"; 388 reset-names = "sdhci";
942 interconnects = <&mc TEGRA186_ <<
943 <&mc TEGRA186_ <<
944 interconnect-names = "dma-mem" <<
945 iommus = <&smmu TEGRA186_SID_S 389 iommus = <&smmu TEGRA186_SID_SDMMC4>;
946 nvidia,pad-autocal-pull-up-off 390 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-o 391 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-off 392 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-o 393 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-off 394 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-o 395 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>; 396 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>; 397 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>; 398 nvidia,dqs-trim = <63>;
955 mmc-hs400-1_8v; 399 mmc-hs400-1_8v;
956 supports-cqe; 400 supports-cqe;
957 status = "disabled"; 401 status = "disabled";
958 }; 402 };
959 403
960 sata@3507000 { <<
961 compatible = "nvidia,tegra186- <<
962 reg = <0x0 0x03507000 0x0 0x00 <<
963 <0x0 0x03500000 0x0 0x00 <<
964 <0x0 0x03A90000 0x0 0x00 <<
965 interrupts = <GIC_SPI 197 IRQ_ <<
966 <<
967 power-domains = <&bpmp TEGRA18 <<
968 interconnects = <&mc TEGRA186_ <<
969 <&mc TEGRA186_ <<
970 interconnect-names = "dma-mem" <<
971 iommus = <&smmu TEGRA186_SID_S <<
972 <<
973 clocks = <&bpmp TEGRA186_CLK_S <<
974 <&bpmp TEGRA186_CLK_S <<
975 clock-names = "sata", "sata-oo <<
976 assigned-clocks = <&bpmp TEGRA <<
977 <&bpmp TEGRA <<
978 assigned-clock-parents = <&bpm <<
979 <&bpm <<
980 assigned-clock-rates = <102000 <<
981 <204000 <<
982 resets = <&bpmp TEGRA186_RESET <<
983 <&bpmp TEGRA186_RESET_ <<
984 reset-names = "sata", "sata-co <<
985 status = "disabled"; <<
986 }; <<
987 <<
988 hda@3510000 { 404 hda@3510000 {
989 compatible = "nvidia,tegra186- 405 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
990 reg = <0x0 0x03510000 0x0 0x10 406 reg = <0x0 0x03510000 0x0 0x10000>;
991 interrupts = <GIC_SPI 161 IRQ_ 407 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&bpmp TEGRA186_CLK_H 408 clocks = <&bpmp TEGRA186_CLK_HDA>,
993 <&bpmp TEGRA186_CLK_H 409 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
994 <&bpmp TEGRA186_CLK_H 410 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
995 clock-names = "hda", "hda2hdmi 411 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
996 resets = <&bpmp TEGRA186_RESET 412 resets = <&bpmp TEGRA186_RESET_HDA>,
997 <&bpmp TEGRA186_RESET 413 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
998 <&bpmp TEGRA186_RESET 414 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
999 reset-names = "hda", "hda2hdmi 415 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 power-domains = <&bpmp TEGRA1 416 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1001 interconnects = <&mc TEGRA186 <<
1002 <&mc TEGRA186 <<
1003 interconnect-names = "dma-mem <<
1004 iommus = <&smmu TEGRA186_SID_ 417 iommus = <&smmu TEGRA186_SID_HDA>;
1005 status = "disabled"; 418 status = "disabled";
1006 }; 419 };
1007 420
1008 padctl: padctl@3520000 { 421 padctl: padctl@3520000 {
1009 compatible = "nvidia,tegra186 422 compatible = "nvidia,tegra186-xusb-padctl";
1010 reg = <0x0 0x03520000 0x0 0x1 423 reg = <0x0 0x03520000 0x0 0x1000>,
1011 <0x0 0x03540000 0x0 0x1 424 <0x0 0x03540000 0x0 0x1000>;
1012 reg-names = "padctl", "ao"; 425 reg-names = "padctl", "ao";
1013 interrupts = <GIC_SPI 167 IRQ <<
1014 426
1015 resets = <&bpmp TEGRA186_RESE 427 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1016 reset-names = "padctl"; 428 reset-names = "padctl";
1017 429
1018 status = "disabled"; 430 status = "disabled";
1019 431
1020 pads { 432 pads {
1021 usb2 { 433 usb2 {
1022 clocks = <&bp 434 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1023 clock-names = 435 clock-names = "trk";
1024 status = "dis 436 status = "disabled";
1025 437
1026 lanes { 438 lanes {
1027 usb2- 439 usb2-0 {
1028 440 status = "disabled";
1029 441 #phy-cells = <0>;
1030 }; 442 };
1031 443
1032 usb2- 444 usb2-1 {
1033 445 status = "disabled";
1034 446 #phy-cells = <0>;
1035 }; 447 };
1036 448
1037 usb2- 449 usb2-2 {
1038 450 status = "disabled";
1039 451 #phy-cells = <0>;
1040 }; 452 };
1041 }; 453 };
1042 }; 454 };
1043 455
1044 hsic { 456 hsic {
1045 clocks = <&bp 457 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1046 clock-names = 458 clock-names = "trk";
1047 status = "dis 459 status = "disabled";
1048 460
1049 lanes { 461 lanes {
1050 hsic- 462 hsic-0 {
1051 463 status = "disabled";
1052 464 #phy-cells = <0>;
1053 }; 465 };
1054 }; 466 };
1055 }; 467 };
1056 468
1057 usb3 { 469 usb3 {
1058 status = "dis 470 status = "disabled";
1059 471
1060 lanes { 472 lanes {
1061 usb3- 473 usb3-0 {
1062 474 status = "disabled";
1063 475 #phy-cells = <0>;
1064 }; 476 };
1065 477
1066 usb3- 478 usb3-1 {
1067 479 status = "disabled";
1068 480 #phy-cells = <0>;
1069 }; 481 };
1070 482
1071 usb3- 483 usb3-2 {
1072 484 status = "disabled";
1073 485 #phy-cells = <0>;
1074 }; 486 };
1075 }; 487 };
1076 }; 488 };
1077 }; 489 };
1078 490
1079 ports { 491 ports {
1080 usb2-0 { 492 usb2-0 {
1081 status = "dis 493 status = "disabled";
1082 }; 494 };
1083 495
1084 usb2-1 { 496 usb2-1 {
1085 status = "dis 497 status = "disabled";
1086 }; 498 };
1087 499
1088 usb2-2 { 500 usb2-2 {
1089 status = "dis 501 status = "disabled";
1090 }; 502 };
1091 503
1092 hsic-0 { 504 hsic-0 {
1093 status = "dis 505 status = "disabled";
1094 }; 506 };
1095 507
1096 usb3-0 { 508 usb3-0 {
1097 status = "dis 509 status = "disabled";
1098 }; 510 };
1099 511
1100 usb3-1 { 512 usb3-1 {
1101 status = "dis 513 status = "disabled";
1102 }; 514 };
1103 515
1104 usb3-2 { 516 usb3-2 {
1105 status = "dis 517 status = "disabled";
1106 }; 518 };
1107 }; 519 };
1108 }; 520 };
1109 521
1110 usb@3530000 { 522 usb@3530000 {
1111 compatible = "nvidia,tegra186 523 compatible = "nvidia,tegra186-xusb";
1112 reg = <0x0 0x03530000 0x0 0x8 524 reg = <0x0 0x03530000 0x0 0x8000>,
1113 <0x0 0x03538000 0x0 0x1 525 <0x0 0x03538000 0x0 0x1000>;
1114 reg-names = "hcd", "fpci"; 526 reg-names = "hcd", "fpci";
>> 527
1115 interrupts = <GIC_SPI 163 IRQ 528 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 164 IRQ !! 529 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>> 530 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
>> 531
1117 clocks = <&bpmp TEGRA186_CLK_ 532 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1118 <&bpmp TEGRA186_CLK_ 533 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1119 <&bpmp TEGRA186_CLK_ 534 <&bpmp TEGRA186_CLK_XUSB_SS>,
1120 <&bpmp TEGRA186_CLK_ 535 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1121 <&bpmp TEGRA186_CLK_ 536 <&bpmp TEGRA186_CLK_CLK_M>,
1122 <&bpmp TEGRA186_CLK_ 537 <&bpmp TEGRA186_CLK_XUSB_FS>,
1123 <&bpmp TEGRA186_CLK_ 538 <&bpmp TEGRA186_CLK_PLLU>,
1124 <&bpmp TEGRA186_CLK_ 539 <&bpmp TEGRA186_CLK_CLK_M>,
1125 <&bpmp TEGRA186_CLK_ 540 <&bpmp TEGRA186_CLK_PLLE>;
1126 clock-names = "xusb_host", "x 541 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1127 "xusb_ss_src", 542 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1128 "pll_u_480m", " 543 "pll_u_480m", "clk_m", "pll_e";
>> 544
1129 power-domains = <&bpmp TEGRA1 545 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1130 <&bpmp TEGRA1 546 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1131 power-domain-names = "xusb_ho 547 power-domain-names = "xusb_host", "xusb_ss";
1132 interconnects = <&mc TEGRA186 <<
1133 <&mc TEGRA186 <<
1134 interconnect-names = "dma-mem <<
1135 iommus = <&smmu TEGRA186_SID_ <<
1136 #address-cells = <1>; <<
1137 #size-cells = <0>; <<
1138 status = "disabled"; <<
1139 <<
1140 nvidia,xusb-padctl = <&padctl 548 nvidia,xusb-padctl = <&padctl>;
1141 }; <<
1142 549
1143 usb@3550000 { <<
1144 compatible = "nvidia,tegra186 <<
1145 reg = <0x0 0x03550000 0x0 0x8 <<
1146 <0x0 0x03558000 0x0 0x1 <<
1147 reg-names = "base", "fpci"; <<
1148 interrupts = <GIC_SPI 166 IRQ <<
1149 clocks = <&bpmp TEGRA186_CLK_ <<
1150 <&bpmp TEGRA186_CLK_ <<
1151 <&bpmp TEGRA186_CLK_ <<
1152 <&bpmp TEGRA186_CLK_ <<
1153 clock-names = "dev", "ss", "s <<
1154 interconnects = <&mc TEGRA186 <<
1155 <&mc TEGRA186 <<
1156 interconnect-names = "dma-mem <<
1157 iommus = <&smmu TEGRA186_SID_ <<
1158 power-domains = <&bpmp TEGRA1 <<
1159 <&bpmp TEGRA1 <<
1160 power-domain-names = "dev", " <<
1161 nvidia,xusb-padctl = <&padctl <<
1162 status = "disabled"; 550 status = "disabled";
>> 551
>> 552 #address-cells = <1>;
>> 553 #size-cells = <0>;
1163 }; 554 };
1164 555
1165 fuse@3820000 { 556 fuse@3820000 {
1166 compatible = "nvidia,tegra186 557 compatible = "nvidia,tegra186-efuse";
1167 reg = <0x0 0x03820000 0x0 0x1 558 reg = <0x0 0x03820000 0x0 0x10000>;
1168 clocks = <&bpmp TEGRA186_CLK_ 559 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1169 clock-names = "fuse"; 560 clock-names = "fuse";
1170 }; 561 };
1171 562
1172 gic: interrupt-controller@3881000 { 563 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400"; 564 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>; 565 #interrupt-cells = <3>;
1175 interrupt-controller; 566 interrupt-controller;
1176 reg = <0x0 0x03881000 0x0 0x1 567 reg = <0x0 0x03881000 0x0 0x1000>,
1177 <0x0 0x03882000 0x0 0x2 !! 568 <0x0 0x03882000 0x0 0x2000>;
1178 <0x0 0x03884000 0x0 0x2 <<
1179 <0x0 0x03886000 0x0 0x2 <<
1180 interrupts = <GIC_PPI 9 569 interrupts = <GIC_PPI 9
1181 (GIC_CPU_MASK_SIMPLE( 570 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1182 interrupt-parent = <&gic>; 571 interrupt-parent = <&gic>;
1183 }; 572 };
1184 573
1185 cec@3960000 { 574 cec@3960000 {
1186 compatible = "nvidia,tegra186 575 compatible = "nvidia,tegra186-cec";
1187 reg = <0x0 0x03960000 0x0 0x1 576 reg = <0x0 0x03960000 0x0 0x10000>;
1188 interrupts = <GIC_SPI 162 IRQ 577 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&bpmp TEGRA186_CLK_ 578 clocks = <&bpmp TEGRA186_CLK_CEC>;
1190 clock-names = "cec"; 579 clock-names = "cec";
1191 status = "disabled"; 580 status = "disabled";
1192 }; 581 };
1193 582
1194 hsp_top0: hsp@3c00000 { 583 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186 584 compatible = "nvidia,tegra186-hsp";
1196 reg = <0x0 0x03c00000 0x0 0xa 585 reg = <0x0 0x03c00000 0x0 0xa0000>;
1197 interrupts = <GIC_SPI 176 IRQ 586 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "doorbell"; 587 interrupt-names = "doorbell";
1199 #mbox-cells = <2>; 588 #mbox-cells = <2>;
1200 status = "disabled"; 589 status = "disabled";
1201 }; 590 };
1202 591
1203 gen2_i2c: i2c@c240000 { 592 gen2_i2c: i2c@c240000 {
1204 compatible = "nvidia,tegra186 !! 593 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1205 reg = <0x0 0x0c240000 0x0 0x1 594 reg = <0x0 0x0c240000 0x0 0x10000>;
1206 interrupts = <GIC_SPI 26 IRQ_ 595 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>; 596 #address-cells = <1>;
1208 #size-cells = <0>; 597 #size-cells = <0>;
1209 clocks = <&bpmp TEGRA186_CLK_ 598 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1210 clock-names = "div-clk"; 599 clock-names = "div-clk";
1211 resets = <&bpmp TEGRA186_RESE 600 resets = <&bpmp TEGRA186_RESET_I2C2>;
1212 reset-names = "i2c"; 601 reset-names = "i2c";
1213 dmas = <&gpcdma 22>, <&gpcdma <<
1214 dma-names = "rx", "tx"; <<
1215 status = "disabled"; 602 status = "disabled";
1216 }; 603 };
1217 604
1218 gen8_i2c: i2c@c250000 { 605 gen8_i2c: i2c@c250000 {
1219 compatible = "nvidia,tegra186 !! 606 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1220 reg = <0x0 0x0c250000 0x0 0x1 607 reg = <0x0 0x0c250000 0x0 0x10000>;
1221 interrupts = <GIC_SPI 32 IRQ_ 608 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>; 609 #address-cells = <1>;
1223 #size-cells = <0>; 610 #size-cells = <0>;
1224 clocks = <&bpmp TEGRA186_CLK_ 611 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1225 clock-names = "div-clk"; 612 clock-names = "div-clk";
1226 resets = <&bpmp TEGRA186_RESE 613 resets = <&bpmp TEGRA186_RESET_I2C8>;
1227 reset-names = "i2c"; 614 reset-names = "i2c";
1228 dmas = <&gpcdma 0>, <&gpcdma <<
1229 dma-names = "rx", "tx"; <<
1230 status = "disabled"; 615 status = "disabled";
1231 }; 616 };
1232 617
1233 uartc: serial@c280000 { 618 uartc: serial@c280000 {
1234 compatible = "nvidia,tegra186 619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1235 reg = <0x0 0x0c280000 0x0 0x4 620 reg = <0x0 0x0c280000 0x0 0x40>;
1236 reg-shift = <2>; 621 reg-shift = <2>;
1237 interrupts = <GIC_SPI 114 IRQ 622 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&bpmp TEGRA186_CLK_ 623 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1239 clock-names = "serial"; 624 clock-names = "serial";
1240 resets = <&bpmp TEGRA186_RESE 625 resets = <&bpmp TEGRA186_RESET_UARTC>;
1241 reset-names = "serial"; 626 reset-names = "serial";
1242 status = "disabled"; 627 status = "disabled";
1243 }; 628 };
1244 629
1245 uartg: serial@c290000 { 630 uartg: serial@c290000 {
1246 compatible = "nvidia,tegra186 631 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1247 reg = <0x0 0x0c290000 0x0 0x4 632 reg = <0x0 0x0c290000 0x0 0x40>;
1248 reg-shift = <2>; 633 reg-shift = <2>;
1249 interrupts = <GIC_SPI 118 IRQ 634 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&bpmp TEGRA186_CLK_ 635 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1251 clock-names = "serial"; 636 clock-names = "serial";
1252 resets = <&bpmp TEGRA186_RESE 637 resets = <&bpmp TEGRA186_RESET_UARTG>;
1253 reset-names = "serial"; 638 reset-names = "serial";
1254 status = "disabled"; 639 status = "disabled";
1255 }; 640 };
1256 641
1257 rtc: rtc@c2a0000 { 642 rtc: rtc@c2a0000 {
1258 compatible = "nvidia,tegra186 643 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1259 reg = <0 0x0c2a0000 0 0x10000 644 reg = <0 0x0c2a0000 0 0x10000>;
1260 interrupt-parent = <&pmc>; 645 interrupt-parent = <&pmc>;
1261 interrupts = <73 IRQ_TYPE_LEV 646 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&bpmp TEGRA186_CLK_ 647 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1263 clock-names = "rtc"; 648 clock-names = "rtc";
1264 status = "disabled"; 649 status = "disabled";
1265 }; 650 };
1266 651
1267 gpio_aon: gpio@c2f0000 { 652 gpio_aon: gpio@c2f0000 {
1268 compatible = "nvidia,tegra186 653 compatible = "nvidia,tegra186-gpio-aon";
1269 reg-names = "security", "gpio 654 reg-names = "security", "gpio";
1270 reg = <0x0 0xc2f0000 0x0 0x10 655 reg = <0x0 0xc2f0000 0x0 0x1000>,
1271 <0x0 0xc2f1000 0x0 0x10 656 <0x0 0xc2f1000 0x0 0x1000>;
1272 interrupts = <GIC_SPI 60 IRQ_ 657 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1273 gpio-controller; 658 gpio-controller;
1274 #gpio-cells = <2>; 659 #gpio-cells = <2>;
1275 interrupt-controller; 660 interrupt-controller;
1276 #interrupt-cells = <2>; 661 #interrupt-cells = <2>;
1277 }; 662 };
1278 663
1279 pwm4: pwm@c340000 { <<
1280 compatible = "nvidia,tegra186 <<
1281 reg = <0x0 0xc340000 0x0 0x10 <<
1282 clocks = <&bpmp TEGRA186_CLK_ <<
1283 resets = <&bpmp TEGRA186_RESE <<
1284 reset-names = "pwm"; <<
1285 status = "disabled"; <<
1286 #pwm-cells = <2>; <<
1287 }; <<
1288 <<
1289 pmc: pmc@c360000 { 664 pmc: pmc@c360000 {
1290 compatible = "nvidia,tegra186 665 compatible = "nvidia,tegra186-pmc";
1291 reg = <0 0x0c360000 0 0x10000 666 reg = <0 0x0c360000 0 0x10000>,
1292 <0 0x0c370000 0 0x10000 667 <0 0x0c370000 0 0x10000>,
1293 <0 0x0c380000 0 0x10000 668 <0 0x0c380000 0 0x10000>,
1294 <0 0x0c390000 0 0x10000 669 <0 0x0c390000 0 0x10000>;
1295 reg-names = "pmc", "wake", "a 670 reg-names = "pmc", "wake", "aotag", "scratch";
1296 671
1297 #interrupt-cells = <2>; 672 #interrupt-cells = <2>;
1298 interrupt-controller; 673 interrupt-controller;
1299 674
1300 sdmmc1_1v8: sdmmc1-1v8 { <<
1301 pins = "sdmmc1-hv"; <<
1302 power-source = <TEGRA <<
1303 }; <<
1304 <<
1305 sdmmc1_3v3: sdmmc1-3v3 { 675 sdmmc1_3v3: sdmmc1-3v3 {
1306 pins = "sdmmc1-hv"; 676 pins = "sdmmc1-hv";
1307 power-source = <TEGRA 677 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1308 }; 678 };
1309 679
1310 sdmmc2_1v8: sdmmc2-1v8 { !! 680 sdmmc1_1v8: sdmmc1-1v8 {
1311 pins = "sdmmc2-hv"; !! 681 pins = "sdmmc1-hv";
1312 power-source = <TEGRA 682 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1313 }; 683 };
1314 684
1315 sdmmc2_3v3: sdmmc2-3v3 { 685 sdmmc2_3v3: sdmmc2-3v3 {
1316 pins = "sdmmc2-hv"; 686 pins = "sdmmc2-hv";
1317 power-source = <TEGRA 687 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1318 }; 688 };
1319 689
1320 sdmmc3_1v8: sdmmc3-1v8 { !! 690 sdmmc2_1v8: sdmmc2-1v8 {
1321 pins = "sdmmc3-hv"; !! 691 pins = "sdmmc2-hv";
1322 power-source = <TEGRA 692 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1323 }; 693 };
1324 694
1325 sdmmc3_3v3: sdmmc3-3v3 { 695 sdmmc3_3v3: sdmmc3-3v3 {
1326 pins = "sdmmc3-hv"; 696 pins = "sdmmc3-hv";
1327 power-source = <TEGRA 697 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1328 }; 698 };
>> 699
>> 700 sdmmc3_1v8: sdmmc3-1v8 {
>> 701 pins = "sdmmc3-hv";
>> 702 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 703 };
1329 }; 704 };
1330 705
1331 ccplex@e000000 { 706 ccplex@e000000 {
1332 compatible = "nvidia,tegra186 707 compatible = "nvidia,tegra186-ccplex-cluster";
1333 reg = <0x0 0x0e000000 0x0 0x4 !! 708 reg = <0x0 0x0e000000 0x0 0x3fffff>;
1334 709
1335 nvidia,bpmp = <&bpmp>; 710 nvidia,bpmp = <&bpmp>;
1336 }; 711 };
1337 712
1338 pcie@10003000 { 713 pcie@10003000 {
1339 compatible = "nvidia,tegra186 714 compatible = "nvidia,tegra186-pcie";
1340 power-domains = <&bpmp TEGRA1 715 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1341 device_type = "pci"; 716 device_type = "pci";
1342 reg = <0x0 0x10003000 0x0 0x0 !! 717 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
1343 <0x0 0x10003800 0x0 0x0 !! 718 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
1344 <0x0 0x40000000 0x0 0x1 !! 719 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1345 reg-names = "pads", "afi", "c 720 reg-names = "pads", "afi", "cs";
1346 721
1347 interrupts = <GIC_SPI 72 IRQ_ 722 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1348 <GIC_SPI 73 IRQ_ 723 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1349 interrupt-names = "intr", "ms 724 interrupt-names = "intr", "msi";
1350 725
1351 #interrupt-cells = <1>; 726 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0 727 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic 728 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1354 729
1355 bus-range = <0x00 0xff>; 730 bus-range = <0x00 0xff>;
1356 #address-cells = <3>; 731 #address-cells = <3>;
1357 #size-cells = <2>; 732 #size-cells = <2>;
1358 733
1359 ranges = <0x02000000 0 0x1000 !! 734 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
1360 <0x02000000 0 0x1000 !! 735 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
1361 <0x02000000 0 0x1000 !! 736 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
1362 <0x01000000 0 0x0 !! 737 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
1363 <0x02000000 0 0x5010 !! 738 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
1364 <0x42000000 0 0x5800 !! 739 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1365 740
1366 clocks = <&bpmp TEGRA186_CLK_ !! 741 clocks = <&bpmp TEGRA186_CLK_AFI>,
1367 <&bpmp TEGRA186_CLK_ !! 742 <&bpmp TEGRA186_CLK_PCIE>,
1368 <&bpmp TEGRA186_CLK_ 743 <&bpmp TEGRA186_CLK_PLLE>;
1369 clock-names = "pex", "afi", " !! 744 clock-names = "afi", "pex", "pll_e";
1370 745
1371 resets = <&bpmp TEGRA186_RESE !! 746 resets = <&bpmp TEGRA186_RESET_AFI>,
1372 <&bpmp TEGRA186_RESE !! 747 <&bpmp TEGRA186_RESET_PCIE>,
1373 <&bpmp TEGRA186_RESE 748 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1374 reset-names = "pex", "afi", " !! 749 reset-names = "afi", "pex", "pcie_x";
1375 <<
1376 interconnects = <&mc TEGRA186 <<
1377 <&mc TEGRA186 <<
1378 interconnect-names = "dma-mem <<
1379 750
1380 iommus = <&smmu TEGRA186_SID_ 751 iommus = <&smmu TEGRA186_SID_AFI>;
1381 iommu-map = <0x0 &smmu TEGRA1 752 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>; 753 iommu-map-mask = <0x0>;
1383 754
1384 status = "disabled"; 755 status = "disabled";
1385 756
1386 pci@1,0 { 757 pci@1,0 {
1387 device_type = "pci"; 758 device_type = "pci";
1388 assigned-addresses = 759 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1389 reg = <0x000800 0 0 0 760 reg = <0x000800 0 0 0 0>;
1390 status = "disabled"; 761 status = "disabled";
1391 762
1392 #address-cells = <3>; 763 #address-cells = <3>;
1393 #size-cells = <2>; 764 #size-cells = <2>;
1394 ranges; 765 ranges;
1395 766
1396 nvidia,num-lanes = <2 767 nvidia,num-lanes = <2>;
1397 }; 768 };
1398 769
1399 pci@2,0 { 770 pci@2,0 {
1400 device_type = "pci"; 771 device_type = "pci";
1401 assigned-addresses = 772 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1402 reg = <0x001000 0 0 0 773 reg = <0x001000 0 0 0 0>;
1403 status = "disabled"; 774 status = "disabled";
1404 775
1405 #address-cells = <3>; 776 #address-cells = <3>;
1406 #size-cells = <2>; 777 #size-cells = <2>;
1407 ranges; 778 ranges;
1408 779
1409 nvidia,num-lanes = <1 780 nvidia,num-lanes = <1>;
1410 }; 781 };
1411 782
1412 pci@3,0 { 783 pci@3,0 {
1413 device_type = "pci"; 784 device_type = "pci";
1414 assigned-addresses = 785 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1415 reg = <0x001800 0 0 0 786 reg = <0x001800 0 0 0 0>;
1416 status = "disabled"; 787 status = "disabled";
1417 788
1418 #address-cells = <3>; 789 #address-cells = <3>;
1419 #size-cells = <2>; 790 #size-cells = <2>;
1420 ranges; 791 ranges;
1421 792
1422 nvidia,num-lanes = <1 793 nvidia,num-lanes = <1>;
1423 }; 794 };
1424 }; 795 };
1425 796
1426 smmu: iommu@12000000 { 797 smmu: iommu@12000000 {
1427 compatible = "nvidia,tegra186 !! 798 compatible = "arm,mmu-500";
1428 reg = <0 0x12000000 0 0x80000 799 reg = <0 0x12000000 0 0x800000>;
1429 interrupts = <GIC_SPI 170 IRQ 800 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 170 IRQ 801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 170 IRQ 802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 170 IRQ 803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 170 IRQ 804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 170 IRQ 805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 170 IRQ 806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 170 IRQ 807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 170 IRQ 808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 170 IRQ 809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 170 IRQ 810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 170 IRQ 811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 170 IRQ 812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 170 IRQ 813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 170 IRQ 814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 170 IRQ 815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ 816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 170 IRQ 817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 170 IRQ 818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 170 IRQ 819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 170 IRQ 820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 170 IRQ 821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 170 IRQ 822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 170 IRQ 823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 170 IRQ 824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 170 IRQ 825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 170 IRQ 826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 170 IRQ 827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 170 IRQ 828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 170 IRQ 829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 170 IRQ 830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 170 IRQ 831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 170 IRQ 832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 170 IRQ 833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 170 IRQ 834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 170 IRQ 835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 170 IRQ 836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 170 IRQ 837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 170 IRQ 838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 170 IRQ 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 170 IRQ 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 170 IRQ 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 170 IRQ 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 170 IRQ 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 170 IRQ 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 170 IRQ 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 170 IRQ 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 170 IRQ 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 170 IRQ 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 170 IRQ 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 170 IRQ 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 170 IRQ 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 170 IRQ 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 170 IRQ 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 170 IRQ 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 170 IRQ 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 170 IRQ 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 170 IRQ 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 170 IRQ 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 170 IRQ 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 170 IRQ 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 170 IRQ 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 170 IRQ 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 170 IRQ 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 170 IRQ 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1494 stream-match-mask = <0x7f80>; 865 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>; 866 #global-interrupts = <1>;
1496 #iommu-cells = <1>; 867 #iommu-cells = <1>;
1497 <<
1498 nvidia,memory-controller = <& <<
1499 }; 868 };
1500 869
1501 host1x@13e00000 { 870 host1x@13e00000 {
1502 compatible = "nvidia,tegra186 !! 871 compatible = "nvidia,tegra186-host1x", "simple-bus";
1503 reg = <0x0 0x13e00000 0x0 0x1 872 reg = <0x0 0x13e00000 0x0 0x10000>,
1504 <0x0 0x13e10000 0x0 0x1 873 <0x0 0x13e10000 0x0 0x10000>;
1505 reg-names = "hypervisor", "vm 874 reg-names = "hypervisor", "vm";
1506 interrupts = <GIC_SPI 265 IRQ 875 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 263 IRQ 876 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-names = "syncpt", " <<
1509 clocks = <&bpmp TEGRA186_CLK_ 877 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1510 clock-names = "host1x"; 878 clock-names = "host1x";
1511 resets = <&bpmp TEGRA186_RESE 879 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1512 reset-names = "host1x"; 880 reset-names = "host1x";
1513 881
1514 #address-cells = <1>; 882 #address-cells = <1>;
1515 #size-cells = <1>; 883 #size-cells = <1>;
1516 884
1517 ranges = <0x15000000 0x0 0x15 885 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1518 <<
1519 interconnects = <&mc TEGRA186 <<
1520 interconnect-names = "dma-mem <<
1521 <<
1522 iommus = <&smmu TEGRA186_SID_ 886 iommus = <&smmu TEGRA186_SID_HOST1X>;
1523 887
1524 /* Context isolation domains <<
1525 iommu-map = <0 &smmu TEGRA186 <<
1526 <1 &smmu TEGRA186 <<
1527 <2 &smmu TEGRA186 <<
1528 <3 &smmu TEGRA186 <<
1529 <4 &smmu TEGRA186 <<
1530 <5 &smmu TEGRA186 <<
1531 <6 &smmu TEGRA186 <<
1532 <7 &smmu TEGRA186 <<
1533 <<
1534 dpaux1: dpaux@15040000 { 888 dpaux1: dpaux@15040000 {
1535 compatible = "nvidia, 889 compatible = "nvidia,tegra186-dpaux";
1536 reg = <0x15040000 0x1 890 reg = <0x15040000 0x10000>;
1537 interrupts = <GIC_SPI 891 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1538 clocks = <&bpmp TEGRA 892 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1539 <&bpmp TEGRA 893 <&bpmp TEGRA186_CLK_PLLDP>;
1540 clock-names = "dpaux" 894 clock-names = "dpaux", "parent";
1541 resets = <&bpmp TEGRA 895 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1542 reset-names = "dpaux" 896 reset-names = "dpaux";
1543 status = "disabled"; 897 status = "disabled";
1544 898
1545 power-domains = <&bpm 899 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1546 900
1547 state_dpaux1_aux: pin 901 state_dpaux1_aux: pinmux-aux {
1548 groups = "dpa 902 groups = "dpaux-io";
1549 function = "a 903 function = "aux";
1550 }; 904 };
1551 905
1552 state_dpaux1_i2c: pin 906 state_dpaux1_i2c: pinmux-i2c {
1553 groups = "dpa 907 groups = "dpaux-io";
1554 function = "i 908 function = "i2c";
1555 }; 909 };
1556 910
1557 state_dpaux1_off: pin 911 state_dpaux1_off: pinmux-off {
1558 groups = "dpa 912 groups = "dpaux-io";
1559 function = "o 913 function = "off";
1560 }; 914 };
1561 915
1562 i2c-bus { 916 i2c-bus {
1563 #address-cell 917 #address-cells = <1>;
1564 #size-cells = 918 #size-cells = <0>;
1565 }; 919 };
1566 }; 920 };
1567 921
1568 display-hub@15200000 { 922 display-hub@15200000 {
1569 compatible = "nvidia, !! 923 compatible = "nvidia,tegra186-display", "simple-bus";
1570 reg = <0x15200000 0x0 924 reg = <0x15200000 0x00040000>;
1571 resets = <&bpmp TEGRA 925 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1572 <&bpmp TEGRA 926 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1573 <&bpmp TEGRA 927 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1574 <&bpmp TEGRA 928 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1575 <&bpmp TEGRA 929 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1576 <&bpmp TEGRA 930 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1577 <&bpmp TEGRA 931 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1578 reset-names = "misc", 932 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1579 "wgrp3" 933 "wgrp3", "wgrp4", "wgrp5";
1580 clocks = <&bpmp TEGRA 934 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1581 <&bpmp TEGRA 935 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1582 <&bpmp TEGRA 936 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1583 clock-names = "disp", 937 clock-names = "disp", "dsc", "hub";
1584 status = "disabled"; 938 status = "disabled";
1585 939
1586 power-domains = <&bpm 940 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1587 941
1588 #address-cells = <1>; 942 #address-cells = <1>;
1589 #size-cells = <1>; 943 #size-cells = <1>;
1590 944
1591 ranges = <0x15200000 945 ranges = <0x15200000 0x15200000 0x40000>;
1592 946
1593 display@15200000 { 947 display@15200000 {
1594 compatible = 948 compatible = "nvidia,tegra186-dc";
1595 reg = <0x1520 949 reg = <0x15200000 0x10000>;
1596 interrupts = 950 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&bp 951 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1598 clock-names = 952 clock-names = "dc";
1599 resets = <&bp 953 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1600 reset-names = 954 reset-names = "dc";
1601 955
1602 power-domains 956 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1603 interconnects <<
1604 <<
1605 interconnect- <<
1606 iommus = <&sm 957 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1607 958
1608 nvidia,output 959 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1609 nvidia,head = 960 nvidia,head = <0>;
1610 }; 961 };
1611 962
1612 display@15210000 { 963 display@15210000 {
1613 compatible = 964 compatible = "nvidia,tegra186-dc";
1614 reg = <0x1521 965 reg = <0x15210000 0x10000>;
1615 interrupts = 966 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&bp 967 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1617 clock-names = 968 clock-names = "dc";
1618 resets = <&bp 969 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1619 reset-names = 970 reset-names = "dc";
1620 971
1621 power-domains 972 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1622 interconnects <<
1623 <<
1624 interconnect- <<
1625 iommus = <&sm 973 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1626 974
1627 nvidia,output 975 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1628 nvidia,head = 976 nvidia,head = <1>;
1629 }; 977 };
1630 978
1631 display@15220000 { 979 display@15220000 {
1632 compatible = 980 compatible = "nvidia,tegra186-dc";
1633 reg = <0x1522 981 reg = <0x15220000 0x10000>;
1634 interrupts = 982 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&bp 983 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1636 clock-names = 984 clock-names = "dc";
1637 resets = <&bp 985 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1638 reset-names = 986 reset-names = "dc";
1639 987
1640 power-domains 988 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1641 interconnects <<
1642 <<
1643 interconnect- <<
1644 iommus = <&sm 989 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1645 990
1646 nvidia,output 991 nvidia,outputs = <&sor0 &sor1>;
1647 nvidia,head = 992 nvidia,head = <2>;
1648 }; 993 };
1649 }; 994 };
1650 995
1651 dsia: dsi@15300000 { 996 dsia: dsi@15300000 {
1652 compatible = "nvidia, 997 compatible = "nvidia,tegra186-dsi";
1653 reg = <0x15300000 0x1 998 reg = <0x15300000 0x10000>;
1654 interrupts = <GIC_SPI 999 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&bpmp TEGRA 1000 clocks = <&bpmp TEGRA186_CLK_DSI>,
1656 <&bpmp TEGRA 1001 <&bpmp TEGRA186_CLK_DSIA_LP>,
1657 <&bpmp TEGRA 1002 <&bpmp TEGRA186_CLK_PLLD>;
1658 clock-names = "dsi", 1003 clock-names = "dsi", "lp", "parent";
1659 resets = <&bpmp TEGRA 1004 resets = <&bpmp TEGRA186_RESET_DSI>;
1660 reset-names = "dsi"; 1005 reset-names = "dsi";
1661 status = "disabled"; 1006 status = "disabled";
1662 1007
1663 power-domains = <&bpm 1008 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1664 }; 1009 };
1665 1010
1666 vic@15340000 { 1011 vic@15340000 {
1667 compatible = "nvidia, 1012 compatible = "nvidia,tegra186-vic";
1668 reg = <0x15340000 0x4 1013 reg = <0x15340000 0x40000>;
1669 interrupts = <GIC_SPI 1014 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1670 clocks = <&bpmp TEGRA 1015 clocks = <&bpmp TEGRA186_CLK_VIC>;
1671 clock-names = "vic"; 1016 clock-names = "vic";
1672 resets = <&bpmp TEGRA 1017 resets = <&bpmp TEGRA186_RESET_VIC>;
1673 reset-names = "vic"; 1018 reset-names = "vic";
1674 1019
1675 power-domains = <&bpm 1020 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1676 interconnects = <&mc <<
1677 <&mc <<
1678 interconnect-names = <<
1679 iommus = <&smmu TEGRA <<
1680 }; <<
1681 <<
1682 nvjpg@15380000 { <<
1683 compatible = "nvidia, <<
1684 reg = <0x15380000 0x4 <<
1685 clocks = <&bpmp TEGRA <<
1686 clock-names = "nvjpg" <<
1687 resets = <&bpmp TEGRA <<
1688 reset-names = "nvjpg" <<
1689 <<
1690 power-domains = <&bpm <<
1691 interconnects = <&mc <<
1692 <&mc <<
1693 interconnect-names = <<
1694 iommus = <&smmu TEGRA <<
1695 }; 1021 };
1696 1022
1697 dsib: dsi@15400000 { 1023 dsib: dsi@15400000 {
1698 compatible = "nvidia, 1024 compatible = "nvidia,tegra186-dsi";
1699 reg = <0x15400000 0x1 1025 reg = <0x15400000 0x10000>;
1700 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&bpmp TEGRA 1027 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1702 <&bpmp TEGRA 1028 <&bpmp TEGRA186_CLK_DSIB_LP>,
1703 <&bpmp TEGRA 1029 <&bpmp TEGRA186_CLK_PLLD>;
1704 clock-names = "dsi", 1030 clock-names = "dsi", "lp", "parent";
1705 resets = <&bpmp TEGRA 1031 resets = <&bpmp TEGRA186_RESET_DSIB>;
1706 reset-names = "dsi"; 1032 reset-names = "dsi";
1707 status = "disabled"; 1033 status = "disabled";
1708 1034
1709 power-domains = <&bpm 1035 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1710 }; 1036 };
1711 1037
1712 nvdec@15480000 { <<
1713 compatible = "nvidia, <<
1714 reg = <0x15480000 0x4 <<
1715 clocks = <&bpmp TEGRA <<
1716 clock-names = "nvdec" <<
1717 resets = <&bpmp TEGRA <<
1718 reset-names = "nvdec" <<
1719 <<
1720 power-domains = <&bpm <<
1721 interconnects = <&mc <<
1722 <&mc <<
1723 <&mc <<
1724 interconnect-names = <<
1725 iommus = <&smmu TEGRA <<
1726 }; <<
1727 <<
1728 nvenc@154c0000 { <<
1729 compatible = "nvidia, <<
1730 reg = <0x154c0000 0x4 <<
1731 clocks = <&bpmp TEGRA <<
1732 clock-names = "nvenc" <<
1733 resets = <&bpmp TEGRA <<
1734 reset-names = "nvenc" <<
1735 <<
1736 power-domains = <&bpm <<
1737 interconnects = <&mc <<
1738 <&mc <<
1739 interconnect-names = <<
1740 iommus = <&smmu TEGRA <<
1741 }; <<
1742 <<
1743 sor0: sor@15540000 { 1038 sor0: sor@15540000 {
1744 compatible = "nvidia, 1039 compatible = "nvidia,tegra186-sor";
1745 reg = <0x15540000 0x1 1040 reg = <0x15540000 0x10000>;
1746 interrupts = <GIC_SPI 1041 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1747 clocks = <&bpmp TEGRA 1042 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1748 <&bpmp TEGRA 1043 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1749 <&bpmp TEGRA 1044 <&bpmp TEGRA186_CLK_PLLD2>,
1750 <&bpmp TEGRA 1045 <&bpmp TEGRA186_CLK_PLLDP>,
1751 <&bpmp TEGRA 1046 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1752 <&bpmp TEGRA 1047 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1753 clock-names = "sor", 1048 clock-names = "sor", "out", "parent", "dp", "safe",
1754 "pad"; 1049 "pad";
1755 resets = <&bpmp TEGRA 1050 resets = <&bpmp TEGRA186_RESET_SOR0>;
1756 reset-names = "sor"; 1051 reset-names = "sor";
1757 pinctrl-0 = <&state_d 1052 pinctrl-0 = <&state_dpaux_aux>;
1758 pinctrl-1 = <&state_d 1053 pinctrl-1 = <&state_dpaux_i2c>;
1759 pinctrl-2 = <&state_d 1054 pinctrl-2 = <&state_dpaux_off>;
1760 pinctrl-names = "aux" 1055 pinctrl-names = "aux", "i2c", "off";
1761 status = "disabled"; 1056 status = "disabled";
1762 1057
1763 power-domains = <&bpm 1058 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1764 nvidia,interface = <0 1059 nvidia,interface = <0>;
1765 }; 1060 };
1766 1061
1767 sor1: sor@15580000 { 1062 sor1: sor@15580000 {
1768 compatible = "nvidia, !! 1063 compatible = "nvidia,tegra186-sor1";
1769 reg = <0x15580000 0x1 1064 reg = <0x15580000 0x10000>;
1770 interrupts = <GIC_SPI 1065 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1771 clocks = <&bpmp TEGRA 1066 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1772 <&bpmp TEGRA 1067 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1773 <&bpmp TEGRA 1068 <&bpmp TEGRA186_CLK_PLLD3>,
1774 <&bpmp TEGRA 1069 <&bpmp TEGRA186_CLK_PLLDP>,
1775 <&bpmp TEGRA 1070 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1776 <&bpmp TEGRA 1071 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1777 clock-names = "sor", 1072 clock-names = "sor", "out", "parent", "dp", "safe",
1778 "pad"; 1073 "pad";
1779 resets = <&bpmp TEGRA 1074 resets = <&bpmp TEGRA186_RESET_SOR1>;
1780 reset-names = "sor"; 1075 reset-names = "sor";
1781 pinctrl-0 = <&state_d 1076 pinctrl-0 = <&state_dpaux1_aux>;
1782 pinctrl-1 = <&state_d 1077 pinctrl-1 = <&state_dpaux1_i2c>;
1783 pinctrl-2 = <&state_d 1078 pinctrl-2 = <&state_dpaux1_off>;
1784 pinctrl-names = "aux" 1079 pinctrl-names = "aux", "i2c", "off";
1785 status = "disabled"; 1080 status = "disabled";
1786 1081
1787 power-domains = <&bpm 1082 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1788 nvidia,interface = <1 1083 nvidia,interface = <1>;
1789 }; 1084 };
1790 1085
1791 dpaux: dpaux@155c0000 { 1086 dpaux: dpaux@155c0000 {
1792 compatible = "nvidia, 1087 compatible = "nvidia,tegra186-dpaux";
1793 reg = <0x155c0000 0x1 1088 reg = <0x155c0000 0x10000>;
1794 interrupts = <GIC_SPI 1089 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&bpmp TEGRA 1090 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1796 <&bpmp TEGRA 1091 <&bpmp TEGRA186_CLK_PLLDP>;
1797 clock-names = "dpaux" 1092 clock-names = "dpaux", "parent";
1798 resets = <&bpmp TEGRA 1093 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1799 reset-names = "dpaux" 1094 reset-names = "dpaux";
1800 status = "disabled"; 1095 status = "disabled";
1801 1096
1802 power-domains = <&bpm 1097 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1803 1098
1804 state_dpaux_aux: pinm 1099 state_dpaux_aux: pinmux-aux {
1805 groups = "dpa 1100 groups = "dpaux-io";
1806 function = "a 1101 function = "aux";
1807 }; 1102 };
1808 1103
1809 state_dpaux_i2c: pinm 1104 state_dpaux_i2c: pinmux-i2c {
1810 groups = "dpa 1105 groups = "dpaux-io";
1811 function = "i 1106 function = "i2c";
1812 }; 1107 };
1813 1108
1814 state_dpaux_off: pinm 1109 state_dpaux_off: pinmux-off {
1815 groups = "dpa 1110 groups = "dpaux-io";
1816 function = "o 1111 function = "off";
1817 }; 1112 };
1818 1113
1819 i2c-bus { 1114 i2c-bus {
1820 #address-cell 1115 #address-cells = <1>;
1821 #size-cells = 1116 #size-cells = <0>;
1822 }; 1117 };
1823 }; 1118 };
1824 1119
1825 padctl@15880000 { 1120 padctl@15880000 {
1826 compatible = "nvidia, 1121 compatible = "nvidia,tegra186-dsi-padctl";
1827 reg = <0x15880000 0x1 1122 reg = <0x15880000 0x10000>;
1828 resets = <&bpmp TEGRA 1123 resets = <&bpmp TEGRA186_RESET_DSI>;
1829 reset-names = "dsi"; 1124 reset-names = "dsi";
1830 status = "disabled"; 1125 status = "disabled";
1831 }; 1126 };
1832 1127
1833 dsic: dsi@15900000 { 1128 dsic: dsi@15900000 {
1834 compatible = "nvidia, 1129 compatible = "nvidia,tegra186-dsi";
1835 reg = <0x15900000 0x1 1130 reg = <0x15900000 0x10000>;
1836 interrupts = <GIC_SPI 1131 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&bpmp TEGRA 1132 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1838 <&bpmp TEGRA 1133 <&bpmp TEGRA186_CLK_DSIC_LP>,
1839 <&bpmp TEGRA 1134 <&bpmp TEGRA186_CLK_PLLD>;
1840 clock-names = "dsi", 1135 clock-names = "dsi", "lp", "parent";
1841 resets = <&bpmp TEGRA 1136 resets = <&bpmp TEGRA186_RESET_DSIC>;
1842 reset-names = "dsi"; 1137 reset-names = "dsi";
1843 status = "disabled"; 1138 status = "disabled";
1844 1139
1845 power-domains = <&bpm 1140 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1846 }; 1141 };
1847 1142
1848 dsid: dsi@15940000 { 1143 dsid: dsi@15940000 {
1849 compatible = "nvidia, 1144 compatible = "nvidia,tegra186-dsi";
1850 reg = <0x15940000 0x1 1145 reg = <0x15940000 0x10000>;
1851 interrupts = <GIC_SPI 1146 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&bpmp TEGRA 1147 clocks = <&bpmp TEGRA186_CLK_DSID>,
1853 <&bpmp TEGRA 1148 <&bpmp TEGRA186_CLK_DSID_LP>,
1854 <&bpmp TEGRA 1149 <&bpmp TEGRA186_CLK_PLLD>;
1855 clock-names = "dsi", 1150 clock-names = "dsi", "lp", "parent";
1856 resets = <&bpmp TEGRA 1151 resets = <&bpmp TEGRA186_RESET_DSID>;
1857 reset-names = "dsi"; 1152 reset-names = "dsi";
1858 status = "disabled"; 1153 status = "disabled";
1859 1154
1860 power-domains = <&bpm 1155 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1861 }; 1156 };
1862 }; 1157 };
1863 1158
1864 gpu@17000000 { 1159 gpu@17000000 {
1865 compatible = "nvidia,gp10b"; 1160 compatible = "nvidia,gp10b";
1866 reg = <0x0 0x17000000 0x0 0x1 1161 reg = <0x0 0x17000000 0x0 0x1000000>,
1867 <0x0 0x18000000 0x0 0x1 1162 <0x0 0x18000000 0x0 0x1000000>;
1868 interrupts = <GIC_SPI 70 IRQ_ !! 1163 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
1869 <GIC_SPI 71 IRQ_ !! 1164 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1870 interrupt-names = "stall", "n 1165 interrupt-names = "stall", "nonstall";
1871 1166
1872 clocks = <&bpmp TEGRA186_CLK_ 1167 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1873 <&bpmp TEGRA186_CLK_ 1168 <&bpmp TEGRA186_CLK_GPU>;
1874 clock-names = "gpu", "pwr"; 1169 clock-names = "gpu", "pwr";
1875 resets = <&bpmp TEGRA186_RESE 1170 resets = <&bpmp TEGRA186_RESET_GPU>;
1876 reset-names = "gpu"; 1171 reset-names = "gpu";
1877 status = "disabled"; 1172 status = "disabled";
1878 1173
1879 power-domains = <&bpmp TEGRA1 1174 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1880 interconnects = <&mc TEGRA186 <<
1881 <&mc TEGRA186 <<
1882 <&mc TEGRA186 <<
1883 <&mc TEGRA186 <<
1884 interconnect-names = "dma-mem <<
1885 }; 1175 };
1886 1176
1887 sram@30000000 { !! 1177 sysram@30000000 {
1888 compatible = "nvidia,tegra186 1178 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1889 reg = <0x0 0x30000000 0x0 0x5 1179 reg = <0x0 0x30000000 0x0 0x50000>;
1890 #address-cells = <1>; !! 1180 #address-cells = <2>;
1891 #size-cells = <1>; !! 1181 #size-cells = <2>;
1892 ranges = <0x0 0x0 0x30000000 !! 1182 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1893 no-memory-wc; <<
1894 1183
1895 cpu_bpmp_tx: sram@4e000 { !! 1184 cpu_bpmp_tx: shmem@4e000 {
1896 reg = <0x4e000 0x1000 !! 1185 compatible = "nvidia,tegra186-bpmp-shmem";
>> 1186 reg = <0x0 0x4e000 0x0 0x1000>;
1897 label = "cpu-bpmp-tx" 1187 label = "cpu-bpmp-tx";
1898 pool; 1188 pool;
1899 }; 1189 };
1900 1190
1901 cpu_bpmp_rx: sram@4f000 { !! 1191 cpu_bpmp_rx: shmem@4f000 {
1902 reg = <0x4f000 0x1000 !! 1192 compatible = "nvidia,tegra186-bpmp-shmem";
>> 1193 reg = <0x0 0x4f000 0x0 0x1000>;
1903 label = "cpu-bpmp-rx" 1194 label = "cpu-bpmp-rx";
1904 pool; 1195 pool;
1905 }; 1196 };
1906 }; 1197 };
1907 1198
1908 bpmp: bpmp { 1199 bpmp: bpmp {
1909 compatible = "nvidia,tegra186 1200 compatible = "nvidia,tegra186-bpmp";
1910 interconnects = <&mc TEGRA186 <<
1911 <&mc TEGRA186 <<
1912 <&mc TEGRA186 <<
1913 <&mc TEGRA186 <<
1914 interconnect-names = "read", <<
1915 iommus = <&smmu TEGRA186_SID_ 1201 iommus = <&smmu TEGRA186_SID_BPMP>;
1916 mboxes = <&hsp_top0 TEGRA_HSP 1202 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1917 TEGRA_HSP 1203 TEGRA_HSP_DB_MASTER_BPMP>;
1918 shmem = <&cpu_bpmp_tx>, <&cpu !! 1204 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1919 #clock-cells = <1>; 1205 #clock-cells = <1>;
1920 #reset-cells = <1>; 1206 #reset-cells = <1>;
1921 #power-domain-cells = <1>; 1207 #power-domain-cells = <1>;
1922 1208
1923 bpmp_i2c: i2c { 1209 bpmp_i2c: i2c {
1924 compatible = "nvidia, 1210 compatible = "nvidia,tegra186-bpmp-i2c";
1925 nvidia,bpmp-bus-id = 1211 nvidia,bpmp-bus-id = <5>;
1926 #address-cells = <1>; 1212 #address-cells = <1>;
1927 #size-cells = <0>; 1213 #size-cells = <0>;
1928 status = "disabled"; 1214 status = "disabled";
1929 }; 1215 };
1930 1216
1931 bpmp_thermal: thermal { 1217 bpmp_thermal: thermal {
1932 compatible = "nvidia, 1218 compatible = "nvidia,tegra186-bpmp-thermal";
1933 #thermal-sensor-cells 1219 #thermal-sensor-cells = <1>;
1934 }; 1220 };
1935 }; 1221 };
1936 1222
1937 cpus { 1223 cpus {
1938 #address-cells = <1>; 1224 #address-cells = <1>;
1939 #size-cells = <0>; 1225 #size-cells = <0>;
1940 1226
1941 denver_0: cpu@0 { !! 1227 cpu@0 {
1942 compatible = "nvidia, 1228 compatible = "nvidia,tegra186-denver";
1943 device_type = "cpu"; 1229 device_type = "cpu";
1944 i-cache-size = <0x200 1230 i-cache-size = <0x20000>;
1945 i-cache-line-size = < 1231 i-cache-line-size = <64>;
1946 i-cache-sets = <512>; 1232 i-cache-sets = <512>;
1947 d-cache-size = <0x100 1233 d-cache-size = <0x10000>;
1948 d-cache-line-size = < 1234 d-cache-line-size = <64>;
1949 d-cache-sets = <256>; 1235 d-cache-sets = <256>;
1950 next-level-cache = <& 1236 next-level-cache = <&L2_DENVER>;
1951 reg = <0x000>; 1237 reg = <0x000>;
1952 }; 1238 };
1953 1239
1954 denver_1: cpu@1 { !! 1240 cpu@1 {
1955 compatible = "nvidia, 1241 compatible = "nvidia,tegra186-denver";
1956 device_type = "cpu"; 1242 device_type = "cpu";
1957 i-cache-size = <0x200 1243 i-cache-size = <0x20000>;
1958 i-cache-line-size = < 1244 i-cache-line-size = <64>;
1959 i-cache-sets = <512>; 1245 i-cache-sets = <512>;
1960 d-cache-size = <0x100 1246 d-cache-size = <0x10000>;
1961 d-cache-line-size = < 1247 d-cache-line-size = <64>;
1962 d-cache-sets = <256>; 1248 d-cache-sets = <256>;
1963 next-level-cache = <& 1249 next-level-cache = <&L2_DENVER>;
1964 reg = <0x001>; 1250 reg = <0x001>;
1965 }; 1251 };
1966 1252
1967 ca57_0: cpu@2 { !! 1253 cpu@2 {
1968 compatible = "arm,cor 1254 compatible = "arm,cortex-a57";
1969 device_type = "cpu"; 1255 device_type = "cpu";
1970 i-cache-size = <0xC00 1256 i-cache-size = <0xC000>;
1971 i-cache-line-size = < 1257 i-cache-line-size = <64>;
1972 i-cache-sets = <256>; 1258 i-cache-sets = <256>;
1973 d-cache-size = <0x800 1259 d-cache-size = <0x8000>;
1974 d-cache-line-size = < 1260 d-cache-line-size = <64>;
1975 d-cache-sets = <256>; 1261 d-cache-sets = <256>;
1976 next-level-cache = <& 1262 next-level-cache = <&L2_A57>;
1977 reg = <0x100>; 1263 reg = <0x100>;
1978 }; 1264 };
1979 1265
1980 ca57_1: cpu@3 { !! 1266 cpu@3 {
1981 compatible = "arm,cor 1267 compatible = "arm,cortex-a57";
1982 device_type = "cpu"; 1268 device_type = "cpu";
1983 i-cache-size = <0xC00 1269 i-cache-size = <0xC000>;
1984 i-cache-line-size = < 1270 i-cache-line-size = <64>;
1985 i-cache-sets = <256>; 1271 i-cache-sets = <256>;
1986 d-cache-size = <0x800 1272 d-cache-size = <0x8000>;
1987 d-cache-line-size = < 1273 d-cache-line-size = <64>;
1988 d-cache-sets = <256>; 1274 d-cache-sets = <256>;
1989 next-level-cache = <& 1275 next-level-cache = <&L2_A57>;
1990 reg = <0x101>; 1276 reg = <0x101>;
1991 }; 1277 };
1992 1278
1993 ca57_2: cpu@4 { !! 1279 cpu@4 {
1994 compatible = "arm,cor 1280 compatible = "arm,cortex-a57";
1995 device_type = "cpu"; 1281 device_type = "cpu";
1996 i-cache-size = <0xC00 1282 i-cache-size = <0xC000>;
1997 i-cache-line-size = < 1283 i-cache-line-size = <64>;
1998 i-cache-sets = <256>; 1284 i-cache-sets = <256>;
1999 d-cache-size = <0x800 1285 d-cache-size = <0x8000>;
2000 d-cache-line-size = < 1286 d-cache-line-size = <64>;
2001 d-cache-sets = <256>; 1287 d-cache-sets = <256>;
2002 next-level-cache = <& 1288 next-level-cache = <&L2_A57>;
2003 reg = <0x102>; 1289 reg = <0x102>;
2004 }; 1290 };
2005 1291
2006 ca57_3: cpu@5 { !! 1292 cpu@5 {
2007 compatible = "arm,cor 1293 compatible = "arm,cortex-a57";
2008 device_type = "cpu"; 1294 device_type = "cpu";
2009 i-cache-size = <0xC00 1295 i-cache-size = <0xC000>;
2010 i-cache-line-size = < 1296 i-cache-line-size = <64>;
2011 i-cache-sets = <256>; 1297 i-cache-sets = <256>;
2012 d-cache-size = <0x800 1298 d-cache-size = <0x8000>;
2013 d-cache-line-size = < 1299 d-cache-line-size = <64>;
2014 d-cache-sets = <256>; 1300 d-cache-sets = <256>;
2015 next-level-cache = <& 1301 next-level-cache = <&L2_A57>;
2016 reg = <0x103>; 1302 reg = <0x103>;
2017 }; 1303 };
2018 1304
2019 L2_DENVER: l2-cache0 { 1305 L2_DENVER: l2-cache0 {
2020 compatible = "cache"; 1306 compatible = "cache";
2021 cache-unified; 1307 cache-unified;
2022 cache-level = <2>; 1308 cache-level = <2>;
2023 cache-size = <0x20000 1309 cache-size = <0x200000>;
2024 cache-line-size = <64 1310 cache-line-size = <64>;
2025 cache-sets = <2048>; 1311 cache-sets = <2048>;
2026 }; 1312 };
2027 1313
2028 L2_A57: l2-cache1 { 1314 L2_A57: l2-cache1 {
2029 compatible = "cache"; 1315 compatible = "cache";
2030 cache-unified; 1316 cache-unified;
2031 cache-level = <2>; 1317 cache-level = <2>;
2032 cache-size = <0x20000 1318 cache-size = <0x200000>;
2033 cache-line-size = <64 1319 cache-line-size = <64>;
2034 cache-sets = <2048>; 1320 cache-sets = <2048>;
2035 }; 1321 };
2036 }; 1322 };
2037 1323
2038 pmu-a57 { <<
2039 compatible = "arm,cortex-a57- <<
2040 interrupts = <GIC_SPI 296 IRQ <<
2041 <GIC_SPI 297 IRQ <<
2042 <GIC_SPI 298 IRQ <<
2043 <GIC_SPI 299 IRQ <<
2044 interrupt-affinity = <&ca57_0 <<
2045 }; <<
2046 <<
2047 pmu-denver { <<
2048 compatible = "nvidia,denver-p <<
2049 interrupts = <GIC_SPI 320 IRQ <<
2050 <GIC_SPI 321 IRQ <<
2051 interrupt-affinity = <&denver <<
2052 }; <<
2053 <<
2054 sound { <<
2055 status = "disabled"; <<
2056 <<
2057 clocks = <&bpmp TEGRA186_CLK_ <<
2058 <&bpmp TEGRA186_CLK_ <<
2059 clock-names = "pll_a", "plla_ <<
2060 assigned-clocks = <&bpmp TEGR <<
2061 <&bpmp TEGR <<
2062 <&bpmp TEGR <<
2063 assigned-clock-parents = <0>, <<
2064 <&bp <<
2065 <&bp <<
2066 /* <<
2067 * PLLA supports dynamic ramp <<
2068 * for this to work and oscil <<
2069 * for 8x and 11.025x sample <<
2070 */ <<
2071 assigned-clock-rates = <25800 <<
2072 <<
2073 iommus = <&smmu TEGRA186_SID_ <<
2074 }; <<
2075 <<
2076 thermal-zones { 1324 thermal-zones {
2077 /* Cortex-A57 cluster */ !! 1325 a57 {
2078 cpu-thermal { <<
2079 polling-delay = <0>; 1326 polling-delay = <0>;
2080 polling-delay-passive 1327 polling-delay-passive = <1000>;
2081 1328
2082 thermal-sensors = <&b !! 1329 thermal-sensors =
>> 1330 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2083 1331
2084 trips { 1332 trips {
2085 critical { 1333 critical {
2086 tempe 1334 temperature = <101000>;
2087 hyste 1335 hysteresis = <0>;
2088 type 1336 type = "critical";
2089 }; 1337 };
2090 }; 1338 };
2091 1339
2092 cooling-maps { 1340 cooling-maps {
2093 }; 1341 };
2094 }; 1342 };
2095 1343
2096 /* Denver cluster */ !! 1344 denver {
2097 aux-thermal { <<
2098 polling-delay = <0>; 1345 polling-delay = <0>;
2099 polling-delay-passive 1346 polling-delay-passive = <1000>;
2100 1347
2101 thermal-sensors = <&b !! 1348 thermal-sensors =
>> 1349 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2102 1350
2103 trips { 1351 trips {
2104 critical { 1352 critical {
2105 tempe 1353 temperature = <101000>;
2106 hyste 1354 hysteresis = <0>;
2107 type 1355 type = "critical";
2108 }; 1356 };
2109 }; 1357 };
2110 1358
2111 cooling-maps { 1359 cooling-maps {
2112 }; 1360 };
2113 }; 1361 };
2114 1362
2115 gpu-thermal { !! 1363 gpu {
2116 polling-delay = <0>; 1364 polling-delay = <0>;
2117 polling-delay-passive 1365 polling-delay-passive = <1000>;
2118 1366
2119 thermal-sensors = <&b !! 1367 thermal-sensors =
>> 1368 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2120 1369
2121 trips { 1370 trips {
2122 critical { 1371 critical {
2123 tempe 1372 temperature = <101000>;
2124 hyste 1373 hysteresis = <0>;
2125 type 1374 type = "critical";
2126 }; 1375 };
2127 }; 1376 };
2128 1377
2129 cooling-maps { 1378 cooling-maps {
2130 }; 1379 };
2131 }; 1380 };
2132 1381
2133 pll-thermal { !! 1382 pll {
2134 polling-delay = <0>; 1383 polling-delay = <0>;
2135 polling-delay-passive 1384 polling-delay-passive = <1000>;
2136 1385
2137 thermal-sensors = <&b !! 1386 thermal-sensors =
>> 1387 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2138 1388
2139 trips { 1389 trips {
2140 critical { 1390 critical {
2141 tempe 1391 temperature = <101000>;
2142 hyste 1392 hysteresis = <0>;
2143 type 1393 type = "critical";
2144 }; 1394 };
2145 }; 1395 };
2146 1396
2147 cooling-maps { 1397 cooling-maps {
2148 }; 1398 };
2149 }; 1399 };
2150 1400
2151 ao-thermal { !! 1401 always_on {
2152 polling-delay = <0>; 1402 polling-delay = <0>;
2153 polling-delay-passive 1403 polling-delay-passive = <1000>;
2154 1404
2155 thermal-sensors = <&b !! 1405 thermal-sensors =
>> 1406 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2156 1407
2157 trips { 1408 trips {
2158 critical { 1409 critical {
2159 tempe 1410 temperature = <101000>;
2160 hyste 1411 hysteresis = <0>;
2161 type 1412 type = "critical";
2162 }; 1413 };
2163 }; 1414 };
2164 1415
2165 cooling-maps { 1416 cooling-maps {
2166 }; 1417 };
2167 }; 1418 };
2168 }; 1419 };
2169 1420
2170 timer { 1421 timer {
2171 compatible = "arm,armv8-timer 1422 compatible = "arm,armv8-timer";
2172 interrupts = <GIC_PPI 13 1423 interrupts = <GIC_PPI 13
2173 (GIC_CPU_MASK 1424 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2174 <GIC_PPI 14 1425 <GIC_PPI 14
2175 (GIC_CPU_MASK 1426 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2176 <GIC_PPI 11 1427 <GIC_PPI 11
2177 (GIC_CPU_MASK 1428 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2178 <GIC_PPI 10 1429 <GIC_PPI 10
2179 (GIC_CPU_MASK 1430 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2180 interrupt-parent = <&gic>; 1431 interrupt-parent = <&gic>;
2181 always-on; 1432 always-on;
2182 }; 1433 };
2183 }; 1434 };
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