1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th
11 #include <dt-bindings/memory/tegra194-mc.h>
12
13 / {
14 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 /* control backbone */
20 bus@0 {
21 compatible = "simple-bus";
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges = <0x0 0x0 0x0 0x0 0x10
26
27 apbmisc: misc@100000 {
28 compatible = "nvidia,t
29 reg = <0x0 0x00100000
30 <0x0 0x0010f000
31 };
32
33 gpio: gpio@2200000 {
34 compatible = "nvidia,t
35 reg-names = "security"
36 reg = <0x0 0x2200000 0
37 <0x0 0x2210000 0
38 interrupts = <GIC_SPI
39 <GIC_SPI
40 <GIC_SPI
41 <GIC_SPI
42 <GIC_SPI
43 <GIC_SPI
44 <GIC_SPI
45 <GIC_SPI
46 <GIC_SPI
47 <GIC_SPI
48 <GIC_SPI
49 <GIC_SPI
50 <GIC_SPI
51 <GIC_SPI
52 <GIC_SPI
53 <GIC_SPI
54 <GIC_SPI
55 <GIC_SPI
56 <GIC_SPI
57 <GIC_SPI
58 <GIC_SPI
59 <GIC_SPI
60 <GIC_SPI
61 <GIC_SPI
62 <GIC_SPI
63 <GIC_SPI
64 <GIC_SPI
65 <GIC_SPI
66 <GIC_SPI
67 <GIC_SPI
68 <GIC_SPI
69 <GIC_SPI
70 <GIC_SPI
71 <GIC_SPI
72 <GIC_SPI
73 <GIC_SPI
74 <GIC_SPI
75 <GIC_SPI
76 <GIC_SPI
77 <GIC_SPI
78 <GIC_SPI
79 <GIC_SPI
80 <GIC_SPI
81 <GIC_SPI
82 <GIC_SPI
83 <GIC_SPI
84 <GIC_SPI
85 <GIC_SPI
86 #interrupt-cells = <2>
87 interrupt-controller;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pinmux
91 };
92
93 cbb-noc@2300000 {
94 compatible = "nvidia,t
95 reg = <0x0 0x02300000
96 interrupts = <GIC_SPI
97 <GIC_SPI
98 nvidia,axi2apb = <&axi
99 nvidia,apbmisc = <&apb
100 status = "okay";
101 };
102
103 axi2apb: axi2apb@2390000 {
104 compatible = "nvidia,t
105 reg = <0x0 0x2390000 0
106 <0x0 0x23a0000 0
107 <0x0 0x23b0000 0
108 <0x0 0x23c0000 0
109 <0x0 0x23d0000 0
110 <0x0 0x23e0000 0
111 status = "okay";
112 };
113
114 pinmux: pinmux@2430000 {
115 compatible = "nvidia,t
116 reg = <0x0 0x2430000 0
117 status = "okay";
118
119 pex_clkreq_c5_bi_dir_s
120 clkreq {
121 nvidia
122 nvidia
123 nvidia
124 nvidia
125 nvidia
126 nvidia
127 };
128 };
129
130 pex_rst_c5_out_state:
131 pex_rst {
132 nvidia
133 nvidia
134 nvidia
135 nvidia
136 nvidia
137 nvidia
138 };
139 };
140 };
141
142 ethernet@2490000 {
143 compatible = "nvidia,t
144 "nvidia,t
145 "snps,dwc
146 reg = <0x0 0x02490000
147 interrupts = <GIC_SPI
148 clocks = <&bpmp TEGRA1
149 <&bpmp TEGRA1
150 <&bpmp TEGRA1
151 <&bpmp TEGRA1
152 <&bpmp TEGRA1
153 clock-names = "master_
154 resets = <&bpmp TEGRA1
155 reset-names = "eqos";
156 interconnects = <&mc T
157 <&mc T
158 interconnect-names = "
159 iommus = <&smmu TEGRA1
160 status = "disabled";
161
162 snps,write-requests =
163 snps,read-requests = <
164 snps,burst-map = <0x7>
165 snps,txpbl = <16>;
166 snps,rxpbl = <8>;
167 };
168
169 gpcdma: dma-controller@2600000
170 compatible = "nvidia,t
171 "nvidia,t
172 reg = <0x0 0x2600000 0
173 resets = <&bpmp TEGRA1
174 reset-names = "gpcdma"
175 interrupts = <GIC_SPI
176 <GIC_SPI
177 <GIC_SPI
178 <GIC_SPI
179 <GIC_SPI
180 <GIC_SPI
181 <GIC_SPI
182 <GIC_SPI
183 <GIC_SPI
184 <GIC_SPI
185 <GIC_SPI
186 <GIC_SPI
187 <GIC_SPI
188 <GIC_SPI
189 <GIC_SPI
190 <GIC_SPI
191 <GIC_SPI
192 <GIC_SPI
193 <GIC_SPI
194 <GIC_SPI
195 <GIC_SPI
196 <GIC_SPI
197 <GIC_SPI
198 <GIC_SPI
199 <GIC_SPI
200 <GIC_SPI
201 <GIC_SPI
202 <GIC_SPI
203 <GIC_SPI
204 <GIC_SPI
205 <GIC_SPI
206 <GIC_SPI
207 #dma-cells = <1>;
208 iommus = <&smmu TEGRA1
209 dma-coherent;
210 dma-channel-mask = <0x
211 status = "okay";
212 };
213
214 aconnect@2900000 {
215 compatible = "nvidia,t
216 "nvidia,t
217 clocks = <&bpmp TEGRA1
218 <&bpmp TEGRA1
219 clock-names = "ape", "
220 power-domains = <&bpmp
221 status = "disabled";
222
223 #address-cells = <2>;
224 #size-cells = <2>;
225 ranges = <0x0 0x029000
226
227 tegra_ahub: ahub@29008
228 compatible = "
229 "
230 reg = <0x0 0x0
231 clocks = <&bpm
232 clock-names =
233 assigned-clock
234 assigned-clock
235 assigned-clock
236 status = "disa
237
238 #address-cells
239 #size-cells =
240 ranges = <0x0
241
242 tegra_i2s1: i2
243 compat
244
245 reg =
246 clocks
247
248 clock-
249 assign
250 assign
251 assign
252 sound-
253 status
254 };
255
256 tegra_i2s2: i2
257 compat
258
259 reg =
260 clocks
261
262 clock-
263 assign
264 assign
265 assign
266 sound-
267 status
268 };
269
270 tegra_i2s3: i2
271 compat
272
273 reg =
274 clocks
275
276 clock-
277 assign
278 assign
279 assign
280 sound-
281 status
282 };
283
284 tegra_i2s4: i2
285 compat
286
287 reg =
288 clocks
289
290 clock-
291 assign
292 assign
293 assign
294 sound-
295 status
296 };
297
298 tegra_i2s5: i2
299 compat
300
301 reg =
302 clocks
303
304 clock-
305 assign
306 assign
307 assign
308 sound-
309 status
310 };
311
312 tegra_i2s6: i2
313 compat
314
315 reg =
316 clocks
317
318 clock-
319 assign
320 assign
321 assign
322 sound-
323 status
324 };
325
326 tegra_sfc1: sf
327 compat
328
329 reg =
330 sound-
331 status
332 };
333
334 tegra_sfc2: sf
335 compat
336
337 reg =
338 sound-
339 status
340 };
341
342 tegra_sfc3: sf
343 compat
344
345 reg =
346 sound-
347 status
348 };
349
350 tegra_sfc4: sf
351 compat
352
353 reg =
354 sound-
355 status
356 };
357
358 tegra_amx1: am
359 compat
360 reg =
361 sound-
362 status
363 };
364
365 tegra_amx2: am
366 compat
367 reg =
368 sound-
369 status
370 };
371
372 tegra_amx3: am
373 compat
374 reg =
375 sound-
376 status
377 };
378
379 tegra_amx4: am
380 compat
381 reg =
382 sound-
383 status
384 };
385
386 tegra_adx1: ad
387 compat
388
389 reg =
390 sound-
391 status
392 };
393
394 tegra_adx2: ad
395 compat
396
397 reg =
398 sound-
399 status
400 };
401
402 tegra_adx3: ad
403 compat
404
405 reg =
406 sound-
407 status
408 };
409
410 tegra_adx4: ad
411 compat
412
413 reg =
414 sound-
415 status
416 };
417
418 tegra_dmic1: d
419 compat
420
421 reg =
422 clocks
423 clock-
424 assign
425 assign
426 assign
427 sound-
428 status
429 };
430
431 tegra_dmic2: d
432 compat
433
434 reg =
435 clocks
436 clock-
437 assign
438 assign
439 assign
440 sound-
441 status
442 };
443
444 tegra_dmic3: d
445 compat
446
447 reg =
448 clocks
449 clock-
450 assign
451 assign
452 assign
453 sound-
454 status
455 };
456
457 tegra_dmic4: d
458 compat
459
460 reg =
461 clocks
462 clock-
463 assign
464 assign
465 assign
466 sound-
467 status
468 };
469
470 tegra_dspk1: d
471 compat
472
473 reg =
474 clocks
475 clock-
476 assign
477 assign
478 assign
479 sound-
480 status
481 };
482
483 tegra_dspk2: d
484 compat
485
486 reg =
487 clocks
488 clock-
489 assign
490 assign
491 assign
492 sound-
493 status
494 };
495
496 tegra_ope1: pr
497 compat
498
499 reg =
500 sound-
501 status
502
503 #addre
504 #size-
505 ranges
506
507 equali
508
509
510
511 };
512
513 dynami
514
515
516
517 };
518 };
519
520 tegra_mvc1: mv
521 compat
522
523 reg =
524 sound-
525 status
526 };
527
528 tegra_mvc2: mv
529 compat
530
531 reg =
532 sound-
533 status
534 };
535
536 tegra_amixer:
537 compat
538
539 reg =
540 sound-
541 status
542 };
543
544 tegra_admaif:
545 compat
546
547 reg =
548 dmas =
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568 dma-na
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588 status
589 interc
590
591 interc
592 iommus
593 };
594
595 tegra_asrc: as
596 compat
597
598 reg =
599 sound-
600 status
601 };
602 };
603
604 adma: dma-controller@2
605 compatible = "
606 "
607 reg = <0x0 0x0
608 interrupt-pare
609 interrupts =
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641 #dma-cells = <
642 clocks = <&bpm
643 clock-names =
644 status = "disa
645 };
646
647 agic: interrupt-contro
648 compatible = "
649 "
650 #interrupt-cel
651 interrupt-cont
652 reg = <0x0 0x0
653 <0x0 0x0
654 interrupts = <
655
656
657 clocks = <&bpm
658 clock-names =
659 status = "disa
660 };
661 };
662
663 mc: memory-controller@2c00000
664 compatible = "nvidia,t
665 reg = <0x0 0x02c00000
666 <0x0 0x02c10000
667 <0x0 0x02c20000
668 <0x0 0x02c30000
669 <0x0 0x02c40000
670 <0x0 0x02c50000
671 <0x0 0x02b80000
672 <0x0 0x02b90000
673 <0x0 0x02ba0000
674 <0x0 0x02bb0000
675 <0x0 0x01700000
676 <0x0 0x01710000
677 <0x0 0x01720000
678 <0x0 0x01730000
679 <0x0 0x01740000
680 <0x0 0x01750000
681 <0x0 0x01760000
682 <0x0 0x01770000
683 reg-names = "sid", "br
684 "ch4", "ch
685 "ch11", "c
686 interrupts = <GIC_SPI
687 #interconnect-cells =
688 status = "disabled";
689
690 #address-cells = <2>;
691 #size-cells = <2>;
692 ranges = <0x0 0x017000
693 <0x0 0x02b800
694 <0x0 0x02c000
695
696 /*
697 * Bit 39 of addresses
698 * controller selects
699 * is accessed. This i
700 * memory in the XBAR
701 * (bit 39 set) or Teg
702 *
703 * As a consequence, t
704 * that bit 39 is neve
705 * via an I/O virtual
706 * devices require acc
707 * drivers must set th
708 *
709 * Limit the DMA range
710 */
711 dma-ranges = <0x0 0x0
712
713 emc: external-memory-c
714 compatible = "
715 reg = <0x0 0x0
716 <0x0 0x0
717 interrupts = <
718 clocks = <&bpm
719 clock-names =
720
721 #interconnect-
722
723 nvidia,bpmp =
724 };
725 };
726
727 timer@3010000 {
728 compatible = "nvidia,t
729 reg = <0x0 0x03010000
730 interrupts = <GIC_SPI
731 <GIC_SPI
732 <GIC_SPI
733 <GIC_SPI
734 <GIC_SPI
735 <GIC_SPI
736 <GIC_SPI
737 <GIC_SPI
738 <GIC_SPI
739 <GIC_SPI
740 status = "okay";
741 };
742
743 uarta: serial@3100000 {
744 compatible = "nvidia,t
745 reg = <0x0 0x03100000
746 reg-shift = <2>;
747 interrupts = <GIC_SPI
748 clocks = <&bpmp TEGRA1
749 resets = <&bpmp TEGRA1
750 status = "disabled";
751 };
752
753 uartb: serial@3110000 {
754 compatible = "nvidia,t
755 reg = <0x0 0x03110000
756 reg-shift = <2>;
757 interrupts = <GIC_SPI
758 clocks = <&bpmp TEGRA1
759 resets = <&bpmp TEGRA1
760 status = "disabled";
761 };
762
763 uartd: serial@3130000 {
764 compatible = "nvidia,t
765 reg = <0x0 0x03130000
766 reg-shift = <2>;
767 interrupts = <GIC_SPI
768 clocks = <&bpmp TEGRA1
769 clock-names = "serial"
770 resets = <&bpmp TEGRA1
771 reset-names = "serial"
772 status = "disabled";
773 };
774
775 uarte: serial@3140000 {
776 compatible = "nvidia,t
777 reg = <0x0 0x03140000
778 reg-shift = <2>;
779 interrupts = <GIC_SPI
780 clocks = <&bpmp TEGRA1
781 clock-names = "serial"
782 resets = <&bpmp TEGRA1
783 reset-names = "serial"
784 status = "disabled";
785 };
786
787 uartf: serial@3150000 {
788 compatible = "nvidia,t
789 reg = <0x0 0x03150000
790 reg-shift = <2>;
791 interrupts = <GIC_SPI
792 clocks = <&bpmp TEGRA1
793 clock-names = "serial"
794 resets = <&bpmp TEGRA1
795 reset-names = "serial"
796 status = "disabled";
797 };
798
799 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t
801 reg = <0x0 0x03160000
802 interrupts = <GIC_SPI
803 #address-cells = <1>;
804 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1
806 clock-names = "div-clk
807 resets = <&bpmp TEGRA1
808 reset-names = "i2c";
809 dmas = <&gpcdma 21>, <
810 dma-names = "rx", "tx"
811 status = "disabled";
812 };
813
814 uarth: serial@3170000 {
815 compatible = "nvidia,t
816 reg = <0x0 0x03170000
817 reg-shift = <2>;
818 interrupts = <GIC_SPI
819 clocks = <&bpmp TEGRA1
820 clock-names = "serial"
821 resets = <&bpmp TEGRA1
822 reset-names = "serial"
823 status = "disabled";
824 };
825
826 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t
828 reg = <0x0 0x03180000
829 interrupts = <GIC_SPI
830 #address-cells = <1>;
831 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1
833 clock-names = "div-clk
834 resets = <&bpmp TEGRA1
835 reset-names = "i2c";
836 dmas = <&gpcdma 23>, <
837 dma-names = "rx", "tx"
838 status = "disabled";
839 };
840
841 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t
844 reg = <0x0 0x03190000
845 interrupts = <GIC_SPI
846 #address-cells = <1>;
847 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1
849 clock-names = "div-clk
850 resets = <&bpmp TEGRA1
851 reset-names = "i2c";
852 pinctrl-0 = <&state_dp
853 pinctrl-1 = <&state_dp
854 pinctrl-names = "defau
855 dmas = <&gpcdma 26>, <
856 dma-names = "rx", "tx"
857 status = "disabled";
858 };
859
860 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t
863 reg = <0x0 0x031b0000
864 interrupts = <GIC_SPI
865 #address-cells = <1>;
866 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1
868 clock-names = "div-clk
869 resets = <&bpmp TEGRA1
870 reset-names = "i2c";
871 pinctrl-0 = <&state_dp
872 pinctrl-1 = <&state_dp
873 pinctrl-names = "defau
874 dmas = <&gpcdma 30>, <
875 dma-names = "rx", "tx"
876 status = "disabled";
877 };
878
879 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t
882 reg = <0x0 0x031c0000
883 interrupts = <GIC_SPI
884 #address-cells = <1>;
885 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1
887 clock-names = "div-clk
888 resets = <&bpmp TEGRA1
889 reset-names = "i2c";
890 pinctrl-0 = <&state_dp
891 pinctrl-1 = <&state_dp
892 pinctrl-names = "defau
893 dmas = <&gpcdma 27>, <
894 dma-names = "rx", "tx"
895 status = "disabled";
896 };
897
898 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t
901 reg = <0x0 0x031e0000
902 interrupts = <GIC_SPI
903 #address-cells = <1>;
904 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1
906 clock-names = "div-clk
907 resets = <&bpmp TEGRA1
908 reset-names = "i2c";
909 pinctrl-0 = <&state_dp
910 pinctrl-1 = <&state_dp
911 pinctrl-names = "defau
912 dmas = <&gpcdma 31>, <
913 dma-names = "rx", "tx"
914 status = "disabled";
915 };
916
917 spi@3270000 {
918 compatible = "nvidia,t
919 reg = <0x0 0x3270000 0
920 interrupts = <GIC_SPI
921 #address-cells = <1>;
922 #size-cells = <0>;
923 clocks = <&bpmp TEGRA1
924 <&bpmp TEGRA1
925 clock-names = "qspi",
926 resets = <&bpmp TEGRA1
927 status = "disabled";
928 };
929
930 pwm1: pwm@3280000 {
931 compatible = "nvidia,t
932 "nvidia,t
933 reg = <0x0 0x3280000 0
934 clocks = <&bpmp TEGRA1
935 resets = <&bpmp TEGRA1
936 reset-names = "pwm";
937 status = "disabled";
938 #pwm-cells = <2>;
939 };
940
941 pwm2: pwm@3290000 {
942 compatible = "nvidia,t
943 "nvidia,t
944 reg = <0x0 0x3290000 0
945 clocks = <&bpmp TEGRA1
946 resets = <&bpmp TEGRA1
947 reset-names = "pwm";
948 status = "disabled";
949 #pwm-cells = <2>;
950 };
951
952 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t
954 "nvidia,t
955 reg = <0x0 0x32a0000 0
956 clocks = <&bpmp TEGRA1
957 resets = <&bpmp TEGRA1
958 reset-names = "pwm";
959 status = "disabled";
960 #pwm-cells = <2>;
961 };
962
963 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t
965 "nvidia,t
966 reg = <0x0 0x32c0000 0
967 clocks = <&bpmp TEGRA1
968 resets = <&bpmp TEGRA1
969 reset-names = "pwm";
970 status = "disabled";
971 #pwm-cells = <2>;
972 };
973
974 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t
976 "nvidia,t
977 reg = <0x0 0x32d0000 0
978 clocks = <&bpmp TEGRA1
979 resets = <&bpmp TEGRA1
980 reset-names = "pwm";
981 status = "disabled";
982 #pwm-cells = <2>;
983 };
984
985 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t
987 "nvidia,t
988 reg = <0x0 0x32e0000 0
989 clocks = <&bpmp TEGRA1
990 resets = <&bpmp TEGRA1
991 reset-names = "pwm";
992 status = "disabled";
993 #pwm-cells = <2>;
994 };
995
996 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t
998 "nvidia,t
999 reg = <0x0 0x32f0000 0
1000 clocks = <&bpmp TEGRA
1001 resets = <&bpmp TEGRA
1002 reset-names = "pwm";
1003 status = "disabled";
1004 #pwm-cells = <2>;
1005 };
1006
1007 spi@3300000 {
1008 compatible = "nvidia,
1009 reg = <0x0 0x3300000
1010 interrupts = <GIC_SPI
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 clocks = <&bpmp TEGRA
1014 <&bpmp TEGRA
1015 clock-names = "qspi",
1016 resets = <&bpmp TEGRA
1017 status = "disabled";
1018 };
1019
1020 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia,
1022 reg = <0x0 0x03400000
1023 interrupts = <GIC_SPI
1024 clocks = <&bpmp TEGRA
1025 <&bpmp TEGRA
1026 clock-names = "sdhci"
1027 assigned-clocks = <&b
1028 <&b
1029 assigned-clock-parent
1030 <&b
1031 <&b
1032 resets = <&bpmp TEGRA
1033 reset-names = "sdhci"
1034 interconnects = <&mc
1035 <&mc
1036 interconnect-names =
1037 iommus = <&smmu TEGRA
1038 pinctrl-names = "sdmm
1039 pinctrl-0 = <&sdmmc1_
1040 pinctrl-1 = <&sdmmc1_
1041 nvidia,pad-autocal-pu
1042
1043 nvidia,pad-autocal-pu
1044
1045 nvidia,pad-autocal-pu
1046 nvidia,pad-autocal-pu
1047
1048 nvidia,pad-autocal-pu
1049 nvidia,pad-autocal-pu
1050 nvidia,default-tap =
1051 nvidia,default-trim =
1052 sd-uhs-sdr25;
1053 sd-uhs-sdr50;
1054 sd-uhs-ddr50;
1055 sd-uhs-sdr104;
1056 status = "disabled";
1057 };
1058
1059 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia,
1061 reg = <0x0 0x03440000
1062 interrupts = <GIC_SPI
1063 clocks = <&bpmp TEGRA
1064 <&bpmp TEGRA
1065 clock-names = "sdhci"
1066 assigned-clocks = <&b
1067 <&b
1068 assigned-clock-parent
1069 <&b
1070 <&b
1071 resets = <&bpmp TEGRA
1072 reset-names = "sdhci"
1073 interconnects = <&mc
1074 <&mc
1075 interconnect-names =
1076 iommus = <&smmu TEGRA
1077 pinctrl-names = "sdmm
1078 pinctrl-0 = <&sdmmc3_
1079 pinctrl-1 = <&sdmmc3_
1080 nvidia,pad-autocal-pu
1081 nvidia,pad-autocal-pu
1082 nvidia,pad-autocal-pu
1083 nvidia,pad-autocal-pu
1084
1085 nvidia,pad-autocal-pu
1086 nvidia,pad-autocal-pu
1087
1088 nvidia,pad-autocal-pu
1089 nvidia,pad-autocal-pu
1090 nvidia,default-tap =
1091 nvidia,default-trim =
1092 sd-uhs-sdr25;
1093 sd-uhs-sdr50;
1094 sd-uhs-ddr50;
1095 sd-uhs-sdr104;
1096 status = "disabled";
1097 };
1098
1099 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia,
1101 reg = <0x0 0x03460000
1102 interrupts = <GIC_SPI
1103 clocks = <&bpmp TEGRA
1104 <&bpmp TEGRA
1105 clock-names = "sdhci"
1106 assigned-clocks = <&b
1107 <&b
1108 assigned-clock-parent
1109 <&b
1110 resets = <&bpmp TEGRA
1111 reset-names = "sdhci"
1112 interconnects = <&mc
1113 <&mc
1114 interconnect-names =
1115 iommus = <&smmu TEGRA
1116 nvidia,pad-autocal-pu
1117 nvidia,pad-autocal-pu
1118 nvidia,pad-autocal-pu
1119 nvidia,pad-autocal-pu
1120
1121 nvidia,pad-autocal-pu
1122 nvidia,pad-autocal-pu
1123
1124 nvidia,default-tap =
1125 nvidia,default-trim =
1126 nvidia,dqs-trim = <40
1127 cap-mmc-highspeed;
1128 mmc-ddr-1_8v;
1129 mmc-hs200-1_8v;
1130 mmc-hs400-1_8v;
1131 mmc-hs400-enhanced-st
1132 supports-cqe;
1133 status = "disabled";
1134 };
1135
1136 hda@3510000 {
1137 compatible = "nvidia,
1138 reg = <0x0 0x3510000
1139 interrupts = <GIC_SPI
1140 clocks = <&bpmp TEGRA
1141 <&bpmp TEGRA
1142 <&bpmp TEGRA
1143 clock-names = "hda",
1144 resets = <&bpmp TEGRA
1145 <&bpmp TEGRA
1146 reset-names = "hda",
1147 power-domains = <&bpm
1148 interconnects = <&mc
1149 <&mc
1150 interconnect-names =
1151 iommus = <&smmu TEGRA
1152 status = "disabled";
1153 };
1154
1155 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia,
1157 reg = <0x0 0x03520000
1158 <0x0 0x03540000
1159 reg-names = "padctl",
1160 interrupts = <GIC_SPI
1161
1162 resets = <&bpmp TEGRA
1163 reset-names = "padctl
1164
1165 status = "disabled";
1166
1167 pads {
1168 usb2 {
1169 clock
1170 clock
1171
1172 lanes
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196 };
1197 };
1198
1199 usb3 {
1200 lanes
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224 };
1225 };
1226 };
1227
1228 ports {
1229 usb2-0 {
1230 statu
1231 };
1232
1233 usb2-1 {
1234 statu
1235 };
1236
1237 usb2-2 {
1238 statu
1239 };
1240
1241 usb2-3 {
1242 statu
1243 };
1244
1245 usb3-0 {
1246 statu
1247 };
1248
1249 usb3-1 {
1250 statu
1251 };
1252
1253 usb3-2 {
1254 statu
1255 };
1256
1257 usb3-3 {
1258 statu
1259 };
1260 };
1261 };
1262
1263 usb@3550000 {
1264 compatible = "nvidia,
1265 reg = <0x0 0x03550000
1266 <0x0 0x03558000
1267 reg-names = "base", "
1268 interrupts = <GIC_SPI
1269 clocks = <&bpmp TEGRA
1270 <&bpmp TEGRA
1271 <&bpmp TEGRA
1272 <&bpmp TEGRA
1273 clock-names = "dev",
1274 interconnects = <&mc
1275 <&mc
1276 interconnect-names =
1277 iommus = <&smmu TEGRA
1278 power-domains = <&bpm
1279 <&bpm
1280 power-domain-names =
1281 nvidia,xusb-padctl =
1282 dma-coherent;
1283 status = "disabled";
1284 };
1285
1286 usb@3610000 {
1287 compatible = "nvidia,
1288 reg = <0x0 0x03610000
1289 <0x0 0x03600000
1290 reg-names = "hcd", "f
1291
1292 interrupts = <GIC_SPI
1293 <GIC_SPI
1294
1295 clocks = <&bpmp TEGRA
1296 <&bpmp TEGRA
1297 <&bpmp TEGRA
1298 <&bpmp TEGRA
1299 <&bpmp TEGRA
1300 <&bpmp TEGRA
1301 <&bpmp TEGRA
1302 <&bpmp TEGRA
1303 <&bpmp TEGRA
1304 clock-names = "xusb_h
1305 "xusb_s
1306 "xusb_f
1307 "pll_e"
1308 interconnects = <&mc
1309 <&mc
1310 interconnect-names =
1311 iommus = <&smmu TEGRA
1312
1313 power-domains = <&bpm
1314 <&bpm
1315 power-domain-names =
1316
1317 nvidia,xusb-padctl =
1318 status = "disabled";
1319 };
1320
1321 fuse@3820000 {
1322 compatible = "nvidia,
1323 reg = <0x0 0x03820000
1324 clocks = <&bpmp TEGRA
1325 clock-names = "fuse";
1326 };
1327
1328 gic: interrupt-controller@388
1329 compatible = "arm,gic
1330 #interrupt-cells = <3
1331 interrupt-controller;
1332 reg = <0x0 0x03881000
1333 <0x0 0x03882000
1334 <0x0 0x03884000
1335 <0x0 0x03886000
1336 interrupts = <GIC_PPI
1337 (GIC_CPU_MASK
1338 interrupt-parent = <&
1339 };
1340
1341 cec@3960000 {
1342 compatible = "nvidia,
1343 reg = <0x0 0x03960000
1344 interrupts = <GIC_SPI
1345 clocks = <&bpmp TEGRA
1346 clock-names = "cec";
1347 status = "disabled";
1348 };
1349
1350 hte_lic: hardware-timestamp@3
1351 compatible = "nvidia,
1352 reg = <0x0 0x3aa0000
1353 interrupts = <GIC_SPI
1354 nvidia,int-threshold
1355 nvidia,slices = <11>;
1356 #timestamp-cells = <1
1357 status = "okay";
1358 };
1359
1360 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia,
1362 reg = <0x0 0x03c00000
1363 interrupts = <GIC_SPI
1364 <GIC_SPI
1365 <GIC_SPI
1366 <GIC_SPI
1367 <GIC_SPI
1368 <GIC_SPI
1369 <GIC_SPI
1370 <GIC_SPI
1371 <GIC_SPI
1372 interrupt-names = "do
1373 "sh
1374 "sh
1375 #mbox-cells = <2>;
1376 };
1377
1378 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia,
1380 reg = <0x0 0x03e10000
1381 reg-names = "ctl";
1382
1383 #phy-cells = <0>;
1384 };
1385
1386 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia,
1388 reg = <0x0 0x03e20000
1389 reg-names = "ctl";
1390
1391 #phy-cells = <0>;
1392 };
1393
1394 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia,
1396 reg = <0x0 0x03e30000
1397 reg-names = "ctl";
1398
1399 #phy-cells = <0>;
1400 };
1401
1402 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia,
1404 reg = <0x0 0x03e40000
1405 reg-names = "ctl";
1406
1407 #phy-cells = <0>;
1408 };
1409
1410 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia,
1412 reg = <0x0 0x03e50000
1413 reg-names = "ctl";
1414
1415 #phy-cells = <0>;
1416 };
1417
1418 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia,
1420 reg = <0x0 0x03e60000
1421 reg-names = "ctl";
1422
1423 #phy-cells = <0>;
1424 };
1425
1426 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia,
1428 reg = <0x0 0x03e70000
1429 reg-names = "ctl";
1430
1431 #phy-cells = <0>;
1432 };
1433
1434 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia,
1436 reg = <0x0 0x03e80000
1437 reg-names = "ctl";
1438
1439 #phy-cells = <0>;
1440 };
1441
1442 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia,
1444 reg = <0x0 0x03e90000
1445 reg-names = "ctl";
1446
1447 #phy-cells = <0>;
1448 };
1449
1450 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia,
1452 reg = <0x0 0x03ea0000
1453 reg-names = "ctl";
1454
1455 #phy-cells = <0>;
1456 };
1457
1458 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia,
1460 reg = <0x0 0x03eb0000
1461 reg-names = "ctl";
1462
1463 #phy-cells = <0>;
1464 };
1465
1466 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia,
1468 reg = <0x0 0x03ec0000
1469 reg-names = "ctl";
1470
1471 #phy-cells = <0>;
1472 };
1473
1474 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia,
1476 reg = <0x0 0x03ed0000
1477 reg-names = "ctl";
1478
1479 #phy-cells = <0>;
1480 };
1481
1482 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia,
1484 reg = <0x0 0x03ee0000
1485 reg-names = "ctl";
1486
1487 #phy-cells = <0>;
1488 };
1489
1490 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia,
1492 reg = <0x0 0x03ef0000
1493 reg-names = "ctl";
1494
1495 #phy-cells = <0>;
1496 };
1497
1498 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia,
1500 reg = <0x0 0x03f00000
1501 reg-names = "ctl";
1502
1503 #phy-cells = <0>;
1504 };
1505
1506 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia,
1508 reg = <0x0 0x03f10000
1509 reg-names = "ctl";
1510
1511 #phy-cells = <0>;
1512 };
1513
1514 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia,
1516 reg = <0x0 0x03f20000
1517 reg-names = "ctl";
1518
1519 #phy-cells = <0>;
1520 };
1521
1522 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia,
1524 reg = <0x0 0x03f30000
1525 reg-names = "ctl";
1526
1527 #phy-cells = <0>;
1528 };
1529
1530 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia,
1532 reg = <0x0 0x03f40000
1533 reg-names = "ctl";
1534
1535 #phy-cells = <0>;
1536 };
1537
1538 sce-noc@b600000 {
1539 compatible = "nvidia,
1540 reg = <0x0 0xb600000
1541 interrupts = <GIC_SPI
1542 <GIC_SPI
1543 nvidia,axi2apb = <&ax
1544 nvidia,apbmisc = <&ap
1545 status = "okay";
1546 };
1547
1548 rce-noc@be00000 {
1549 compatible = "nvidia,
1550 reg = <0x0 0xbe00000
1551 interrupts = <GIC_SPI
1552 <GIC_SPI
1553 nvidia,axi2apb = <&ax
1554 nvidia,apbmisc = <&ap
1555 status = "okay";
1556 };
1557
1558 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia,
1560 reg = <0x0 0x0c150000
1561 interrupts = <GIC_SPI
1562 <GIC_SPI
1563 <GIC_SPI
1564 <GIC_SPI
1565 /*
1566 * Shared interrupt 0
1567 * we only have 4 sha
1568 */
1569 interrupt-names = "sh
1570 #mbox-cells = <2>;
1571 };
1572
1573 hte_aon: hardware-timestamp@c
1574 compatible = "nvidia,
1575 reg = <0x0 0xc1e0000
1576 interrupts = <GIC_SPI
1577 nvidia,int-threshold
1578 nvidia,slices = <3>;
1579 #timestamp-cells = <1
1580 status = "okay";
1581 };
1582
1583 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia,
1585 reg = <0x0 0x0c240000
1586 interrupts = <GIC_SPI
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA
1590 clock-names = "div-cl
1591 resets = <&bpmp TEGRA
1592 reset-names = "i2c";
1593 dmas = <&gpcdma 22>,
1594 dma-names = "rx", "tx
1595 status = "disabled";
1596 };
1597
1598 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia,
1600 reg = <0x0 0x0c250000
1601 interrupts = <GIC_SPI
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA
1605 clock-names = "div-cl
1606 resets = <&bpmp TEGRA
1607 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, <
1609 dma-names = "rx", "tx
1610 status = "disabled";
1611 };
1612
1613 uartc: serial@c280000 {
1614 compatible = "nvidia,
1615 reg = <0x0 0x0c280000
1616 reg-shift = <2>;
1617 interrupts = <GIC_SPI
1618 clocks = <&bpmp TEGRA
1619 clock-names = "serial
1620 resets = <&bpmp TEGRA
1621 reset-names = "serial
1622 status = "disabled";
1623 };
1624
1625 uartg: serial@c290000 {
1626 compatible = "nvidia,
1627 reg = <0x0 0x0c290000
1628 reg-shift = <2>;
1629 interrupts = <GIC_SPI
1630 clocks = <&bpmp TEGRA
1631 clock-names = "serial
1632 resets = <&bpmp TEGRA
1633 reset-names = "serial
1634 status = "disabled";
1635 };
1636
1637 rtc: rtc@c2a0000 {
1638 compatible = "nvidia,
1639 reg = <0x0 0x0c2a0000
1640 interrupt-parent = <&
1641 interrupts = <73 IRQ_
1642 clocks = <&bpmp TEGRA
1643 clock-names = "rtc";
1644 status = "disabled";
1645 };
1646
1647 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia,
1649 reg-names = "security
1650 reg = <0x0 0xc2f0000
1651 <0x0 0xc2f1000
1652 interrupts = <GIC_SPI
1653 <GIC_SPI
1654 <GIC_SPI
1655 <GIC_SPI
1656 gpio-controller;
1657 #gpio-cells = <2>;
1658 interrupt-controller;
1659 #interrupt-cells = <2
1660 gpio-ranges = <&pinmu
1661 };
1662
1663 pinmux_aon: pinmux@c300000 {
1664 compatible = "nvidia,
1665 reg = <0x0 0xc300000
1666
1667 status = "okay";
1668 };
1669
1670 pwm4: pwm@c340000 {
1671 compatible = "nvidia,
1672 "nvidia,
1673 reg = <0x0 0xc340000
1674 clocks = <&bpmp TEGRA
1675 resets = <&bpmp TEGRA
1676 reset-names = "pwm";
1677 status = "disabled";
1678 #pwm-cells = <2>;
1679 };
1680
1681 pmc: pmc@c360000 {
1682 compatible = "nvidia,
1683 reg = <0x0 0x0c360000
1684 <0x0 0x0c370000
1685 <0x0 0x0c380000
1686 <0x0 0x0c390000
1687 <0x0 0x0c3a0000
1688 reg-names = "pmc", "w
1689
1690 #interrupt-cells = <2
1691 interrupt-controller;
1692
1693 sdmmc1_1v8: sdmmc1-1v
1694 pins = "sdmmc
1695 power-source
1696 };
1697
1698 sdmmc1_3v3: sdmmc1-3v
1699 pins = "sdmmc
1700 power-source
1701 };
1702
1703 sdmmc3_1v8: sdmmc3-1v
1704 pins = "sdmmc
1705 power-source
1706 };
1707
1708 sdmmc3_3v3: sdmmc3-3v
1709 pins = "sdmmc
1710 power-source
1711 };
1712 };
1713
1714 aon-noc@c600000 {
1715 compatible = "nvidia,
1716 reg = <0x0 0xc600000
1717 interrupts = <GIC_SPI
1718 <GIC_SPI
1719 nvidia,apbmisc = <&ap
1720 status = "okay";
1721 };
1722
1723 bpmp-noc@d600000 {
1724 compatible = "nvidia,
1725 reg = <0x0 0xd600000
1726 interrupts = <GIC_SPI
1727 <GIC_SPI
1728 nvidia,axi2apb = <&ax
1729 nvidia,apbmisc = <&ap
1730 status = "okay";
1731 };
1732
1733 iommu@10000000 {
1734 compatible = "nvidia,
1735 reg = <0x0 0x10000000
1736 interrupts = <GIC_SPI
1737 <GIC_SPI
1738 <GIC_SPI
1739 <GIC_SPI
1740 <GIC_SPI
1741 <GIC_SPI
1742 <GIC_SPI
1743 <GIC_SPI
1744 <GIC_SPI
1745 <GIC_SPI
1746 <GIC_SPI
1747 <GIC_SPI
1748 <GIC_SPI
1749 <GIC_SPI
1750 <GIC_SPI
1751 <GIC_SPI
1752 <GIC_SPI
1753 <GIC_SPI
1754 <GIC_SPI
1755 <GIC_SPI
1756 <GIC_SPI
1757 <GIC_SPI
1758 <GIC_SPI
1759 <GIC_SPI
1760 <GIC_SPI
1761 <GIC_SPI
1762 <GIC_SPI
1763 <GIC_SPI
1764 <GIC_SPI
1765 <GIC_SPI
1766 <GIC_SPI
1767 <GIC_SPI
1768 <GIC_SPI
1769 <GIC_SPI
1770 <GIC_SPI
1771 <GIC_SPI
1772 <GIC_SPI
1773 <GIC_SPI
1774 <GIC_SPI
1775 <GIC_SPI
1776 <GIC_SPI
1777 <GIC_SPI
1778 <GIC_SPI
1779 <GIC_SPI
1780 <GIC_SPI
1781 <GIC_SPI
1782 <GIC_SPI
1783 <GIC_SPI
1784 <GIC_SPI
1785 <GIC_SPI
1786 <GIC_SPI
1787 <GIC_SPI
1788 <GIC_SPI
1789 <GIC_SPI
1790 <GIC_SPI
1791 <GIC_SPI
1792 <GIC_SPI
1793 <GIC_SPI
1794 <GIC_SPI
1795 <GIC_SPI
1796 <GIC_SPI
1797 <GIC_SPI
1798 <GIC_SPI
1799 <GIC_SPI
1800 <GIC_SPI
1801 stream-match-mask = <
1802 #global-interrupts =
1803 #iommu-cells = <1>;
1804
1805 nvidia,memory-control
1806 status = "disabled";
1807 };
1808
1809 smmu: iommu@12000000 {
1810 compatible = "nvidia,
1811 reg = <0x0 0x12000000
1812 <0x0 0x11000000
1813 interrupts = <GIC_SPI
1814 <GIC_SPI
1815 <GIC_SPI
1816 <GIC_SPI
1817 <GIC_SPI
1818 <GIC_SPI
1819 <GIC_SPI
1820 <GIC_SPI
1821 <GIC_SPI
1822 <GIC_SPI
1823 <GIC_SPI
1824 <GIC_SPI
1825 <GIC_SPI
1826 <GIC_SPI
1827 <GIC_SPI
1828 <GIC_SPI
1829 <GIC_SPI
1830 <GIC_SPI
1831 <GIC_SPI
1832 <GIC_SPI
1833 <GIC_SPI
1834 <GIC_SPI
1835 <GIC_SPI
1836 <GIC_SPI
1837 <GIC_SPI
1838 <GIC_SPI
1839 <GIC_SPI
1840 <GIC_SPI
1841 <GIC_SPI
1842 <GIC_SPI
1843 <GIC_SPI
1844 <GIC_SPI
1845 <GIC_SPI
1846 <GIC_SPI
1847 <GIC_SPI
1848 <GIC_SPI
1849 <GIC_SPI
1850 <GIC_SPI
1851 <GIC_SPI
1852 <GIC_SPI
1853 <GIC_SPI
1854 <GIC_SPI
1855 <GIC_SPI
1856 <GIC_SPI
1857 <GIC_SPI
1858 <GIC_SPI
1859 <GIC_SPI
1860 <GIC_SPI
1861 <GIC_SPI
1862 <GIC_SPI
1863 <GIC_SPI
1864 <GIC_SPI
1865 <GIC_SPI
1866 <GIC_SPI
1867 <GIC_SPI
1868 <GIC_SPI
1869 <GIC_SPI
1870 <GIC_SPI
1871 <GIC_SPI
1872 <GIC_SPI
1873 <GIC_SPI
1874 <GIC_SPI
1875 <GIC_SPI
1876 <GIC_SPI
1877 <GIC_SPI
1878 <GIC_SPI
1879 stream-match-mask = <
1880 #global-interrupts =
1881 #iommu-cells = <1>;
1882
1883 nvidia,memory-control
1884 status = "okay";
1885 };
1886
1887 host1x@13e00000 {
1888 compatible = "nvidia,
1889 reg = <0x0 0x13e00000
1890 <0x0 0x13e10000
1891 reg-names = "hypervis
1892 interrupts = <GIC_SPI
1893 <GIC_SPI
1894 interrupt-names = "sy
1895 clocks = <&bpmp TEGRA
1896 clock-names = "host1x
1897 resets = <&bpmp TEGRA
1898 reset-names = "host1x
1899
1900 #address-cells = <2>;
1901 #size-cells = <2>;
1902 ranges = <0x0 0x14800
1903
1904 interconnects = <&mc
1905 interconnect-names =
1906 iommus = <&smmu TEGRA
1907 dma-coherent;
1908
1909 /* Context isolation
1910 iommu-map = <0 &smmu
1911 <1 &smmu
1912 <2 &smmu
1913 <3 &smmu
1914 <4 &smmu
1915 <5 &smmu
1916 <6 &smmu
1917 <7 &smmu
1918
1919 nvdec@15140000 {
1920 compatible =
1921 reg = <0x0 0x
1922 clocks = <&bp
1923 clock-names =
1924 resets = <&bp
1925 reset-names =
1926
1927 power-domains
1928 interconnects
1929
1930
1931 interconnect-
1932 iommus = <&sm
1933 dma-coherent;
1934
1935 nvidia,host1x
1936 };
1937
1938 display-hub@15200000
1939 compatible =
1940 reg = <0x0 0x
1941 resets = <&bp
1942 <&bp
1943 <&bp
1944 <&bp
1945 <&bp
1946 <&bp
1947 <&bp
1948 reset-names =
1949
1950 clocks = <&bp
1951 <&bp
1952 clock-names =
1953 status = "dis
1954
1955 power-domains
1956
1957 #address-cell
1958 #size-cells =
1959 ranges = <0x0
1960
1961 display@15200
1962 compa
1963 reg =
1964 inter
1965 clock
1966 clock
1967 reset
1968 reset
1969
1970 power
1971 inter
1972
1973 inter
1974
1975 nvidi
1976 nvidi
1977 };
1978
1979 display@15210
1980 compa
1981 reg =
1982 inter
1983 clock
1984 clock
1985 reset
1986 reset
1987
1988 power
1989 inter
1990
1991 inter
1992
1993 nvidi
1994 nvidi
1995 };
1996
1997 display@15220
1998 compa
1999 reg =
2000 inter
2001 clock
2002 clock
2003 reset
2004 reset
2005
2006 power
2007 inter
2008
2009 inter
2010
2011 nvidi
2012 nvidi
2013 };
2014
2015 display@15230
2016 compa
2017 reg =
2018 inter
2019 clock
2020 clock
2021 reset
2022 reset
2023
2024 power
2025 inter
2026
2027 inter
2028
2029 nvidi
2030 nvidi
2031 };
2032 };
2033
2034 vic@15340000 {
2035 compatible =
2036 reg = <0x0 0x
2037 interrupts =
2038 clocks = <&bp
2039 clock-names =
2040 resets = <&bp
2041 reset-names =
2042
2043 power-domains
2044 interconnects
2045
2046 interconnect-
2047 iommus = <&sm
2048 dma-coherent;
2049 };
2050
2051 nvjpg@15380000 {
2052 compatible =
2053 reg = <0x0 0x
2054 clocks = <&bp
2055 clock-names =
2056 resets = <&bp
2057 reset-names =
2058
2059 power-domains
2060 interconnects
2061
2062 interconnect-
2063 iommus = <&sm
2064 dma-coherent;
2065 };
2066
2067 nvdec@15480000 {
2068 compatible =
2069 reg = <0x0 0x
2070 clocks = <&bp
2071 clock-names =
2072 resets = <&bp
2073 reset-names =
2074
2075 power-domains
2076 interconnects
2077
2078
2079 interconnect-
2080 iommus = <&sm
2081 dma-coherent;
2082
2083 nvidia,host1x
2084 };
2085
2086 nvenc@154c0000 {
2087 compatible =
2088 reg = <0x0 0x
2089 clocks = <&bp
2090 clock-names =
2091 resets = <&bp
2092 reset-names =
2093
2094 power-domains
2095 interconnects
2096
2097
2098 interconnect-
2099 iommus = <&sm
2100 dma-coherent;
2101
2102 nvidia,host1x
2103 };
2104
2105 dpaux0: dpaux@155c000
2106 compatible =
2107 reg = <0x0 0x
2108 interrupts =
2109 clocks = <&bp
2110 <&bp
2111 clock-names =
2112 resets = <&bp
2113 reset-names =
2114 status = "dis
2115
2116 power-domains
2117
2118 state_dpaux0_
2119 group
2120 funct
2121 };
2122
2123 state_dpaux0_
2124 group
2125 funct
2126 };
2127
2128 state_dpaux0_
2129 group
2130 funct
2131 };
2132
2133 i2c-bus {
2134 #addr
2135 #size
2136 };
2137 };
2138
2139 dpaux1: dpaux@155d000
2140 compatible =
2141 reg = <0x0 0x
2142 interrupts =
2143 clocks = <&bp
2144 <&bp
2145 clock-names =
2146 resets = <&bp
2147 reset-names =
2148 status = "dis
2149
2150 power-domains
2151
2152 state_dpaux1_
2153 group
2154 funct
2155 };
2156
2157 state_dpaux1_
2158 group
2159 funct
2160 };
2161
2162 state_dpaux1_
2163 group
2164 funct
2165 };
2166
2167 i2c-bus {
2168 #addr
2169 #size
2170 };
2171 };
2172
2173 dpaux2: dpaux@155e000
2174 compatible =
2175 reg = <0x0 0x
2176 interrupts =
2177 clocks = <&bp
2178 <&bp
2179 clock-names =
2180 resets = <&bp
2181 reset-names =
2182 status = "dis
2183
2184 power-domains
2185
2186 state_dpaux2_
2187 group
2188 funct
2189 };
2190
2191 state_dpaux2_
2192 group
2193 funct
2194 };
2195
2196 state_dpaux2_
2197 group
2198 funct
2199 };
2200
2201 i2c-bus {
2202 #addr
2203 #size
2204 };
2205 };
2206
2207 dpaux3: dpaux@155f000
2208 compatible =
2209 reg = <0x0 0x
2210 interrupts =
2211 clocks = <&bp
2212 <&bp
2213 clock-names =
2214 resets = <&bp
2215 reset-names =
2216 status = "dis
2217
2218 power-domains
2219
2220 state_dpaux3_
2221 group
2222 funct
2223 };
2224
2225 state_dpaux3_
2226 group
2227 funct
2228 };
2229
2230 state_dpaux3_
2231 group
2232 funct
2233 };
2234
2235 i2c-bus {
2236 #addr
2237 #size
2238 };
2239 };
2240
2241 nvenc@15a80000 {
2242 compatible =
2243 reg = <0x0 0x
2244 clocks = <&bp
2245 clock-names =
2246 resets = <&bp
2247 reset-names =
2248
2249 power-domains
2250 interconnects
2251
2252
2253 interconnect-
2254 iommus = <&sm
2255 dma-coherent;
2256
2257 nvidia,host1x
2258 };
2259
2260 sor0: sor@15b00000 {
2261 compatible =
2262 reg = <0x0 0x
2263 interrupts =
2264 clocks = <&bp
2265 <&bp
2266 <&bp
2267 <&bp
2268 <&bp
2269 <&bp
2270 clock-names =
2271
2272 resets = <&bp
2273 reset-names =
2274 pinctrl-0 = <
2275 pinctrl-1 = <
2276 pinctrl-2 = <
2277 pinctrl-names
2278 status = "dis
2279
2280 power-domains
2281 nvidia,interf
2282 };
2283
2284 sor1: sor@15b40000 {
2285 compatible =
2286 reg = <0x0 0x
2287 interrupts =
2288 clocks = <&bp
2289 <&bp
2290 <&bp
2291 <&bp
2292 <&bp
2293 <&bp
2294 clock-names =
2295
2296 resets = <&bp
2297 reset-names =
2298 pinctrl-0 = <
2299 pinctrl-1 = <
2300 pinctrl-2 = <
2301 pinctrl-names
2302 status = "dis
2303
2304 power-domains
2305 nvidia,interf
2306 };
2307
2308 sor2: sor@15b80000 {
2309 compatible =
2310 reg = <0x0 0x
2311 interrupts =
2312 clocks = <&bp
2313 <&bp
2314 <&bp
2315 <&bp
2316 <&bp
2317 <&bp
2318 clock-names =
2319
2320 resets = <&bp
2321 reset-names =
2322 pinctrl-0 = <
2323 pinctrl-1 = <
2324 pinctrl-2 = <
2325 pinctrl-names
2326 status = "dis
2327
2328 power-domains
2329 nvidia,interf
2330 };
2331
2332 sor3: sor@15bc0000 {
2333 compatible =
2334 reg = <0x0 0x
2335 interrupts =
2336 clocks = <&bp
2337 <&bp
2338 <&bp
2339 <&bp
2340 <&bp
2341 <&bp
2342 clock-names =
2343
2344 resets = <&bp
2345 reset-names =
2346 pinctrl-0 = <
2347 pinctrl-1 = <
2348 pinctrl-2 = <
2349 pinctrl-names
2350 status = "dis
2351
2352 power-domains
2353 nvidia,interf
2354 };
2355 };
2356
2357 pcie@14100000 {
2358 compatible = "nvidia,
2359 power-domains = <&bpm
2360 reg = <0x00 0x1410000
2361 <0x00 0x3000000
2362 <0x00 0x3004000
2363 <0x00 0x3008000
2364 reg-names = "appl", "
2365
2366 status = "disabled";
2367
2368 #address-cells = <3>;
2369 #size-cells = <2>;
2370 device_type = "pci";
2371 num-lanes = <1>;
2372 linux,pci-domain = <1
2373
2374 clocks = <&bpmp TEGRA
2375 clock-names = "core";
2376
2377 resets = <&bpmp TEGRA
2378 <&bpmp TEGRA
2379 reset-names = "apb",
2380
2381 interrupts = <GIC_SPI
2382 <GIC_SPI
2383 interrupt-names = "in
2384
2385 #interrupt-cells = <1
2386 interrupt-map-mask =
2387 interrupt-map = <0 0
2388
2389 nvidia,bpmp = <&bpmp
2390
2391 nvidia,aspm-cmrt-us =
2392 nvidia,aspm-pwr-on-t-
2393 nvidia,aspm-l0s-entra
2394
2395 bus-range = <0x0 0xff
2396
2397 ranges = <0x43000000
2398 <0x02000000
2399 <0x01000000
2400
2401 interconnects = <&mc
2402 <&mc
2403 interconnect-names =
2404 iommu-map = <0x0 &smm
2405 iommu-map-mask = <0x0
2406 dma-coherent;
2407 };
2408
2409 pcie@14120000 {
2410 compatible = "nvidia,
2411 power-domains = <&bpm
2412 reg = <0x00 0x1412000
2413 <0x00 0x3200000
2414 <0x00 0x3204000
2415 <0x00 0x3208000
2416 reg-names = "appl", "
2417
2418 status = "disabled";
2419
2420 #address-cells = <3>;
2421 #size-cells = <2>;
2422 device_type = "pci";
2423 num-lanes = <1>;
2424 linux,pci-domain = <2
2425
2426 clocks = <&bpmp TEGRA
2427 clock-names = "core";
2428
2429 resets = <&bpmp TEGRA
2430 <&bpmp TEGRA
2431 reset-names = "apb",
2432
2433 interrupts = <GIC_SPI
2434 <GIC_SPI
2435 interrupt-names = "in
2436
2437 #interrupt-cells = <1
2438 interrupt-map-mask =
2439 interrupt-map = <0 0
2440
2441 nvidia,bpmp = <&bpmp
2442
2443 nvidia,aspm-cmrt-us =
2444 nvidia,aspm-pwr-on-t-
2445 nvidia,aspm-l0s-entra
2446
2447 bus-range = <0x0 0xff
2448
2449 ranges = <0x43000000
2450 <0x02000000
2451 <0x01000000
2452
2453 interconnects = <&mc
2454 <&mc
2455 interconnect-names =
2456 iommu-map = <0x0 &smm
2457 iommu-map-mask = <0x0
2458 dma-coherent;
2459 };
2460
2461 pcie@14140000 {
2462 compatible = "nvidia,
2463 power-domains = <&bpm
2464 reg = <0x00 0x1414000
2465 <0x00 0x3400000
2466 <0x00 0x3404000
2467 <0x00 0x3408000
2468 reg-names = "appl", "
2469
2470 status = "disabled";
2471
2472 #address-cells = <3>;
2473 #size-cells = <2>;
2474 device_type = "pci";
2475 num-lanes = <1>;
2476 linux,pci-domain = <3
2477
2478 clocks = <&bpmp TEGRA
2479 clock-names = "core";
2480
2481 resets = <&bpmp TEGRA
2482 <&bpmp TEGRA
2483 reset-names = "apb",
2484
2485 interrupts = <GIC_SPI
2486 <GIC_SPI
2487 interrupt-names = "in
2488
2489 #interrupt-cells = <1
2490 interrupt-map-mask =
2491 interrupt-map = <0 0
2492
2493 nvidia,bpmp = <&bpmp
2494
2495 nvidia,aspm-cmrt-us =
2496 nvidia,aspm-pwr-on-t-
2497 nvidia,aspm-l0s-entra
2498
2499 bus-range = <0x0 0xff
2500
2501 ranges = <0x43000000
2502 <0x02000000
2503 <0x01000000
2504
2505 interconnects = <&mc
2506 <&mc
2507 interconnect-names =
2508 iommu-map = <0x0 &smm
2509 iommu-map-mask = <0x0
2510 dma-coherent;
2511 };
2512
2513 pcie@14160000 {
2514 compatible = "nvidia,
2515 power-domains = <&bpm
2516 reg = <0x00 0x1416000
2517 <0x00 0x3600000
2518 <0x00 0x3604000
2519 <0x00 0x3608000
2520 reg-names = "appl", "
2521
2522 status = "disabled";
2523
2524 #address-cells = <3>;
2525 #size-cells = <2>;
2526 device_type = "pci";
2527 num-lanes = <4>;
2528 linux,pci-domain = <4
2529
2530 clocks = <&bpmp TEGRA
2531 clock-names = "core";
2532
2533 resets = <&bpmp TEGRA
2534 <&bpmp TEGRA
2535 reset-names = "apb",
2536
2537 interrupts = <GIC_SPI
2538 <GIC_SPI
2539 interrupt-names = "in
2540
2541 #interrupt-cells = <1
2542 interrupt-map-mask =
2543 interrupt-map = <0 0
2544
2545 nvidia,bpmp = <&bpmp
2546
2547 nvidia,aspm-cmrt-us =
2548 nvidia,aspm-pwr-on-t-
2549 nvidia,aspm-l0s-entra
2550
2551 bus-range = <0x0 0xff
2552
2553 ranges = <0x43000000
2554 <0x02000000
2555 <0x01000000
2556
2557 interconnects = <&mc
2558 <&mc
2559 interconnect-names =
2560 iommu-map = <0x0 &smm
2561 iommu-map-mask = <0x0
2562 dma-coherent;
2563 };
2564
2565 pcie-ep@14160000 {
2566 compatible = "nvidia,
2567 power-domains = <&bpm
2568 reg = <0x00 0x1416000
2569 <0x00 0x3604000
2570 <0x00 0x3608000
2571 <0x14 0x0000000
2572 reg-names = "appl", "
2573
2574 status = "disabled";
2575
2576 num-lanes = <4>;
2577 num-ib-windows = <2>;
2578 num-ob-windows = <8>;
2579
2580 clocks = <&bpmp TEGRA
2581 clock-names = "core";
2582
2583 resets = <&bpmp TEGRA
2584 <&bpmp TEGRA
2585 reset-names = "apb",
2586
2587 interrupts = <GIC_SPI
2588 interrupt-names = "in
2589
2590 nvidia,bpmp = <&bpmp
2591
2592 nvidia,aspm-cmrt-us =
2593 nvidia,aspm-pwr-on-t-
2594 nvidia,aspm-l0s-entra
2595
2596 interconnects = <&mc
2597 <&mc
2598 interconnect-names =
2599 iommu-map = <0x0 &smm
2600 iommu-map-mask = <0x0
2601 dma-coherent;
2602 };
2603
2604 pcie@14180000 {
2605 compatible = "nvidia,
2606 power-domains = <&bpm
2607 reg = <0x00 0x1418000
2608 <0x00 0x3800000
2609 <0x00 0x3804000
2610 <0x00 0x3808000
2611 reg-names = "appl", "
2612
2613 status = "disabled";
2614
2615 #address-cells = <3>;
2616 #size-cells = <2>;
2617 device_type = "pci";
2618 num-lanes = <8>;
2619 linux,pci-domain = <0
2620
2621 clocks = <&bpmp TEGRA
2622 clock-names = "core";
2623
2624 resets = <&bpmp TEGRA
2625 <&bpmp TEGRA
2626 reset-names = "apb",
2627
2628 interrupts = <GIC_SPI
2629 <GIC_SPI
2630 interrupt-names = "in
2631
2632 #interrupt-cells = <1
2633 interrupt-map-mask =
2634 interrupt-map = <0 0
2635
2636 nvidia,bpmp = <&bpmp
2637
2638 nvidia,aspm-cmrt-us =
2639 nvidia,aspm-pwr-on-t-
2640 nvidia,aspm-l0s-entra
2641
2642 bus-range = <0x0 0xff
2643
2644 ranges = <0x43000000
2645 <0x02000000
2646 <0x01000000
2647
2648 interconnects = <&mc
2649 <&mc
2650 interconnect-names =
2651 iommu-map = <0x0 &smm
2652 iommu-map-mask = <0x0
2653 dma-coherent;
2654 };
2655
2656 pcie-ep@14180000 {
2657 compatible = "nvidia,
2658 power-domains = <&bpm
2659 reg = <0x00 0x1418000
2660 <0x00 0x3804000
2661 <0x00 0x3808000
2662 <0x18 0x0000000
2663 reg-names = "appl", "
2664
2665 status = "disabled";
2666
2667 num-lanes = <8>;
2668 num-ib-windows = <2>;
2669 num-ob-windows = <8>;
2670
2671 clocks = <&bpmp TEGRA
2672 clock-names = "core";
2673
2674 resets = <&bpmp TEGRA
2675 <&bpmp TEGRA
2676 reset-names = "apb",
2677
2678 interrupts = <GIC_SPI
2679 interrupt-names = "in
2680
2681 nvidia,bpmp = <&bpmp
2682
2683 nvidia,aspm-cmrt-us =
2684 nvidia,aspm-pwr-on-t-
2685 nvidia,aspm-l0s-entra
2686
2687 interconnects = <&mc
2688 <&mc
2689 interconnect-names =
2690 iommu-map = <0x0 &smm
2691 iommu-map-mask = <0x0
2692 dma-coherent;
2693 };
2694
2695 pcie@141a0000 {
2696 compatible = "nvidia,
2697 power-domains = <&bpm
2698 reg = <0x00 0x141a000
2699 <0x00 0x3a00000
2700 <0x00 0x3a04000
2701 <0x00 0x3a08000
2702 reg-names = "appl", "
2703
2704 status = "disabled";
2705
2706 #address-cells = <3>;
2707 #size-cells = <2>;
2708 device_type = "pci";
2709 num-lanes = <8>;
2710 linux,pci-domain = <5
2711
2712 pinctrl-names = "defa
2713 pinctrl-0 = <&pex_rst
2714
2715 clocks = <&bpmp TEGRA
2716 clock-names = "core";
2717
2718 resets = <&bpmp TEGRA
2719 <&bpmp TEGRA
2720 reset-names = "apb",
2721
2722 interrupts = <GIC_SPI
2723 <GIC_SPI
2724 interrupt-names = "in
2725
2726 nvidia,bpmp = <&bpmp
2727
2728 #interrupt-cells = <1
2729 interrupt-map-mask =
2730 interrupt-map = <0 0
2731
2732 nvidia,aspm-cmrt-us =
2733 nvidia,aspm-pwr-on-t-
2734 nvidia,aspm-l0s-entra
2735
2736 bus-range = <0x0 0xff
2737
2738 ranges = <0x43000000
2739 <0x02000000
2740 <0x01000000
2741
2742 interconnects = <&mc
2743 <&mc
2744 interconnect-names =
2745 iommu-map = <0x0 &smm
2746 iommu-map-mask = <0x0
2747 dma-coherent;
2748 };
2749
2750 pcie-ep@141a0000 {
2751 compatible = "nvidia,
2752 power-domains = <&bpm
2753 reg = <0x00 0x141a000
2754 <0x00 0x3a04000
2755 <0x00 0x3a08000
2756 <0x1c 0x0000000
2757 reg-names = "appl", "
2758
2759 status = "disabled";
2760
2761 num-lanes = <8>;
2762 num-ib-windows = <2>;
2763 num-ob-windows = <8>;
2764
2765 pinctrl-names = "defa
2766 pinctrl-0 = <&pex_clk
2767
2768 clocks = <&bpmp TEGRA
2769 clock-names = "core";
2770
2771 resets = <&bpmp TEGRA
2772 <&bpmp TEGRA
2773 reset-names = "apb",
2774
2775 interrupts = <GIC_SPI
2776 interrupt-names = "in
2777
2778 nvidia,bpmp = <&bpmp
2779
2780 nvidia,aspm-cmrt-us =
2781 nvidia,aspm-pwr-on-t-
2782 nvidia,aspm-l0s-entra
2783
2784 interconnects = <&mc
2785 <&mc
2786 interconnect-names =
2787 iommu-map = <0x0 &smm
2788 iommu-map-mask = <0x0
2789 dma-coherent;
2790 };
2791
2792 gpu@17000000 {
2793 compatible = "nvidia,
2794 reg = <0x0 0x17000000
2795 <0x0 0x18000000
2796 interrupts = <GIC_SPI
2797 <GIC_SPI
2798 interrupt-names = "st
2799 clocks = <&bpmp TEGRA
2800 <&bpmp TEGRA
2801 <&bpmp TEGRA
2802 clock-names = "gpu",
2803 resets = <&bpmp TEGRA
2804 reset-names = "gpu";
2805 dma-coherent;
2806
2807 power-domains = <&bpm
2808 interconnects = <&mc
2809 <&mc
2810 <&mc
2811 <&mc
2812 <&mc
2813 <&mc
2814 <&mc
2815 <&mc
2816 <&mc
2817 <&mc
2818 <&mc
2819 <&mc
2820 interconnect-names =
2821
2822
2823
2824 };
2825 };
2826
2827 sram@40000000 {
2828 compatible = "nvidia,tegra194
2829 reg = <0x0 0x40000000 0x0 0x5
2830
2831 #address-cells = <1>;
2832 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000
2834
2835 no-memory-wc;
2836
2837 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000
2839 label = "cpu-bpmp-tx"
2840 pool;
2841 };
2842
2843 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000
2845 label = "cpu-bpmp-rx"
2846 pool;
2847 };
2848 };
2849
2850 bpmp: bpmp {
2851 compatible = "nvidia,tegra186
2852 mboxes = <&hsp_top0 TEGRA_HSP
2853 TEGRA_HSP
2854 shmem = <&cpu_bpmp_tx>, <&cpu
2855 #clock-cells = <1>;
2856 #reset-cells = <1>;
2857 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194
2859 <&mc TEGRA194
2860 <&mc TEGRA194
2861 <&mc TEGRA194
2862 interconnect-names = "read",
2863 iommus = <&smmu TEGRA194_SID_
2864
2865 bpmp_i2c: i2c {
2866 compatible = "nvidia,
2867 nvidia,bpmp-bus-id =
2868 #address-cells = <1>;
2869 #size-cells = <0>;
2870 };
2871
2872 bpmp_thermal: thermal {
2873 compatible = "nvidia,
2874 #thermal-sensor-cells
2875 };
2876 };
2877
2878 cpus {
2879 compatible = "nvidia,tegra194
2880 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>;
2882 #size-cells = <0>;
2883
2884 cpu0_0: cpu@0 {
2885 compatible = "nvidia,
2886 device_type = "cpu";
2887 reg = <0x000>;
2888 enable-method = "psci
2889 i-cache-size = <13107
2890 i-cache-line-size = <
2891 i-cache-sets = <512>;
2892 d-cache-size = <65536
2893 d-cache-line-size = <
2894 d-cache-sets = <256>;
2895 next-level-cache = <&
2896 };
2897
2898 cpu0_1: cpu@1 {
2899 compatible = "nvidia,
2900 device_type = "cpu";
2901 reg = <0x001>;
2902 enable-method = "psci
2903 i-cache-size = <13107
2904 i-cache-line-size = <
2905 i-cache-sets = <512>;
2906 d-cache-size = <65536
2907 d-cache-line-size = <
2908 d-cache-sets = <256>;
2909 next-level-cache = <&
2910 };
2911
2912 cpu1_0: cpu@100 {
2913 compatible = "nvidia,
2914 device_type = "cpu";
2915 reg = <0x100>;
2916 enable-method = "psci
2917 i-cache-size = <13107
2918 i-cache-line-size = <
2919 i-cache-sets = <512>;
2920 d-cache-size = <65536
2921 d-cache-line-size = <
2922 d-cache-sets = <256>;
2923 next-level-cache = <&
2924 };
2925
2926 cpu1_1: cpu@101 {
2927 compatible = "nvidia,
2928 device_type = "cpu";
2929 reg = <0x101>;
2930 enable-method = "psci
2931 i-cache-size = <13107
2932 i-cache-line-size = <
2933 i-cache-sets = <512>;
2934 d-cache-size = <65536
2935 d-cache-line-size = <
2936 d-cache-sets = <256>;
2937 next-level-cache = <&
2938 };
2939
2940 cpu2_0: cpu@200 {
2941 compatible = "nvidia,
2942 device_type = "cpu";
2943 reg = <0x200>;
2944 enable-method = "psci
2945 i-cache-size = <13107
2946 i-cache-line-size = <
2947 i-cache-sets = <512>;
2948 d-cache-size = <65536
2949 d-cache-line-size = <
2950 d-cache-sets = <256>;
2951 next-level-cache = <&
2952 };
2953
2954 cpu2_1: cpu@201 {
2955 compatible = "nvidia,
2956 device_type = "cpu";
2957 reg = <0x201>;
2958 enable-method = "psci
2959 i-cache-size = <13107
2960 i-cache-line-size = <
2961 i-cache-sets = <512>;
2962 d-cache-size = <65536
2963 d-cache-line-size = <
2964 d-cache-sets = <256>;
2965 next-level-cache = <&
2966 };
2967
2968 cpu3_0: cpu@300 {
2969 compatible = "nvidia,
2970 device_type = "cpu";
2971 reg = <0x300>;
2972 enable-method = "psci
2973 i-cache-size = <13107
2974 i-cache-line-size = <
2975 i-cache-sets = <512>;
2976 d-cache-size = <65536
2977 d-cache-line-size = <
2978 d-cache-sets = <256>;
2979 next-level-cache = <&
2980 };
2981
2982 cpu3_1: cpu@301 {
2983 compatible = "nvidia,
2984 device_type = "cpu";
2985 reg = <0x301>;
2986 enable-method = "psci
2987 i-cache-size = <13107
2988 i-cache-line-size = <
2989 i-cache-sets = <512>;
2990 d-cache-size = <65536
2991 d-cache-line-size = <
2992 d-cache-sets = <256>;
2993 next-level-cache = <&
2994 };
2995
2996 cpu-map {
2997 cluster0 {
2998 core0 {
2999 cpu =
3000 };
3001
3002 core1 {
3003 cpu =
3004 };
3005 };
3006
3007 cluster1 {
3008 core0 {
3009 cpu =
3010 };
3011
3012 core1 {
3013 cpu =
3014 };
3015 };
3016
3017 cluster2 {
3018 core0 {
3019 cpu =
3020 };
3021
3022 core1 {
3023 cpu =
3024 };
3025 };
3026
3027 cluster3 {
3028 core0 {
3029 cpu =
3030 };
3031
3032 core1 {
3033 cpu =
3034 };
3035 };
3036 };
3037
3038 l2c_0: l2-cache0 {
3039 compatible = "cache";
3040 cache-unified;
3041 cache-size = <2097152
3042 cache-line-size = <64
3043 cache-sets = <2048>;
3044 cache-level = <2>;
3045 next-level-cache = <&
3046 };
3047
3048 l2c_1: l2-cache1 {
3049 compatible = "cache";
3050 cache-unified;
3051 cache-size = <2097152
3052 cache-line-size = <64
3053 cache-sets = <2048>;
3054 cache-level = <2>;
3055 next-level-cache = <&
3056 };
3057
3058 l2c_2: l2-cache2 {
3059 compatible = "cache";
3060 cache-unified;
3061 cache-size = <2097152
3062 cache-line-size = <64
3063 cache-sets = <2048>;
3064 cache-level = <2>;
3065 next-level-cache = <&
3066 };
3067
3068 l2c_3: l2-cache3 {
3069 compatible = "cache";
3070 cache-unified;
3071 cache-size = <2097152
3072 cache-line-size = <64
3073 cache-sets = <2048>;
3074 cache-level = <2>;
3075 next-level-cache = <&
3076 };
3077
3078 l3c: l3-cache {
3079 compatible = "cache";
3080 cache-unified;
3081 cache-size = <4194304
3082 cache-line-size = <64
3083 cache-level = <3>;
3084 cache-sets = <4096>;
3085 };
3086 };
3087
3088 pmu {
3089 compatible = "nvidia,carmel-p
3090 interrupts = <GIC_SPI 384 IRQ
3091 <GIC_SPI 385 IRQ
3092 <GIC_SPI 386 IRQ
3093 <GIC_SPI 387 IRQ
3094 <GIC_SPI 388 IRQ
3095 <GIC_SPI 389 IRQ
3096 <GIC_SPI 390 IRQ
3097 <GIC_SPI 391 IRQ
3098 interrupt-affinity = <&cpu0_0
3099 &cpu2_0
3100 };
3101
3102 psci {
3103 compatible = "arm,psci-1.0";
3104 status = "okay";
3105 method = "smc";
3106 };
3107
3108 tcu: serial {
3109 compatible = "nvidia,tegra194
3110 mboxes = <&hsp_top0 TEGRA_HSP
3111 <&hsp_aon TEGRA_HSP_
3112 mbox-names = "rx", "tx";
3113 };
3114
3115 sound {
3116 status = "disabled";
3117
3118 clocks = <&bpmp TEGRA194_CLK_
3119 <&bpmp TEGRA194_CLK_
3120 clock-names = "pll_a", "plla_
3121 assigned-clocks = <&bpmp TEGR
3122 <&bpmp TEGR
3123 <&bpmp TEGR
3124 assigned-clock-parents = <0>,
3125 <&bp
3126 <&bp
3127 /*
3128 * PLLA supports dynamic ramp
3129 * for this to work and oscil
3130 * for 8x and 11.025x sample
3131 */
3132 assigned-clock-rates = <25800
3133 };
3134
3135 thermal-zones {
3136 cpu-thermal {
3137 thermal-sensors = <&{
3138 status = "disabled";
3139 };
3140
3141 gpu-thermal {
3142 thermal-sensors = <&{
3143 status = "disabled";
3144 };
3145
3146 aux-thermal {
3147 thermal-sensors = <&{
3148 status = "disabled";
3149 };
3150
3151 pllx-thermal {
3152 thermal-sensors = <&{
3153 status = "disabled";
3154 };
3155
3156 ao-thermal {
3157 thermal-sensors = <&{
3158 status = "disabled";
3159 };
3160
3161 tj-thermal {
3162 thermal-sensors = <&{
3163 status = "disabled";
3164 };
3165 };
3166
3167 timer {
3168 compatible = "arm,armv8-timer
3169 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK
3171 <GIC_PPI 14
3172 (GIC_CPU_MASK
3173 <GIC_PPI 11
3174 (GIC_CPU_MASK
3175 <GIC_PPI 10
3176 (GIC_CPU_MASK
3177 interrupt-parent = <&gic>;
3178 always-on;
3179 };
3180 };
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