1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> <<
8 #include <dt-bindings/power/tegra194-powergate <<
9 #include <dt-bindings/reset/tegra194-reset.h> 6 #include <dt-bindings/reset/tegra194-reset.h>
>> 7 #include <dt-bindings/power/tegra194-powergate.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 8 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> <<
12 9
13 / { 10 / {
14 compatible = "nvidia,tegra194"; 11 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
16 #address-cells = <2>; 13 #address-cells = <2>;
17 #size-cells = <2>; 14 #size-cells = <2>;
18 15
19 /* control backbone */ 16 /* control backbone */
20 bus@0 { !! 17 cbb {
21 compatible = "simple-bus"; 18 compatible = "simple-bus";
22 !! 19 #address-cells = <1>;
23 #address-cells = <2>; !! 20 #size-cells = <1>;
24 #size-cells = <2>; !! 21 ranges = <0x0 0x0 0x0 0x40000000>;
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t <<
29 reg = <0x0 0x00100000 <<
30 <0x0 0x0010f000 <<
31 }; <<
32 22
33 gpio: gpio@2200000 { 23 gpio: gpio@2200000 {
34 compatible = "nvidia,t 24 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 25 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 26 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 27 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 28 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI <<
40 <GIC_SPI <<
41 <GIC_SPI <<
42 <GIC_SPI <<
43 <GIC_SPI <<
44 <GIC_SPI <<
45 <GIC_SPI <<
46 <GIC_SPI 29 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI <<
48 <GIC_SPI <<
49 <GIC_SPI <<
50 <GIC_SPI <<
51 <GIC_SPI <<
52 <GIC_SPI <<
53 <GIC_SPI <<
54 <GIC_SPI 30 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI <<
56 <GIC_SPI <<
57 <GIC_SPI <<
58 <GIC_SPI <<
59 <GIC_SPI <<
60 <GIC_SPI <<
61 <GIC_SPI <<
62 <GIC_SPI 31 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI <<
64 <GIC_SPI <<
65 <GIC_SPI <<
66 <GIC_SPI <<
67 <GIC_SPI <<
68 <GIC_SPI <<
69 <GIC_SPI <<
70 <GIC_SPI 32 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI !! 33 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
72 <GIC_SPI <<
73 <GIC_SPI <<
74 <GIC_SPI <<
75 <GIC_SPI <<
76 <GIC_SPI <<
77 <GIC_SPI <<
78 <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 #interrupt-cells = <2> 34 #interrupt-cells = <2>;
87 interrupt-controller; 35 interrupt-controller;
88 #gpio-cells = <2>; 36 #gpio-cells = <2>;
89 gpio-controller; 37 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 38 };
141 39
142 ethernet@2490000 { 40 ethernet@2490000 {
143 compatible = "nvidia,t !! 41 compatible = "nvidia,tegra186-eqos",
144 "nvidia,t <<
145 "snps,dwc 42 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 43 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 45 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 46 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 47 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 48 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 49 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 51 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 52 reset-names = "eqos";
156 interconnects = <&mc T <<
157 <&mc T <<
158 interconnect-names = " <<
159 iommus = <&smmu TEGRA1 <<
160 status = "disabled"; 53 status = "disabled";
161 54
162 snps,write-requests = 55 snps,write-requests = <1>;
163 snps,read-requests = < 56 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 57 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 58 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 59 snps,rxpbl = <8>;
167 }; 60 };
168 61
169 gpcdma: dma-controller@2600000 <<
170 compatible = "nvidia,t <<
171 "nvidia,t <<
172 reg = <0x0 0x2600000 0 <<
173 resets = <&bpmp TEGRA1 <<
174 reset-names = "gpcdma" <<
175 interrupts = <GIC_SPI <<
176 <GIC_SPI <<
177 <GIC_SPI <<
178 <GIC_SPI <<
179 <GIC_SPI <<
180 <GIC_SPI <<
181 <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 #dma-cells = <1>; <<
208 iommus = <&smmu TEGRA1 <<
209 dma-coherent; <<
210 dma-channel-mask = <0x <<
211 status = "okay"; <<
212 }; <<
213 <<
214 aconnect@2900000 { <<
215 compatible = "nvidia,t <<
216 "nvidia,t <<
217 clocks = <&bpmp TEGRA1 <<
218 <&bpmp TEGRA1 <<
219 clock-names = "ape", " <<
220 power-domains = <&bpmp <<
221 status = "disabled"; <<
222 <<
223 #address-cells = <2>; <<
224 #size-cells = <2>; <<
225 ranges = <0x0 0x029000 <<
226 <<
227 tegra_ahub: ahub@29008 <<
228 compatible = " <<
229 " <<
230 reg = <0x0 0x0 <<
231 clocks = <&bpm <<
232 clock-names = <<
233 assigned-clock <<
234 assigned-clock <<
235 assigned-clock <<
236 status = "disa <<
237 <<
238 #address-cells <<
239 #size-cells = <<
240 ranges = <0x0 <<
241 <<
242 tegra_i2s1: i2 <<
243 compat <<
244 <<
245 reg = <<
246 clocks <<
247 <<
248 clock- <<
249 assign <<
250 assign <<
251 assign <<
252 sound- <<
253 status <<
254 }; <<
255 <<
256 tegra_i2s2: i2 <<
257 compat <<
258 <<
259 reg = <<
260 clocks <<
261 <<
262 clock- <<
263 assign <<
264 assign <<
265 assign <<
266 sound- <<
267 status <<
268 }; <<
269 <<
270 tegra_i2s3: i2 <<
271 compat <<
272 <<
273 reg = <<
274 clocks <<
275 <<
276 clock- <<
277 assign <<
278 assign <<
279 assign <<
280 sound- <<
281 status <<
282 }; <<
283 <<
284 tegra_i2s4: i2 <<
285 compat <<
286 <<
287 reg = <<
288 clocks <<
289 <<
290 clock- <<
291 assign <<
292 assign <<
293 assign <<
294 sound- <<
295 status <<
296 }; <<
297 <<
298 tegra_i2s5: i2 <<
299 compat <<
300 <<
301 reg = <<
302 clocks <<
303 <<
304 clock- <<
305 assign <<
306 assign <<
307 assign <<
308 sound- <<
309 status <<
310 }; <<
311 <<
312 tegra_i2s6: i2 <<
313 compat <<
314 <<
315 reg = <<
316 clocks <<
317 <<
318 clock- <<
319 assign <<
320 assign <<
321 assign <<
322 sound- <<
323 status <<
324 }; <<
325 <<
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d <<
419 compat <<
420 <<
421 reg = <<
422 clocks <<
423 clock- <<
424 assign <<
425 assign <<
426 assign <<
427 sound- <<
428 status <<
429 }; <<
430 <<
431 tegra_dmic2: d <<
432 compat <<
433 <<
434 reg = <<
435 clocks <<
436 clock- <<
437 assign <<
438 assign <<
439 assign <<
440 sound- <<
441 status <<
442 }; <<
443 <<
444 tegra_dmic3: d <<
445 compat <<
446 <<
447 reg = <<
448 clocks <<
449 clock- <<
450 assign <<
451 assign <<
452 assign <<
453 sound- <<
454 status <<
455 }; <<
456 <<
457 tegra_dmic4: d <<
458 compat <<
459 <<
460 reg = <<
461 clocks <<
462 clock- <<
463 assign <<
464 assign <<
465 assign <<
466 sound- <<
467 status <<
468 }; <<
469 <<
470 tegra_dspk1: d <<
471 compat <<
472 <<
473 reg = <<
474 clocks <<
475 clock- <<
476 assign <<
477 assign <<
478 assign <<
479 sound- <<
480 status <<
481 }; <<
482 <<
483 tegra_dspk2: d <<
484 compat <<
485 <<
486 reg = <<
487 clocks <<
488 clock- <<
489 assign <<
490 assign <<
491 assign <<
492 sound- <<
493 status <<
494 }; <<
495 <<
496 tegra_ope1: pr <<
497 compat <<
498 <<
499 reg = <<
500 sound- <<
501 status <<
502 <<
503 #addre <<
504 #size- <<
505 ranges <<
506 <<
507 equali <<
508 <<
509 <<
510 <<
511 }; <<
512 <<
513 dynami <<
514 <<
515 <<
516 <<
517 }; <<
518 }; <<
519 <<
520 tegra_mvc1: mv <<
521 compat <<
522 <<
523 reg = <<
524 sound- <<
525 status <<
526 }; <<
527 <<
528 tegra_mvc2: mv <<
529 compat <<
530 <<
531 reg = <<
532 sound- <<
533 status <<
534 }; <<
535 <<
536 tegra_amixer: <<
537 compat <<
538 <<
539 reg = <<
540 sound- <<
541 status <<
542 }; <<
543 <<
544 tegra_admaif: <<
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 <<
595 tegra_asrc: as <<
596 compat <<
597 <<
598 reg = <<
599 sound- <<
600 status <<
601 }; <<
602 }; <<
603 <<
604 adma: dma-controller@2 <<
605 compatible = " <<
606 " <<
607 reg = <0x0 0x0 <<
608 interrupt-pare <<
609 interrupts = <<
610 <<
611 <<
612 <<
613 <<
614 <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; <<
646 <<
647 agic: interrupt-contro <<
648 compatible = " <<
649 " <<
650 #interrupt-cel <<
651 interrupt-cont <<
652 reg = <0x0 0x0 <<
653 <0x0 0x0 <<
654 interrupts = < <<
655 <<
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; <<
661 }; <<
662 <<
663 mc: memory-controller@2c00000 <<
664 compatible = "nvidia,t <<
665 reg = <0x0 0x02c00000 <<
666 <0x0 0x02c10000 <<
667 <0x0 0x02c20000 <<
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI <<
687 #interconnect-cells = <<
688 status = "disabled"; <<
689 <<
690 #address-cells = <2>; <<
691 #size-cells = <2>; <<
692 ranges = <0x0 0x017000 <<
693 <0x0 0x02b800 <<
694 <0x0 0x02c000 <<
695 <<
696 /* <<
697 * Bit 39 of addresses <<
698 * controller selects <<
699 * is accessed. This i <<
700 * memory in the XBAR <<
701 * (bit 39 set) or Teg <<
702 * <<
703 * As a consequence, t <<
704 * that bit 39 is neve <<
705 * via an I/O virtual <<
706 * devices require acc <<
707 * drivers must set th <<
708 * <<
709 * Limit the DMA range <<
710 */ <<
711 dma-ranges = <0x0 0x0 <<
712 <<
713 emc: external-memory-c <<
714 compatible = " <<
715 reg = <0x0 0x0 <<
716 <0x0 0x0 <<
717 interrupts = < <<
718 clocks = <&bpm <<
719 clock-names = <<
720 <<
721 #interconnect- <<
722 <<
723 nvidia,bpmp = <<
724 }; <<
725 }; <<
726 <<
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 62 uarta: serial@3100000 {
744 compatible = "nvidia,t 63 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 64 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 65 reg-shift = <2>;
747 interrupts = <GIC_SPI 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 67 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 68 clock-names = "serial";
749 resets = <&bpmp TEGRA1 69 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 70 reset-names = "serial";
750 status = "disabled"; 71 status = "disabled";
751 }; 72 };
752 73
753 uartb: serial@3110000 { 74 uartb: serial@3110000 {
754 compatible = "nvidia,t 75 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 76 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 77 reg-shift = <2>;
757 interrupts = <GIC_SPI 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 79 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 80 clock-names = "serial";
759 resets = <&bpmp TEGRA1 81 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 82 reset-names = "serial";
760 status = "disabled"; 83 status = "disabled";
761 }; 84 };
762 85
763 uartd: serial@3130000 { 86 uartd: serial@3130000 {
764 compatible = "nvidia,t 87 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 88 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 89 reg-shift = <2>;
767 interrupts = <GIC_SPI 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 91 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 92 clock-names = "serial";
770 resets = <&bpmp TEGRA1 93 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 94 reset-names = "serial";
772 status = "disabled"; 95 status = "disabled";
773 }; 96 };
774 97
775 uarte: serial@3140000 { 98 uarte: serial@3140000 {
776 compatible = "nvidia,t 99 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 100 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 101 reg-shift = <2>;
779 interrupts = <GIC_SPI 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 103 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 104 clock-names = "serial";
782 resets = <&bpmp TEGRA1 105 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 106 reset-names = "serial";
784 status = "disabled"; 107 status = "disabled";
785 }; 108 };
786 109
787 uartf: serial@3150000 { 110 uartf: serial@3150000 {
788 compatible = "nvidia,t 111 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 112 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 113 reg-shift = <2>;
791 interrupts = <GIC_SPI 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 115 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 116 clock-names = "serial";
794 resets = <&bpmp TEGRA1 117 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 118 reset-names = "serial";
796 status = "disabled"; 119 status = "disabled";
797 }; 120 };
798 121
799 gen1_i2c: i2c@3160000 { 122 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 123 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 124 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 126 #address-cells = <1>;
804 #size-cells = <0>; 127 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 128 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 129 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 130 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 131 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 132 status = "disabled";
812 }; 133 };
813 134
814 uarth: serial@3170000 { 135 uarth: serial@3170000 {
815 compatible = "nvidia,t 136 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 137 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 138 reg-shift = <2>;
818 interrupts = <GIC_SPI 139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 140 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 141 clock-names = "serial";
821 resets = <&bpmp TEGRA1 142 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 143 reset-names = "serial";
823 status = "disabled"; 144 status = "disabled";
824 }; 145 };
825 146
826 cam_i2c: i2c@3180000 { 147 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 148 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 149 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 150 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 151 #address-cells = <1>;
831 #size-cells = <0>; 152 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 153 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 154 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 155 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 156 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 157 status = "disabled";
839 }; 158 };
840 159
841 /* shares pads with dpaux1 */ 160 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 161 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 162 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 163 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 164 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 165 #address-cells = <1>;
847 #size-cells = <0>; 166 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 167 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 168 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 169 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 170 reset-names = "i2c";
852 pinctrl-0 = <&state_dp <<
853 pinctrl-1 = <&state_dp <<
854 pinctrl-names = "defau <<
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 171 status = "disabled";
858 }; 172 };
859 173
860 /* shares pads with dpaux0 */ 174 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 175 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 176 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 177 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 179 #address-cells = <1>;
866 #size-cells = <0>; 180 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 181 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 182 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 183 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 184 reset-names = "i2c";
871 pinctrl-0 = <&state_dp <<
872 pinctrl-1 = <&state_dp <<
873 pinctrl-names = "defau <<
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 185 status = "disabled";
877 }; 186 };
878 187
879 /* shares pads with dpaux2 */ !! 188 gen7_i2c: i2c@31c0000 {
880 dp_aux_ch2_i2c: i2c@31c0000 { <<
881 compatible = "nvidia,t 189 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 190 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 192 #address-cells = <1>;
885 #size-cells = <0>; 193 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 194 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 195 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 196 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 197 reset-names = "i2c";
890 pinctrl-0 = <&state_dp <<
891 pinctrl-1 = <&state_dp <<
892 pinctrl-names = "defau <<
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 198 status = "disabled";
896 }; 199 };
897 200
898 /* shares pads with dpaux3 */ !! 201 gen9_i2c: i2c@31e0000 {
899 dp_aux_ch3_i2c: i2c@31e0000 { <<
900 compatible = "nvidia,t 202 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 203 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 205 #address-cells = <1>;
904 #size-cells = <0>; 206 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 207 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 208 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 209 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 210 reset-names = "i2c";
909 pinctrl-0 = <&state_dp <<
910 pinctrl-1 = <&state_dp <<
911 pinctrl-names = "defau <<
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 spi@3270000 { <<
918 compatible = "nvidia,t <<
919 reg = <0x0 0x3270000 0 <<
920 interrupts = <GIC_SPI <<
921 #address-cells = <1>; <<
922 #size-cells = <0>; <<
923 clocks = <&bpmp TEGRA1 <<
924 <&bpmp TEGRA1 <<
925 clock-names = "qspi", <<
926 resets = <&bpmp TEGRA1 <<
927 status = "disabled"; 211 status = "disabled";
928 }; 212 };
929 213
930 pwm1: pwm@3280000 { 214 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 215 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 216 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 217 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 218 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 219 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 220 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 221 reset-names = "pwm";
937 status = "disabled"; 222 status = "disabled";
938 #pwm-cells = <2>; 223 #pwm-cells = <2>;
939 }; 224 };
940 225
941 pwm2: pwm@3290000 { 226 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 227 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 228 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 229 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 230 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 231 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 232 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 233 reset-names = "pwm";
948 status = "disabled"; 234 status = "disabled";
949 #pwm-cells = <2>; 235 #pwm-cells = <2>;
950 }; 236 };
951 237
952 pwm3: pwm@32a0000 { 238 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 239 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 240 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 241 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 242 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 243 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 244 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 245 reset-names = "pwm";
959 status = "disabled"; 246 status = "disabled";
960 #pwm-cells = <2>; 247 #pwm-cells = <2>;
961 }; 248 };
962 249
963 pwm5: pwm@32c0000 { 250 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 251 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 252 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 253 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 254 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 255 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 256 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 257 reset-names = "pwm";
970 status = "disabled"; 258 status = "disabled";
971 #pwm-cells = <2>; 259 #pwm-cells = <2>;
972 }; 260 };
973 261
974 pwm6: pwm@32d0000 { 262 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 263 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 264 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 265 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 266 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 267 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 268 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 269 reset-names = "pwm";
981 status = "disabled"; 270 status = "disabled";
982 #pwm-cells = <2>; 271 #pwm-cells = <2>;
983 }; 272 };
984 273
985 pwm7: pwm@32e0000 { 274 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 275 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 276 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 277 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 278 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 279 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 280 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 281 reset-names = "pwm";
992 status = "disabled"; 282 status = "disabled";
993 #pwm-cells = <2>; 283 #pwm-cells = <2>;
994 }; 284 };
995 285
996 pwm8: pwm@32f0000 { 286 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 287 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 288 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 289 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 290 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 291 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 292 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 293 reset-names = "pwm";
1003 status = "disabled"; 294 status = "disabled";
1004 #pwm-cells = <2>; 295 #pwm-cells = <2>;
1005 }; 296 };
1006 297
1007 spi@3300000 { !! 298 sdmmc1: sdhci@3400000 {
1008 compatible = "nvidia, !! 299 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1009 reg = <0x0 0x3300000 !! 300 reg = <0x03400000 0x10000>;
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { <<
1021 compatible = "nvidia, <<
1022 reg = <0x0 0x03400000 <<
1023 interrupts = <GIC_SPI 301 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA !! 302 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
1025 <&bpmp TEGRA !! 303 clock-names = "sdhci";
1026 clock-names = "sdhci" <<
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 304 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 305 reset-names = "sdhci";
1034 interconnects = <&mc <<
1035 <&mc <<
1036 interconnect-names = <<
1037 iommus = <&smmu TEGRA <<
1038 pinctrl-names = "sdmm <<
1039 pinctrl-0 = <&sdmmc1_ <<
1040 pinctrl-1 = <&sdmmc1_ <<
1041 nvidia,pad-autocal-pu <<
1042 <<
1043 nvidia,pad-autocal-pu <<
1044 <<
1045 nvidia,pad-autocal-pu <<
1046 nvidia,pad-autocal-pu <<
1047 <<
1048 nvidia,pad-autocal-pu <<
1049 nvidia,pad-autocal-pu <<
1050 nvidia,default-tap = <<
1051 nvidia,default-trim = <<
1052 sd-uhs-sdr25; <<
1053 sd-uhs-sdr50; <<
1054 sd-uhs-ddr50; <<
1055 sd-uhs-sdr104; <<
1056 status = "disabled"; 306 status = "disabled";
1057 }; 307 };
1058 308
1059 sdmmc3: mmc@3440000 { !! 309 sdmmc3: sdhci@3440000 {
1060 compatible = "nvidia, !! 310 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1061 reg = <0x0 0x03440000 !! 311 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA !! 313 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
1064 <&bpmp TEGRA !! 314 clock-names = "sdhci";
1065 clock-names = "sdhci" <<
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 315 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 316 reset-names = "sdhci";
1073 interconnects = <&mc <<
1074 <&mc <<
1075 interconnect-names = <<
1076 iommus = <&smmu TEGRA <<
1077 pinctrl-names = "sdmm <<
1078 pinctrl-0 = <&sdmmc3_ <<
1079 pinctrl-1 = <&sdmmc3_ <<
1080 nvidia,pad-autocal-pu <<
1081 nvidia,pad-autocal-pu <<
1082 nvidia,pad-autocal-pu <<
1083 nvidia,pad-autocal-pu <<
1084 <<
1085 nvidia,pad-autocal-pu <<
1086 nvidia,pad-autocal-pu <<
1087 <<
1088 nvidia,pad-autocal-pu <<
1089 nvidia,pad-autocal-pu <<
1090 nvidia,default-tap = <<
1091 nvidia,default-trim = <<
1092 sd-uhs-sdr25; <<
1093 sd-uhs-sdr50; <<
1094 sd-uhs-ddr50; <<
1095 sd-uhs-sdr104; <<
1096 status = "disabled"; 317 status = "disabled";
1097 }; 318 };
1098 319
1099 sdmmc4: mmc@3460000 { !! 320 sdmmc4: sdhci@3460000 {
1100 compatible = "nvidia, !! 321 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1101 reg = <0x0 0x03460000 !! 322 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA !! 324 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
1104 <&bpmp TEGRA !! 325 clock-names = "sdhci";
1105 clock-names = "sdhci" <<
1106 assigned-clocks = <&b <<
1107 <&b <<
1108 assigned-clock-parent <<
1109 <&b <<
1110 resets = <&bpmp TEGRA 326 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 327 reset-names = "sdhci";
1112 interconnects = <&mc <<
1113 <&mc <<
1114 interconnect-names = <<
1115 iommus = <&smmu TEGRA <<
1116 nvidia,pad-autocal-pu <<
1117 nvidia,pad-autocal-pu <<
1118 nvidia,pad-autocal-pu <<
1119 nvidia,pad-autocal-pu <<
1120 <<
1121 nvidia,pad-autocal-pu <<
1122 nvidia,pad-autocal-pu <<
1123 <<
1124 nvidia,default-tap = <<
1125 nvidia,default-trim = <<
1126 nvidia,dqs-trim = <40 <<
1127 cap-mmc-highspeed; <<
1128 mmc-ddr-1_8v; <<
1129 mmc-hs200-1_8v; <<
1130 mmc-hs400-1_8v; <<
1131 mmc-hs400-enhanced-st <<
1132 supports-cqe; <<
1133 status = "disabled"; 328 status = "disabled";
1134 }; 329 };
1135 330
1136 hda@3510000 { 331 hda@3510000 {
1137 compatible = "nvidia, !! 332 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 333 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 334 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 335 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA !! 336 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
1142 <&bpmp TEGRA !! 337 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
1143 clock-names = "hda", !! 338 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
1144 resets = <&bpmp TEGRA 339 resets = <&bpmp TEGRA194_RESET_HDA>,
>> 340 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
1145 <&bpmp TEGRA 341 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", !! 342 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
1147 power-domains = <&bpm 343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc <<
1149 <&mc <<
1150 interconnect-names = <<
1151 iommus = <&smmu TEGRA <<
1152 status = "disabled"; 344 status = "disabled";
1153 }; 345 };
1154 346
1155 xusb_padctl: padctl@3520000 { <<
1156 compatible = "nvidia, <<
1157 reg = <0x0 0x03520000 <<
1158 <0x0 0x03540000 <<
1159 reg-names = "padctl", <<
1160 interrupts = <GIC_SPI <<
1161 <<
1162 resets = <&bpmp TEGRA <<
1163 reset-names = "padctl <<
1164 <<
1165 status = "disabled"; <<
1166 <<
1167 pads { <<
1168 usb2 { <<
1169 clock <<
1170 clock <<
1171 <<
1172 lanes <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 <<
1178 <<
1179 <<
1180 <<
1181 <<
1182 <<
1183 <<
1184 <<
1185 <<
1186 <<
1187 <<
1188 <<
1189 <<
1190 <<
1191 <<
1192 <<
1193 <<
1194 <<
1195 <<
1196 }; <<
1197 }; <<
1198 <<
1199 usb3 { <<
1200 lanes <<
1201 <<
1202 <<
1203 <<
1204 <<
1205 <<
1206 <<
1207 <<
1208 <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 <<
1214 <<
1215 <<
1216 <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 <<
1222 <<
1223 <<
1224 }; <<
1225 }; <<
1226 }; <<
1227 <<
1228 ports { <<
1229 usb2-0 { <<
1230 statu <<
1231 }; <<
1232 <<
1233 usb2-1 { <<
1234 statu <<
1235 }; <<
1236 <<
1237 usb2-2 { <<
1238 statu <<
1239 }; <<
1240 <<
1241 usb2-3 { <<
1242 statu <<
1243 }; <<
1244 <<
1245 usb3-0 { <<
1246 statu <<
1247 }; <<
1248 <<
1249 usb3-1 { <<
1250 statu <<
1251 }; <<
1252 <<
1253 usb3-2 { <<
1254 statu <<
1255 }; <<
1256 <<
1257 usb3-3 { <<
1258 statu <<
1259 }; <<
1260 }; <<
1261 }; <<
1262 <<
1263 usb@3550000 { <<
1264 compatible = "nvidia, <<
1265 reg = <0x0 0x03550000 <<
1266 <0x0 0x03558000 <<
1267 reg-names = "base", " <<
1268 interrupts = <GIC_SPI <<
1269 clocks = <&bpmp TEGRA <<
1270 <&bpmp TEGRA <<
1271 <&bpmp TEGRA <<
1272 <&bpmp TEGRA <<
1273 clock-names = "dev", <<
1274 interconnects = <&mc <<
1275 <&mc <<
1276 interconnect-names = <<
1277 iommus = <&smmu TEGRA <<
1278 power-domains = <&bpm <<
1279 <&bpm <<
1280 power-domain-names = <<
1281 nvidia,xusb-padctl = <<
1282 dma-coherent; <<
1283 status = "disabled"; <<
1284 }; <<
1285 <<
1286 usb@3610000 { <<
1287 compatible = "nvidia, <<
1288 reg = <0x0 0x03610000 <<
1289 <0x0 0x03600000 <<
1290 reg-names = "hcd", "f <<
1291 <<
1292 interrupts = <GIC_SPI <<
1293 <GIC_SPI <<
1294 <<
1295 clocks = <&bpmp TEGRA <<
1296 <&bpmp TEGRA <<
1297 <&bpmp TEGRA <<
1298 <&bpmp TEGRA <<
1299 <&bpmp TEGRA <<
1300 <&bpmp TEGRA <<
1301 <&bpmp TEGRA <<
1302 <&bpmp TEGRA <<
1303 <&bpmp TEGRA <<
1304 clock-names = "xusb_h <<
1305 "xusb_s <<
1306 "xusb_f <<
1307 "pll_e" <<
1308 interconnects = <&mc <<
1309 <&mc <<
1310 interconnect-names = <<
1311 iommus = <&smmu TEGRA <<
1312 <<
1313 power-domains = <&bpm <<
1314 <&bpm <<
1315 power-domain-names = <<
1316 <<
1317 nvidia,xusb-padctl = <<
1318 status = "disabled"; <<
1319 }; <<
1320 <<
1321 fuse@3820000 { <<
1322 compatible = "nvidia, <<
1323 reg = <0x0 0x03820000 <<
1324 clocks = <&bpmp TEGRA <<
1325 clock-names = "fuse"; <<
1326 }; <<
1327 <<
1328 gic: interrupt-controller@388 347 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 348 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 349 #interrupt-cells = <3>;
1331 interrupt-controller; 350 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 351 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 352 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 353 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 354 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 355 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 357 interrupt-parent = <&gic>;
1339 }; 358 };
1340 359
1341 cec@3960000 { 360 cec@3960000 {
1342 compatible = "nvidia, 361 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 362 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 363 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 364 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 365 clock-names = "cec";
1347 status = "disabled"; 366 status = "disabled";
1348 }; 367 };
1349 368
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 369 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, !! 370 compatible = "nvidia,tegra186-hsp";
1362 reg = <0x0 0x03c00000 !! 371 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI !! 372 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1364 <GIC_SPI !! 373 interrupt-names = "doorbell";
1365 <GIC_SPI <<
1366 <GIC_SPI <<
1367 <GIC_SPI <<
1368 <GIC_SPI <<
1369 <GIC_SPI <<
1370 <GIC_SPI <<
1371 <GIC_SPI <<
1372 interrupt-names = "do <<
1373 "sh <<
1374 "sh <<
1375 #mbox-cells = <2>; 374 #mbox-cells = <2>;
1376 }; 375 };
1377 376
1378 p2u_hsio_0: phy@3e10000 { <<
1379 compatible = "nvidia, <<
1380 reg = <0x0 0x03e10000 <<
1381 reg-names = "ctl"; <<
1382 <<
1383 #phy-cells = <0>; <<
1384 }; <<
1385 <<
1386 p2u_hsio_1: phy@3e20000 { <<
1387 compatible = "nvidia, <<
1388 reg = <0x0 0x03e20000 <<
1389 reg-names = "ctl"; <<
1390 <<
1391 #phy-cells = <0>; <<
1392 }; <<
1393 <<
1394 p2u_hsio_2: phy@3e30000 { <<
1395 compatible = "nvidia, <<
1396 reg = <0x0 0x03e30000 <<
1397 reg-names = "ctl"; <<
1398 <<
1399 #phy-cells = <0>; <<
1400 }; <<
1401 <<
1402 p2u_hsio_3: phy@3e40000 { <<
1403 compatible = "nvidia, <<
1404 reg = <0x0 0x03e40000 <<
1405 reg-names = "ctl"; <<
1406 <<
1407 #phy-cells = <0>; <<
1408 }; <<
1409 <<
1410 p2u_hsio_4: phy@3e50000 { <<
1411 compatible = "nvidia, <<
1412 reg = <0x0 0x03e50000 <<
1413 reg-names = "ctl"; <<
1414 <<
1415 #phy-cells = <0>; <<
1416 }; <<
1417 <<
1418 p2u_hsio_5: phy@3e60000 { <<
1419 compatible = "nvidia, <<
1420 reg = <0x0 0x03e60000 <<
1421 reg-names = "ctl"; <<
1422 <<
1423 #phy-cells = <0>; <<
1424 }; <<
1425 <<
1426 p2u_hsio_6: phy@3e70000 { <<
1427 compatible = "nvidia, <<
1428 reg = <0x0 0x03e70000 <<
1429 reg-names = "ctl"; <<
1430 <<
1431 #phy-cells = <0>; <<
1432 }; <<
1433 <<
1434 p2u_hsio_7: phy@3e80000 { <<
1435 compatible = "nvidia, <<
1436 reg = <0x0 0x03e80000 <<
1437 reg-names = "ctl"; <<
1438 <<
1439 #phy-cells = <0>; <<
1440 }; <<
1441 <<
1442 p2u_hsio_8: phy@3e90000 { <<
1443 compatible = "nvidia, <<
1444 reg = <0x0 0x03e90000 <<
1445 reg-names = "ctl"; <<
1446 <<
1447 #phy-cells = <0>; <<
1448 }; <<
1449 <<
1450 p2u_hsio_9: phy@3ea0000 { <<
1451 compatible = "nvidia, <<
1452 reg = <0x0 0x03ea0000 <<
1453 reg-names = "ctl"; <<
1454 <<
1455 #phy-cells = <0>; <<
1456 }; <<
1457 <<
1458 p2u_nvhs_0: phy@3eb0000 { <<
1459 compatible = "nvidia, <<
1460 reg = <0x0 0x03eb0000 <<
1461 reg-names = "ctl"; <<
1462 <<
1463 #phy-cells = <0>; <<
1464 }; <<
1465 <<
1466 p2u_nvhs_1: phy@3ec0000 { <<
1467 compatible = "nvidia, <<
1468 reg = <0x0 0x03ec0000 <<
1469 reg-names = "ctl"; <<
1470 <<
1471 #phy-cells = <0>; <<
1472 }; <<
1473 <<
1474 p2u_nvhs_2: phy@3ed0000 { <<
1475 compatible = "nvidia, <<
1476 reg = <0x0 0x03ed0000 <<
1477 reg-names = "ctl"; <<
1478 <<
1479 #phy-cells = <0>; <<
1480 }; <<
1481 <<
1482 p2u_nvhs_3: phy@3ee0000 { <<
1483 compatible = "nvidia, <<
1484 reg = <0x0 0x03ee0000 <<
1485 reg-names = "ctl"; <<
1486 <<
1487 #phy-cells = <0>; <<
1488 }; <<
1489 <<
1490 p2u_nvhs_4: phy@3ef0000 { <<
1491 compatible = "nvidia, <<
1492 reg = <0x0 0x03ef0000 <<
1493 reg-names = "ctl"; <<
1494 <<
1495 #phy-cells = <0>; <<
1496 }; <<
1497 <<
1498 p2u_nvhs_5: phy@3f00000 { <<
1499 compatible = "nvidia, <<
1500 reg = <0x0 0x03f00000 <<
1501 reg-names = "ctl"; <<
1502 <<
1503 #phy-cells = <0>; <<
1504 }; <<
1505 <<
1506 p2u_nvhs_6: phy@3f10000 { <<
1507 compatible = "nvidia, <<
1508 reg = <0x0 0x03f10000 <<
1509 reg-names = "ctl"; <<
1510 <<
1511 #phy-cells = <0>; <<
1512 }; <<
1513 <<
1514 p2u_nvhs_7: phy@3f20000 { <<
1515 compatible = "nvidia, <<
1516 reg = <0x0 0x03f20000 <<
1517 reg-names = "ctl"; <<
1518 <<
1519 #phy-cells = <0>; <<
1520 }; <<
1521 <<
1522 p2u_hsio_10: phy@3f30000 { <<
1523 compatible = "nvidia, <<
1524 reg = <0x0 0x03f30000 <<
1525 reg-names = "ctl"; <<
1526 <<
1527 #phy-cells = <0>; <<
1528 }; <<
1529 <<
1530 p2u_hsio_11: phy@3f40000 { <<
1531 compatible = "nvidia, <<
1532 reg = <0x0 0x03f40000 <<
1533 reg-names = "ctl"; <<
1534 <<
1535 #phy-cells = <0>; <<
1536 }; <<
1537 <<
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { <<
1559 compatible = "nvidia, <<
1560 reg = <0x0 0x0c150000 <<
1561 interrupts = <GIC_SPI <<
1562 <GIC_SPI <<
1563 <GIC_SPI <<
1564 <GIC_SPI <<
1565 /* <<
1566 * Shared interrupt 0 <<
1567 * we only have 4 sha <<
1568 */ <<
1569 interrupt-names = "sh <<
1570 #mbox-cells = <2>; <<
1571 }; <<
1572 <<
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 377 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 378 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 379 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 381 #address-cells = <1>;
1588 #size-cells = <0>; 382 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 383 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 384 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 385 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 386 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 387 status = "disabled";
1596 }; 388 };
1597 389
1598 gen8_i2c: i2c@c250000 { 390 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 391 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 392 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 394 #address-cells = <1>;
1603 #size-cells = <0>; 395 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 396 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 397 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 398 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 399 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 400 status = "disabled";
1611 }; 401 };
1612 402
1613 uartc: serial@c280000 { 403 uartc: serial@c280000 {
1614 compatible = "nvidia, 404 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 405 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 406 reg-shift = <2>;
1617 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 408 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 409 clock-names = "serial";
1620 resets = <&bpmp TEGRA 410 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 411 reset-names = "serial";
1622 status = "disabled"; 412 status = "disabled";
1623 }; 413 };
1624 414
1625 uartg: serial@c290000 { 415 uartg: serial@c290000 {
1626 compatible = "nvidia, 416 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 417 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 418 reg-shift = <2>;
1629 interrupts = <GIC_SPI 419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 420 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 421 clock-names = "serial";
1632 resets = <&bpmp TEGRA 422 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 423 reset-names = "serial";
1634 status = "disabled"; 424 status = "disabled";
1635 }; 425 };
1636 426
1637 rtc: rtc@c2a0000 { 427 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 428 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 429 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 430 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 431 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 432 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 433 clock-names = "rtc";
1644 status = "disabled"; 434 status = "disabled";
1645 }; 435 };
1646 436
1647 gpio_aon: gpio@c2f0000 { 437 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 438 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 439 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 440 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 441 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 443 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 444 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 445 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1656 gpio-controller; 446 gpio-controller;
1657 #gpio-cells = <2>; 447 #gpio-cells = <2>;
1658 interrupt-controller; 448 interrupt-controller;
1659 #interrupt-cells = <2 449 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 450 };
1669 451
1670 pwm4: pwm@c340000 { 452 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 453 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 454 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 455 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 456 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 457 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 458 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 459 reset-names = "pwm";
1677 status = "disabled"; 460 status = "disabled";
1678 #pwm-cells = <2>; 461 #pwm-cells = <2>;
1679 }; 462 };
1680 463
1681 pmc: pmc@c360000 { 464 pmc: pmc@c360000 {
1682 compatible = "nvidia, 465 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 466 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 467 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 468 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 469 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 470 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 471 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 472
1690 #interrupt-cells = <2 473 #interrupt-cells = <2>;
1691 interrupt-controller; 474 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v <<
1699 pins = "sdmmc <<
1700 power-source <<
1701 }; <<
1702 <<
1703 sdmmc3_1v8: sdmmc3-1v <<
1704 pins = "sdmmc <<
1705 power-source <<
1706 }; <<
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v <<
1709 pins = "sdmmc <<
1710 power-source <<
1711 }; <<
1712 }; <<
1713 <<
1714 aon-noc@c600000 { <<
1715 compatible = "nvidia, <<
1716 reg = <0x0 0xc600000 <<
1717 interrupts = <GIC_SPI <<
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 <<
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; <<
1732 <<
1733 iommu@10000000 { <<
1734 compatible = "nvidia, <<
1735 reg = <0x0 0x10000000 <<
1736 interrupts = <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 <GIC_SPI <<
1747 <GIC_SPI <<
1748 <GIC_SPI <<
1749 <GIC_SPI <<
1750 <GIC_SPI <<
1751 <GIC_SPI <<
1752 <GIC_SPI <<
1753 <GIC_SPI <<
1754 <GIC_SPI <<
1755 <GIC_SPI <<
1756 <GIC_SPI <<
1757 <GIC_SPI <<
1758 <GIC_SPI <<
1759 <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 <GIC_SPI <<
1770 <GIC_SPI <<
1771 <GIC_SPI <<
1772 <GIC_SPI <<
1773 <GIC_SPI <<
1774 <GIC_SPI <<
1775 <GIC_SPI <<
1776 <GIC_SPI <<
1777 <GIC_SPI <<
1778 <GIC_SPI <<
1779 <GIC_SPI <<
1780 <GIC_SPI <<
1781 <GIC_SPI <<
1782 <GIC_SPI <<
1783 <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 <GIC_SPI <<
1792 <GIC_SPI <<
1793 <GIC_SPI <<
1794 <GIC_SPI <<
1795 <GIC_SPI <<
1796 <GIC_SPI <<
1797 <GIC_SPI <<
1798 <GIC_SPI <<
1799 <GIC_SPI <<
1800 <GIC_SPI <<
1801 stream-match-mask = < <<
1802 #global-interrupts = <<
1803 #iommu-cells = <1>; <<
1804 <<
1805 nvidia,memory-control <<
1806 status = "disabled"; <<
1807 }; <<
1808 <<
1809 smmu: iommu@12000000 { <<
1810 compatible = "nvidia, <<
1811 reg = <0x0 0x12000000 <<
1812 <0x0 0x11000000 <<
1813 interrupts = <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 <GIC_SPI <<
1834 <GIC_SPI <<
1835 <GIC_SPI <<
1836 <GIC_SPI <<
1837 <GIC_SPI <<
1838 <GIC_SPI <<
1839 <GIC_SPI <<
1840 <GIC_SPI <<
1841 <GIC_SPI <<
1842 <GIC_SPI <<
1843 <GIC_SPI <<
1844 <GIC_SPI <<
1845 <GIC_SPI <<
1846 <GIC_SPI <<
1847 <GIC_SPI <<
1848 <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 <GIC_SPI <<
1857 <GIC_SPI <<
1858 <GIC_SPI <<
1859 <GIC_SPI <<
1860 <GIC_SPI <<
1861 <GIC_SPI <<
1862 <GIC_SPI <<
1863 <GIC_SPI <<
1864 <GIC_SPI <<
1865 <GIC_SPI <<
1866 <GIC_SPI <<
1867 <GIC_SPI <<
1868 <GIC_SPI <<
1869 <GIC_SPI <<
1870 <GIC_SPI <<
1871 <GIC_SPI <<
1872 <GIC_SPI <<
1873 <GIC_SPI <<
1874 <GIC_SPI <<
1875 <GIC_SPI <<
1876 <GIC_SPI <<
1877 <GIC_SPI <<
1878 <GIC_SPI <<
1879 stream-match-mask = < <<
1880 #global-interrupts = <<
1881 #iommu-cells = <1>; <<
1882 <<
1883 nvidia,memory-control <<
1884 status = "okay"; <<
1885 }; 475 };
1886 476
1887 host1x@13e00000 { 477 host1x@13e00000 {
1888 compatible = "nvidia, !! 478 compatible = "nvidia,tegra194-host1x", "simple-bus";
1889 reg = <0x0 0x13e00000 !! 479 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 480 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 481 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 483 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy <<
1895 clocks = <&bpmp TEGRA 484 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 485 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 486 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 487 reset-names = "host1x";
1899 488
1900 #address-cells = <2>; !! 489 #address-cells = <1>;
1901 #size-cells = <2>; !! 490 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 <<
1904 interconnects = <&mc <<
1905 interconnect-names = <<
1906 iommus = <&smmu TEGRA <<
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 <<
1919 nvdec@15140000 { <<
1920 compatible = <<
1921 reg = <0x0 0x <<
1922 clocks = <&bp <<
1923 clock-names = <<
1924 resets = <&bp <<
1925 reset-names = <<
1926 <<
1927 power-domains <<
1928 interconnects <<
1929 <<
1930 <<
1931 interconnect- <<
1932 iommus = <&sm <<
1933 dma-coherent; <<
1934 491
1935 nvidia,host1x !! 492 ranges = <0x15000000 0x15000000 0x01000000>;
1936 }; <<
1937 493
1938 display-hub@15200000 494 display-hub@15200000 {
1939 compatible = !! 495 compatible = "nvidia,tegra194-display", "simple-bus";
1940 reg = <0x0 0x !! 496 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 497 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 498 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 499 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 500 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 501 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 502 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 503 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 504 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 505 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 506 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 507 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 508 clock-names = "disp", "hub";
1953 status = "dis 509 status = "disabled";
1954 510
1955 power-domains 511 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 512
1957 #address-cell !! 513 #address-cells = <1>;
1958 #size-cells = !! 514 #size-cells = <1>;
1959 ranges = <0x0 !! 515
>> 516 ranges = <0x15200000 0x15200000 0x40000>;
1960 517
1961 display@15200 518 display@15200000 {
1962 compa 519 compatible = "nvidia,tegra194-dc";
1963 reg = !! 520 reg = <0x15200000 0x10000>;
1964 inter 521 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 522 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 523 clock-names = "dc";
1967 reset 524 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 525 reset-names = "dc";
1969 526
1970 power 527 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter <<
1972 <<
1973 inter <<
1974 528
1975 nvidi 529 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 530 nvidia,head = <0>;
1977 }; 531 };
1978 532
1979 display@15210 533 display@15210000 {
1980 compa 534 compatible = "nvidia,tegra194-dc";
1981 reg = !! 535 reg = <0x15210000 0x10000>;
1982 inter 536 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 537 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 538 clock-names = "dc";
1985 reset 539 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 540 reset-names = "dc";
1987 541
1988 power 542 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter <<
1990 <<
1991 inter <<
1992 543
1993 nvidi 544 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 545 nvidia,head = <1>;
1995 }; 546 };
1996 547
1997 display@15220 548 display@15220000 {
1998 compa 549 compatible = "nvidia,tegra194-dc";
1999 reg = !! 550 reg = <0x15220000 0x10000>;
2000 inter 551 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 552 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 553 clock-names = "dc";
2003 reset 554 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 555 reset-names = "dc";
2005 556
2006 power 557 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter <<
2008 <<
2009 inter <<
2010 558
2011 nvidi 559 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 560 nvidia,head = <2>;
2013 }; 561 };
2014 562
2015 display@15230 563 display@15230000 {
2016 compa 564 compatible = "nvidia,tegra194-dc";
2017 reg = !! 565 reg = <0x15230000 0x10000>;
2018 inter 566 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 567 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 568 clock-names = "dc";
2021 reset 569 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 570 reset-names = "dc";
2023 571
2024 power 572 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter <<
2026 <<
2027 inter <<
2028 573
2029 nvidi 574 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 575 nvidia,head = <3>;
2031 }; 576 };
2032 }; 577 };
2033 578
2034 vic@15340000 { 579 vic@15340000 {
2035 compatible = 580 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 581 reg = <0x15340000 0x00040000>;
2037 interrupts = 582 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 583 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 584 clock-names = "vic";
2040 resets = <&bp 585 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 586 reset-names = "vic";
2042 587
2043 power-domains 588 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects <<
2045 <<
2046 interconnect- <<
2047 iommus = <&sm <<
2048 dma-coherent; <<
2049 }; <<
2050 <<
2051 nvjpg@15380000 { <<
2052 compatible = <<
2053 reg = <0x0 0x <<
2054 clocks = <&bp <<
2055 clock-names = <<
2056 resets = <&bp <<
2057 reset-names = <<
2058 <<
2059 power-domains <<
2060 interconnects <<
2061 <<
2062 interconnect- <<
2063 iommus = <&sm <<
2064 dma-coherent; <<
2065 }; <<
2066 <<
2067 nvdec@15480000 { <<
2068 compatible = <<
2069 reg = <0x0 0x <<
2070 clocks = <&bp <<
2071 clock-names = <<
2072 resets = <&bp <<
2073 reset-names = <<
2074 <<
2075 power-domains <<
2076 interconnects <<
2077 <<
2078 <<
2079 interconnect- <<
2080 iommus = <&sm <<
2081 dma-coherent; <<
2082 <<
2083 nvidia,host1x <<
2084 }; <<
2085 <<
2086 nvenc@154c0000 { <<
2087 compatible = <<
2088 reg = <0x0 0x <<
2089 clocks = <&bp <<
2090 clock-names = <<
2091 resets = <&bp <<
2092 reset-names = <<
2093 <<
2094 power-domains <<
2095 interconnects <<
2096 <<
2097 <<
2098 interconnect- <<
2099 iommus = <&sm <<
2100 dma-coherent; <<
2101 <<
2102 nvidia,host1x <<
2103 }; 589 };
2104 590
2105 dpaux0: dpaux@155c000 591 dpaux0: dpaux@155c0000 {
2106 compatible = 592 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 593 reg = <0x155c0000 0x10000>;
2108 interrupts = 594 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 595 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 596 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 597 clock-names = "dpaux", "parent";
2112 resets = <&bp 598 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 599 reset-names = "dpaux";
2114 status = "dis 600 status = "disabled";
2115 601
2116 power-domains 602 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 603
2118 state_dpaux0_ 604 state_dpaux0_aux: pinmux-aux {
2119 group 605 groups = "dpaux-io";
2120 funct 606 function = "aux";
2121 }; 607 };
2122 608
2123 state_dpaux0_ 609 state_dpaux0_i2c: pinmux-i2c {
2124 group 610 groups = "dpaux-io";
2125 funct 611 function = "i2c";
2126 }; 612 };
2127 613
2128 state_dpaux0_ 614 state_dpaux0_off: pinmux-off {
2129 group 615 groups = "dpaux-io";
2130 funct 616 function = "off";
2131 }; 617 };
2132 618
2133 i2c-bus { 619 i2c-bus {
2134 #addr 620 #address-cells = <1>;
2135 #size 621 #size-cells = <0>;
2136 }; 622 };
2137 }; 623 };
2138 624
2139 dpaux1: dpaux@155d000 625 dpaux1: dpaux@155d0000 {
2140 compatible = 626 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 627 reg = <0x155d0000 0x10000>;
2142 interrupts = 628 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 629 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 630 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 631 clock-names = "dpaux", "parent";
2146 resets = <&bp 632 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 633 reset-names = "dpaux";
2148 status = "dis 634 status = "disabled";
2149 635
2150 power-domains 636 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 637
2152 state_dpaux1_ 638 state_dpaux1_aux: pinmux-aux {
2153 group 639 groups = "dpaux-io";
2154 funct 640 function = "aux";
2155 }; 641 };
2156 642
2157 state_dpaux1_ 643 state_dpaux1_i2c: pinmux-i2c {
2158 group 644 groups = "dpaux-io";
2159 funct 645 function = "i2c";
2160 }; 646 };
2161 647
2162 state_dpaux1_ 648 state_dpaux1_off: pinmux-off {
2163 group 649 groups = "dpaux-io";
2164 funct 650 function = "off";
2165 }; 651 };
2166 652
2167 i2c-bus { 653 i2c-bus {
2168 #addr 654 #address-cells = <1>;
2169 #size 655 #size-cells = <0>;
2170 }; 656 };
2171 }; 657 };
2172 658
2173 dpaux2: dpaux@155e000 659 dpaux2: dpaux@155e0000 {
2174 compatible = 660 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 661 reg = <0x155e0000 0x10000>;
2176 interrupts = 662 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 663 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 664 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 665 clock-names = "dpaux", "parent";
2180 resets = <&bp 666 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 667 reset-names = "dpaux";
2182 status = "dis 668 status = "disabled";
2183 669
2184 power-domains 670 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 671
2186 state_dpaux2_ 672 state_dpaux2_aux: pinmux-aux {
2187 group 673 groups = "dpaux-io";
2188 funct 674 function = "aux";
2189 }; 675 };
2190 676
2191 state_dpaux2_ 677 state_dpaux2_i2c: pinmux-i2c {
2192 group 678 groups = "dpaux-io";
2193 funct 679 function = "i2c";
2194 }; 680 };
2195 681
2196 state_dpaux2_ 682 state_dpaux2_off: pinmux-off {
2197 group 683 groups = "dpaux-io";
2198 funct 684 function = "off";
2199 }; 685 };
2200 686
2201 i2c-bus { 687 i2c-bus {
2202 #addr 688 #address-cells = <1>;
2203 #size 689 #size-cells = <0>;
2204 }; 690 };
2205 }; 691 };
2206 692
2207 dpaux3: dpaux@155f000 693 dpaux3: dpaux@155f0000 {
2208 compatible = 694 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 695 reg = <0x155f0000 0x10000>;
2210 interrupts = 696 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 697 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 698 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 699 clock-names = "dpaux", "parent";
2214 resets = <&bp 700 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 701 reset-names = "dpaux";
2216 status = "dis 702 status = "disabled";
2217 703
2218 power-domains 704 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 705
2220 state_dpaux3_ 706 state_dpaux3_aux: pinmux-aux {
2221 group 707 groups = "dpaux-io";
2222 funct 708 function = "aux";
2223 }; 709 };
2224 710
2225 state_dpaux3_ 711 state_dpaux3_i2c: pinmux-i2c {
2226 group 712 groups = "dpaux-io";
2227 funct 713 function = "i2c";
2228 }; 714 };
2229 715
2230 state_dpaux3_ 716 state_dpaux3_off: pinmux-off {
2231 group 717 groups = "dpaux-io";
2232 funct 718 function = "off";
2233 }; 719 };
2234 720
2235 i2c-bus { 721 i2c-bus {
2236 #addr 722 #address-cells = <1>;
2237 #size 723 #size-cells = <0>;
2238 }; 724 };
2239 }; 725 };
2240 726
2241 nvenc@15a80000 { <<
2242 compatible = <<
2243 reg = <0x0 0x <<
2244 clocks = <&bp <<
2245 clock-names = <<
2246 resets = <&bp <<
2247 reset-names = <<
2248 <<
2249 power-domains <<
2250 interconnects <<
2251 <<
2252 <<
2253 interconnect- <<
2254 iommus = <&sm <<
2255 dma-coherent; <<
2256 <<
2257 nvidia,host1x <<
2258 }; <<
2259 <<
2260 sor0: sor@15b00000 { 727 sor0: sor@15b00000 {
2261 compatible = 728 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 729 reg = <0x15b00000 0x40000>;
2263 interrupts = 730 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 731 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 732 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 733 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 734 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 735 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 736 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 737 clock-names = "sor", "out", "parent", "dp", "safe",
2271 738 "pad";
2272 resets = <&bp 739 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 740 reset-names = "sor";
2274 pinctrl-0 = < 741 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 742 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 743 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 744 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 745 status = "disabled";
2279 746
2280 power-domains 747 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 748 nvidia,interface = <0>;
2282 }; 749 };
2283 750
2284 sor1: sor@15b40000 { 751 sor1: sor@15b40000 {
2285 compatible = 752 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 753 reg = <0x155c0000 0x40000>;
2287 interrupts = 754 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 755 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 756 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 757 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 758 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 759 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 760 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 761 clock-names = "sor", "out", "parent", "dp", "safe",
2295 762 "pad";
2296 resets = <&bp 763 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 764 reset-names = "sor";
2298 pinctrl-0 = < 765 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 766 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 767 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 768 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 769 status = "disabled";
2303 770
2304 power-domains 771 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 772 nvidia,interface = <1>;
2306 }; 773 };
2307 774
2308 sor2: sor@15b80000 { 775 sor2: sor@15b80000 {
2309 compatible = 776 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 777 reg = <0x15b80000 0x40000>;
2311 interrupts = 778 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 779 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 780 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 781 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 782 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 783 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 784 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 785 clock-names = "sor", "out", "parent", "dp", "safe",
2319 786 "pad";
2320 resets = <&bp 787 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 788 reset-names = "sor";
2322 pinctrl-0 = < 789 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 790 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 791 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 792 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 793 status = "disabled";
2327 794
2328 power-domains 795 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 796 nvidia,interface = <2>;
2330 }; 797 };
2331 798
2332 sor3: sor@15bc0000 { 799 sor3: sor@15bc0000 {
2333 compatible = 800 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 801 reg = <0x15bc0000 0x40000>;
2335 interrupts = 802 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 803 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 804 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 805 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 806 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 807 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 808 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 809 clock-names = "sor", "out", "parent", "dp", "safe",
2343 810 "pad";
2344 resets = <&bp 811 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 812 reset-names = "sor";
2346 pinctrl-0 = < 813 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 814 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 815 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 816 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 817 status = "disabled";
2351 818
2352 power-domains 819 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 820 nvidia,interface = <3>;
2354 }; 821 };
2355 }; 822 };
2356 <<
2357 pcie@14100000 { <<
2358 compatible = "nvidia, <<
2359 power-domains = <&bpm <<
2360 reg = <0x00 0x1410000 <<
2361 <0x00 0x3000000 <<
2362 <0x00 0x3004000 <<
2363 <0x00 0x3008000 <<
2364 reg-names = "appl", " <<
2365 <<
2366 status = "disabled"; <<
2367 <<
2368 #address-cells = <3>; <<
2369 #size-cells = <2>; <<
2370 device_type = "pci"; <<
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 <<
2377 resets = <&bpmp TEGRA <<
2378 <&bpmp TEGRA <<
2379 reset-names = "apb", <<
2380 <<
2381 interrupts = <GIC_SPI <<
2382 <GIC_SPI <<
2383 interrupt-names = "in <<
2384 <<
2385 #interrupt-cells = <1 <<
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 <<
2389 nvidia,bpmp = <&bpmp <<
2390 <<
2391 nvidia,aspm-cmrt-us = <<
2392 nvidia,aspm-pwr-on-t- <<
2393 nvidia,aspm-l0s-entra <<
2394 <<
2395 bus-range = <0x0 0xff <<
2396 <<
2397 ranges = <0x43000000 <<
2398 <0x02000000 <<
2399 <0x01000000 <<
2400 <<
2401 interconnects = <&mc <<
2402 <&mc <<
2403 interconnect-names = <<
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 <<
2409 pcie@14120000 { <<
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 <<
2418 status = "disabled"; <<
2419 <<
2420 #address-cells = <3>; <<
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 <<
2426 clocks = <&bpmp TEGRA <<
2427 clock-names = "core"; <<
2428 <<
2429 resets = <&bpmp TEGRA <<
2430 <&bpmp TEGRA <<
2431 reset-names = "apb", <<
2432 <<
2433 interrupts = <GIC_SPI <<
2434 <GIC_SPI <<
2435 interrupt-names = "in <<
2436 <<
2437 #interrupt-cells = <1 <<
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 <<
2441 nvidia,bpmp = <&bpmp <<
2442 <<
2443 nvidia,aspm-cmrt-us = <<
2444 nvidia,aspm-pwr-on-t- <<
2445 nvidia,aspm-l0s-entra <<
2446 <<
2447 bus-range = <0x0 0xff <<
2448 <<
2449 ranges = <0x43000000 <<
2450 <0x02000000 <<
2451 <0x01000000 <<
2452 <<
2453 interconnects = <&mc <<
2454 <&mc <<
2455 interconnect-names = <<
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 <<
2461 pcie@14140000 { <<
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 <<
2470 status = "disabled"; <<
2471 <<
2472 #address-cells = <3>; <<
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 <<
2478 clocks = <&bpmp TEGRA <<
2479 clock-names = "core"; <<
2480 <<
2481 resets = <&bpmp TEGRA <<
2482 <&bpmp TEGRA <<
2483 reset-names = "apb", <<
2484 <<
2485 interrupts = <GIC_SPI <<
2486 <GIC_SPI <<
2487 interrupt-names = "in <<
2488 <<
2489 #interrupt-cells = <1 <<
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 <<
2493 nvidia,bpmp = <&bpmp <<
2494 <<
2495 nvidia,aspm-cmrt-us = <<
2496 nvidia,aspm-pwr-on-t- <<
2497 nvidia,aspm-l0s-entra <<
2498 <<
2499 bus-range = <0x0 0xff <<
2500 <<
2501 ranges = <0x43000000 <<
2502 <0x02000000 <<
2503 <0x01000000 <<
2504 <<
2505 interconnects = <&mc <<
2506 <&mc <<
2507 interconnect-names = <<
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 <<
2513 pcie@14160000 { <<
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 <<
2522 status = "disabled"; <<
2523 <<
2524 #address-cells = <3>; <<
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 <<
2530 clocks = <&bpmp TEGRA <<
2531 clock-names = "core"; <<
2532 <<
2533 resets = <&bpmp TEGRA <<
2534 <&bpmp TEGRA <<
2535 reset-names = "apb", <<
2536 <<
2537 interrupts = <GIC_SPI <<
2538 <GIC_SPI <<
2539 interrupt-names = "in <<
2540 <<
2541 #interrupt-cells = <1 <<
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 <<
2545 nvidia,bpmp = <&bpmp <<
2546 <<
2547 nvidia,aspm-cmrt-us = <<
2548 nvidia,aspm-pwr-on-t- <<
2549 nvidia,aspm-l0s-entra <<
2550 <<
2551 bus-range = <0x0 0xff <<
2552 <<
2553 ranges = <0x43000000 <<
2554 <0x02000000 <<
2555 <0x01000000 <<
2556 <<
2557 interconnects = <&mc <<
2558 <&mc <<
2559 interconnect-names = <<
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 <<
2565 pcie-ep@14160000 { <<
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 <<
2574 status = "disabled"; <<
2575 <<
2576 num-lanes = <4>; <<
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 <<
2580 clocks = <&bpmp TEGRA <<
2581 clock-names = "core"; <<
2582 <<
2583 resets = <&bpmp TEGRA <<
2584 <&bpmp TEGRA <<
2585 reset-names = "apb", <<
2586 <<
2587 interrupts = <GIC_SPI <<
2588 interrupt-names = "in <<
2589 <<
2590 nvidia,bpmp = <&bpmp <<
2591 <<
2592 nvidia,aspm-cmrt-us = <<
2593 nvidia,aspm-pwr-on-t- <<
2594 nvidia,aspm-l0s-entra <<
2595 <<
2596 interconnects = <&mc <<
2597 <&mc <<
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 <<
2604 pcie@14180000 { <<
2605 compatible = "nvidia, <<
2606 power-domains = <&bpm <<
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 <<
2613 status = "disabled"; <<
2614 <<
2615 #address-cells = <3>; <<
2616 #size-cells = <2>; <<
2617 device_type = "pci"; <<
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 <<
2621 clocks = <&bpmp TEGRA <<
2622 clock-names = "core"; <<
2623 <<
2624 resets = <&bpmp TEGRA <<
2625 <&bpmp TEGRA <<
2626 reset-names = "apb", <<
2627 <<
2628 interrupts = <GIC_SPI <<
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 <<
2632 #interrupt-cells = <1 <<
2633 interrupt-map-mask = <<
2634 interrupt-map = <0 0 <<
2635 <<
2636 nvidia,bpmp = <&bpmp <<
2637 <<
2638 nvidia,aspm-cmrt-us = <<
2639 nvidia,aspm-pwr-on-t- <<
2640 nvidia,aspm-l0s-entra <<
2641 <<
2642 bus-range = <0x0 0xff <<
2643 <<
2644 ranges = <0x43000000 <<
2645 <0x02000000 <<
2646 <0x01000000 <<
2647 <<
2648 interconnects = <&mc <<
2649 <&mc <<
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 <<
2656 pcie-ep@14180000 { <<
2657 compatible = "nvidia, <<
2658 power-domains = <&bpm <<
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 <<
2665 status = "disabled"; <<
2666 <<
2667 num-lanes = <8>; <<
2668 num-ib-windows = <2>; <<
2669 num-ob-windows = <8>; <<
2670 <<
2671 clocks = <&bpmp TEGRA <<
2672 clock-names = "core"; <<
2673 <<
2674 resets = <&bpmp TEGRA <<
2675 <&bpmp TEGRA <<
2676 reset-names = "apb", <<
2677 <<
2678 interrupts = <GIC_SPI <<
2679 interrupt-names = "in <<
2680 <<
2681 nvidia,bpmp = <&bpmp <<
2682 <<
2683 nvidia,aspm-cmrt-us = <<
2684 nvidia,aspm-pwr-on-t- <<
2685 nvidia,aspm-l0s-entra <<
2686 <<
2687 interconnects = <&mc <<
2688 <&mc <<
2689 interconnect-names = <<
2690 iommu-map = <0x0 &smm <<
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 <<
2695 pcie@141a0000 { <<
2696 compatible = "nvidia, <<
2697 power-domains = <&bpm <<
2698 reg = <0x00 0x141a000 <<
2699 <0x00 0x3a00000 <<
2700 <0x00 0x3a04000 <<
2701 <0x00 0x3a08000 <<
2702 reg-names = "appl", " <<
2703 <<
2704 status = "disabled"; <<
2705 <<
2706 #address-cells = <3>; <<
2707 #size-cells = <2>; <<
2708 device_type = "pci"; <<
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 <<
2712 pinctrl-names = "defa <<
2713 pinctrl-0 = <&pex_rst <<
2714 <<
2715 clocks = <&bpmp TEGRA <<
2716 clock-names = "core"; <<
2717 <<
2718 resets = <&bpmp TEGRA <<
2719 <&bpmp TEGRA <<
2720 reset-names = "apb", <<
2721 <<
2722 interrupts = <GIC_SPI <<
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 <<
2726 nvidia,bpmp = <&bpmp <<
2727 <<
2728 #interrupt-cells = <1 <<
2729 interrupt-map-mask = <<
2730 interrupt-map = <0 0 <<
2731 <<
2732 nvidia,aspm-cmrt-us = <<
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 <<
2736 bus-range = <0x0 0xff <<
2737 <<
2738 ranges = <0x43000000 <<
2739 <0x02000000 <<
2740 <0x01000000 <<
2741 <<
2742 interconnects = <&mc <<
2743 <&mc <<
2744 interconnect-names = <<
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 <<
2750 pcie-ep@141a0000 { <<
2751 compatible = "nvidia, <<
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 <<
2759 status = "disabled"; <<
2760 <<
2761 num-lanes = <8>; <<
2762 num-ib-windows = <2>; <<
2763 num-ob-windows = <8>; <<
2764 <<
2765 pinctrl-names = "defa <<
2766 pinctrl-0 = <&pex_clk <<
2767 <<
2768 clocks = <&bpmp TEGRA <<
2769 clock-names = "core"; <<
2770 <<
2771 resets = <&bpmp TEGRA <<
2772 <&bpmp TEGRA <<
2773 reset-names = "apb", <<
2774 <<
2775 interrupts = <GIC_SPI <<
2776 interrupt-names = "in <<
2777 <<
2778 nvidia,bpmp = <&bpmp <<
2779 <<
2780 nvidia,aspm-cmrt-us = <<
2781 nvidia,aspm-pwr-on-t- <<
2782 nvidia,aspm-l0s-entra <<
2783 <<
2784 interconnects = <&mc <<
2785 <&mc <<
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 <<
2792 gpu@17000000 { <<
2793 compatible = "nvidia, <<
2794 reg = <0x0 0x17000000 <<
2795 <0x0 0x18000000 <<
2796 interrupts = <GIC_SPI <<
2797 <GIC_SPI <<
2798 interrupt-names = "st <<
2799 clocks = <&bpmp TEGRA <<
2800 <&bpmp TEGRA <<
2801 <&bpmp TEGRA <<
2802 clock-names = "gpu", <<
2803 resets = <&bpmp TEGRA <<
2804 reset-names = "gpu"; <<
2805 dma-coherent; <<
2806 <<
2807 power-domains = <&bpm <<
2808 interconnects = <&mc <<
2809 <&mc <<
2810 <&mc <<
2811 <&mc <<
2812 <&mc <<
2813 <&mc <<
2814 <&mc <<
2815 <&mc <<
2816 <&mc <<
2817 <&mc <<
2818 <&mc <<
2819 <&mc <<
2820 interconnect-names = <<
2821 <<
2822 <<
2823 <<
2824 }; <<
2825 }; 823 };
2826 824
2827 sram@40000000 { !! 825 sysram@40000000 {
2828 compatible = "nvidia,tegra194 826 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 827 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 828 #address-cells = <1>;
2832 #size-cells = <1>; 829 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 830 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 831
2835 no-memory-wc; !! 832 cpu_bpmp_tx: shmem@4e000 {
2836 !! 833 compatible = "nvidia,tegra194-bpmp-shmem";
2837 cpu_bpmp_tx: sram@4e000 { <<
2838 reg = <0x4e000 0x1000 834 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 835 label = "cpu-bpmp-tx";
2840 pool; 836 pool;
2841 }; 837 };
2842 838
2843 cpu_bpmp_rx: sram@4f000 { !! 839 cpu_bpmp_rx: shmem@4f000 {
>> 840 compatible = "nvidia,tegra194-bpmp-shmem";
2844 reg = <0x4f000 0x1000 841 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 842 label = "cpu-bpmp-rx";
2846 pool; 843 pool;
2847 }; 844 };
2848 }; 845 };
2849 846
2850 bpmp: bpmp { 847 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 848 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 849 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 850 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu !! 851 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2855 #clock-cells = <1>; 852 #clock-cells = <1>;
2856 #reset-cells = <1>; 853 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 854 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 <<
2859 <&mc TEGRA194 <<
2860 <&mc TEGRA194 <<
2861 <&mc TEGRA194 <<
2862 interconnect-names = "read", <<
2863 iommus = <&smmu TEGRA194_SID_ <<
2864 855
2865 bpmp_i2c: i2c { 856 bpmp_i2c: i2c {
2866 compatible = "nvidia, 857 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 858 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 859 #address-cells = <1>;
2869 #size-cells = <0>; 860 #size-cells = <0>;
2870 }; 861 };
2871 862
2872 bpmp_thermal: thermal { 863 bpmp_thermal: thermal {
2873 compatible = "nvidia, 864 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 865 #thermal-sensor-cells = <1>;
2875 }; 866 };
2876 }; 867 };
2877 868
2878 cpus { 869 cpus {
2879 compatible = "nvidia,tegra194 <<
2880 nvidia,bpmp = <&bpmp>; <<
2881 #address-cells = <1>; 870 #address-cells = <1>;
2882 #size-cells = <0>; 871 #size-cells = <0>;
2883 872
2884 cpu0_0: cpu@0 { !! 873 cpu@0 {
2885 compatible = "nvidia, !! 874 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2886 device_type = "cpu"; 875 device_type = "cpu";
2887 reg = <0x000>; !! 876 reg = <0x10000>;
2888 enable-method = "psci 877 enable-method = "psci";
2889 i-cache-size = <13107 <<
2890 i-cache-line-size = < <<
2891 i-cache-sets = <512>; <<
2892 d-cache-size = <65536 <<
2893 d-cache-line-size = < <<
2894 d-cache-sets = <256>; <<
2895 next-level-cache = <& <<
2896 }; 878 };
2897 879
2898 cpu0_1: cpu@1 { !! 880 cpu@1 {
2899 compatible = "nvidia, !! 881 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2900 device_type = "cpu"; 882 device_type = "cpu";
2901 reg = <0x001>; !! 883 reg = <0x10001>;
2902 enable-method = "psci 884 enable-method = "psci";
2903 i-cache-size = <13107 <<
2904 i-cache-line-size = < <<
2905 i-cache-sets = <512>; <<
2906 d-cache-size = <65536 <<
2907 d-cache-line-size = < <<
2908 d-cache-sets = <256>; <<
2909 next-level-cache = <& <<
2910 }; 885 };
2911 886
2912 cpu1_0: cpu@100 { !! 887 cpu@2 {
2913 compatible = "nvidia, !! 888 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2914 device_type = "cpu"; 889 device_type = "cpu";
2915 reg = <0x100>; 890 reg = <0x100>;
2916 enable-method = "psci 891 enable-method = "psci";
2917 i-cache-size = <13107 <<
2918 i-cache-line-size = < <<
2919 i-cache-sets = <512>; <<
2920 d-cache-size = <65536 <<
2921 d-cache-line-size = < <<
2922 d-cache-sets = <256>; <<
2923 next-level-cache = <& <<
2924 }; 892 };
2925 893
2926 cpu1_1: cpu@101 { !! 894 cpu@3 {
2927 compatible = "nvidia, !! 895 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2928 device_type = "cpu"; 896 device_type = "cpu";
2929 reg = <0x101>; 897 reg = <0x101>;
2930 enable-method = "psci 898 enable-method = "psci";
2931 i-cache-size = <13107 <<
2932 i-cache-line-size = < <<
2933 i-cache-sets = <512>; <<
2934 d-cache-size = <65536 <<
2935 d-cache-line-size = < <<
2936 d-cache-sets = <256>; <<
2937 next-level-cache = <& <<
2938 }; 899 };
2939 900
2940 cpu2_0: cpu@200 { !! 901 cpu@4 {
2941 compatible = "nvidia, !! 902 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2942 device_type = "cpu"; 903 device_type = "cpu";
2943 reg = <0x200>; 904 reg = <0x200>;
2944 enable-method = "psci 905 enable-method = "psci";
2945 i-cache-size = <13107 <<
2946 i-cache-line-size = < <<
2947 i-cache-sets = <512>; <<
2948 d-cache-size = <65536 <<
2949 d-cache-line-size = < <<
2950 d-cache-sets = <256>; <<
2951 next-level-cache = <& <<
2952 }; 906 };
2953 907
2954 cpu2_1: cpu@201 { !! 908 cpu@5 {
2955 compatible = "nvidia, !! 909 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2956 device_type = "cpu"; 910 device_type = "cpu";
2957 reg = <0x201>; 911 reg = <0x201>;
2958 enable-method = "psci 912 enable-method = "psci";
2959 i-cache-size = <13107 <<
2960 i-cache-line-size = < <<
2961 i-cache-sets = <512>; <<
2962 d-cache-size = <65536 <<
2963 d-cache-line-size = < <<
2964 d-cache-sets = <256>; <<
2965 next-level-cache = <& <<
2966 }; 913 };
2967 914
2968 cpu3_0: cpu@300 { !! 915 cpu@6 {
2969 compatible = "nvidia, !! 916 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2970 device_type = "cpu"; 917 device_type = "cpu";
2971 reg = <0x300>; !! 918 reg = <0x10300>;
2972 enable-method = "psci 919 enable-method = "psci";
2973 i-cache-size = <13107 <<
2974 i-cache-line-size = < <<
2975 i-cache-sets = <512>; <<
2976 d-cache-size = <65536 <<
2977 d-cache-line-size = < <<
2978 d-cache-sets = <256>; <<
2979 next-level-cache = <& <<
2980 }; 920 };
2981 921
2982 cpu3_1: cpu@301 { !! 922 cpu@7 {
2983 compatible = "nvidia, !! 923 compatible = "nvidia,tegra194-carmel", "arm,armv8";
2984 device_type = "cpu"; 924 device_type = "cpu";
2985 reg = <0x301>; !! 925 reg = <0x10301>;
2986 enable-method = "psci 926 enable-method = "psci";
2987 i-cache-size = <13107 <<
2988 i-cache-line-size = < <<
2989 i-cache-sets = <512>; <<
2990 d-cache-size = <65536 <<
2991 d-cache-line-size = < <<
2992 d-cache-sets = <256>; <<
2993 next-level-cache = <& <<
2994 }; <<
2995 <<
2996 cpu-map { <<
2997 cluster0 { <<
2998 core0 { <<
2999 cpu = <<
3000 }; <<
3001 <<
3002 core1 { <<
3003 cpu = <<
3004 }; <<
3005 }; <<
3006 <<
3007 cluster1 { <<
3008 core0 { <<
3009 cpu = <<
3010 }; <<
3011 <<
3012 core1 { <<
3013 cpu = <<
3014 }; <<
3015 }; <<
3016 <<
3017 cluster2 { <<
3018 core0 { <<
3019 cpu = <<
3020 }; <<
3021 <<
3022 core1 { <<
3023 cpu = <<
3024 }; <<
3025 }; <<
3026 <<
3027 cluster3 { <<
3028 core0 { <<
3029 cpu = <<
3030 }; <<
3031 <<
3032 core1 { <<
3033 cpu = <<
3034 }; <<
3035 }; <<
3036 }; 927 };
3037 <<
3038 l2c_0: l2-cache0 { <<
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 <<
3042 cache-line-size = <64 <<
3043 cache-sets = <2048>; <<
3044 cache-level = <2>; <<
3045 next-level-cache = <& <<
3046 }; <<
3047 <<
3048 l2c_1: l2-cache1 { <<
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 <<
3052 cache-line-size = <64 <<
3053 cache-sets = <2048>; <<
3054 cache-level = <2>; <<
3055 next-level-cache = <& <<
3056 }; <<
3057 <<
3058 l2c_2: l2-cache2 { <<
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 <<
3062 cache-line-size = <64 <<
3063 cache-sets = <2048>; <<
3064 cache-level = <2>; <<
3065 next-level-cache = <& <<
3066 }; <<
3067 <<
3068 l2c_3: l2-cache3 { <<
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 <<
3072 cache-line-size = <64 <<
3073 cache-sets = <2048>; <<
3074 cache-level = <2>; <<
3075 next-level-cache = <& <<
3076 }; <<
3077 <<
3078 l3c: l3-cache { <<
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 <<
3082 cache-line-size = <64 <<
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; <<
3085 }; <<
3086 }; <<
3087 <<
3088 pmu { <<
3089 compatible = "nvidia,carmel-p <<
3090 interrupts = <GIC_SPI 384 IRQ <<
3091 <GIC_SPI 385 IRQ <<
3092 <GIC_SPI 386 IRQ <<
3093 <GIC_SPI 387 IRQ <<
3094 <GIC_SPI 388 IRQ <<
3095 <GIC_SPI 389 IRQ <<
3096 <GIC_SPI 390 IRQ <<
3097 <GIC_SPI 391 IRQ <<
3098 interrupt-affinity = <&cpu0_0 <<
3099 &cpu2_0 <<
3100 }; 928 };
3101 929
3102 psci { 930 psci {
3103 compatible = "arm,psci-1.0"; 931 compatible = "arm,psci-1.0";
3104 status = "okay"; 932 status = "okay";
3105 method = "smc"; 933 method = "smc";
3106 }; 934 };
3107 935
3108 tcu: serial { <<
3109 compatible = "nvidia,tegra194 <<
3110 mboxes = <&hsp_top0 TEGRA_HSP <<
3111 <&hsp_aon TEGRA_HSP_ <<
3112 mbox-names = "rx", "tx"; <<
3113 }; <<
3114 <<
3115 sound { <<
3116 status = "disabled"; <<
3117 <<
3118 clocks = <&bpmp TEGRA194_CLK_ <<
3119 <&bpmp TEGRA194_CLK_ <<
3120 clock-names = "pll_a", "plla_ <<
3121 assigned-clocks = <&bpmp TEGR <<
3122 <&bpmp TEGR <<
3123 <&bpmp TEGR <<
3124 assigned-clock-parents = <0>, <<
3125 <&bp <<
3126 <&bp <<
3127 /* <<
3128 * PLLA supports dynamic ramp <<
3129 * for this to work and oscil <<
3130 * for 8x and 11.025x sample <<
3131 */ <<
3132 assigned-clock-rates = <25800 <<
3133 }; <<
3134 <<
3135 thermal-zones { 936 thermal-zones {
3136 cpu-thermal { !! 937 cpu {
3137 thermal-sensors = <&{ !! 938 thermal-sensors = <&{/bpmp/thermal}
>> 939 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 940 status = "disabled";
3139 }; 941 };
3140 942
3141 gpu-thermal { !! 943 gpu {
3142 thermal-sensors = <&{ !! 944 thermal-sensors = <&{/bpmp/thermal}
>> 945 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 946 status = "disabled";
3144 }; 947 };
3145 948
3146 aux-thermal { !! 949 aux {
3147 thermal-sensors = <&{ !! 950 thermal-sensors = <&{/bpmp/thermal}
>> 951 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 952 status = "disabled";
3149 }; 953 };
3150 954
3151 pllx-thermal { !! 955 pllx {
3152 thermal-sensors = <&{ !! 956 thermal-sensors = <&{/bpmp/thermal}
>> 957 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 958 status = "disabled";
3154 }; 959 };
3155 960
3156 ao-thermal { !! 961 ao {
3157 thermal-sensors = <&{ !! 962 thermal-sensors = <&{/bpmp/thermal}
>> 963 TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 964 status = "disabled";
3159 }; 965 };
3160 966
3161 tj-thermal { !! 967 tj {
3162 thermal-sensors = <&{ !! 968 thermal-sensors = <&{/bpmp/thermal}
>> 969 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 970 status = "disabled";
3164 }; 971 };
3165 }; 972 };
3166 973
3167 timer { 974 timer {
3168 compatible = "arm,armv8-timer 975 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 976 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 977 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 978 <GIC_PPI 14
3172 (GIC_CPU_MASK 979 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 980 <GIC_PPI 11
3174 (GIC_CPU_MASK 981 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 982 <GIC_PPI 10
3176 (GIC_CPU_MASK 983 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 984 interrupt-parent = <&gic>;
3178 always-on; <<
3179 }; 985 };
3180 }; 986 };
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