1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 7 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 8 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 10 #include <dt-bindings/memory/tegra194-mc.h>
12 11
13 / { 12 / {
14 compatible = "nvidia,tegra194"; 13 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
16 #address-cells = <2>; 15 #address-cells = <2>;
17 #size-cells = <2>; 16 #size-cells = <2>;
18 17
19 /* control backbone */ 18 /* control backbone */
20 bus@0 { 19 bus@0 {
21 compatible = "simple-bus"; 20 compatible = "simple-bus";
>> 21 #address-cells = <1>;
>> 22 #size-cells = <1>;
>> 23 ranges = <0x0 0x0 0x0 0x40000000>;
22 24
23 #address-cells = <2>; !! 25 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 26 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 27 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 28 <0x0010f000 0x1000>;
31 }; 29 };
32 30
33 gpio: gpio@2200000 { 31 gpio: gpio@2200000 {
34 compatible = "nvidia,t 32 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 33 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 34 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 35 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI <<
40 <GIC_SPI <<
41 <GIC_SPI <<
42 <GIC_SPI <<
43 <GIC_SPI <<
44 <GIC_SPI <<
45 <GIC_SPI <<
46 <GIC_SPI 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI <<
48 <GIC_SPI <<
49 <GIC_SPI <<
50 <GIC_SPI <<
51 <GIC_SPI <<
52 <GIC_SPI <<
53 <GIC_SPI <<
54 <GIC_SPI 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI <<
56 <GIC_SPI <<
57 <GIC_SPI <<
58 <GIC_SPI <<
59 <GIC_SPI <<
60 <GIC_SPI <<
61 <GIC_SPI <<
62 <GIC_SPI 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI <<
64 <GIC_SPI <<
65 <GIC_SPI <<
66 <GIC_SPI <<
67 <GIC_SPI <<
68 <GIC_SPI <<
69 <GIC_SPI <<
70 <GIC_SPI 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI !! 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
72 <GIC_SPI <<
73 <GIC_SPI <<
74 <GIC_SPI <<
75 <GIC_SPI <<
76 <GIC_SPI <<
77 <GIC_SPI <<
78 <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 #interrupt-cells = <2> 42 #interrupt-cells = <2>;
87 interrupt-controller; 43 interrupt-controller;
88 #gpio-cells = <2>; 44 #gpio-cells = <2>;
89 gpio-controller; 45 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 46 };
141 47
142 ethernet@2490000 { 48 ethernet@2490000 {
143 compatible = "nvidia,t 49 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 50 "nvidia,tegra186-eqos",
145 "snps,dwc 51 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 52 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 56 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 57 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 60 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 61 reset-names = "eqos";
156 interconnects = <&mc T 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
157 <&mc T 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
158 interconnect-names = " 64 interconnect-names = "dma-mem", "write";
159 iommus = <&smmu TEGRA1 <<
160 status = "disabled"; 65 status = "disabled";
161 66
162 snps,write-requests = 67 snps,write-requests = <1>;
163 snps,read-requests = < 68 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 69 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 70 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 71 snps,rxpbl = <8>;
167 }; 72 };
168 73
169 gpcdma: dma-controller@2600000 <<
170 compatible = "nvidia,t <<
171 "nvidia,t <<
172 reg = <0x0 0x2600000 0 <<
173 resets = <&bpmp TEGRA1 <<
174 reset-names = "gpcdma" <<
175 interrupts = <GIC_SPI <<
176 <GIC_SPI <<
177 <GIC_SPI <<
178 <GIC_SPI <<
179 <GIC_SPI <<
180 <GIC_SPI <<
181 <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 #dma-cells = <1>; <<
208 iommus = <&smmu TEGRA1 <<
209 dma-coherent; <<
210 dma-channel-mask = <0x <<
211 status = "okay"; <<
212 }; <<
213 <<
214 aconnect@2900000 { 74 aconnect@2900000 {
215 compatible = "nvidia,t 75 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 76 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 77 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 78 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 79 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 81 #address-cells = <1>;
>> 82 #size-cells = <1>;
>> 83 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 84 status = "disabled";
222 85
223 #address-cells = <2>; !! 86 adma: dma-controller@2930000 {
224 #size-cells = <2>; !! 87 compatible = "nvidia,tegra194-adma",
225 ranges = <0x0 0x029000 !! 88 "nvidia,tegra186-adma";
>> 89 reg = <0x02930000 0x20000>;
>> 90 interrupt-parent = <&agic>;
>> 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 123 #dma-cells = <1>;
>> 124 clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> 125 clock-names = "d_audio";
>> 126 status = "disabled";
>> 127 };
>> 128
>> 129 agic: interrupt-controller@2a40000 {
>> 130 compatible = "nvidia,tegra194-agic",
>> 131 "nvidia,tegra210-agic";
>> 132 #interrupt-cells = <3>;
>> 133 interrupt-controller;
>> 134 reg = <0x02a41000 0x1000>,
>> 135 <0x02a42000 0x2000>;
>> 136 interrupts = <GIC_SPI 145
>> 137 (GIC_CPU_MASK_SIMPLE(4) |
>> 138 IRQ_TYPE_LEVEL_HIGH)>;
>> 139 clocks = <&bpmp TEGRA194_CLK_APE>;
>> 140 clock-names = "clk";
>> 141 status = "disabled";
>> 142 };
226 143
227 tegra_ahub: ahub@29008 144 tegra_ahub: ahub@2900800 {
228 compatible = " 145 compatible = "nvidia,tegra194-ahub",
229 " 146 "nvidia,tegra186-ahub";
230 reg = <0x0 0x0 !! 147 reg = <0x02900800 0x800>;
231 clocks = <&bpm 148 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = 149 clock-names = "ahub";
233 assigned-clock 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock !! 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
235 assigned-clock !! 152 #address-cells = <1>;
>> 153 #size-cells = <1>;
>> 154 ranges = <0x02900800 0x02900800 0x11800>;
236 status = "disa 155 status = "disabled";
237 156
238 #address-cells !! 157 tegra_admaif: admaif@290f000 {
239 #size-cells = !! 158 compatible = "nvidia,tegra194-admaif",
240 ranges = <0x0 !! 159 "nvidia,tegra186-admaif";
>> 160 reg = <0x0290f000 0x1000>;
>> 161 dmas = <&adma 1>, <&adma 1>,
>> 162 <&adma 2>, <&adma 2>,
>> 163 <&adma 3>, <&adma 3>,
>> 164 <&adma 4>, <&adma 4>,
>> 165 <&adma 5>, <&adma 5>,
>> 166 <&adma 6>, <&adma 6>,
>> 167 <&adma 7>, <&adma 7>,
>> 168 <&adma 8>, <&adma 8>,
>> 169 <&adma 9>, <&adma 9>,
>> 170 <&adma 10>, <&adma 10>,
>> 171 <&adma 11>, <&adma 11>,
>> 172 <&adma 12>, <&adma 12>,
>> 173 <&adma 13>, <&adma 13>,
>> 174 <&adma 14>, <&adma 14>,
>> 175 <&adma 15>, <&adma 15>,
>> 176 <&adma 16>, <&adma 16>,
>> 177 <&adma 17>, <&adma 17>,
>> 178 <&adma 18>, <&adma 18>,
>> 179 <&adma 19>, <&adma 19>,
>> 180 <&adma 20>, <&adma 20>;
>> 181 dma-names = "rx1", "tx1",
>> 182 "rx2", "tx2",
>> 183 "rx3", "tx3",
>> 184 "rx4", "tx4",
>> 185 "rx5", "tx5",
>> 186 "rx6", "tx6",
>> 187 "rx7", "tx7",
>> 188 "rx8", "tx8",
>> 189 "rx9", "tx9",
>> 190 "rx10", "tx10",
>> 191 "rx11", "tx11",
>> 192 "rx12", "tx12",
>> 193 "rx13", "tx13",
>> 194 "rx14", "tx14",
>> 195 "rx15", "tx15",
>> 196 "rx16", "tx16",
>> 197 "rx17", "tx17",
>> 198 "rx18", "tx18",
>> 199 "rx19", "tx19",
>> 200 "rx20", "tx20";
>> 201 status = "disabled";
>> 202 };
241 203
242 tegra_i2s1: i2 204 tegra_i2s1: i2s@2901000 {
243 compat 205 compatible = "nvidia,tegra194-i2s",
244 206 "nvidia,tegra210-i2s";
245 reg = !! 207 reg = <0x2901000 0x100>;
246 clocks 208 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock- 210 clock-names = "i2s", "sync_input";
249 assign 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assign 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assign 213 assigned-clock-rates = <1536000>;
252 sound- 214 sound-name-prefix = "I2S1";
253 status 215 status = "disabled";
254 }; 216 };
255 217
256 tegra_i2s2: i2 218 tegra_i2s2: i2s@2901100 {
257 compat 219 compatible = "nvidia,tegra194-i2s",
258 220 "nvidia,tegra210-i2s";
259 reg = !! 221 reg = <0x2901100 0x100>;
260 clocks 222 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock- 224 clock-names = "i2s", "sync_input";
263 assign 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assign 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assign 227 assigned-clock-rates = <1536000>;
266 sound- 228 sound-name-prefix = "I2S2";
267 status 229 status = "disabled";
268 }; 230 };
269 231
270 tegra_i2s3: i2 232 tegra_i2s3: i2s@2901200 {
271 compat 233 compatible = "nvidia,tegra194-i2s",
272 234 "nvidia,tegra210-i2s";
273 reg = !! 235 reg = <0x2901200 0x100>;
274 clocks 236 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock- 238 clock-names = "i2s", "sync_input";
277 assign 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assign 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assign 241 assigned-clock-rates = <1536000>;
280 sound- 242 sound-name-prefix = "I2S3";
281 status 243 status = "disabled";
282 }; 244 };
283 245
284 tegra_i2s4: i2 246 tegra_i2s4: i2s@2901300 {
285 compat 247 compatible = "nvidia,tegra194-i2s",
286 248 "nvidia,tegra210-i2s";
287 reg = !! 249 reg = <0x2901300 0x100>;
288 clocks 250 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock- 252 clock-names = "i2s", "sync_input";
291 assign 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assign 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assign 255 assigned-clock-rates = <1536000>;
294 sound- 256 sound-name-prefix = "I2S4";
295 status 257 status = "disabled";
296 }; 258 };
297 259
298 tegra_i2s5: i2 260 tegra_i2s5: i2s@2901400 {
299 compat 261 compatible = "nvidia,tegra194-i2s",
300 262 "nvidia,tegra210-i2s";
301 reg = !! 263 reg = <0x2901400 0x100>;
302 clocks 264 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock- 266 clock-names = "i2s", "sync_input";
305 assign 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assign 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assign 269 assigned-clock-rates = <1536000>;
308 sound- 270 sound-name-prefix = "I2S5";
309 status 271 status = "disabled";
310 }; 272 };
311 273
312 tegra_i2s6: i2 274 tegra_i2s6: i2s@2901500 {
313 compat 275 compatible = "nvidia,tegra194-i2s",
314 276 "nvidia,tegra210-i2s";
315 reg = !! 277 reg = <0x2901500 0x100>;
316 clocks 278 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock- 280 clock-names = "i2s", "sync_input";
319 assign 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assign 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assign 283 assigned-clock-rates = <1536000>;
322 sound- 284 sound-name-prefix = "I2S6";
323 status 285 status = "disabled";
324 }; 286 };
325 287
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d 288 tegra_dmic1: dmic@2904000 {
419 compat 289 compatible = "nvidia,tegra194-dmic",
420 290 "nvidia,tegra210-dmic";
421 reg = !! 291 reg = <0x2904000 0x100>;
422 clocks 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock- 293 clock-names = "dmic";
424 assign 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assign 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assign 296 assigned-clock-rates = <3072000>;
427 sound- 297 sound-name-prefix = "DMIC1";
428 status 298 status = "disabled";
429 }; 299 };
430 300
431 tegra_dmic2: d 301 tegra_dmic2: dmic@2904100 {
432 compat 302 compatible = "nvidia,tegra194-dmic",
433 303 "nvidia,tegra210-dmic";
434 reg = !! 304 reg = <0x2904100 0x100>;
435 clocks 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock- 306 clock-names = "dmic";
437 assign 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assign 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assign 309 assigned-clock-rates = <3072000>;
440 sound- 310 sound-name-prefix = "DMIC2";
441 status 311 status = "disabled";
442 }; 312 };
443 313
444 tegra_dmic3: d 314 tegra_dmic3: dmic@2904200 {
445 compat 315 compatible = "nvidia,tegra194-dmic",
446 316 "nvidia,tegra210-dmic";
447 reg = !! 317 reg = <0x2904200 0x100>;
448 clocks 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock- 319 clock-names = "dmic";
450 assign 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assign 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assign 322 assigned-clock-rates = <3072000>;
453 sound- 323 sound-name-prefix = "DMIC3";
454 status 324 status = "disabled";
455 }; 325 };
456 326
457 tegra_dmic4: d 327 tegra_dmic4: dmic@2904300 {
458 compat 328 compatible = "nvidia,tegra194-dmic",
459 329 "nvidia,tegra210-dmic";
460 reg = !! 330 reg = <0x2904300 0x100>;
461 clocks 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock- 332 clock-names = "dmic";
463 assign 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assign 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assign 335 assigned-clock-rates = <3072000>;
466 sound- 336 sound-name-prefix = "DMIC4";
467 status 337 status = "disabled";
468 }; 338 };
469 339
470 tegra_dspk1: d 340 tegra_dspk1: dspk@2905000 {
471 compat 341 compatible = "nvidia,tegra194-dspk",
472 342 "nvidia,tegra186-dspk";
473 reg = !! 343 reg = <0x2905000 0x100>;
474 clocks 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock- 345 clock-names = "dspk";
476 assign 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assign 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assign 348 assigned-clock-rates = <12288000>;
479 sound- 349 sound-name-prefix = "DSPK1";
480 status 350 status = "disabled";
481 }; 351 };
482 352
483 tegra_dspk2: d 353 tegra_dspk2: dspk@2905100 {
484 compat 354 compatible = "nvidia,tegra194-dspk",
485 355 "nvidia,tegra186-dspk";
486 reg = !! 356 reg = <0x2905100 0x100>;
487 clocks 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock- 358 clock-names = "dspk";
489 assign 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assign 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assign 361 assigned-clock-rates = <12288000>;
492 sound- 362 sound-name-prefix = "DSPK2";
493 status 363 status = "disabled";
494 }; 364 };
>> 365 };
>> 366 };
495 367
496 tegra_ope1: pr !! 368 pinmux: pinmux@2430000 {
497 compat !! 369 compatible = "nvidia,tegra194-pinmux";
498 !! 370 reg = <0x2430000 0x17000>,
499 reg = !! 371 <0xc300000 0x4000>;
500 sound- <<
501 status <<
502 <<
503 #addre <<
504 #size- <<
505 ranges <<
506 <<
507 equali <<
508 <<
509 <<
510 <<
511 }; <<
512 <<
513 dynami <<
514 <<
515 <<
516 <<
517 }; <<
518 }; <<
519 <<
520 tegra_mvc1: mv <<
521 compat <<
522 <<
523 reg = <<
524 sound- <<
525 status <<
526 }; <<
527 <<
528 tegra_mvc2: mv <<
529 compat <<
530 <<
531 reg = <<
532 sound- <<
533 status <<
534 }; <<
535 <<
536 tegra_amixer: <<
537 compat <<
538 <<
539 reg = <<
540 sound- <<
541 status <<
542 }; <<
543 372
544 tegra_admaif: !! 373 status = "okay";
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 374
595 tegra_asrc: as !! 375 pex_rst_c5_out_state: pex_rst_c5_out {
596 compat !! 376 pex_rst {
597 !! 377 nvidia,pins = "pex_l5_rst_n_pgg1";
598 reg = !! 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
599 sound- !! 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
600 status !! 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
>> 381 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
>> 382 nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
601 }; 384 };
602 }; 385 };
603 386
604 adma: dma-controller@2 !! 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
605 compatible = " !! 388 clkreq {
606 " !! 389 nvidia,pins = "pex_l5_clkreq_n_pgg0";
607 reg = <0x0 0x0 !! 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
608 interrupt-pare !! 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
609 interrupts = !! 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
610 !! 393 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
611 !! 394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
612 !! 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 !! 396 };
614 <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; <<
646 <<
647 agic: interrupt-contro <<
648 compatible = " <<
649 " <<
650 #interrupt-cel <<
651 interrupt-cont <<
652 reg = <0x0 0x0 <<
653 <0x0 0x0 <<
654 interrupts = < <<
655 <<
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; 397 };
661 }; 398 };
662 399
663 mc: memory-controller@2c00000 400 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 401 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 402 reg = <0x02c00000 0x100000>,
666 <0x0 0x02c10000 !! 403 <0x02b80000 0x040000>,
667 <0x0 0x02c20000 !! 404 <0x01700000 0x100000>;
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
687 #interconnect-cells = 406 #interconnect-cells = <1>;
688 status = "disabled"; 407 status = "disabled";
689 408
690 #address-cells = <2>; 409 #address-cells = <2>;
691 #size-cells = <2>; 410 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 411
693 <0x0 0x02b800 !! 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 415
696 /* 416 /*
697 * Bit 39 of addresses 417 * Bit 39 of addresses passing through the memory
698 * controller selects 418 * controller selects the XBAR format used when memory
699 * is accessed. This i 419 * is accessed. This is used to transparently access
700 * memory in the XBAR 420 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 421 * (bit 39 set) or Tegra (bit 39 clear).
702 * 422 *
703 * As a consequence, t 423 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 424 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 425 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 426 * devices require access to the XBAR switch, their
707 * drivers must set th 427 * drivers must set this bit explicitly.
708 * 428 *
709 * Limit the DMA range 429 * Limit the DMA range for memory clients to [38:0].
710 */ 430 */
711 dma-ranges = <0x0 0x0 !! 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 432
713 emc: external-memory-c 433 emc: external-memory-controller@2c60000 {
714 compatible = " 434 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 435 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 436 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < <<
718 clocks = <&bpm 437 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 438 clock-names = "emc";
720 439
721 #interconnect- 440 #interconnect-cells = <0>;
722 441
723 nvidia,bpmp = 442 nvidia,bpmp = <&bpmp>;
724 }; 443 };
725 }; 444 };
726 445
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 446 uarta: serial@3100000 {
744 compatible = "nvidia,t 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 448 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 449 reg-shift = <2>;
747 interrupts = <GIC_SPI 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 451 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 452 clock-names = "serial";
749 resets = <&bpmp TEGRA1 453 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 454 reset-names = "serial";
750 status = "disabled"; 455 status = "disabled";
751 }; 456 };
752 457
753 uartb: serial@3110000 { 458 uartb: serial@3110000 {
754 compatible = "nvidia,t 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 460 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 461 reg-shift = <2>;
757 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 463 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 464 clock-names = "serial";
759 resets = <&bpmp TEGRA1 465 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 466 reset-names = "serial";
760 status = "disabled"; 467 status = "disabled";
761 }; 468 };
762 469
763 uartd: serial@3130000 { 470 uartd: serial@3130000 {
764 compatible = "nvidia,t 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 472 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 473 reg-shift = <2>;
767 interrupts = <GIC_SPI 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 475 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 476 clock-names = "serial";
770 resets = <&bpmp TEGRA1 477 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 478 reset-names = "serial";
772 status = "disabled"; 479 status = "disabled";
773 }; 480 };
774 481
775 uarte: serial@3140000 { 482 uarte: serial@3140000 {
776 compatible = "nvidia,t 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 484 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 485 reg-shift = <2>;
779 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 487 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 488 clock-names = "serial";
782 resets = <&bpmp TEGRA1 489 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 490 reset-names = "serial";
784 status = "disabled"; 491 status = "disabled";
785 }; 492 };
786 493
787 uartf: serial@3150000 { 494 uartf: serial@3150000 {
788 compatible = "nvidia,t 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 496 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 497 reg-shift = <2>;
791 interrupts = <GIC_SPI 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 499 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 500 clock-names = "serial";
794 resets = <&bpmp TEGRA1 501 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 502 reset-names = "serial";
796 status = "disabled"; 503 status = "disabled";
797 }; 504 };
798 505
799 gen1_i2c: i2c@3160000 { 506 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 507 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 508 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 510 #address-cells = <1>;
804 #size-cells = <0>; 511 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 512 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 513 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 514 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 515 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 516 status = "disabled";
812 }; 517 };
813 518
814 uarth: serial@3170000 { 519 uarth: serial@3170000 {
815 compatible = "nvidia,t 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 521 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 522 reg-shift = <2>;
818 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 524 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 525 clock-names = "serial";
821 resets = <&bpmp TEGRA1 526 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 527 reset-names = "serial";
823 status = "disabled"; 528 status = "disabled";
824 }; 529 };
825 530
826 cam_i2c: i2c@3180000 { 531 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 532 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 533 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 535 #address-cells = <1>;
831 #size-cells = <0>; 536 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 537 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 538 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 539 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 540 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 541 status = "disabled";
839 }; 542 };
840 543
841 /* shares pads with dpaux1 */ 544 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 545 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 546 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 547 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 549 #address-cells = <1>;
847 #size-cells = <0>; 550 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 551 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 552 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 553 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 554 reset-names = "i2c";
852 pinctrl-0 = <&state_dp 555 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dp 556 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "defau 557 pinctrl-names = "default", "idle";
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 558 status = "disabled";
858 }; 559 };
859 560
860 /* shares pads with dpaux0 */ 561 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 562 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 563 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 564 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 566 #address-cells = <1>;
866 #size-cells = <0>; 567 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 568 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 569 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 570 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 571 reset-names = "i2c";
871 pinctrl-0 = <&state_dp 572 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dp 573 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "defau 574 pinctrl-names = "default", "idle";
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 575 status = "disabled";
877 }; 576 };
878 577
879 /* shares pads with dpaux2 */ 578 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 { 579 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t 580 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 581 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 583 #address-cells = <1>;
885 #size-cells = <0>; 584 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 585 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 586 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 587 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 588 reset-names = "i2c";
890 pinctrl-0 = <&state_dp 589 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dp 590 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "defau 591 pinctrl-names = "default", "idle";
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 592 status = "disabled";
896 }; 593 };
897 594
898 /* shares pads with dpaux3 */ 595 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 { 596 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t 597 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 598 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 600 #address-cells = <1>;
904 #size-cells = <0>; 601 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 602 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 603 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 604 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 605 reset-names = "i2c";
909 pinctrl-0 = <&state_dp 606 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dp 607 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "defau 608 pinctrl-names = "default", "idle";
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 spi@3270000 { <<
918 compatible = "nvidia,t <<
919 reg = <0x0 0x3270000 0 <<
920 interrupts = <GIC_SPI <<
921 #address-cells = <1>; <<
922 #size-cells = <0>; <<
923 clocks = <&bpmp TEGRA1 <<
924 <&bpmp TEGRA1 <<
925 clock-names = "qspi", <<
926 resets = <&bpmp TEGRA1 <<
927 status = "disabled"; 609 status = "disabled";
928 }; 610 };
929 611
930 pwm1: pwm@3280000 { 612 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 613 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 614 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 615 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 616 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 617 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 618 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 619 reset-names = "pwm";
937 status = "disabled"; 620 status = "disabled";
938 #pwm-cells = <2>; 621 #pwm-cells = <2>;
939 }; 622 };
940 623
941 pwm2: pwm@3290000 { 624 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 625 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 626 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 627 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 628 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 629 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 630 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 631 reset-names = "pwm";
948 status = "disabled"; 632 status = "disabled";
949 #pwm-cells = <2>; 633 #pwm-cells = <2>;
950 }; 634 };
951 635
952 pwm3: pwm@32a0000 { 636 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 637 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 638 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 639 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 640 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 641 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 642 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 643 reset-names = "pwm";
959 status = "disabled"; 644 status = "disabled";
960 #pwm-cells = <2>; 645 #pwm-cells = <2>;
961 }; 646 };
962 647
963 pwm5: pwm@32c0000 { 648 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 649 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 650 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 651 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 652 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 653 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 654 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 655 reset-names = "pwm";
970 status = "disabled"; 656 status = "disabled";
971 #pwm-cells = <2>; 657 #pwm-cells = <2>;
972 }; 658 };
973 659
974 pwm6: pwm@32d0000 { 660 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 661 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 662 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 663 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 664 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 665 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 666 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 667 reset-names = "pwm";
981 status = "disabled"; 668 status = "disabled";
982 #pwm-cells = <2>; 669 #pwm-cells = <2>;
983 }; 670 };
984 671
985 pwm7: pwm@32e0000 { 672 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 673 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 674 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 675 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 676 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 677 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 678 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 679 reset-names = "pwm";
992 status = "disabled"; 680 status = "disabled";
993 #pwm-cells = <2>; 681 #pwm-cells = <2>;
994 }; 682 };
995 683
996 pwm8: pwm@32f0000 { 684 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 685 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 686 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 687 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 688 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 689 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 690 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 691 reset-names = "pwm";
1003 status = "disabled"; 692 status = "disabled";
1004 #pwm-cells = <2>; 693 #pwm-cells = <2>;
1005 }; 694 };
1006 695
1007 spi@3300000 { <<
1008 compatible = "nvidia, <<
1009 reg = <0x0 0x3300000 <<
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { 696 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia, 697 compatible = "nvidia,tegra194-sdhci";
1022 reg = <0x0 0x03400000 !! 698 reg = <0x03400000 0x10000>;
1023 interrupts = <GIC_SPI 699 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA 700 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA 701 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci" 702 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 703 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 704 reset-names = "sdhci";
1034 interconnects = <&mc 705 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035 <&mc 706 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036 interconnect-names = 707 interconnect-names = "dma-mem", "write";
1037 iommus = <&smmu TEGRA <<
1038 pinctrl-names = "sdmm <<
1039 pinctrl-0 = <&sdmmc1_ <<
1040 pinctrl-1 = <&sdmmc1_ <<
1041 nvidia,pad-autocal-pu 708 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 709 <0x07>;
1043 nvidia,pad-autocal-pu 710 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 711 <0x07>;
1045 nvidia,pad-autocal-pu 712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 713 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 714 <0x07>;
1048 nvidia,pad-autocal-pu 715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 717 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 718 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; <<
1053 sd-uhs-sdr50; <<
1054 sd-uhs-ddr50; <<
1055 sd-uhs-sdr104; <<
1056 status = "disabled"; 719 status = "disabled";
1057 }; 720 };
1058 721
1059 sdmmc3: mmc@3440000 { 722 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia, 723 compatible = "nvidia,tegra194-sdhci";
1061 reg = <0x0 0x03440000 !! 724 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 725 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA 726 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA 727 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci" 728 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 729 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 730 reset-names = "sdhci";
1073 interconnects = <&mc 731 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074 <&mc 732 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075 interconnect-names = 733 interconnect-names = "dma-mem", "write";
1076 iommus = <&smmu TEGRA <<
1077 pinctrl-names = "sdmm <<
1078 pinctrl-0 = <&sdmmc3_ <<
1079 pinctrl-1 = <&sdmmc3_ <<
1080 nvidia,pad-autocal-pu 734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 737 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 738 <0x07>;
1085 nvidia,pad-autocal-pu 739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 740 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 741 <0x07>;
1088 nvidia,pad-autocal-pu 742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 744 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 745 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; <<
1093 sd-uhs-sdr50; <<
1094 sd-uhs-ddr50; <<
1095 sd-uhs-sdr104; <<
1096 status = "disabled"; 746 status = "disabled";
1097 }; 747 };
1098 748
1099 sdmmc4: mmc@3460000 { 749 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia, 750 compatible = "nvidia,tegra194-sdhci";
1101 reg = <0x0 0x03460000 !! 751 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 752 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA 753 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA 754 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci" 755 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&b 756 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 757 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 758 assigned-clock-parents =
1109 <&b 759 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 760 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 761 reset-names = "sdhci";
1112 interconnects = <&mc 762 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113 <&mc 763 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114 interconnect-names = 764 interconnect-names = "dma-mem", "write";
1115 iommus = <&smmu TEGRA <<
1116 nvidia,pad-autocal-pu 765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 768 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 769 <0x0a>;
1121 nvidia,pad-autocal-pu 770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 771 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 772 <0x0a>;
1124 nvidia,default-tap = 773 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 774 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 775 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; <<
1128 mmc-ddr-1_8v; <<
1129 mmc-hs200-1_8v; <<
1130 mmc-hs400-1_8v; <<
1131 mmc-hs400-enhanced-st <<
1132 supports-cqe; 776 supports-cqe;
1133 status = "disabled"; 777 status = "disabled";
1134 }; 778 };
1135 779
1136 hda@3510000 { 780 hda@3510000 {
1137 compatible = "nvidia, !! 781 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 782 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 783 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 784 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA 785 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA 786 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", 787 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA 788 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA !! 789 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
1146 reset-names = "hda", !! 790 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
>> 791 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1147 power-domains = <&bpm 792 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc 793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149 <&mc 794 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150 interconnect-names = 795 interconnect-names = "dma-mem", "write";
1151 iommus = <&smmu TEGRA <<
1152 status = "disabled"; 796 status = "disabled";
1153 }; 797 };
1154 798
1155 xusb_padctl: padctl@3520000 { 799 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia, 800 compatible = "nvidia,tegra194-xusb-padctl";
1157 reg = <0x0 0x03520000 !! 801 reg = <0x03520000 0x1000>,
1158 <0x0 0x03540000 !! 802 <0x03540000 0x1000>;
1159 reg-names = "padctl", 803 reg-names = "padctl", "ao";
1160 interrupts = <GIC_SPI 804 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161 805
1162 resets = <&bpmp TEGRA 806 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl 807 reset-names = "padctl";
1164 808
1165 status = "disabled"; 809 status = "disabled";
1166 810
1167 pads { 811 pads {
1168 usb2 { 812 usb2 {
1169 clock 813 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock 814 clock-names = "trk";
1171 815
1172 lanes 816 lanes {
1173 817 usb2-0 {
1174 818 nvidia,function = "xusb";
1175 819 status = "disabled";
1176 820 #phy-cells = <0>;
1177 821 };
1178 822
1179 823 usb2-1 {
1180 824 nvidia,function = "xusb";
1181 825 status = "disabled";
1182 826 #phy-cells = <0>;
1183 827 };
1184 828
1185 829 usb2-2 {
1186 830 nvidia,function = "xusb";
1187 831 status = "disabled";
1188 832 #phy-cells = <0>;
1189 833 };
1190 834
1191 835 usb2-3 {
1192 836 nvidia,function = "xusb";
1193 837 status = "disabled";
1194 838 #phy-cells = <0>;
1195 839 };
1196 }; 840 };
1197 }; 841 };
1198 842
1199 usb3 { 843 usb3 {
1200 lanes 844 lanes {
1201 845 usb3-0 {
1202 846 nvidia,function = "xusb";
1203 847 status = "disabled";
1204 848 #phy-cells = <0>;
1205 849 };
1206 850
1207 851 usb3-1 {
1208 852 nvidia,function = "xusb";
1209 853 status = "disabled";
1210 854 #phy-cells = <0>;
1211 855 };
1212 856
1213 857 usb3-2 {
1214 858 nvidia,function = "xusb";
1215 859 status = "disabled";
1216 860 #phy-cells = <0>;
1217 861 };
1218 862
1219 863 usb3-3 {
1220 864 nvidia,function = "xusb";
1221 865 status = "disabled";
1222 866 #phy-cells = <0>;
1223 867 };
1224 }; 868 };
1225 }; 869 };
1226 }; 870 };
1227 871
1228 ports { 872 ports {
1229 usb2-0 { 873 usb2-0 {
1230 statu 874 status = "disabled";
1231 }; 875 };
1232 876
1233 usb2-1 { 877 usb2-1 {
1234 statu 878 status = "disabled";
1235 }; 879 };
1236 880
1237 usb2-2 { 881 usb2-2 {
1238 statu 882 status = "disabled";
1239 }; 883 };
1240 884
1241 usb2-3 { 885 usb2-3 {
1242 statu 886 status = "disabled";
1243 }; 887 };
1244 888
1245 usb3-0 { 889 usb3-0 {
1246 statu 890 status = "disabled";
1247 }; 891 };
1248 892
1249 usb3-1 { 893 usb3-1 {
1250 statu 894 status = "disabled";
1251 }; 895 };
1252 896
1253 usb3-2 { 897 usb3-2 {
1254 statu 898 status = "disabled";
1255 }; 899 };
1256 900
1257 usb3-3 { 901 usb3-3 {
1258 statu 902 status = "disabled";
1259 }; 903 };
1260 }; 904 };
1261 }; 905 };
1262 906
1263 usb@3550000 { 907 usb@3550000 {
1264 compatible = "nvidia, 908 compatible = "nvidia,tegra194-xudc";
1265 reg = <0x0 0x03550000 !! 909 reg = <0x03550000 0x8000>,
1266 <0x0 0x03558000 !! 910 <0x03558000 0x1000>;
1267 reg-names = "base", " 911 reg-names = "base", "fpci";
1268 interrupts = <GIC_SPI 912 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&bpmp TEGRA 913 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA 914 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA 915 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA 916 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", 917 clock-names = "dev", "ss", "ss_src", "fs_src";
1274 interconnects = <&mc <<
1275 <&mc <<
1276 interconnect-names = <<
1277 iommus = <&smmu TEGRA <<
1278 power-domains = <&bpm 918 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpm 919 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = 920 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = 921 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent; <<
1283 status = "disabled"; 922 status = "disabled";
1284 }; 923 };
1285 924
1286 usb@3610000 { 925 usb@3610000 {
1287 compatible = "nvidia, 926 compatible = "nvidia,tegra194-xusb";
1288 reg = <0x0 0x03610000 !! 927 reg = <0x03610000 0x40000>,
1289 <0x0 0x03600000 !! 928 <0x03600000 0x10000>;
1290 reg-names = "hcd", "f 929 reg-names = "hcd", "fpci";
1291 930
1292 interrupts = <GIC_SPI 931 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 932 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294 933
1295 clocks = <&bpmp TEGRA 934 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA 935 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA 936 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA 937 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA 938 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA 939 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA 940 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA 941 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA 942 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_h 943 clock-names = "xusb_host", "xusb_falcon_src",
1305 "xusb_s 944 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306 "xusb_f 945 "xusb_fs_src", "pll_u_480m", "clk_m",
1307 "pll_e" 946 "pll_e";
1308 interconnects = <&mc <<
1309 <&mc <<
1310 interconnect-names = <<
1311 iommus = <&smmu TEGRA <<
1312 947
1313 power-domains = <&bpm 948 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpm 949 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = 950 power-domain-names = "xusb_host", "xusb_ss";
1316 951
1317 nvidia,xusb-padctl = 952 nvidia,xusb-padctl = <&xusb_padctl>;
1318 status = "disabled"; 953 status = "disabled";
1319 }; 954 };
1320 955
1321 fuse@3820000 { 956 fuse@3820000 {
1322 compatible = "nvidia, 957 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 958 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 959 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 960 clock-names = "fuse";
1326 }; 961 };
1327 962
1328 gic: interrupt-controller@388 963 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 964 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 965 #interrupt-cells = <3>;
1331 interrupt-controller; 966 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 967 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 968 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 969 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 970 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 971 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 972 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 973 interrupt-parent = <&gic>;
1339 }; 974 };
1340 975
1341 cec@3960000 { 976 cec@3960000 {
1342 compatible = "nvidia, 977 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 978 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 979 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 980 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 981 clock-names = "cec";
1347 status = "disabled"; 982 status = "disabled";
1348 }; 983 };
1349 984
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 985 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, !! 986 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1362 reg = <0x0 0x03c00000 !! 987 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 988 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 989 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 990 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 991 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 992 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 993 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 994 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 995 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 996 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 997 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 998 "shared3", "shared4", "shared5", "shared6",
1374 "sh 999 "shared7";
1375 #mbox-cells = <2>; 1000 #mbox-cells = <2>;
1376 }; 1001 };
1377 1002
1378 p2u_hsio_0: phy@3e10000 { 1003 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 1004 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 1005 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 1006 reg-names = "ctl";
1382 1007
1383 #phy-cells = <0>; 1008 #phy-cells = <0>;
1384 }; 1009 };
1385 1010
1386 p2u_hsio_1: phy@3e20000 { 1011 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 1012 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 1013 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 1014 reg-names = "ctl";
1390 1015
1391 #phy-cells = <0>; 1016 #phy-cells = <0>;
1392 }; 1017 };
1393 1018
1394 p2u_hsio_2: phy@3e30000 { 1019 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 1020 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 1021 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 1022 reg-names = "ctl";
1398 1023
1399 #phy-cells = <0>; 1024 #phy-cells = <0>;
1400 }; 1025 };
1401 1026
1402 p2u_hsio_3: phy@3e40000 { 1027 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 1028 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 1029 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 1030 reg-names = "ctl";
1406 1031
1407 #phy-cells = <0>; 1032 #phy-cells = <0>;
1408 }; 1033 };
1409 1034
1410 p2u_hsio_4: phy@3e50000 { 1035 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 1036 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 1037 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 1038 reg-names = "ctl";
1414 1039
1415 #phy-cells = <0>; 1040 #phy-cells = <0>;
1416 }; 1041 };
1417 1042
1418 p2u_hsio_5: phy@3e60000 { 1043 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 1044 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 1045 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 1046 reg-names = "ctl";
1422 1047
1423 #phy-cells = <0>; 1048 #phy-cells = <0>;
1424 }; 1049 };
1425 1050
1426 p2u_hsio_6: phy@3e70000 { 1051 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 1052 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 1053 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 1054 reg-names = "ctl";
1430 1055
1431 #phy-cells = <0>; 1056 #phy-cells = <0>;
1432 }; 1057 };
1433 1058
1434 p2u_hsio_7: phy@3e80000 { 1059 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 1060 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 1061 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 1062 reg-names = "ctl";
1438 1063
1439 #phy-cells = <0>; 1064 #phy-cells = <0>;
1440 }; 1065 };
1441 1066
1442 p2u_hsio_8: phy@3e90000 { 1067 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 1068 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 1069 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 1070 reg-names = "ctl";
1446 1071
1447 #phy-cells = <0>; 1072 #phy-cells = <0>;
1448 }; 1073 };
1449 1074
1450 p2u_hsio_9: phy@3ea0000 { 1075 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 1076 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 1077 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 1078 reg-names = "ctl";
1454 1079
1455 #phy-cells = <0>; 1080 #phy-cells = <0>;
1456 }; 1081 };
1457 1082
1458 p2u_nvhs_0: phy@3eb0000 { 1083 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 1084 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 1085 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 1086 reg-names = "ctl";
1462 1087
1463 #phy-cells = <0>; 1088 #phy-cells = <0>;
1464 }; 1089 };
1465 1090
1466 p2u_nvhs_1: phy@3ec0000 { 1091 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 1092 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 1093 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 1094 reg-names = "ctl";
1470 1095
1471 #phy-cells = <0>; 1096 #phy-cells = <0>;
1472 }; 1097 };
1473 1098
1474 p2u_nvhs_2: phy@3ed0000 { 1099 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 1100 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 1101 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 1102 reg-names = "ctl";
1478 1103
1479 #phy-cells = <0>; 1104 #phy-cells = <0>;
1480 }; 1105 };
1481 1106
1482 p2u_nvhs_3: phy@3ee0000 { 1107 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 1108 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 1109 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 1110 reg-names = "ctl";
1486 1111
1487 #phy-cells = <0>; 1112 #phy-cells = <0>;
1488 }; 1113 };
1489 1114
1490 p2u_nvhs_4: phy@3ef0000 { 1115 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 1116 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 1117 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 1118 reg-names = "ctl";
1494 1119
1495 #phy-cells = <0>; 1120 #phy-cells = <0>;
1496 }; 1121 };
1497 1122
1498 p2u_nvhs_5: phy@3f00000 { 1123 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 1124 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 1125 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 1126 reg-names = "ctl";
1502 1127
1503 #phy-cells = <0>; 1128 #phy-cells = <0>;
1504 }; 1129 };
1505 1130
1506 p2u_nvhs_6: phy@3f10000 { 1131 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 1132 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 1133 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 1134 reg-names = "ctl";
1510 1135
1511 #phy-cells = <0>; 1136 #phy-cells = <0>;
1512 }; 1137 };
1513 1138
1514 p2u_nvhs_7: phy@3f20000 { 1139 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 1140 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 1141 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 1142 reg-names = "ctl";
1518 1143
1519 #phy-cells = <0>; 1144 #phy-cells = <0>;
1520 }; 1145 };
1521 1146
1522 p2u_hsio_10: phy@3f30000 { 1147 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 1148 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 1149 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 1150 reg-names = "ctl";
1526 1151
1527 #phy-cells = <0>; 1152 #phy-cells = <0>;
1528 }; 1153 };
1529 1154
1530 p2u_hsio_11: phy@3f40000 { 1155 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 1156 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 1157 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 1158 reg-names = "ctl";
1534 1159
1535 #phy-cells = <0>; 1160 #phy-cells = <0>;
1536 }; 1161 };
1537 1162
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 1163 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, !! 1164 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1560 reg = <0x0 0x0c150000 !! 1165 reg = <0x0c150000 0x90000>;
1561 interrupts = <GIC_SPI 1166 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 1167 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 1168 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 1169 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1170 /*
1566 * Shared interrupt 0 1171 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 1172 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 1173 */
1569 interrupt-names = "sh 1174 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 1175 #mbox-cells = <2>;
1571 }; 1176 };
1572 1177
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 1178 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 1179 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 1180 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 1181 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 1182 #address-cells = <1>;
1588 #size-cells = <0>; 1183 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 1184 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 1185 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 1186 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 1187 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 1188 status = "disabled";
1596 }; 1189 };
1597 1190
1598 gen8_i2c: i2c@c250000 { 1191 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 1192 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 1193 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 1195 #address-cells = <1>;
1603 #size-cells = <0>; 1196 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 1197 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 1198 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 1199 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 1200 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 1201 status = "disabled";
1611 }; 1202 };
1612 1203
1613 uartc: serial@c280000 { 1204 uartc: serial@c280000 {
1614 compatible = "nvidia, 1205 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 1206 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 1207 reg-shift = <2>;
1617 interrupts = <GIC_SPI 1208 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 1209 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 1210 clock-names = "serial";
1620 resets = <&bpmp TEGRA 1211 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 1212 reset-names = "serial";
1622 status = "disabled"; 1213 status = "disabled";
1623 }; 1214 };
1624 1215
1625 uartg: serial@c290000 { 1216 uartg: serial@c290000 {
1626 compatible = "nvidia, 1217 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 1218 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 1219 reg-shift = <2>;
1629 interrupts = <GIC_SPI 1220 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 1221 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 1222 clock-names = "serial";
1632 resets = <&bpmp TEGRA 1223 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 1224 reset-names = "serial";
1634 status = "disabled"; 1225 status = "disabled";
1635 }; 1226 };
1636 1227
1637 rtc: rtc@c2a0000 { 1228 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 1229 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 1230 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 1231 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 1232 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 1233 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 1234 clock-names = "rtc";
1644 status = "disabled"; 1235 status = "disabled";
1645 }; 1236 };
1646 1237
1647 gpio_aon: gpio@c2f0000 { 1238 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 1239 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 1240 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 1241 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 1242 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI !! 1243 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1653 <GIC_SPI <<
1654 <GIC_SPI <<
1655 <GIC_SPI <<
1656 gpio-controller; 1244 gpio-controller;
1657 #gpio-cells = <2>; 1245 #gpio-cells = <2>;
1658 interrupt-controller; 1246 interrupt-controller;
1659 #interrupt-cells = <2 1247 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 1248 };
1669 1249
1670 pwm4: pwm@c340000 { 1250 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 1251 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 1252 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 1253 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 1254 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 1255 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 1256 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 1257 reset-names = "pwm";
1677 status = "disabled"; 1258 status = "disabled";
1678 #pwm-cells = <2>; 1259 #pwm-cells = <2>;
1679 }; 1260 };
1680 1261
1681 pmc: pmc@c360000 { 1262 pmc: pmc@c360000 {
1682 compatible = "nvidia, 1263 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 1264 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 1265 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 1266 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 1267 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 1268 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 1269 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 1270
1690 #interrupt-cells = <2 1271 #interrupt-cells = <2>;
1691 interrupt-controller; 1272 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v <<
1699 pins = "sdmmc <<
1700 power-source <<
1701 }; <<
1702 <<
1703 sdmmc3_1v8: sdmmc3-1v <<
1704 pins = "sdmmc <<
1705 power-source <<
1706 }; <<
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v <<
1709 pins = "sdmmc <<
1710 power-source <<
1711 }; <<
1712 }; <<
1713 <<
1714 aon-noc@c600000 { <<
1715 compatible = "nvidia, <<
1716 reg = <0x0 0xc600000 <<
1717 interrupts = <GIC_SPI <<
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 <<
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; <<
1732 <<
1733 iommu@10000000 { <<
1734 compatible = "nvidia, <<
1735 reg = <0x0 0x10000000 <<
1736 interrupts = <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 <GIC_SPI <<
1747 <GIC_SPI <<
1748 <GIC_SPI <<
1749 <GIC_SPI <<
1750 <GIC_SPI <<
1751 <GIC_SPI <<
1752 <GIC_SPI <<
1753 <GIC_SPI <<
1754 <GIC_SPI <<
1755 <GIC_SPI <<
1756 <GIC_SPI <<
1757 <GIC_SPI <<
1758 <GIC_SPI <<
1759 <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 <GIC_SPI <<
1770 <GIC_SPI <<
1771 <GIC_SPI <<
1772 <GIC_SPI <<
1773 <GIC_SPI <<
1774 <GIC_SPI <<
1775 <GIC_SPI <<
1776 <GIC_SPI <<
1777 <GIC_SPI <<
1778 <GIC_SPI <<
1779 <GIC_SPI <<
1780 <GIC_SPI <<
1781 <GIC_SPI <<
1782 <GIC_SPI <<
1783 <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 <GIC_SPI <<
1792 <GIC_SPI <<
1793 <GIC_SPI <<
1794 <GIC_SPI <<
1795 <GIC_SPI <<
1796 <GIC_SPI <<
1797 <GIC_SPI <<
1798 <GIC_SPI <<
1799 <GIC_SPI <<
1800 <GIC_SPI <<
1801 stream-match-mask = < <<
1802 #global-interrupts = <<
1803 #iommu-cells = <1>; <<
1804 <<
1805 nvidia,memory-control <<
1806 status = "disabled"; <<
1807 }; <<
1808 <<
1809 smmu: iommu@12000000 { <<
1810 compatible = "nvidia, <<
1811 reg = <0x0 0x12000000 <<
1812 <0x0 0x11000000 <<
1813 interrupts = <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 <GIC_SPI <<
1834 <GIC_SPI <<
1835 <GIC_SPI <<
1836 <GIC_SPI <<
1837 <GIC_SPI <<
1838 <GIC_SPI <<
1839 <GIC_SPI <<
1840 <GIC_SPI <<
1841 <GIC_SPI <<
1842 <GIC_SPI <<
1843 <GIC_SPI <<
1844 <GIC_SPI <<
1845 <GIC_SPI <<
1846 <GIC_SPI <<
1847 <GIC_SPI <<
1848 <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 <GIC_SPI <<
1857 <GIC_SPI <<
1858 <GIC_SPI <<
1859 <GIC_SPI <<
1860 <GIC_SPI <<
1861 <GIC_SPI <<
1862 <GIC_SPI <<
1863 <GIC_SPI <<
1864 <GIC_SPI <<
1865 <GIC_SPI <<
1866 <GIC_SPI <<
1867 <GIC_SPI <<
1868 <GIC_SPI <<
1869 <GIC_SPI <<
1870 <GIC_SPI <<
1871 <GIC_SPI <<
1872 <GIC_SPI <<
1873 <GIC_SPI <<
1874 <GIC_SPI <<
1875 <GIC_SPI <<
1876 <GIC_SPI <<
1877 <GIC_SPI <<
1878 <GIC_SPI <<
1879 stream-match-mask = < <<
1880 #global-interrupts = <<
1881 #iommu-cells = <1>; <<
1882 <<
1883 nvidia,memory-control <<
1884 status = "okay"; <<
1885 }; 1273 };
1886 1274
1887 host1x@13e00000 { 1275 host1x@13e00000 {
1888 compatible = "nvidia, 1276 compatible = "nvidia,tegra194-host1x";
1889 reg = <0x0 0x13e00000 !! 1277 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 1278 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 1279 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 1280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1281 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy 1282 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA 1283 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 1284 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 1285 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 1286 reset-names = "host1x";
1899 1287
1900 #address-cells = <2>; !! 1288 #address-cells = <1>;
1901 #size-cells = <2>; !! 1289 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 1290
>> 1291 ranges = <0x15000000 0x15000000 0x01000000>;
1904 interconnects = <&mc 1292 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905 interconnect-names = 1293 interconnect-names = "dma-mem";
1906 iommus = <&smmu TEGRA <<
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 <<
1919 nvdec@15140000 { <<
1920 compatible = <<
1921 reg = <0x0 0x <<
1922 clocks = <&bp <<
1923 clock-names = <<
1924 resets = <&bp <<
1925 reset-names = <<
1926 <<
1927 power-domains <<
1928 interconnects <<
1929 <<
1930 <<
1931 interconnect- <<
1932 iommus = <&sm <<
1933 dma-coherent; <<
1934 <<
1935 nvidia,host1x <<
1936 }; <<
1937 1294
1938 display-hub@15200000 1295 display-hub@15200000 {
1939 compatible = 1296 compatible = "nvidia,tegra194-display";
1940 reg = <0x0 0x !! 1297 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 1298 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 1299 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 1300 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 1301 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 1302 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 1303 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 1304 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 1305 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 1306 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 1307 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 1308 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 1309 clock-names = "disp", "hub";
1953 status = "dis 1310 status = "disabled";
1954 1311
1955 power-domains 1312 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 1313
1957 #address-cell !! 1314 #address-cells = <1>;
1958 #size-cells = !! 1315 #size-cells = <1>;
1959 ranges = <0x0 !! 1316
>> 1317 ranges = <0x15200000 0x15200000 0x40000>;
1960 1318
1961 display@15200 1319 display@15200000 {
1962 compa 1320 compatible = "nvidia,tegra194-dc";
1963 reg = !! 1321 reg = <0x15200000 0x10000>;
1964 inter 1322 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 1323 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 1324 clock-names = "dc";
1967 reset 1325 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 1326 reset-names = "dc";
1969 1327
1970 power 1328 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter 1329 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 1330 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 inter 1331 interconnect-names = "dma-mem", "read-1";
1974 1332
1975 nvidi 1333 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 1334 nvidia,head = <0>;
1977 }; 1335 };
1978 1336
1979 display@15210 1337 display@15210000 {
1980 compa 1338 compatible = "nvidia,tegra194-dc";
1981 reg = !! 1339 reg = <0x15210000 0x10000>;
1982 inter 1340 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 1341 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 1342 clock-names = "dc";
1985 reset 1343 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 1344 reset-names = "dc";
1987 1345
1988 power 1346 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter 1347 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 1348 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 inter 1349 interconnect-names = "dma-mem", "read-1";
1992 1350
1993 nvidi 1351 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 1352 nvidia,head = <1>;
1995 }; 1353 };
1996 1354
1997 display@15220 1355 display@15220000 {
1998 compa 1356 compatible = "nvidia,tegra194-dc";
1999 reg = !! 1357 reg = <0x15220000 0x10000>;
2000 inter 1358 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 1359 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 1360 clock-names = "dc";
2003 reset 1361 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 1362 reset-names = "dc";
2005 1363
2006 power 1364 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter 1365 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008 1366 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009 inter 1367 interconnect-names = "dma-mem", "read-1";
2010 1368
2011 nvidi 1369 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 1370 nvidia,head = <2>;
2013 }; 1371 };
2014 1372
2015 display@15230 1373 display@15230000 {
2016 compa 1374 compatible = "nvidia,tegra194-dc";
2017 reg = !! 1375 reg = <0x15230000 0x10000>;
2018 inter 1376 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 1377 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 1378 clock-names = "dc";
2021 reset 1379 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 1380 reset-names = "dc";
2023 1381
2024 power 1382 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter 1383 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026 1384 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027 inter 1385 interconnect-names = "dma-mem", "read-1";
2028 1386
2029 nvidi 1387 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 1388 nvidia,head = <3>;
2031 }; 1389 };
2032 }; 1390 };
2033 1391
2034 vic@15340000 { 1392 vic@15340000 {
2035 compatible = 1393 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 1394 reg = <0x15340000 0x00040000>;
2037 interrupts = 1395 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 1396 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 1397 clock-names = "vic";
2040 resets = <&bp 1398 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 1399 reset-names = "vic";
2042 1400
2043 power-domains 1401 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects 1402 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045 1403 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046 interconnect- 1404 interconnect-names = "dma-mem", "write";
2047 iommus = <&sm <<
2048 dma-coherent; <<
2049 }; <<
2050 <<
2051 nvjpg@15380000 { <<
2052 compatible = <<
2053 reg = <0x0 0x <<
2054 clocks = <&bp <<
2055 clock-names = <<
2056 resets = <&bp <<
2057 reset-names = <<
2058 <<
2059 power-domains <<
2060 interconnects <<
2061 <<
2062 interconnect- <<
2063 iommus = <&sm <<
2064 dma-coherent; <<
2065 }; <<
2066 <<
2067 nvdec@15480000 { <<
2068 compatible = <<
2069 reg = <0x0 0x <<
2070 clocks = <&bp <<
2071 clock-names = <<
2072 resets = <&bp <<
2073 reset-names = <<
2074 <<
2075 power-domains <<
2076 interconnects <<
2077 <<
2078 <<
2079 interconnect- <<
2080 iommus = <&sm <<
2081 dma-coherent; <<
2082 <<
2083 nvidia,host1x <<
2084 }; <<
2085 <<
2086 nvenc@154c0000 { <<
2087 compatible = <<
2088 reg = <0x0 0x <<
2089 clocks = <&bp <<
2090 clock-names = <<
2091 resets = <&bp <<
2092 reset-names = <<
2093 <<
2094 power-domains <<
2095 interconnects <<
2096 <<
2097 <<
2098 interconnect- <<
2099 iommus = <&sm <<
2100 dma-coherent; <<
2101 <<
2102 nvidia,host1x <<
2103 }; 1405 };
2104 1406
2105 dpaux0: dpaux@155c000 1407 dpaux0: dpaux@155c0000 {
2106 compatible = 1408 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 1409 reg = <0x155c0000 0x10000>;
2108 interrupts = 1410 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 1411 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 1412 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 1413 clock-names = "dpaux", "parent";
2112 resets = <&bp 1414 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 1415 reset-names = "dpaux";
2114 status = "dis 1416 status = "disabled";
2115 1417
2116 power-domains 1418 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 1419
2118 state_dpaux0_ 1420 state_dpaux0_aux: pinmux-aux {
2119 group 1421 groups = "dpaux-io";
2120 funct 1422 function = "aux";
2121 }; 1423 };
2122 1424
2123 state_dpaux0_ 1425 state_dpaux0_i2c: pinmux-i2c {
2124 group 1426 groups = "dpaux-io";
2125 funct 1427 function = "i2c";
2126 }; 1428 };
2127 1429
2128 state_dpaux0_ 1430 state_dpaux0_off: pinmux-off {
2129 group 1431 groups = "dpaux-io";
2130 funct 1432 function = "off";
2131 }; 1433 };
2132 1434
2133 i2c-bus { 1435 i2c-bus {
2134 #addr 1436 #address-cells = <1>;
2135 #size 1437 #size-cells = <0>;
2136 }; 1438 };
2137 }; 1439 };
2138 1440
2139 dpaux1: dpaux@155d000 1441 dpaux1: dpaux@155d0000 {
2140 compatible = 1442 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1443 reg = <0x155d0000 0x10000>;
2142 interrupts = 1444 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1445 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1446 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1447 clock-names = "dpaux", "parent";
2146 resets = <&bp 1448 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 1449 reset-names = "dpaux";
2148 status = "dis 1450 status = "disabled";
2149 1451
2150 power-domains 1452 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 1453
2152 state_dpaux1_ 1454 state_dpaux1_aux: pinmux-aux {
2153 group 1455 groups = "dpaux-io";
2154 funct 1456 function = "aux";
2155 }; 1457 };
2156 1458
2157 state_dpaux1_ 1459 state_dpaux1_i2c: pinmux-i2c {
2158 group 1460 groups = "dpaux-io";
2159 funct 1461 function = "i2c";
2160 }; 1462 };
2161 1463
2162 state_dpaux1_ 1464 state_dpaux1_off: pinmux-off {
2163 group 1465 groups = "dpaux-io";
2164 funct 1466 function = "off";
2165 }; 1467 };
2166 1468
2167 i2c-bus { 1469 i2c-bus {
2168 #addr 1470 #address-cells = <1>;
2169 #size 1471 #size-cells = <0>;
2170 }; 1472 };
2171 }; 1473 };
2172 1474
2173 dpaux2: dpaux@155e000 1475 dpaux2: dpaux@155e0000 {
2174 compatible = 1476 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 1477 reg = <0x155e0000 0x10000>;
2176 interrupts = 1478 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 1479 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 1480 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 1481 clock-names = "dpaux", "parent";
2180 resets = <&bp 1482 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 1483 reset-names = "dpaux";
2182 status = "dis 1484 status = "disabled";
2183 1485
2184 power-domains 1486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 1487
2186 state_dpaux2_ 1488 state_dpaux2_aux: pinmux-aux {
2187 group 1489 groups = "dpaux-io";
2188 funct 1490 function = "aux";
2189 }; 1491 };
2190 1492
2191 state_dpaux2_ 1493 state_dpaux2_i2c: pinmux-i2c {
2192 group 1494 groups = "dpaux-io";
2193 funct 1495 function = "i2c";
2194 }; 1496 };
2195 1497
2196 state_dpaux2_ 1498 state_dpaux2_off: pinmux-off {
2197 group 1499 groups = "dpaux-io";
2198 funct 1500 function = "off";
2199 }; 1501 };
2200 1502
2201 i2c-bus { 1503 i2c-bus {
2202 #addr 1504 #address-cells = <1>;
2203 #size 1505 #size-cells = <0>;
2204 }; 1506 };
2205 }; 1507 };
2206 1508
2207 dpaux3: dpaux@155f000 1509 dpaux3: dpaux@155f0000 {
2208 compatible = 1510 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 1511 reg = <0x155f0000 0x10000>;
2210 interrupts = 1512 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 1513 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 1514 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 1515 clock-names = "dpaux", "parent";
2214 resets = <&bp 1516 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 1517 reset-names = "dpaux";
2216 status = "dis 1518 status = "disabled";
2217 1519
2218 power-domains 1520 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 1521
2220 state_dpaux3_ 1522 state_dpaux3_aux: pinmux-aux {
2221 group 1523 groups = "dpaux-io";
2222 funct 1524 function = "aux";
2223 }; 1525 };
2224 1526
2225 state_dpaux3_ 1527 state_dpaux3_i2c: pinmux-i2c {
2226 group 1528 groups = "dpaux-io";
2227 funct 1529 function = "i2c";
2228 }; 1530 };
2229 1531
2230 state_dpaux3_ 1532 state_dpaux3_off: pinmux-off {
2231 group 1533 groups = "dpaux-io";
2232 funct 1534 function = "off";
2233 }; 1535 };
2234 1536
2235 i2c-bus { 1537 i2c-bus {
2236 #addr 1538 #address-cells = <1>;
2237 #size 1539 #size-cells = <0>;
2238 }; 1540 };
2239 }; 1541 };
2240 1542
2241 nvenc@15a80000 { <<
2242 compatible = <<
2243 reg = <0x0 0x <<
2244 clocks = <&bp <<
2245 clock-names = <<
2246 resets = <&bp <<
2247 reset-names = <<
2248 <<
2249 power-domains <<
2250 interconnects <<
2251 <<
2252 <<
2253 interconnect- <<
2254 iommus = <&sm <<
2255 dma-coherent; <<
2256 <<
2257 nvidia,host1x <<
2258 }; <<
2259 <<
2260 sor0: sor@15b00000 { 1543 sor0: sor@15b00000 {
2261 compatible = 1544 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 1545 reg = <0x15b00000 0x40000>;
2263 interrupts = 1546 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 1547 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 1548 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 1549 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 1550 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 1551 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 1552 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 1553 clock-names = "sor", "out", "parent", "dp", "safe",
2271 1554 "pad";
2272 resets = <&bp 1555 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 1556 reset-names = "sor";
2274 pinctrl-0 = < 1557 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 1558 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 1559 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 1560 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 1561 status = "disabled";
2279 1562
2280 power-domains 1563 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 1564 nvidia,interface = <0>;
2282 }; 1565 };
2283 1566
2284 sor1: sor@15b40000 { 1567 sor1: sor@15b40000 {
2285 compatible = 1568 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 1569 reg = <0x15b40000 0x40000>;
2287 interrupts = 1570 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 1571 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 1572 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 1573 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 1574 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 1575 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 1576 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 1577 clock-names = "sor", "out", "parent", "dp", "safe",
2295 1578 "pad";
2296 resets = <&bp 1579 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 1580 reset-names = "sor";
2298 pinctrl-0 = < 1581 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 1582 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 1583 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 1584 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 1585 status = "disabled";
2303 1586
2304 power-domains 1587 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 1588 nvidia,interface = <1>;
2306 }; 1589 };
2307 1590
2308 sor2: sor@15b80000 { 1591 sor2: sor@15b80000 {
2309 compatible = 1592 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 1593 reg = <0x15b80000 0x40000>;
2311 interrupts = 1594 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 1595 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 1596 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 1597 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 1598 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 1599 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 1600 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 1601 clock-names = "sor", "out", "parent", "dp", "safe",
2319 1602 "pad";
2320 resets = <&bp 1603 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 1604 reset-names = "sor";
2322 pinctrl-0 = < 1605 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 1606 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 1607 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 1608 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 1609 status = "disabled";
2327 1610
2328 power-domains 1611 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 1612 nvidia,interface = <2>;
2330 }; 1613 };
2331 1614
2332 sor3: sor@15bc0000 { 1615 sor3: sor@15bc0000 {
2333 compatible = 1616 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 1617 reg = <0x15bc0000 0x40000>;
2335 interrupts = 1618 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 1619 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 1620 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 1621 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 1622 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 1623 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 1624 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 1625 clock-names = "sor", "out", "parent", "dp", "safe",
2343 1626 "pad";
2344 resets = <&bp 1627 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 1628 reset-names = "sor";
2346 pinctrl-0 = < 1629 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 1630 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 1631 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 1632 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 1633 status = "disabled";
2351 1634
2352 power-domains 1635 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 1636 nvidia,interface = <3>;
2354 }; 1637 };
2355 }; 1638 };
2356 1639
2357 pcie@14100000 { !! 1640 gpu@17000000 {
2358 compatible = "nvidia, !! 1641 compatible = "nvidia,gv11b";
2359 power-domains = <&bpm !! 1642 reg = <0x17000000 0x1000000>,
2360 reg = <0x00 0x1410000 !! 1643 <0x18000000 0x1000000>;
2361 <0x00 0x3000000 !! 1644 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2362 <0x00 0x3004000 !! 1645 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2363 <0x00 0x3008000 !! 1646 interrupt-names = "stall", "nonstall";
2364 reg-names = "appl", " !! 1647 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2365 !! 1648 <&bpmp TEGRA194_CLK_GPU_PWR>,
2366 status = "disabled"; !! 1649 <&bpmp TEGRA194_CLK_FUSE>;
2367 !! 1650 clock-names = "gpu", "pwr", "fuse";
2368 #address-cells = <3>; !! 1651 resets = <&bpmp TEGRA194_RESET_GPU>;
2369 #size-cells = <2>; !! 1652 reset-names = "gpu";
2370 device_type = "pci"; !! 1653 dma-coherent;
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 1654
2377 resets = <&bpmp TEGRA !! 1655 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2378 <&bpmp TEGRA !! 1656 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2379 reset-names = "apb", !! 1657 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
>> 1658 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
>> 1659 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
>> 1660 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
>> 1661 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
>> 1662 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
>> 1663 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
>> 1664 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
>> 1665 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
>> 1666 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
>> 1667 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
>> 1668 interconnect-names = "dma-mem", "read-0-hp", "write-0",
>> 1669 "read-1", "read-1-hp", "write-1",
>> 1670 "read-2", "read-2-hp", "write-2",
>> 1671 "read-3", "read-3-hp", "write-3";
>> 1672 };
>> 1673 };
2380 1674
2381 interrupts = <GIC_SPI !! 1675 pcie@14100000 {
2382 <GIC_SPI !! 1676 compatible = "nvidia,tegra194-pcie";
2383 interrupt-names = "in !! 1677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1678 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
>> 1679 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1680 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1681 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1682 reg-names = "appl", "config", "atu_dma", "dbi";
2384 1683
2385 #interrupt-cells = <1 !! 1684 status = "disabled";
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 1685
2389 nvidia,bpmp = <&bpmp !! 1686 #address-cells = <3>;
>> 1687 #size-cells = <2>;
>> 1688 device_type = "pci";
>> 1689 num-lanes = <1>;
>> 1690 num-viewport = <8>;
>> 1691 linux,pci-domain = <1>;
2390 1692
2391 nvidia,aspm-cmrt-us = !! 1693 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2392 nvidia,aspm-pwr-on-t- !! 1694 clock-names = "core";
2393 nvidia,aspm-l0s-entra <<
2394 1695
2395 bus-range = <0x0 0xff !! 1696 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 1697 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 1698 reset-names = "apb", "core";
2396 1699
2397 ranges = <0x43000000 !! 1700 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2398 <0x02000000 !! 1701 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2399 <0x01000000 !! 1702 interrupt-names = "intr", "msi";
2400 1703
2401 interconnects = <&mc !! 1704 #interrupt-cells = <1>;
2402 <&mc !! 1705 interrupt-map-mask = <0 0 0 0>;
2403 interconnect-names = !! 1706 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 1707
2409 pcie@14120000 { !! 1708 nvidia,bpmp = <&bpmp 1>;
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 1709
2418 status = "disabled"; !! 1710 nvidia,aspm-cmrt-us = <60>;
>> 1711 nvidia,aspm-pwr-on-t-us = <20>;
>> 1712 nvidia,aspm-l0s-entrance-latency-us = <3>;
2419 1713
2420 #address-cells = <3>; !! 1714 bus-range = <0x0 0xff>;
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 1715
2426 clocks = <&bpmp TEGRA !! 1716 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2427 clock-names = "core"; !! 1717 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1718 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2428 1719
2429 resets = <&bpmp TEGRA !! 1720 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2430 <&bpmp TEGRA !! 1721 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2431 reset-names = "apb", !! 1722 interconnect-names = "read", "write";
>> 1723 };
2432 1724
2433 interrupts = <GIC_SPI !! 1725 pcie@14120000 {
2434 <GIC_SPI !! 1726 compatible = "nvidia,tegra194-pcie";
2435 interrupt-names = "in !! 1727 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1728 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
>> 1729 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1730 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1731 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1732 reg-names = "appl", "config", "atu_dma", "dbi";
2436 1733
2437 #interrupt-cells = <1 !! 1734 status = "disabled";
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 1735
2441 nvidia,bpmp = <&bpmp !! 1736 #address-cells = <3>;
>> 1737 #size-cells = <2>;
>> 1738 device_type = "pci";
>> 1739 num-lanes = <1>;
>> 1740 num-viewport = <8>;
>> 1741 linux,pci-domain = <2>;
2442 1742
2443 nvidia,aspm-cmrt-us = !! 1743 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2444 nvidia,aspm-pwr-on-t- !! 1744 clock-names = "core";
2445 nvidia,aspm-l0s-entra <<
2446 1745
2447 bus-range = <0x0 0xff !! 1746 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 1747 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 1748 reset-names = "apb", "core";
2448 1749
2449 ranges = <0x43000000 !! 1750 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2450 <0x02000000 !! 1751 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2451 <0x01000000 !! 1752 interrupt-names = "intr", "msi";
2452 1753
2453 interconnects = <&mc !! 1754 #interrupt-cells = <1>;
2454 <&mc !! 1755 interrupt-map-mask = <0 0 0 0>;
2455 interconnect-names = !! 1756 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 1757
2461 pcie@14140000 { !! 1758 nvidia,bpmp = <&bpmp 2>;
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 1759
2470 status = "disabled"; !! 1760 nvidia,aspm-cmrt-us = <60>;
>> 1761 nvidia,aspm-pwr-on-t-us = <20>;
>> 1762 nvidia,aspm-l0s-entrance-latency-us = <3>;
2471 1763
2472 #address-cells = <3>; !! 1764 bus-range = <0x0 0xff>;
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 1765
2478 clocks = <&bpmp TEGRA !! 1766 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2479 clock-names = "core"; !! 1767 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1768 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2480 1769
2481 resets = <&bpmp TEGRA !! 1770 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2482 <&bpmp TEGRA !! 1771 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2483 reset-names = "apb", !! 1772 interconnect-names = "read", "write";
>> 1773 };
2484 1774
2485 interrupts = <GIC_SPI !! 1775 pcie@14140000 {
2486 <GIC_SPI !! 1776 compatible = "nvidia,tegra194-pcie";
2487 interrupt-names = "in !! 1777 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1778 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
>> 1779 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1780 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1781 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1782 reg-names = "appl", "config", "atu_dma", "dbi";
2488 1783
2489 #interrupt-cells = <1 !! 1784 status = "disabled";
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 1785
2493 nvidia,bpmp = <&bpmp !! 1786 #address-cells = <3>;
>> 1787 #size-cells = <2>;
>> 1788 device_type = "pci";
>> 1789 num-lanes = <1>;
>> 1790 num-viewport = <8>;
>> 1791 linux,pci-domain = <3>;
2494 1792
2495 nvidia,aspm-cmrt-us = !! 1793 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2496 nvidia,aspm-pwr-on-t- !! 1794 clock-names = "core";
2497 nvidia,aspm-l0s-entra <<
2498 1795
2499 bus-range = <0x0 0xff !! 1796 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 1797 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 1798 reset-names = "apb", "core";
2500 1799
2501 ranges = <0x43000000 !! 1800 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2502 <0x02000000 !! 1801 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2503 <0x01000000 !! 1802 interrupt-names = "intr", "msi";
2504 1803
2505 interconnects = <&mc !! 1804 #interrupt-cells = <1>;
2506 <&mc !! 1805 interrupt-map-mask = <0 0 0 0>;
2507 interconnect-names = !! 1806 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 1807
2513 pcie@14160000 { !! 1808 nvidia,bpmp = <&bpmp 3>;
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 1809
2522 status = "disabled"; !! 1810 nvidia,aspm-cmrt-us = <60>;
>> 1811 nvidia,aspm-pwr-on-t-us = <20>;
>> 1812 nvidia,aspm-l0s-entrance-latency-us = <3>;
2523 1813
2524 #address-cells = <3>; !! 1814 bus-range = <0x0 0xff>;
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 1815
2530 clocks = <&bpmp TEGRA !! 1816 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2531 clock-names = "core"; !! 1817 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
>> 1818 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2532 1819
2533 resets = <&bpmp TEGRA !! 1820 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2534 <&bpmp TEGRA !! 1821 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2535 reset-names = "apb", !! 1822 interconnect-names = "read", "write";
>> 1823 };
2536 1824
2537 interrupts = <GIC_SPI !! 1825 pcie@14160000 {
2538 <GIC_SPI !! 1826 compatible = "nvidia,tegra194-pcie";
2539 interrupt-names = "in !! 1827 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 1828 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 1829 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1830 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1831 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1832 reg-names = "appl", "config", "atu_dma", "dbi";
2540 1833
2541 #interrupt-cells = <1 !! 1834 status = "disabled";
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 1835
2545 nvidia,bpmp = <&bpmp !! 1836 #address-cells = <3>;
>> 1837 #size-cells = <2>;
>> 1838 device_type = "pci";
>> 1839 num-lanes = <4>;
>> 1840 num-viewport = <8>;
>> 1841 linux,pci-domain = <4>;
2546 1842
2547 nvidia,aspm-cmrt-us = !! 1843 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2548 nvidia,aspm-pwr-on-t- !! 1844 clock-names = "core";
2549 nvidia,aspm-l0s-entra <<
2550 1845
2551 bus-range = <0x0 0xff !! 1846 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 1847 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1848 reset-names = "apb", "core";
2552 1849
2553 ranges = <0x43000000 !! 1850 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2554 <0x02000000 !! 1851 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2555 <0x01000000 !! 1852 interrupt-names = "intr", "msi";
2556 1853
2557 interconnects = <&mc !! 1854 #interrupt-cells = <1>;
2558 <&mc !! 1855 interrupt-map-mask = <0 0 0 0>;
2559 interconnect-names = !! 1856 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 1857
2565 pcie-ep@14160000 { !! 1858 nvidia,bpmp = <&bpmp 4>;
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 1859
2574 status = "disabled"; !! 1860 nvidia,aspm-cmrt-us = <60>;
>> 1861 nvidia,aspm-pwr-on-t-us = <20>;
>> 1862 nvidia,aspm-l0s-entrance-latency-us = <3>;
2575 1863
2576 num-lanes = <4>; !! 1864 bus-range = <0x0 0xff>;
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 1865
2580 clocks = <&bpmp TEGRA !! 1866 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2581 clock-names = "core"; !! 1867 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 1868 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2582 1869
2583 resets = <&bpmp TEGRA !! 1870 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2584 <&bpmp TEGRA !! 1871 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2585 reset-names = "apb", !! 1872 interconnect-names = "read", "write";
>> 1873 };
2586 1874
2587 interrupts = <GIC_SPI !! 1875 pcie@14180000 {
2588 interrupt-names = "in !! 1876 compatible = "nvidia,tegra194-pcie";
>> 1877 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 1878 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 1879 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1880 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1881 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1882 reg-names = "appl", "config", "atu_dma", "dbi";
2589 1883
2590 nvidia,bpmp = <&bpmp !! 1884 status = "disabled";
2591 1885
2592 nvidia,aspm-cmrt-us = !! 1886 #address-cells = <3>;
2593 nvidia,aspm-pwr-on-t- !! 1887 #size-cells = <2>;
2594 nvidia,aspm-l0s-entra !! 1888 device_type = "pci";
>> 1889 num-lanes = <8>;
>> 1890 num-viewport = <8>;
>> 1891 linux,pci-domain = <0>;
2595 1892
2596 interconnects = <&mc !! 1893 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2597 <&mc !! 1894 clock-names = "core";
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 1895
2604 pcie@14180000 { !! 1896 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2605 compatible = "nvidia, !! 1897 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2606 power-domains = <&bpm !! 1898 reset-names = "apb", "core";
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 1899
2613 status = "disabled"; !! 1900 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1901 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1902 interrupt-names = "intr", "msi";
2614 1903
2615 #address-cells = <3>; !! 1904 #interrupt-cells = <1>;
2616 #size-cells = <2>; !! 1905 interrupt-map-mask = <0 0 0 0>;
2617 device_type = "pci"; !! 1906 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 1907
2621 clocks = <&bpmp TEGRA !! 1908 nvidia,bpmp = <&bpmp 0>;
2622 clock-names = "core"; <<
2623 1909
2624 resets = <&bpmp TEGRA !! 1910 nvidia,aspm-cmrt-us = <60>;
2625 <&bpmp TEGRA !! 1911 nvidia,aspm-pwr-on-t-us = <20>;
2626 reset-names = "apb", !! 1912 nvidia,aspm-l0s-entrance-latency-us = <3>;
2627 1913
2628 interrupts = <GIC_SPI !! 1914 bus-range = <0x0 0xff>;
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 1915
2632 #interrupt-cells = <1 !! 1916 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2633 interrupt-map-mask = !! 1917 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2634 interrupt-map = <0 0 !! 1918 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2635 1919
2636 nvidia,bpmp = <&bpmp !! 1920 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 1921 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 1922 interconnect-names = "read", "write";
>> 1923 };
2637 1924
2638 nvidia,aspm-cmrt-us = !! 1925 pcie@141a0000 {
2639 nvidia,aspm-pwr-on-t- !! 1926 compatible = "nvidia,tegra194-pcie";
2640 nvidia,aspm-l0s-entra !! 1927 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 1928 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 1929 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1930 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1931 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1932 reg-names = "appl", "config", "atu_dma", "dbi";
2641 1933
2642 bus-range = <0x0 0xff !! 1934 status = "disabled";
2643 1935
2644 ranges = <0x43000000 !! 1936 #address-cells = <3>;
2645 <0x02000000 !! 1937 #size-cells = <2>;
2646 <0x01000000 !! 1938 device_type = "pci";
>> 1939 num-lanes = <8>;
>> 1940 num-viewport = <8>;
>> 1941 linux,pci-domain = <5>;
2647 1942
2648 interconnects = <&mc !! 1943 pinctrl-names = "default";
2649 <&mc !! 1944 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 1945
2656 pcie-ep@14180000 { !! 1946 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2657 compatible = "nvidia, !! 1947 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2658 power-domains = <&bpm !! 1948 clock-names = "core", "core_m";
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 1949
2665 status = "disabled"; !! 1950 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 1951 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 1952 reset-names = "apb", "core";
2666 1953
2667 num-lanes = <8>; !! 1954 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2668 num-ib-windows = <2>; !! 1955 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2669 num-ob-windows = <8>; !! 1956 interrupt-names = "intr", "msi";
2670 1957
2671 clocks = <&bpmp TEGRA !! 1958 nvidia,bpmp = <&bpmp 5>;
2672 clock-names = "core"; <<
2673 1959
2674 resets = <&bpmp TEGRA !! 1960 #interrupt-cells = <1>;
2675 <&bpmp TEGRA !! 1961 interrupt-map-mask = <0 0 0 0>;
2676 reset-names = "apb", !! 1962 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2677 1963
2678 interrupts = <GIC_SPI !! 1964 nvidia,aspm-cmrt-us = <60>;
2679 interrupt-names = "in !! 1965 nvidia,aspm-pwr-on-t-us = <20>;
>> 1966 nvidia,aspm-l0s-entrance-latency-us = <3>;
2680 1967
2681 nvidia,bpmp = <&bpmp !! 1968 bus-range = <0x0 0xff>;
2682 1969
2683 nvidia,aspm-cmrt-us = !! 1970 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2684 nvidia,aspm-pwr-on-t- !! 1971 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2685 nvidia,aspm-l0s-entra !! 1972 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2686 1973
2687 interconnects = <&mc !! 1974 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2688 <&mc !! 1975 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2689 interconnect-names = !! 1976 interconnect-names = "read", "write";
2690 iommu-map = <0x0 &smm !! 1977 };
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 1978
2695 pcie@141a0000 { !! 1979 pcie_ep@14160000 {
2696 compatible = "nvidia, !! 1980 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2697 power-domains = <&bpm !! 1981 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2698 reg = <0x00 0x141a000 !! 1982 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2699 <0x00 0x3a00000 !! 1983 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2700 <0x00 0x3a04000 !! 1984 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2701 <0x00 0x3a08000 !! 1985 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2702 reg-names = "appl", " !! 1986 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2703 1987
2704 status = "disabled"; !! 1988 status = "disabled";
2705 1989
2706 #address-cells = <3>; !! 1990 num-lanes = <4>;
2707 #size-cells = <2>; !! 1991 num-ib-windows = <2>;
2708 device_type = "pci"; !! 1992 num-ob-windows = <8>;
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 1993
2712 pinctrl-names = "defa !! 1994 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2713 pinctrl-0 = <&pex_rst !! 1995 clock-names = "core";
2714 1996
2715 clocks = <&bpmp TEGRA !! 1997 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2716 clock-names = "core"; !! 1998 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1999 reset-names = "apb", "core";
2717 2000
2718 resets = <&bpmp TEGRA !! 2001 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2719 <&bpmp TEGRA !! 2002 interrupt-names = "intr";
2720 reset-names = "apb", <<
2721 2003
2722 interrupts = <GIC_SPI !! 2004 nvidia,bpmp = <&bpmp 4>;
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 2005
2726 nvidia,bpmp = <&bpmp !! 2006 nvidia,aspm-cmrt-us = <60>;
>> 2007 nvidia,aspm-pwr-on-t-us = <20>;
>> 2008 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2009 };
2727 2010
2728 #interrupt-cells = <1 !! 2011 pcie_ep@14180000 {
2729 interrupt-map-mask = !! 2012 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2730 interrupt-map = <0 0 !! 2013 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2014 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2015 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2016 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2017 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2018 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2731 2019
2732 nvidia,aspm-cmrt-us = !! 2020 status = "disabled";
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 2021
2736 bus-range = <0x0 0xff !! 2022 num-lanes = <8>;
>> 2023 num-ib-windows = <2>;
>> 2024 num-ob-windows = <8>;
2737 2025
2738 ranges = <0x43000000 !! 2026 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2739 <0x02000000 !! 2027 clock-names = "core";
2740 <0x01000000 <<
2741 2028
2742 interconnects = <&mc !! 2029 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2743 <&mc !! 2030 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2744 interconnect-names = !! 2031 reset-names = "apb", "core";
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 2032
2750 pcie-ep@141a0000 { !! 2033 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2751 compatible = "nvidia, !! 2034 interrupt-names = "intr";
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 2035
2759 status = "disabled"; !! 2036 nvidia,bpmp = <&bpmp 0>;
2760 2037
2761 num-lanes = <8>; !! 2038 nvidia,aspm-cmrt-us = <60>;
2762 num-ib-windows = <2>; !! 2039 nvidia,aspm-pwr-on-t-us = <20>;
2763 num-ob-windows = <8>; !! 2040 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2041 };
2764 2042
2765 pinctrl-names = "defa !! 2043 pcie_ep@141a0000 {
2766 pinctrl-0 = <&pex_clk !! 2044 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
>> 2045 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2046 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2047 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2048 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2049 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2050 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2767 2051
2768 clocks = <&bpmp TEGRA !! 2052 status = "disabled";
2769 clock-names = "core"; <<
2770 2053
2771 resets = <&bpmp TEGRA !! 2054 num-lanes = <8>;
2772 <&bpmp TEGRA !! 2055 num-ib-windows = <2>;
2773 reset-names = "apb", !! 2056 num-ob-windows = <8>;
2774 2057
2775 interrupts = <GIC_SPI !! 2058 pinctrl-names = "default";
2776 interrupt-names = "in !! 2059 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2777 2060
2778 nvidia,bpmp = <&bpmp !! 2061 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2062 clock-names = "core";
2779 2063
2780 nvidia,aspm-cmrt-us = !! 2064 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2781 nvidia,aspm-pwr-on-t- !! 2065 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2782 nvidia,aspm-l0s-entra !! 2066 reset-names = "apb", "core";
2783 2067
2784 interconnects = <&mc !! 2068 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2785 <&mc !! 2069 interrupt-names = "intr";
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 2070
2792 gpu@17000000 { !! 2071 nvidia,bpmp = <&bpmp 5>;
2793 compatible = "nvidia, <<
2794 reg = <0x0 0x17000000 <<
2795 <0x0 0x18000000 <<
2796 interrupts = <GIC_SPI <<
2797 <GIC_SPI <<
2798 interrupt-names = "st <<
2799 clocks = <&bpmp TEGRA <<
2800 <&bpmp TEGRA <<
2801 <&bpmp TEGRA <<
2802 clock-names = "gpu", <<
2803 resets = <&bpmp TEGRA <<
2804 reset-names = "gpu"; <<
2805 dma-coherent; <<
2806 2072
2807 power-domains = <&bpm !! 2073 nvidia,aspm-cmrt-us = <60>;
2808 interconnects = <&mc !! 2074 nvidia,aspm-pwr-on-t-us = <20>;
2809 <&mc !! 2075 nvidia,aspm-l0s-entrance-latency-us = <3>;
2810 <&mc <<
2811 <&mc <<
2812 <&mc <<
2813 <&mc <<
2814 <&mc <<
2815 <&mc <<
2816 <&mc <<
2817 <&mc <<
2818 <&mc <<
2819 <&mc <<
2820 interconnect-names = <<
2821 <<
2822 <<
2823 <<
2824 }; <<
2825 }; 2076 };
2826 2077
2827 sram@40000000 { 2078 sram@40000000 {
2828 compatible = "nvidia,tegra194 2079 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 2080 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 2081 #address-cells = <1>;
2832 #size-cells = <1>; 2082 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 2083 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 2084
2835 no-memory-wc; <<
2836 <<
2837 cpu_bpmp_tx: sram@4e000 { 2085 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000 2086 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 2087 label = "cpu-bpmp-tx";
2840 pool; 2088 pool;
2841 }; 2089 };
2842 2090
2843 cpu_bpmp_rx: sram@4f000 { 2091 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000 2092 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 2093 label = "cpu-bpmp-rx";
2846 pool; 2094 pool;
2847 }; 2095 };
2848 }; 2096 };
2849 2097
2850 bpmp: bpmp { 2098 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 2099 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 2100 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 2101 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu !! 2102 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2855 #clock-cells = <1>; 2103 #clock-cells = <1>;
2856 #reset-cells = <1>; 2104 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 2105 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 2106 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859 <&mc TEGRA194 2107 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860 <&mc TEGRA194 2108 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861 <&mc TEGRA194 2109 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862 interconnect-names = "read", 2110 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863 iommus = <&smmu TEGRA194_SID_ <<
2864 2111
2865 bpmp_i2c: i2c { 2112 bpmp_i2c: i2c {
2866 compatible = "nvidia, 2113 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 2114 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 2115 #address-cells = <1>;
2869 #size-cells = <0>; 2116 #size-cells = <0>;
2870 }; 2117 };
2871 2118
2872 bpmp_thermal: thermal { 2119 bpmp_thermal: thermal {
2873 compatible = "nvidia, 2120 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 2121 #thermal-sensor-cells = <1>;
2875 }; 2122 };
2876 }; 2123 };
2877 2124
2878 cpus { 2125 cpus {
2879 compatible = "nvidia,tegra194 2126 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>; 2127 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>; 2128 #address-cells = <1>;
2882 #size-cells = <0>; 2129 #size-cells = <0>;
2883 2130
2884 cpu0_0: cpu@0 { 2131 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 2132 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 2133 device_type = "cpu";
2887 reg = <0x000>; 2134 reg = <0x000>;
2888 enable-method = "psci 2135 enable-method = "psci";
2889 i-cache-size = <13107 2136 i-cache-size = <131072>;
2890 i-cache-line-size = < 2137 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 2138 i-cache-sets = <512>;
2892 d-cache-size = <65536 2139 d-cache-size = <65536>;
2893 d-cache-line-size = < 2140 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 2141 d-cache-sets = <256>;
2895 next-level-cache = <& 2142 next-level-cache = <&l2c_0>;
2896 }; 2143 };
2897 2144
2898 cpu0_1: cpu@1 { 2145 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 2146 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 2147 device_type = "cpu";
2901 reg = <0x001>; 2148 reg = <0x001>;
2902 enable-method = "psci 2149 enable-method = "psci";
2903 i-cache-size = <13107 2150 i-cache-size = <131072>;
2904 i-cache-line-size = < 2151 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 2152 i-cache-sets = <512>;
2906 d-cache-size = <65536 2153 d-cache-size = <65536>;
2907 d-cache-line-size = < 2154 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 2155 d-cache-sets = <256>;
2909 next-level-cache = <& 2156 next-level-cache = <&l2c_0>;
2910 }; 2157 };
2911 2158
2912 cpu1_0: cpu@100 { 2159 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 2160 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 2161 device_type = "cpu";
2915 reg = <0x100>; 2162 reg = <0x100>;
2916 enable-method = "psci 2163 enable-method = "psci";
2917 i-cache-size = <13107 2164 i-cache-size = <131072>;
2918 i-cache-line-size = < 2165 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 2166 i-cache-sets = <512>;
2920 d-cache-size = <65536 2167 d-cache-size = <65536>;
2921 d-cache-line-size = < 2168 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 2169 d-cache-sets = <256>;
2923 next-level-cache = <& 2170 next-level-cache = <&l2c_1>;
2924 }; 2171 };
2925 2172
2926 cpu1_1: cpu@101 { 2173 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 2174 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 2175 device_type = "cpu";
2929 reg = <0x101>; 2176 reg = <0x101>;
2930 enable-method = "psci 2177 enable-method = "psci";
2931 i-cache-size = <13107 2178 i-cache-size = <131072>;
2932 i-cache-line-size = < 2179 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 2180 i-cache-sets = <512>;
2934 d-cache-size = <65536 2181 d-cache-size = <65536>;
2935 d-cache-line-size = < 2182 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 2183 d-cache-sets = <256>;
2937 next-level-cache = <& 2184 next-level-cache = <&l2c_1>;
2938 }; 2185 };
2939 2186
2940 cpu2_0: cpu@200 { 2187 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 2188 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 2189 device_type = "cpu";
2943 reg = <0x200>; 2190 reg = <0x200>;
2944 enable-method = "psci 2191 enable-method = "psci";
2945 i-cache-size = <13107 2192 i-cache-size = <131072>;
2946 i-cache-line-size = < 2193 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 2194 i-cache-sets = <512>;
2948 d-cache-size = <65536 2195 d-cache-size = <65536>;
2949 d-cache-line-size = < 2196 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 2197 d-cache-sets = <256>;
2951 next-level-cache = <& 2198 next-level-cache = <&l2c_2>;
2952 }; 2199 };
2953 2200
2954 cpu2_1: cpu@201 { 2201 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 2202 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 2203 device_type = "cpu";
2957 reg = <0x201>; 2204 reg = <0x201>;
2958 enable-method = "psci 2205 enable-method = "psci";
2959 i-cache-size = <13107 2206 i-cache-size = <131072>;
2960 i-cache-line-size = < 2207 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 2208 i-cache-sets = <512>;
2962 d-cache-size = <65536 2209 d-cache-size = <65536>;
2963 d-cache-line-size = < 2210 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 2211 d-cache-sets = <256>;
2965 next-level-cache = <& 2212 next-level-cache = <&l2c_2>;
2966 }; 2213 };
2967 2214
2968 cpu3_0: cpu@300 { 2215 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 2216 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 2217 device_type = "cpu";
2971 reg = <0x300>; 2218 reg = <0x300>;
2972 enable-method = "psci 2219 enable-method = "psci";
2973 i-cache-size = <13107 2220 i-cache-size = <131072>;
2974 i-cache-line-size = < 2221 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 2222 i-cache-sets = <512>;
2976 d-cache-size = <65536 2223 d-cache-size = <65536>;
2977 d-cache-line-size = < 2224 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 2225 d-cache-sets = <256>;
2979 next-level-cache = <& 2226 next-level-cache = <&l2c_3>;
2980 }; 2227 };
2981 2228
2982 cpu3_1: cpu@301 { 2229 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 2230 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 2231 device_type = "cpu";
2985 reg = <0x301>; 2232 reg = <0x301>;
2986 enable-method = "psci 2233 enable-method = "psci";
2987 i-cache-size = <13107 2234 i-cache-size = <131072>;
2988 i-cache-line-size = < 2235 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 2236 i-cache-sets = <512>;
2990 d-cache-size = <65536 2237 d-cache-size = <65536>;
2991 d-cache-line-size = < 2238 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 2239 d-cache-sets = <256>;
2993 next-level-cache = <& 2240 next-level-cache = <&l2c_3>;
2994 }; 2241 };
2995 2242
2996 cpu-map { 2243 cpu-map {
2997 cluster0 { 2244 cluster0 {
2998 core0 { 2245 core0 {
2999 cpu = 2246 cpu = <&cpu0_0>;
3000 }; 2247 };
3001 2248
3002 core1 { 2249 core1 {
3003 cpu = 2250 cpu = <&cpu0_1>;
3004 }; 2251 };
3005 }; 2252 };
3006 2253
3007 cluster1 { 2254 cluster1 {
3008 core0 { 2255 core0 {
3009 cpu = 2256 cpu = <&cpu1_0>;
3010 }; 2257 };
3011 2258
3012 core1 { 2259 core1 {
3013 cpu = 2260 cpu = <&cpu1_1>;
3014 }; 2261 };
3015 }; 2262 };
3016 2263
3017 cluster2 { 2264 cluster2 {
3018 core0 { 2265 core0 {
3019 cpu = 2266 cpu = <&cpu2_0>;
3020 }; 2267 };
3021 2268
3022 core1 { 2269 core1 {
3023 cpu = 2270 cpu = <&cpu2_1>;
3024 }; 2271 };
3025 }; 2272 };
3026 2273
3027 cluster3 { 2274 cluster3 {
3028 core0 { 2275 core0 {
3029 cpu = 2276 cpu = <&cpu3_0>;
3030 }; 2277 };
3031 2278
3032 core1 { 2279 core1 {
3033 cpu = 2280 cpu = <&cpu3_1>;
3034 }; 2281 };
3035 }; 2282 };
3036 }; 2283 };
3037 2284
3038 l2c_0: l2-cache0 { 2285 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 2286 cache-size = <2097152>;
3042 cache-line-size = <64 2287 cache-line-size = <64>;
3043 cache-sets = <2048>; 2288 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 2289 next-level-cache = <&l3c>;
3046 }; 2290 };
3047 2291
3048 l2c_1: l2-cache1 { 2292 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 2293 cache-size = <2097152>;
3052 cache-line-size = <64 2294 cache-line-size = <64>;
3053 cache-sets = <2048>; 2295 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 2296 next-level-cache = <&l3c>;
3056 }; 2297 };
3057 2298
3058 l2c_2: l2-cache2 { 2299 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 2300 cache-size = <2097152>;
3062 cache-line-size = <64 2301 cache-line-size = <64>;
3063 cache-sets = <2048>; 2302 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 2303 next-level-cache = <&l3c>;
3066 }; 2304 };
3067 2305
3068 l2c_3: l2-cache3 { 2306 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 2307 cache-size = <2097152>;
3072 cache-line-size = <64 2308 cache-line-size = <64>;
3073 cache-sets = <2048>; 2309 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 2310 next-level-cache = <&l3c>;
3076 }; 2311 };
3077 2312
3078 l3c: l3-cache { 2313 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 2314 cache-size = <4194304>;
3082 cache-line-size = <64 2315 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 2316 cache-sets = <4096>;
3085 }; 2317 };
3086 }; 2318 };
3087 2319
3088 pmu { <<
3089 compatible = "nvidia,carmel-p <<
3090 interrupts = <GIC_SPI 384 IRQ <<
3091 <GIC_SPI 385 IRQ <<
3092 <GIC_SPI 386 IRQ <<
3093 <GIC_SPI 387 IRQ <<
3094 <GIC_SPI 388 IRQ <<
3095 <GIC_SPI 389 IRQ <<
3096 <GIC_SPI 390 IRQ <<
3097 <GIC_SPI 391 IRQ <<
3098 interrupt-affinity = <&cpu0_0 <<
3099 &cpu2_0 <<
3100 }; <<
3101 <<
3102 psci { 2320 psci {
3103 compatible = "arm,psci-1.0"; 2321 compatible = "arm,psci-1.0";
3104 status = "okay"; 2322 status = "okay";
3105 method = "smc"; 2323 method = "smc";
3106 }; 2324 };
3107 2325
3108 tcu: serial { !! 2326 tcu: tcu {
3109 compatible = "nvidia,tegra194 2327 compatible = "nvidia,tegra194-tcu";
3110 mboxes = <&hsp_top0 TEGRA_HSP 2328 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3111 <&hsp_aon TEGRA_HSP_ !! 2329 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3112 mbox-names = "rx", "tx"; 2330 mbox-names = "rx", "tx";
3113 }; 2331 };
3114 2332
3115 sound { <<
3116 status = "disabled"; <<
3117 <<
3118 clocks = <&bpmp TEGRA194_CLK_ <<
3119 <&bpmp TEGRA194_CLK_ <<
3120 clock-names = "pll_a", "plla_ <<
3121 assigned-clocks = <&bpmp TEGR <<
3122 <&bpmp TEGR <<
3123 <&bpmp TEGR <<
3124 assigned-clock-parents = <0>, <<
3125 <&bp <<
3126 <&bp <<
3127 /* <<
3128 * PLLA supports dynamic ramp <<
3129 * for this to work and oscil <<
3130 * for 8x and 11.025x sample <<
3131 */ <<
3132 assigned-clock-rates = <25800 <<
3133 }; <<
3134 <<
3135 thermal-zones { 2333 thermal-zones {
3136 cpu-thermal { !! 2334 cpu {
3137 thermal-sensors = <&{ !! 2335 thermal-sensors = <&{/bpmp/thermal}
>> 2336 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 2337 status = "disabled";
3139 }; 2338 };
3140 2339
3141 gpu-thermal { !! 2340 gpu {
3142 thermal-sensors = <&{ !! 2341 thermal-sensors = <&{/bpmp/thermal}
>> 2342 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 2343 status = "disabled";
3144 }; 2344 };
3145 2345
3146 aux-thermal { !! 2346 aux {
3147 thermal-sensors = <&{ !! 2347 thermal-sensors = <&{/bpmp/thermal}
>> 2348 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 2349 status = "disabled";
3149 }; 2350 };
3150 2351
3151 pllx-thermal { !! 2352 pllx {
3152 thermal-sensors = <&{ !! 2353 thermal-sensors = <&{/bpmp/thermal}
>> 2354 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 2355 status = "disabled";
3154 }; 2356 };
3155 2357
3156 ao-thermal { !! 2358 ao {
3157 thermal-sensors = <&{ !! 2359 thermal-sensors = <&{/bpmp/thermal}
>> 2360 TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 2361 status = "disabled";
3159 }; 2362 };
3160 2363
3161 tj-thermal { !! 2364 tj {
3162 thermal-sensors = <&{ !! 2365 thermal-sensors = <&{/bpmp/thermal}
>> 2366 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 2367 status = "disabled";
3164 }; 2368 };
3165 }; 2369 };
3166 2370
3167 timer { 2371 timer {
3168 compatible = "arm,armv8-timer 2372 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 2373 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 2374 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 2375 <GIC_PPI 14
3172 (GIC_CPU_MASK 2376 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 2377 <GIC_PPI 11
3174 (GIC_CPU_MASK 2378 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 2379 <GIC_PPI 10
3176 (GIC_CPU_MASK 2380 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 2381 interrupt-parent = <&gic>;
3178 always-on; 2382 always-on;
3179 }; 2383 };
3180 }; 2384 };
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