1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 7 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 8 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 10 #include <dt-bindings/memory/tegra194-mc.h>
12 11
13 / { 12 / {
14 compatible = "nvidia,tegra194"; 13 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
16 #address-cells = <2>; 15 #address-cells = <2>;
17 #size-cells = <2>; 16 #size-cells = <2>;
18 17
19 /* control backbone */ 18 /* control backbone */
20 bus@0 { 19 bus@0 {
21 compatible = "simple-bus"; 20 compatible = "simple-bus";
>> 21 #address-cells = <1>;
>> 22 #size-cells = <1>;
>> 23 ranges = <0x0 0x0 0x0 0x40000000>;
22 24
23 #address-cells = <2>; !! 25 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 26 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 27 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 28 <0x0010f000 0x1000>;
31 }; 29 };
32 30
33 gpio: gpio@2200000 { 31 gpio: gpio@2200000 {
34 compatible = "nvidia,t 32 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 33 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 34 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 35 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI <<
40 <GIC_SPI <<
41 <GIC_SPI <<
42 <GIC_SPI <<
43 <GIC_SPI <<
44 <GIC_SPI <<
45 <GIC_SPI <<
46 <GIC_SPI 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI <<
48 <GIC_SPI <<
49 <GIC_SPI <<
50 <GIC_SPI <<
51 <GIC_SPI <<
52 <GIC_SPI <<
53 <GIC_SPI <<
54 <GIC_SPI 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI <<
56 <GIC_SPI <<
57 <GIC_SPI <<
58 <GIC_SPI <<
59 <GIC_SPI <<
60 <GIC_SPI <<
61 <GIC_SPI <<
62 <GIC_SPI 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI <<
64 <GIC_SPI <<
65 <GIC_SPI <<
66 <GIC_SPI <<
67 <GIC_SPI <<
68 <GIC_SPI <<
69 <GIC_SPI <<
70 <GIC_SPI 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI !! 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
72 <GIC_SPI <<
73 <GIC_SPI <<
74 <GIC_SPI <<
75 <GIC_SPI <<
76 <GIC_SPI <<
77 <GIC_SPI <<
78 <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 #interrupt-cells = <2> 42 #interrupt-cells = <2>;
87 interrupt-controller; 43 interrupt-controller;
88 #gpio-cells = <2>; 44 #gpio-cells = <2>;
89 gpio-controller; 45 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 46 };
141 47
142 ethernet@2490000 { 48 ethernet@2490000 {
143 compatible = "nvidia,t 49 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 50 "nvidia,tegra186-eqos",
145 "snps,dwc 51 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 52 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 56 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 57 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 60 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 61 reset-names = "eqos";
156 interconnects = <&mc T 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
157 <&mc T 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
158 interconnect-names = " 64 interconnect-names = "dma-mem", "write";
159 iommus = <&smmu TEGRA1 <<
160 status = "disabled"; 65 status = "disabled";
161 66
162 snps,write-requests = 67 snps,write-requests = <1>;
163 snps,read-requests = < 68 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 69 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 70 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 71 snps,rxpbl = <8>;
167 }; 72 };
168 73
169 gpcdma: dma-controller@2600000 <<
170 compatible = "nvidia,t <<
171 "nvidia,t <<
172 reg = <0x0 0x2600000 0 <<
173 resets = <&bpmp TEGRA1 <<
174 reset-names = "gpcdma" <<
175 interrupts = <GIC_SPI <<
176 <GIC_SPI <<
177 <GIC_SPI <<
178 <GIC_SPI <<
179 <GIC_SPI <<
180 <GIC_SPI <<
181 <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 #dma-cells = <1>; <<
208 iommus = <&smmu TEGRA1 <<
209 dma-coherent; <<
210 dma-channel-mask = <0x <<
211 status = "okay"; <<
212 }; <<
213 <<
214 aconnect@2900000 { 74 aconnect@2900000 {
215 compatible = "nvidia,t 75 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 76 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 77 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 78 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 79 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 81 #address-cells = <1>;
>> 82 #size-cells = <1>;
>> 83 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 84 status = "disabled";
222 85
223 #address-cells = <2>; !! 86 adma: dma-controller@2930000 {
224 #size-cells = <2>; !! 87 compatible = "nvidia,tegra194-adma",
225 ranges = <0x0 0x029000 !! 88 "nvidia,tegra186-adma";
>> 89 reg = <0x02930000 0x20000>;
>> 90 interrupt-parent = <&agic>;
>> 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 123 #dma-cells = <1>;
>> 124 clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> 125 clock-names = "d_audio";
>> 126 status = "disabled";
>> 127 };
>> 128
>> 129 agic: interrupt-controller@2a40000 {
>> 130 compatible = "nvidia,tegra194-agic",
>> 131 "nvidia,tegra210-agic";
>> 132 #interrupt-cells = <3>;
>> 133 interrupt-controller;
>> 134 reg = <0x02a41000 0x1000>,
>> 135 <0x02a42000 0x2000>;
>> 136 interrupts = <GIC_SPI 145
>> 137 (GIC_CPU_MASK_SIMPLE(4) |
>> 138 IRQ_TYPE_LEVEL_HIGH)>;
>> 139 clocks = <&bpmp TEGRA194_CLK_APE>;
>> 140 clock-names = "clk";
>> 141 status = "disabled";
>> 142 };
226 143
227 tegra_ahub: ahub@29008 144 tegra_ahub: ahub@2900800 {
228 compatible = " 145 compatible = "nvidia,tegra194-ahub",
229 " 146 "nvidia,tegra186-ahub";
230 reg = <0x0 0x0 !! 147 reg = <0x02900800 0x800>;
231 clocks = <&bpm 148 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = 149 clock-names = "ahub";
233 assigned-clock 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock !! 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
235 assigned-clock !! 152 #address-cells = <1>;
>> 153 #size-cells = <1>;
>> 154 ranges = <0x02900800 0x02900800 0x11800>;
236 status = "disa 155 status = "disabled";
237 156
238 #address-cells !! 157 tegra_admaif: admaif@290f000 {
239 #size-cells = !! 158 compatible = "nvidia,tegra194-admaif",
240 ranges = <0x0 !! 159 "nvidia,tegra186-admaif";
>> 160 reg = <0x0290f000 0x1000>;
>> 161 dmas = <&adma 1>, <&adma 1>,
>> 162 <&adma 2>, <&adma 2>,
>> 163 <&adma 3>, <&adma 3>,
>> 164 <&adma 4>, <&adma 4>,
>> 165 <&adma 5>, <&adma 5>,
>> 166 <&adma 6>, <&adma 6>,
>> 167 <&adma 7>, <&adma 7>,
>> 168 <&adma 8>, <&adma 8>,
>> 169 <&adma 9>, <&adma 9>,
>> 170 <&adma 10>, <&adma 10>,
>> 171 <&adma 11>, <&adma 11>,
>> 172 <&adma 12>, <&adma 12>,
>> 173 <&adma 13>, <&adma 13>,
>> 174 <&adma 14>, <&adma 14>,
>> 175 <&adma 15>, <&adma 15>,
>> 176 <&adma 16>, <&adma 16>,
>> 177 <&adma 17>, <&adma 17>,
>> 178 <&adma 18>, <&adma 18>,
>> 179 <&adma 19>, <&adma 19>,
>> 180 <&adma 20>, <&adma 20>;
>> 181 dma-names = "rx1", "tx1",
>> 182 "rx2", "tx2",
>> 183 "rx3", "tx3",
>> 184 "rx4", "tx4",
>> 185 "rx5", "tx5",
>> 186 "rx6", "tx6",
>> 187 "rx7", "tx7",
>> 188 "rx8", "tx8",
>> 189 "rx9", "tx9",
>> 190 "rx10", "tx10",
>> 191 "rx11", "tx11",
>> 192 "rx12", "tx12",
>> 193 "rx13", "tx13",
>> 194 "rx14", "tx14",
>> 195 "rx15", "tx15",
>> 196 "rx16", "tx16",
>> 197 "rx17", "tx17",
>> 198 "rx18", "tx18",
>> 199 "rx19", "tx19",
>> 200 "rx20", "tx20";
>> 201 status = "disabled";
>> 202 };
241 203
242 tegra_i2s1: i2 204 tegra_i2s1: i2s@2901000 {
243 compat 205 compatible = "nvidia,tegra194-i2s",
244 206 "nvidia,tegra210-i2s";
245 reg = !! 207 reg = <0x2901000 0x100>;
246 clocks 208 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock- 210 clock-names = "i2s", "sync_input";
249 assign 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assign 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assign 213 assigned-clock-rates = <1536000>;
252 sound- 214 sound-name-prefix = "I2S1";
253 status 215 status = "disabled";
254 }; 216 };
255 217
256 tegra_i2s2: i2 218 tegra_i2s2: i2s@2901100 {
257 compat 219 compatible = "nvidia,tegra194-i2s",
258 220 "nvidia,tegra210-i2s";
259 reg = !! 221 reg = <0x2901100 0x100>;
260 clocks 222 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock- 224 clock-names = "i2s", "sync_input";
263 assign 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assign 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assign 227 assigned-clock-rates = <1536000>;
266 sound- 228 sound-name-prefix = "I2S2";
267 status 229 status = "disabled";
268 }; 230 };
269 231
270 tegra_i2s3: i2 232 tegra_i2s3: i2s@2901200 {
271 compat 233 compatible = "nvidia,tegra194-i2s",
272 234 "nvidia,tegra210-i2s";
273 reg = !! 235 reg = <0x2901200 0x100>;
274 clocks 236 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock- 238 clock-names = "i2s", "sync_input";
277 assign 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assign 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assign 241 assigned-clock-rates = <1536000>;
280 sound- 242 sound-name-prefix = "I2S3";
281 status 243 status = "disabled";
282 }; 244 };
283 245
284 tegra_i2s4: i2 246 tegra_i2s4: i2s@2901300 {
285 compat 247 compatible = "nvidia,tegra194-i2s",
286 248 "nvidia,tegra210-i2s";
287 reg = !! 249 reg = <0x2901300 0x100>;
288 clocks 250 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock- 252 clock-names = "i2s", "sync_input";
291 assign 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assign 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assign 255 assigned-clock-rates = <1536000>;
294 sound- 256 sound-name-prefix = "I2S4";
295 status 257 status = "disabled";
296 }; 258 };
297 259
298 tegra_i2s5: i2 260 tegra_i2s5: i2s@2901400 {
299 compat 261 compatible = "nvidia,tegra194-i2s",
300 262 "nvidia,tegra210-i2s";
301 reg = !! 263 reg = <0x2901400 0x100>;
302 clocks 264 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock- 266 clock-names = "i2s", "sync_input";
305 assign 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assign 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assign 269 assigned-clock-rates = <1536000>;
308 sound- 270 sound-name-prefix = "I2S5";
309 status 271 status = "disabled";
310 }; 272 };
311 273
312 tegra_i2s6: i2 274 tegra_i2s6: i2s@2901500 {
313 compat 275 compatible = "nvidia,tegra194-i2s",
314 276 "nvidia,tegra210-i2s";
315 reg = !! 277 reg = <0x2901500 0x100>;
316 clocks 278 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock- 280 clock-names = "i2s", "sync_input";
319 assign 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assign 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assign 283 assigned-clock-rates = <1536000>;
322 sound- 284 sound-name-prefix = "I2S6";
323 status 285 status = "disabled";
324 }; 286 };
325 287
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d 288 tegra_dmic1: dmic@2904000 {
419 compat 289 compatible = "nvidia,tegra194-dmic",
420 290 "nvidia,tegra210-dmic";
421 reg = !! 291 reg = <0x2904000 0x100>;
422 clocks 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock- 293 clock-names = "dmic";
424 assign 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assign 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assign 296 assigned-clock-rates = <3072000>;
427 sound- 297 sound-name-prefix = "DMIC1";
428 status 298 status = "disabled";
429 }; 299 };
430 300
431 tegra_dmic2: d 301 tegra_dmic2: dmic@2904100 {
432 compat 302 compatible = "nvidia,tegra194-dmic",
433 303 "nvidia,tegra210-dmic";
434 reg = !! 304 reg = <0x2904100 0x100>;
435 clocks 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock- 306 clock-names = "dmic";
437 assign 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assign 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assign 309 assigned-clock-rates = <3072000>;
440 sound- 310 sound-name-prefix = "DMIC2";
441 status 311 status = "disabled";
442 }; 312 };
443 313
444 tegra_dmic3: d 314 tegra_dmic3: dmic@2904200 {
445 compat 315 compatible = "nvidia,tegra194-dmic",
446 316 "nvidia,tegra210-dmic";
447 reg = !! 317 reg = <0x2904200 0x100>;
448 clocks 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock- 319 clock-names = "dmic";
450 assign 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assign 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assign 322 assigned-clock-rates = <3072000>;
453 sound- 323 sound-name-prefix = "DMIC3";
454 status 324 status = "disabled";
455 }; 325 };
456 326
457 tegra_dmic4: d 327 tegra_dmic4: dmic@2904300 {
458 compat 328 compatible = "nvidia,tegra194-dmic",
459 329 "nvidia,tegra210-dmic";
460 reg = !! 330 reg = <0x2904300 0x100>;
461 clocks 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock- 332 clock-names = "dmic";
463 assign 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assign 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assign 335 assigned-clock-rates = <3072000>;
466 sound- 336 sound-name-prefix = "DMIC4";
467 status 337 status = "disabled";
468 }; 338 };
469 339
470 tegra_dspk1: d 340 tegra_dspk1: dspk@2905000 {
471 compat 341 compatible = "nvidia,tegra194-dspk",
472 342 "nvidia,tegra186-dspk";
473 reg = !! 343 reg = <0x2905000 0x100>;
474 clocks 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock- 345 clock-names = "dspk";
476 assign 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assign 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assign 348 assigned-clock-rates = <12288000>;
479 sound- 349 sound-name-prefix = "DSPK1";
480 status 350 status = "disabled";
481 }; 351 };
482 352
483 tegra_dspk2: d 353 tegra_dspk2: dspk@2905100 {
484 compat 354 compatible = "nvidia,tegra194-dspk",
485 355 "nvidia,tegra186-dspk";
486 reg = !! 356 reg = <0x2905100 0x100>;
487 clocks 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock- 358 clock-names = "dspk";
489 assign 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assign 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assign 361 assigned-clock-rates = <12288000>;
492 sound- 362 sound-name-prefix = "DSPK2";
493 status 363 status = "disabled";
494 }; 364 };
>> 365 };
>> 366 };
495 367
496 tegra_ope1: pr !! 368 pinmux: pinmux@2430000 {
497 compat !! 369 compatible = "nvidia,tegra194-pinmux";
498 !! 370 reg = <0x2430000 0x17000>,
499 reg = !! 371 <0xc300000 0x4000>;
500 sound- <<
501 status <<
502 <<
503 #addre <<
504 #size- <<
505 ranges <<
506 <<
507 equali <<
508 <<
509 <<
510 <<
511 }; <<
512 <<
513 dynami <<
514 <<
515 <<
516 <<
517 }; <<
518 }; <<
519 <<
520 tegra_mvc1: mv <<
521 compat <<
522 <<
523 reg = <<
524 sound- <<
525 status <<
526 }; <<
527 <<
528 tegra_mvc2: mv <<
529 compat <<
530 <<
531 reg = <<
532 sound- <<
533 status <<
534 }; <<
535 <<
536 tegra_amixer: <<
537 compat <<
538 <<
539 reg = <<
540 sound- <<
541 status <<
542 }; <<
543 372
544 tegra_admaif: !! 373 status = "okay";
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 374
595 tegra_asrc: as !! 375 pex_rst_c5_out_state: pex_rst_c5_out {
596 compat !! 376 pex_rst {
597 !! 377 nvidia,pins = "pex_l5_rst_n_pgg1";
598 reg = !! 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
599 sound- !! 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
600 status !! 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
>> 381 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
>> 382 nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
601 }; 384 };
602 }; 385 };
603 386
604 adma: dma-controller@2 !! 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
605 compatible = " !! 388 clkreq {
606 " !! 389 nvidia,pins = "pex_l5_clkreq_n_pgg0";
607 reg = <0x0 0x0 !! 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
608 interrupt-pare !! 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
609 interrupts = !! 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
610 !! 393 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
611 !! 394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
612 !! 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 !! 396 };
614 <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; <<
646 <<
647 agic: interrupt-contro <<
648 compatible = " <<
649 " <<
650 #interrupt-cel <<
651 interrupt-cont <<
652 reg = <0x0 0x0 <<
653 <0x0 0x0 <<
654 interrupts = < <<
655 <<
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; 397 };
661 }; 398 };
662 399
663 mc: memory-controller@2c00000 400 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 401 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 402 reg = <0x02c00000 0x100000>,
666 <0x0 0x02c10000 !! 403 <0x02b80000 0x040000>,
667 <0x0 0x02c20000 !! 404 <0x01700000 0x100000>;
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
687 #interconnect-cells = 406 #interconnect-cells = <1>;
688 status = "disabled"; 407 status = "disabled";
689 408
690 #address-cells = <2>; 409 #address-cells = <2>;
691 #size-cells = <2>; 410 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 411
693 <0x0 0x02b800 !! 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 415
696 /* 416 /*
697 * Bit 39 of addresses 417 * Bit 39 of addresses passing through the memory
698 * controller selects 418 * controller selects the XBAR format used when memory
699 * is accessed. This i 419 * is accessed. This is used to transparently access
700 * memory in the XBAR 420 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 421 * (bit 39 set) or Tegra (bit 39 clear).
702 * 422 *
703 * As a consequence, t 423 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 424 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 425 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 426 * devices require access to the XBAR switch, their
707 * drivers must set th 427 * drivers must set this bit explicitly.
708 * 428 *
709 * Limit the DMA range 429 * Limit the DMA range for memory clients to [38:0].
710 */ 430 */
711 dma-ranges = <0x0 0x0 !! 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 432
713 emc: external-memory-c 433 emc: external-memory-controller@2c60000 {
714 compatible = " 434 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 435 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 436 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < <<
718 clocks = <&bpm 437 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 438 clock-names = "emc";
720 439
721 #interconnect- 440 #interconnect-cells = <0>;
722 441
723 nvidia,bpmp = 442 nvidia,bpmp = <&bpmp>;
724 }; 443 };
725 }; 444 };
726 445
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 446 uarta: serial@3100000 {
744 compatible = "nvidia,t 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 448 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 449 reg-shift = <2>;
747 interrupts = <GIC_SPI 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 451 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 452 clock-names = "serial";
749 resets = <&bpmp TEGRA1 453 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 454 reset-names = "serial";
750 status = "disabled"; 455 status = "disabled";
751 }; 456 };
752 457
753 uartb: serial@3110000 { 458 uartb: serial@3110000 {
754 compatible = "nvidia,t 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 460 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 461 reg-shift = <2>;
757 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 463 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 464 clock-names = "serial";
759 resets = <&bpmp TEGRA1 465 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 466 reset-names = "serial";
760 status = "disabled"; 467 status = "disabled";
761 }; 468 };
762 469
763 uartd: serial@3130000 { 470 uartd: serial@3130000 {
764 compatible = "nvidia,t 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 472 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 473 reg-shift = <2>;
767 interrupts = <GIC_SPI 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 475 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 476 clock-names = "serial";
770 resets = <&bpmp TEGRA1 477 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 478 reset-names = "serial";
772 status = "disabled"; 479 status = "disabled";
773 }; 480 };
774 481
775 uarte: serial@3140000 { 482 uarte: serial@3140000 {
776 compatible = "nvidia,t 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 484 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 485 reg-shift = <2>;
779 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 487 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 488 clock-names = "serial";
782 resets = <&bpmp TEGRA1 489 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 490 reset-names = "serial";
784 status = "disabled"; 491 status = "disabled";
785 }; 492 };
786 493
787 uartf: serial@3150000 { 494 uartf: serial@3150000 {
788 compatible = "nvidia,t 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 496 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 497 reg-shift = <2>;
791 interrupts = <GIC_SPI 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 499 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 500 clock-names = "serial";
794 resets = <&bpmp TEGRA1 501 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 502 reset-names = "serial";
796 status = "disabled"; 503 status = "disabled";
797 }; 504 };
798 505
799 gen1_i2c: i2c@3160000 { 506 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 507 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 508 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 510 #address-cells = <1>;
804 #size-cells = <0>; 511 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 512 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 513 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 514 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 515 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 516 status = "disabled";
812 }; 517 };
813 518
814 uarth: serial@3170000 { 519 uarth: serial@3170000 {
815 compatible = "nvidia,t 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 521 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 522 reg-shift = <2>;
818 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 524 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 525 clock-names = "serial";
821 resets = <&bpmp TEGRA1 526 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 527 reset-names = "serial";
823 status = "disabled"; 528 status = "disabled";
824 }; 529 };
825 530
826 cam_i2c: i2c@3180000 { 531 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 532 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 533 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 535 #address-cells = <1>;
831 #size-cells = <0>; 536 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 537 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 538 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 539 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 540 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 541 status = "disabled";
839 }; 542 };
840 543
841 /* shares pads with dpaux1 */ 544 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 545 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 546 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 547 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 549 #address-cells = <1>;
847 #size-cells = <0>; 550 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 551 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 552 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 553 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 554 reset-names = "i2c";
852 pinctrl-0 = <&state_dp 555 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dp 556 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "defau 557 pinctrl-names = "default", "idle";
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 558 status = "disabled";
858 }; 559 };
859 560
860 /* shares pads with dpaux0 */ 561 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 562 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 563 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 564 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 566 #address-cells = <1>;
866 #size-cells = <0>; 567 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 568 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 569 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 570 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 571 reset-names = "i2c";
871 pinctrl-0 = <&state_dp 572 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dp 573 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "defau 574 pinctrl-names = "default", "idle";
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 575 status = "disabled";
877 }; 576 };
878 577
879 /* shares pads with dpaux2 */ 578 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 { 579 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t 580 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 581 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 583 #address-cells = <1>;
885 #size-cells = <0>; 584 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 585 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 586 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 587 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 588 reset-names = "i2c";
890 pinctrl-0 = <&state_dp 589 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dp 590 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "defau 591 pinctrl-names = "default", "idle";
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 592 status = "disabled";
896 }; 593 };
897 594
898 /* shares pads with dpaux3 */ 595 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 { 596 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t 597 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 598 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 600 #address-cells = <1>;
904 #size-cells = <0>; 601 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 602 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 603 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 604 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 605 reset-names = "i2c";
909 pinctrl-0 = <&state_dp 606 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dp 607 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "defau 608 pinctrl-names = "default", "idle";
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; 609 status = "disabled";
915 }; 610 };
916 611
917 spi@3270000 { 612 spi@3270000 {
918 compatible = "nvidia,t 613 compatible = "nvidia,tegra194-qspi";
919 reg = <0x0 0x3270000 0 !! 614 reg = <0x3270000 0x1000>;
920 interrupts = <GIC_SPI 615 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
921 #address-cells = <1>; 616 #address-cells = <1>;
922 #size-cells = <0>; 617 #size-cells = <0>;
923 clocks = <&bpmp TEGRA1 618 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA1 619 <&bpmp TEGRA194_CLK_QSPI0_PM>;
925 clock-names = "qspi", 620 clock-names = "qspi", "qspi_out";
926 resets = <&bpmp TEGRA1 621 resets = <&bpmp TEGRA194_RESET_QSPI0>;
>> 622 reset-names = "qspi";
>> 623 status = "disabled";
>> 624 };
>> 625
>> 626 spi@3300000 {
>> 627 compatible = "nvidia,tegra194-qspi";
>> 628 reg = <0x3300000 0x1000>;
>> 629 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>> 630 #address-cells = <1>;
>> 631 #size-cells = <0>;
>> 632 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
>> 633 <&bpmp TEGRA194_CLK_QSPI1_PM>;
>> 634 clock-names = "qspi", "qspi_out";
>> 635 resets = <&bpmp TEGRA194_RESET_QSPI1>;
>> 636 reset-names = "qspi";
927 status = "disabled"; 637 status = "disabled";
928 }; 638 };
929 639
930 pwm1: pwm@3280000 { 640 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 641 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 642 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 643 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 644 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 645 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 646 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 647 reset-names = "pwm";
937 status = "disabled"; 648 status = "disabled";
938 #pwm-cells = <2>; 649 #pwm-cells = <2>;
939 }; 650 };
940 651
941 pwm2: pwm@3290000 { 652 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 653 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 654 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 655 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 656 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 657 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 658 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 659 reset-names = "pwm";
948 status = "disabled"; 660 status = "disabled";
949 #pwm-cells = <2>; 661 #pwm-cells = <2>;
950 }; 662 };
951 663
952 pwm3: pwm@32a0000 { 664 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 665 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 666 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 667 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 668 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 669 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 670 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 671 reset-names = "pwm";
959 status = "disabled"; 672 status = "disabled";
960 #pwm-cells = <2>; 673 #pwm-cells = <2>;
961 }; 674 };
962 675
963 pwm5: pwm@32c0000 { 676 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 677 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 678 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 679 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 680 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 681 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 682 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 683 reset-names = "pwm";
970 status = "disabled"; 684 status = "disabled";
971 #pwm-cells = <2>; 685 #pwm-cells = <2>;
972 }; 686 };
973 687
974 pwm6: pwm@32d0000 { 688 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 689 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 690 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 691 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 692 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 693 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 694 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 695 reset-names = "pwm";
981 status = "disabled"; 696 status = "disabled";
982 #pwm-cells = <2>; 697 #pwm-cells = <2>;
983 }; 698 };
984 699
985 pwm7: pwm@32e0000 { 700 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 701 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 702 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 703 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 704 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 705 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 706 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 707 reset-names = "pwm";
992 status = "disabled"; 708 status = "disabled";
993 #pwm-cells = <2>; 709 #pwm-cells = <2>;
994 }; 710 };
995 711
996 pwm8: pwm@32f0000 { 712 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 713 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 714 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 715 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 716 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 717 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 718 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 719 reset-names = "pwm";
1003 status = "disabled"; 720 status = "disabled";
1004 #pwm-cells = <2>; 721 #pwm-cells = <2>;
1005 }; 722 };
1006 723
1007 spi@3300000 { <<
1008 compatible = "nvidia, <<
1009 reg = <0x0 0x3300000 <<
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { 724 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia, 725 compatible = "nvidia,tegra194-sdhci";
1022 reg = <0x0 0x03400000 !! 726 reg = <0x03400000 0x10000>;
1023 interrupts = <GIC_SPI 727 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA 728 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA 729 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci" 730 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 731 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 732 reset-names = "sdhci";
1034 interconnects = <&mc 733 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035 <&mc 734 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036 interconnect-names = 735 interconnect-names = "dma-mem", "write";
1037 iommus = <&smmu TEGRA <<
1038 pinctrl-names = "sdmm <<
1039 pinctrl-0 = <&sdmmc1_ <<
1040 pinctrl-1 = <&sdmmc1_ <<
1041 nvidia,pad-autocal-pu 736 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 737 <0x07>;
1043 nvidia,pad-autocal-pu 738 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 739 <0x07>;
1045 nvidia,pad-autocal-pu 740 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 741 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 742 <0x07>;
1048 nvidia,pad-autocal-pu 743 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 744 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 745 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 746 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; <<
1053 sd-uhs-sdr50; <<
1054 sd-uhs-ddr50; <<
1055 sd-uhs-sdr104; <<
1056 status = "disabled"; 747 status = "disabled";
1057 }; 748 };
1058 749
1059 sdmmc3: mmc@3440000 { 750 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia, 751 compatible = "nvidia,tegra194-sdhci";
1061 reg = <0x0 0x03440000 !! 752 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 753 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA 754 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA 755 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci" 756 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 757 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 758 reset-names = "sdhci";
1073 interconnects = <&mc 759 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074 <&mc 760 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075 interconnect-names = 761 interconnect-names = "dma-mem", "write";
1076 iommus = <&smmu TEGRA <<
1077 pinctrl-names = "sdmm <<
1078 pinctrl-0 = <&sdmmc3_ <<
1079 pinctrl-1 = <&sdmmc3_ <<
1080 nvidia,pad-autocal-pu 762 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 763 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 764 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 765 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 766 <0x07>;
1085 nvidia,pad-autocal-pu 767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 768 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 769 <0x07>;
1088 nvidia,pad-autocal-pu 770 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 771 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 772 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 773 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; <<
1093 sd-uhs-sdr50; <<
1094 sd-uhs-ddr50; <<
1095 sd-uhs-sdr104; <<
1096 status = "disabled"; 774 status = "disabled";
1097 }; 775 };
1098 776
1099 sdmmc4: mmc@3460000 { 777 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia, 778 compatible = "nvidia,tegra194-sdhci";
1101 reg = <0x0 0x03460000 !! 779 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA 781 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA 782 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci" 783 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&b 784 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 785 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 786 assigned-clock-parents =
1109 <&b 787 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 788 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 789 reset-names = "sdhci";
1112 interconnects = <&mc 790 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113 <&mc 791 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114 interconnect-names = 792 interconnect-names = "dma-mem", "write";
1115 iommus = <&smmu TEGRA <<
1116 nvidia,pad-autocal-pu 793 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 794 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 795 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 796 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 797 <0x0a>;
1121 nvidia,pad-autocal-pu 798 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 799 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 800 <0x0a>;
1124 nvidia,default-tap = 801 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 802 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 803 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; <<
1128 mmc-ddr-1_8v; <<
1129 mmc-hs200-1_8v; <<
1130 mmc-hs400-1_8v; <<
1131 mmc-hs400-enhanced-st <<
1132 supports-cqe; 804 supports-cqe;
1133 status = "disabled"; 805 status = "disabled";
1134 }; 806 };
1135 807
1136 hda@3510000 { 808 hda@3510000 {
1137 compatible = "nvidia, !! 809 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 810 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 811 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 812 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA 813 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA 814 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", 815 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA 816 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA !! 817 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
1146 reset-names = "hda", !! 818 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
>> 819 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1147 power-domains = <&bpm 820 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc 821 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149 <&mc 822 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150 interconnect-names = 823 interconnect-names = "dma-mem", "write";
1151 iommus = <&smmu TEGRA <<
1152 status = "disabled"; 824 status = "disabled";
1153 }; 825 };
1154 826
1155 xusb_padctl: padctl@3520000 { 827 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia, 828 compatible = "nvidia,tegra194-xusb-padctl";
1157 reg = <0x0 0x03520000 !! 829 reg = <0x03520000 0x1000>,
1158 <0x0 0x03540000 !! 830 <0x03540000 0x1000>;
1159 reg-names = "padctl", 831 reg-names = "padctl", "ao";
1160 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161 833
1162 resets = <&bpmp TEGRA 834 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl 835 reset-names = "padctl";
1164 836
1165 status = "disabled"; 837 status = "disabled";
1166 838
1167 pads { 839 pads {
1168 usb2 { 840 usb2 {
1169 clock 841 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock 842 clock-names = "trk";
1171 843
1172 lanes 844 lanes {
1173 845 usb2-0 {
1174 846 nvidia,function = "xusb";
1175 847 status = "disabled";
1176 848 #phy-cells = <0>;
1177 849 };
1178 850
1179 851 usb2-1 {
1180 852 nvidia,function = "xusb";
1181 853 status = "disabled";
1182 854 #phy-cells = <0>;
1183 855 };
1184 856
1185 857 usb2-2 {
1186 858 nvidia,function = "xusb";
1187 859 status = "disabled";
1188 860 #phy-cells = <0>;
1189 861 };
1190 862
1191 863 usb2-3 {
1192 864 nvidia,function = "xusb";
1193 865 status = "disabled";
1194 866 #phy-cells = <0>;
1195 867 };
1196 }; 868 };
1197 }; 869 };
1198 870
1199 usb3 { 871 usb3 {
1200 lanes 872 lanes {
1201 873 usb3-0 {
1202 874 nvidia,function = "xusb";
1203 875 status = "disabled";
1204 876 #phy-cells = <0>;
1205 877 };
1206 878
1207 879 usb3-1 {
1208 880 nvidia,function = "xusb";
1209 881 status = "disabled";
1210 882 #phy-cells = <0>;
1211 883 };
1212 884
1213 885 usb3-2 {
1214 886 nvidia,function = "xusb";
1215 887 status = "disabled";
1216 888 #phy-cells = <0>;
1217 889 };
1218 890
1219 891 usb3-3 {
1220 892 nvidia,function = "xusb";
1221 893 status = "disabled";
1222 894 #phy-cells = <0>;
1223 895 };
1224 }; 896 };
1225 }; 897 };
1226 }; 898 };
1227 899
1228 ports { 900 ports {
1229 usb2-0 { 901 usb2-0 {
1230 statu 902 status = "disabled";
1231 }; 903 };
1232 904
1233 usb2-1 { 905 usb2-1 {
1234 statu 906 status = "disabled";
1235 }; 907 };
1236 908
1237 usb2-2 { 909 usb2-2 {
1238 statu 910 status = "disabled";
1239 }; 911 };
1240 912
1241 usb2-3 { 913 usb2-3 {
1242 statu 914 status = "disabled";
1243 }; 915 };
1244 916
1245 usb3-0 { 917 usb3-0 {
1246 statu 918 status = "disabled";
1247 }; 919 };
1248 920
1249 usb3-1 { 921 usb3-1 {
1250 statu 922 status = "disabled";
1251 }; 923 };
1252 924
1253 usb3-2 { 925 usb3-2 {
1254 statu 926 status = "disabled";
1255 }; 927 };
1256 928
1257 usb3-3 { 929 usb3-3 {
1258 statu 930 status = "disabled";
1259 }; 931 };
1260 }; 932 };
1261 }; 933 };
1262 934
1263 usb@3550000 { 935 usb@3550000 {
1264 compatible = "nvidia, 936 compatible = "nvidia,tegra194-xudc";
1265 reg = <0x0 0x03550000 !! 937 reg = <0x03550000 0x8000>,
1266 <0x0 0x03558000 !! 938 <0x03558000 0x1000>;
1267 reg-names = "base", " 939 reg-names = "base", "fpci";
1268 interrupts = <GIC_SPI 940 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&bpmp TEGRA 941 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA 942 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA 943 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA 944 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", 945 clock-names = "dev", "ss", "ss_src", "fs_src";
1274 interconnects = <&mc <<
1275 <&mc <<
1276 interconnect-names = <<
1277 iommus = <&smmu TEGRA <<
1278 power-domains = <&bpm 946 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpm 947 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = 948 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = 949 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent; <<
1283 status = "disabled"; 950 status = "disabled";
1284 }; 951 };
1285 952
1286 usb@3610000 { 953 usb@3610000 {
1287 compatible = "nvidia, 954 compatible = "nvidia,tegra194-xusb";
1288 reg = <0x0 0x03610000 !! 955 reg = <0x03610000 0x40000>,
1289 <0x0 0x03600000 !! 956 <0x03600000 0x10000>;
1290 reg-names = "hcd", "f 957 reg-names = "hcd", "fpci";
1291 958
1292 interrupts = <GIC_SPI 959 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 960 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294 961
1295 clocks = <&bpmp TEGRA 962 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA 963 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA 964 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA 965 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA 966 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA 967 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA 968 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA 969 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA 970 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_h 971 clock-names = "xusb_host", "xusb_falcon_src",
1305 "xusb_s 972 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306 "xusb_f 973 "xusb_fs_src", "pll_u_480m", "clk_m",
1307 "pll_e" 974 "pll_e";
1308 interconnects = <&mc <<
1309 <&mc <<
1310 interconnect-names = <<
1311 iommus = <&smmu TEGRA <<
1312 975
1313 power-domains = <&bpm 976 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpm 977 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = 978 power-domain-names = "xusb_host", "xusb_ss";
1316 979
1317 nvidia,xusb-padctl = 980 nvidia,xusb-padctl = <&xusb_padctl>;
1318 status = "disabled"; 981 status = "disabled";
1319 }; 982 };
1320 983
1321 fuse@3820000 { 984 fuse@3820000 {
1322 compatible = "nvidia, 985 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 986 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 987 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 988 clock-names = "fuse";
1326 }; 989 };
1327 990
1328 gic: interrupt-controller@388 991 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 992 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 993 #interrupt-cells = <3>;
1331 interrupt-controller; 994 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 995 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 996 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 997 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 998 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 999 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 1000 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 1001 interrupt-parent = <&gic>;
1339 }; 1002 };
1340 1003
1341 cec@3960000 { 1004 cec@3960000 {
1342 compatible = "nvidia, 1005 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 1006 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 1008 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 1009 clock-names = "cec";
1347 status = "disabled"; 1010 status = "disabled";
1348 }; 1011 };
1349 1012
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 1013 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, !! 1014 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1362 reg = <0x0 0x03c00000 !! 1015 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 1016 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1017 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1018 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1019 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1020 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1021 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1022 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1023 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1024 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 1025 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 1026 "shared3", "shared4", "shared5", "shared6",
1374 "sh 1027 "shared7";
1375 #mbox-cells = <2>; 1028 #mbox-cells = <2>;
1376 }; 1029 };
1377 1030
1378 p2u_hsio_0: phy@3e10000 { 1031 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 1032 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 1033 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 1034 reg-names = "ctl";
1382 1035
1383 #phy-cells = <0>; 1036 #phy-cells = <0>;
1384 }; 1037 };
1385 1038
1386 p2u_hsio_1: phy@3e20000 { 1039 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 1040 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 1041 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 1042 reg-names = "ctl";
1390 1043
1391 #phy-cells = <0>; 1044 #phy-cells = <0>;
1392 }; 1045 };
1393 1046
1394 p2u_hsio_2: phy@3e30000 { 1047 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 1048 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 1049 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 1050 reg-names = "ctl";
1398 1051
1399 #phy-cells = <0>; 1052 #phy-cells = <0>;
1400 }; 1053 };
1401 1054
1402 p2u_hsio_3: phy@3e40000 { 1055 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 1056 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 1057 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 1058 reg-names = "ctl";
1406 1059
1407 #phy-cells = <0>; 1060 #phy-cells = <0>;
1408 }; 1061 };
1409 1062
1410 p2u_hsio_4: phy@3e50000 { 1063 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 1064 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 1065 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 1066 reg-names = "ctl";
1414 1067
1415 #phy-cells = <0>; 1068 #phy-cells = <0>;
1416 }; 1069 };
1417 1070
1418 p2u_hsio_5: phy@3e60000 { 1071 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 1072 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 1073 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 1074 reg-names = "ctl";
1422 1075
1423 #phy-cells = <0>; 1076 #phy-cells = <0>;
1424 }; 1077 };
1425 1078
1426 p2u_hsio_6: phy@3e70000 { 1079 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 1080 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 1081 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 1082 reg-names = "ctl";
1430 1083
1431 #phy-cells = <0>; 1084 #phy-cells = <0>;
1432 }; 1085 };
1433 1086
1434 p2u_hsio_7: phy@3e80000 { 1087 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 1088 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 1089 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 1090 reg-names = "ctl";
1438 1091
1439 #phy-cells = <0>; 1092 #phy-cells = <0>;
1440 }; 1093 };
1441 1094
1442 p2u_hsio_8: phy@3e90000 { 1095 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 1096 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 1097 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 1098 reg-names = "ctl";
1446 1099
1447 #phy-cells = <0>; 1100 #phy-cells = <0>;
1448 }; 1101 };
1449 1102
1450 p2u_hsio_9: phy@3ea0000 { 1103 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 1104 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 1105 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 1106 reg-names = "ctl";
1454 1107
1455 #phy-cells = <0>; 1108 #phy-cells = <0>;
1456 }; 1109 };
1457 1110
1458 p2u_nvhs_0: phy@3eb0000 { 1111 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 1112 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 1113 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 1114 reg-names = "ctl";
1462 1115
1463 #phy-cells = <0>; 1116 #phy-cells = <0>;
1464 }; 1117 };
1465 1118
1466 p2u_nvhs_1: phy@3ec0000 { 1119 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 1120 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 1121 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 1122 reg-names = "ctl";
1470 1123
1471 #phy-cells = <0>; 1124 #phy-cells = <0>;
1472 }; 1125 };
1473 1126
1474 p2u_nvhs_2: phy@3ed0000 { 1127 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 1128 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 1129 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 1130 reg-names = "ctl";
1478 1131
1479 #phy-cells = <0>; 1132 #phy-cells = <0>;
1480 }; 1133 };
1481 1134
1482 p2u_nvhs_3: phy@3ee0000 { 1135 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 1136 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 1137 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 1138 reg-names = "ctl";
1486 1139
1487 #phy-cells = <0>; 1140 #phy-cells = <0>;
1488 }; 1141 };
1489 1142
1490 p2u_nvhs_4: phy@3ef0000 { 1143 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 1144 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 1145 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 1146 reg-names = "ctl";
1494 1147
1495 #phy-cells = <0>; 1148 #phy-cells = <0>;
1496 }; 1149 };
1497 1150
1498 p2u_nvhs_5: phy@3f00000 { 1151 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 1152 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 1153 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 1154 reg-names = "ctl";
1502 1155
1503 #phy-cells = <0>; 1156 #phy-cells = <0>;
1504 }; 1157 };
1505 1158
1506 p2u_nvhs_6: phy@3f10000 { 1159 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 1160 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 1161 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 1162 reg-names = "ctl";
1510 1163
1511 #phy-cells = <0>; 1164 #phy-cells = <0>;
1512 }; 1165 };
1513 1166
1514 p2u_nvhs_7: phy@3f20000 { 1167 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 1168 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 1169 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 1170 reg-names = "ctl";
1518 1171
1519 #phy-cells = <0>; 1172 #phy-cells = <0>;
1520 }; 1173 };
1521 1174
1522 p2u_hsio_10: phy@3f30000 { 1175 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 1176 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 1177 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 1178 reg-names = "ctl";
1526 1179
1527 #phy-cells = <0>; 1180 #phy-cells = <0>;
1528 }; 1181 };
1529 1182
1530 p2u_hsio_11: phy@3f40000 { 1183 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 1184 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 1185 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 1186 reg-names = "ctl";
1534 1187
1535 #phy-cells = <0>; 1188 #phy-cells = <0>;
1536 }; 1189 };
1537 1190
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 1191 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, !! 1192 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1560 reg = <0x0 0x0c150000 !! 1193 reg = <0x0c150000 0x90000>;
1561 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 1195 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 1196 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 1197 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1198 /*
1566 * Shared interrupt 0 1199 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 1200 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 1201 */
1569 interrupt-names = "sh 1202 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 1203 #mbox-cells = <2>;
1571 }; 1204 };
1572 1205
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 1206 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 1207 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 1208 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 1210 #address-cells = <1>;
1588 #size-cells = <0>; 1211 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 1212 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 1213 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 1214 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 1215 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 1216 status = "disabled";
1596 }; 1217 };
1597 1218
1598 gen8_i2c: i2c@c250000 { 1219 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 1220 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 1221 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 1222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 1223 #address-cells = <1>;
1603 #size-cells = <0>; 1224 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 1225 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 1226 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 1227 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 1228 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 1229 status = "disabled";
1611 }; 1230 };
1612 1231
1613 uartc: serial@c280000 { 1232 uartc: serial@c280000 {
1614 compatible = "nvidia, 1233 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 1234 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 1235 reg-shift = <2>;
1617 interrupts = <GIC_SPI 1236 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 1237 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 1238 clock-names = "serial";
1620 resets = <&bpmp TEGRA 1239 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 1240 reset-names = "serial";
1622 status = "disabled"; 1241 status = "disabled";
1623 }; 1242 };
1624 1243
1625 uartg: serial@c290000 { 1244 uartg: serial@c290000 {
1626 compatible = "nvidia, 1245 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 1246 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 1247 reg-shift = <2>;
1629 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 1249 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 1250 clock-names = "serial";
1632 resets = <&bpmp TEGRA 1251 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 1252 reset-names = "serial";
1634 status = "disabled"; 1253 status = "disabled";
1635 }; 1254 };
1636 1255
1637 rtc: rtc@c2a0000 { 1256 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 1257 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 1258 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 1259 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 1260 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 1261 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 1262 clock-names = "rtc";
1644 status = "disabled"; 1263 status = "disabled";
1645 }; 1264 };
1646 1265
1647 gpio_aon: gpio@c2f0000 { 1266 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 1267 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 1268 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 1269 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 1270 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI !! 1271 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1653 <GIC_SPI <<
1654 <GIC_SPI <<
1655 <GIC_SPI <<
1656 gpio-controller; 1272 gpio-controller;
1657 #gpio-cells = <2>; 1273 #gpio-cells = <2>;
1658 interrupt-controller; 1274 interrupt-controller;
1659 #interrupt-cells = <2 1275 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 1276 };
1669 1277
1670 pwm4: pwm@c340000 { 1278 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 1279 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 1280 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 1281 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 1282 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 1283 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 1284 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 1285 reset-names = "pwm";
1677 status = "disabled"; 1286 status = "disabled";
1678 #pwm-cells = <2>; 1287 #pwm-cells = <2>;
1679 }; 1288 };
1680 1289
1681 pmc: pmc@c360000 { 1290 pmc: pmc@c360000 {
1682 compatible = "nvidia, 1291 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 1292 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 1293 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 1294 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 1295 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 1296 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 1297 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 1298
1690 #interrupt-cells = <2 1299 #interrupt-cells = <2>;
1691 interrupt-controller; 1300 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v <<
1699 pins = "sdmmc <<
1700 power-source <<
1701 }; <<
1702 <<
1703 sdmmc3_1v8: sdmmc3-1v <<
1704 pins = "sdmmc <<
1705 power-source <<
1706 }; <<
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v <<
1709 pins = "sdmmc <<
1710 power-source <<
1711 }; <<
1712 }; <<
1713 <<
1714 aon-noc@c600000 { <<
1715 compatible = "nvidia, <<
1716 reg = <0x0 0xc600000 <<
1717 interrupts = <GIC_SPI <<
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 <<
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; <<
1732 <<
1733 iommu@10000000 { <<
1734 compatible = "nvidia, <<
1735 reg = <0x0 0x10000000 <<
1736 interrupts = <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 <GIC_SPI <<
1747 <GIC_SPI <<
1748 <GIC_SPI <<
1749 <GIC_SPI <<
1750 <GIC_SPI <<
1751 <GIC_SPI <<
1752 <GIC_SPI <<
1753 <GIC_SPI <<
1754 <GIC_SPI <<
1755 <GIC_SPI <<
1756 <GIC_SPI <<
1757 <GIC_SPI <<
1758 <GIC_SPI <<
1759 <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 <GIC_SPI <<
1770 <GIC_SPI <<
1771 <GIC_SPI <<
1772 <GIC_SPI <<
1773 <GIC_SPI <<
1774 <GIC_SPI <<
1775 <GIC_SPI <<
1776 <GIC_SPI <<
1777 <GIC_SPI <<
1778 <GIC_SPI <<
1779 <GIC_SPI <<
1780 <GIC_SPI <<
1781 <GIC_SPI <<
1782 <GIC_SPI <<
1783 <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 <GIC_SPI <<
1792 <GIC_SPI <<
1793 <GIC_SPI <<
1794 <GIC_SPI <<
1795 <GIC_SPI <<
1796 <GIC_SPI <<
1797 <GIC_SPI <<
1798 <GIC_SPI <<
1799 <GIC_SPI <<
1800 <GIC_SPI <<
1801 stream-match-mask = < <<
1802 #global-interrupts = <<
1803 #iommu-cells = <1>; <<
1804 <<
1805 nvidia,memory-control <<
1806 status = "disabled"; <<
1807 }; <<
1808 <<
1809 smmu: iommu@12000000 { <<
1810 compatible = "nvidia, <<
1811 reg = <0x0 0x12000000 <<
1812 <0x0 0x11000000 <<
1813 interrupts = <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 <GIC_SPI <<
1834 <GIC_SPI <<
1835 <GIC_SPI <<
1836 <GIC_SPI <<
1837 <GIC_SPI <<
1838 <GIC_SPI <<
1839 <GIC_SPI <<
1840 <GIC_SPI <<
1841 <GIC_SPI <<
1842 <GIC_SPI <<
1843 <GIC_SPI <<
1844 <GIC_SPI <<
1845 <GIC_SPI <<
1846 <GIC_SPI <<
1847 <GIC_SPI <<
1848 <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 <GIC_SPI <<
1857 <GIC_SPI <<
1858 <GIC_SPI <<
1859 <GIC_SPI <<
1860 <GIC_SPI <<
1861 <GIC_SPI <<
1862 <GIC_SPI <<
1863 <GIC_SPI <<
1864 <GIC_SPI <<
1865 <GIC_SPI <<
1866 <GIC_SPI <<
1867 <GIC_SPI <<
1868 <GIC_SPI <<
1869 <GIC_SPI <<
1870 <GIC_SPI <<
1871 <GIC_SPI <<
1872 <GIC_SPI <<
1873 <GIC_SPI <<
1874 <GIC_SPI <<
1875 <GIC_SPI <<
1876 <GIC_SPI <<
1877 <GIC_SPI <<
1878 <GIC_SPI <<
1879 stream-match-mask = < <<
1880 #global-interrupts = <<
1881 #iommu-cells = <1>; <<
1882 <<
1883 nvidia,memory-control <<
1884 status = "okay"; <<
1885 }; 1301 };
1886 1302
1887 host1x@13e00000 { 1303 host1x@13e00000 {
1888 compatible = "nvidia, 1304 compatible = "nvidia,tegra194-host1x";
1889 reg = <0x0 0x13e00000 !! 1305 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 1306 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 1307 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 1308 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1309 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy 1310 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA 1311 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 1312 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 1313 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 1314 reset-names = "host1x";
1899 1315
1900 #address-cells = <2>; !! 1316 #address-cells = <1>;
1901 #size-cells = <2>; !! 1317 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 1318
>> 1319 ranges = <0x15000000 0x15000000 0x01000000>;
1904 interconnects = <&mc 1320 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905 interconnect-names = 1321 interconnect-names = "dma-mem";
1906 iommus = <&smmu TEGRA <<
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 <<
1919 nvdec@15140000 { <<
1920 compatible = <<
1921 reg = <0x0 0x <<
1922 clocks = <&bp <<
1923 clock-names = <<
1924 resets = <&bp <<
1925 reset-names = <<
1926 <<
1927 power-domains <<
1928 interconnects <<
1929 <<
1930 <<
1931 interconnect- <<
1932 iommus = <&sm <<
1933 dma-coherent; <<
1934 <<
1935 nvidia,host1x <<
1936 }; <<
1937 1322
1938 display-hub@15200000 1323 display-hub@15200000 {
1939 compatible = 1324 compatible = "nvidia,tegra194-display";
1940 reg = <0x0 0x !! 1325 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 1326 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 1327 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 1328 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 1329 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 1330 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 1331 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 1332 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 1333 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 1334 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 1335 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 1336 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 1337 clock-names = "disp", "hub";
1953 status = "dis 1338 status = "disabled";
1954 1339
1955 power-domains 1340 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 1341
1957 #address-cell !! 1342 #address-cells = <1>;
1958 #size-cells = !! 1343 #size-cells = <1>;
1959 ranges = <0x0 !! 1344
>> 1345 ranges = <0x15200000 0x15200000 0x40000>;
1960 1346
1961 display@15200 1347 display@15200000 {
1962 compa 1348 compatible = "nvidia,tegra194-dc";
1963 reg = !! 1349 reg = <0x15200000 0x10000>;
1964 inter 1350 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 1351 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 1352 clock-names = "dc";
1967 reset 1353 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 1354 reset-names = "dc";
1969 1355
1970 power 1356 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter 1357 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 1358 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 inter 1359 interconnect-names = "dma-mem", "read-1";
1974 1360
1975 nvidi 1361 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 1362 nvidia,head = <0>;
1977 }; 1363 };
1978 1364
1979 display@15210 1365 display@15210000 {
1980 compa 1366 compatible = "nvidia,tegra194-dc";
1981 reg = !! 1367 reg = <0x15210000 0x10000>;
1982 inter 1368 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 1369 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 1370 clock-names = "dc";
1985 reset 1371 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 1372 reset-names = "dc";
1987 1373
1988 power 1374 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter 1375 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 1376 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 inter 1377 interconnect-names = "dma-mem", "read-1";
1992 1378
1993 nvidi 1379 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 1380 nvidia,head = <1>;
1995 }; 1381 };
1996 1382
1997 display@15220 1383 display@15220000 {
1998 compa 1384 compatible = "nvidia,tegra194-dc";
1999 reg = !! 1385 reg = <0x15220000 0x10000>;
2000 inter 1386 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 1387 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 1388 clock-names = "dc";
2003 reset 1389 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 1390 reset-names = "dc";
2005 1391
2006 power 1392 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter 1393 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008 1394 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009 inter 1395 interconnect-names = "dma-mem", "read-1";
2010 1396
2011 nvidi 1397 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 1398 nvidia,head = <2>;
2013 }; 1399 };
2014 1400
2015 display@15230 1401 display@15230000 {
2016 compa 1402 compatible = "nvidia,tegra194-dc";
2017 reg = !! 1403 reg = <0x15230000 0x10000>;
2018 inter 1404 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 1405 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 1406 clock-names = "dc";
2021 reset 1407 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 1408 reset-names = "dc";
2023 1409
2024 power 1410 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter 1411 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026 1412 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027 inter 1413 interconnect-names = "dma-mem", "read-1";
2028 1414
2029 nvidi 1415 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 1416 nvidia,head = <3>;
2031 }; 1417 };
2032 }; 1418 };
2033 1419
2034 vic@15340000 { 1420 vic@15340000 {
2035 compatible = 1421 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 1422 reg = <0x15340000 0x00040000>;
2037 interrupts = 1423 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 1424 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 1425 clock-names = "vic";
2040 resets = <&bp 1426 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 1427 reset-names = "vic";
2042 1428
2043 power-domains 1429 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects 1430 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045 1431 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046 interconnect- 1432 interconnect-names = "dma-mem", "write";
2047 iommus = <&sm <<
2048 dma-coherent; <<
2049 }; <<
2050 <<
2051 nvjpg@15380000 { <<
2052 compatible = <<
2053 reg = <0x0 0x <<
2054 clocks = <&bp <<
2055 clock-names = <<
2056 resets = <&bp <<
2057 reset-names = <<
2058 <<
2059 power-domains <<
2060 interconnects <<
2061 <<
2062 interconnect- <<
2063 iommus = <&sm <<
2064 dma-coherent; <<
2065 }; <<
2066 <<
2067 nvdec@15480000 { <<
2068 compatible = <<
2069 reg = <0x0 0x <<
2070 clocks = <&bp <<
2071 clock-names = <<
2072 resets = <&bp <<
2073 reset-names = <<
2074 <<
2075 power-domains <<
2076 interconnects <<
2077 <<
2078 <<
2079 interconnect- <<
2080 iommus = <&sm <<
2081 dma-coherent; <<
2082 <<
2083 nvidia,host1x <<
2084 }; <<
2085 <<
2086 nvenc@154c0000 { <<
2087 compatible = <<
2088 reg = <0x0 0x <<
2089 clocks = <&bp <<
2090 clock-names = <<
2091 resets = <&bp <<
2092 reset-names = <<
2093 <<
2094 power-domains <<
2095 interconnects <<
2096 <<
2097 <<
2098 interconnect- <<
2099 iommus = <&sm <<
2100 dma-coherent; <<
2101 <<
2102 nvidia,host1x <<
2103 }; 1433 };
2104 1434
2105 dpaux0: dpaux@155c000 1435 dpaux0: dpaux@155c0000 {
2106 compatible = 1436 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 1437 reg = <0x155c0000 0x10000>;
2108 interrupts = 1438 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 1439 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 1440 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 1441 clock-names = "dpaux", "parent";
2112 resets = <&bp 1442 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 1443 reset-names = "dpaux";
2114 status = "dis 1444 status = "disabled";
2115 1445
2116 power-domains 1446 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 1447
2118 state_dpaux0_ 1448 state_dpaux0_aux: pinmux-aux {
2119 group 1449 groups = "dpaux-io";
2120 funct 1450 function = "aux";
2121 }; 1451 };
2122 1452
2123 state_dpaux0_ 1453 state_dpaux0_i2c: pinmux-i2c {
2124 group 1454 groups = "dpaux-io";
2125 funct 1455 function = "i2c";
2126 }; 1456 };
2127 1457
2128 state_dpaux0_ 1458 state_dpaux0_off: pinmux-off {
2129 group 1459 groups = "dpaux-io";
2130 funct 1460 function = "off";
2131 }; 1461 };
2132 1462
2133 i2c-bus { 1463 i2c-bus {
2134 #addr 1464 #address-cells = <1>;
2135 #size 1465 #size-cells = <0>;
2136 }; 1466 };
2137 }; 1467 };
2138 1468
2139 dpaux1: dpaux@155d000 1469 dpaux1: dpaux@155d0000 {
2140 compatible = 1470 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1471 reg = <0x155d0000 0x10000>;
2142 interrupts = 1472 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1473 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1474 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1475 clock-names = "dpaux", "parent";
2146 resets = <&bp 1476 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 1477 reset-names = "dpaux";
2148 status = "dis 1478 status = "disabled";
2149 1479
2150 power-domains 1480 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 1481
2152 state_dpaux1_ 1482 state_dpaux1_aux: pinmux-aux {
2153 group 1483 groups = "dpaux-io";
2154 funct 1484 function = "aux";
2155 }; 1485 };
2156 1486
2157 state_dpaux1_ 1487 state_dpaux1_i2c: pinmux-i2c {
2158 group 1488 groups = "dpaux-io";
2159 funct 1489 function = "i2c";
2160 }; 1490 };
2161 1491
2162 state_dpaux1_ 1492 state_dpaux1_off: pinmux-off {
2163 group 1493 groups = "dpaux-io";
2164 funct 1494 function = "off";
2165 }; 1495 };
2166 1496
2167 i2c-bus { 1497 i2c-bus {
2168 #addr 1498 #address-cells = <1>;
2169 #size 1499 #size-cells = <0>;
2170 }; 1500 };
2171 }; 1501 };
2172 1502
2173 dpaux2: dpaux@155e000 1503 dpaux2: dpaux@155e0000 {
2174 compatible = 1504 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 1505 reg = <0x155e0000 0x10000>;
2176 interrupts = 1506 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 1507 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 1508 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 1509 clock-names = "dpaux", "parent";
2180 resets = <&bp 1510 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 1511 reset-names = "dpaux";
2182 status = "dis 1512 status = "disabled";
2183 1513
2184 power-domains 1514 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 1515
2186 state_dpaux2_ 1516 state_dpaux2_aux: pinmux-aux {
2187 group 1517 groups = "dpaux-io";
2188 funct 1518 function = "aux";
2189 }; 1519 };
2190 1520
2191 state_dpaux2_ 1521 state_dpaux2_i2c: pinmux-i2c {
2192 group 1522 groups = "dpaux-io";
2193 funct 1523 function = "i2c";
2194 }; 1524 };
2195 1525
2196 state_dpaux2_ 1526 state_dpaux2_off: pinmux-off {
2197 group 1527 groups = "dpaux-io";
2198 funct 1528 function = "off";
2199 }; 1529 };
2200 1530
2201 i2c-bus { 1531 i2c-bus {
2202 #addr 1532 #address-cells = <1>;
2203 #size 1533 #size-cells = <0>;
2204 }; 1534 };
2205 }; 1535 };
2206 1536
2207 dpaux3: dpaux@155f000 1537 dpaux3: dpaux@155f0000 {
2208 compatible = 1538 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 1539 reg = <0x155f0000 0x10000>;
2210 interrupts = 1540 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 1541 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 1542 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 1543 clock-names = "dpaux", "parent";
2214 resets = <&bp 1544 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 1545 reset-names = "dpaux";
2216 status = "dis 1546 status = "disabled";
2217 1547
2218 power-domains 1548 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 1549
2220 state_dpaux3_ 1550 state_dpaux3_aux: pinmux-aux {
2221 group 1551 groups = "dpaux-io";
2222 funct 1552 function = "aux";
2223 }; 1553 };
2224 1554
2225 state_dpaux3_ 1555 state_dpaux3_i2c: pinmux-i2c {
2226 group 1556 groups = "dpaux-io";
2227 funct 1557 function = "i2c";
2228 }; 1558 };
2229 1559
2230 state_dpaux3_ 1560 state_dpaux3_off: pinmux-off {
2231 group 1561 groups = "dpaux-io";
2232 funct 1562 function = "off";
2233 }; 1563 };
2234 1564
2235 i2c-bus { 1565 i2c-bus {
2236 #addr 1566 #address-cells = <1>;
2237 #size 1567 #size-cells = <0>;
2238 }; 1568 };
2239 }; 1569 };
2240 1570
2241 nvenc@15a80000 { <<
2242 compatible = <<
2243 reg = <0x0 0x <<
2244 clocks = <&bp <<
2245 clock-names = <<
2246 resets = <&bp <<
2247 reset-names = <<
2248 <<
2249 power-domains <<
2250 interconnects <<
2251 <<
2252 <<
2253 interconnect- <<
2254 iommus = <&sm <<
2255 dma-coherent; <<
2256 <<
2257 nvidia,host1x <<
2258 }; <<
2259 <<
2260 sor0: sor@15b00000 { 1571 sor0: sor@15b00000 {
2261 compatible = 1572 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 1573 reg = <0x15b00000 0x40000>;
2263 interrupts = 1574 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 1575 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 1576 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 1577 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 1578 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 1579 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 1580 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 1581 clock-names = "sor", "out", "parent", "dp", "safe",
2271 1582 "pad";
2272 resets = <&bp 1583 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 1584 reset-names = "sor";
2274 pinctrl-0 = < 1585 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 1586 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 1587 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 1588 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 1589 status = "disabled";
2279 1590
2280 power-domains 1591 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 1592 nvidia,interface = <0>;
2282 }; 1593 };
2283 1594
2284 sor1: sor@15b40000 { 1595 sor1: sor@15b40000 {
2285 compatible = 1596 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 1597 reg = <0x15b40000 0x40000>;
2287 interrupts = 1598 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 1599 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 1600 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 1601 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 1602 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 1603 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 1604 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 1605 clock-names = "sor", "out", "parent", "dp", "safe",
2295 1606 "pad";
2296 resets = <&bp 1607 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 1608 reset-names = "sor";
2298 pinctrl-0 = < 1609 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 1610 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 1611 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 1612 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 1613 status = "disabled";
2303 1614
2304 power-domains 1615 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 1616 nvidia,interface = <1>;
2306 }; 1617 };
2307 1618
2308 sor2: sor@15b80000 { 1619 sor2: sor@15b80000 {
2309 compatible = 1620 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 1621 reg = <0x15b80000 0x40000>;
2311 interrupts = 1622 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 1623 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 1624 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 1625 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 1626 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 1627 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 1628 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 1629 clock-names = "sor", "out", "parent", "dp", "safe",
2319 1630 "pad";
2320 resets = <&bp 1631 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 1632 reset-names = "sor";
2322 pinctrl-0 = < 1633 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 1634 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 1635 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 1636 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 1637 status = "disabled";
2327 1638
2328 power-domains 1639 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 1640 nvidia,interface = <2>;
2330 }; 1641 };
2331 1642
2332 sor3: sor@15bc0000 { 1643 sor3: sor@15bc0000 {
2333 compatible = 1644 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 1645 reg = <0x15bc0000 0x40000>;
2335 interrupts = 1646 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 1647 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 1648 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 1649 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 1650 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 1651 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 1652 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 1653 clock-names = "sor", "out", "parent", "dp", "safe",
2343 1654 "pad";
2344 resets = <&bp 1655 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 1656 reset-names = "sor";
2346 pinctrl-0 = < 1657 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 1658 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 1659 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 1660 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 1661 status = "disabled";
2351 1662
2352 power-domains 1663 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 1664 nvidia,interface = <3>;
2354 }; 1665 };
2355 }; 1666 };
2356 1667
2357 pcie@14100000 { !! 1668 gpu@17000000 {
2358 compatible = "nvidia, !! 1669 compatible = "nvidia,gv11b";
2359 power-domains = <&bpm !! 1670 reg = <0x17000000 0x1000000>,
2360 reg = <0x00 0x1410000 !! 1671 <0x18000000 0x1000000>;
2361 <0x00 0x3000000 !! 1672 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2362 <0x00 0x3004000 !! 1673 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2363 <0x00 0x3008000 !! 1674 interrupt-names = "stall", "nonstall";
2364 reg-names = "appl", " !! 1675 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2365 !! 1676 <&bpmp TEGRA194_CLK_GPU_PWR>,
2366 status = "disabled"; !! 1677 <&bpmp TEGRA194_CLK_FUSE>;
2367 !! 1678 clock-names = "gpu", "pwr", "fuse";
2368 #address-cells = <3>; !! 1679 resets = <&bpmp TEGRA194_RESET_GPU>;
2369 #size-cells = <2>; !! 1680 reset-names = "gpu";
2370 device_type = "pci"; !! 1681 dma-coherent;
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 1682
2377 resets = <&bpmp TEGRA !! 1683 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2378 <&bpmp TEGRA !! 1684 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2379 reset-names = "apb", !! 1685 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
>> 1686 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
>> 1687 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
>> 1688 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
>> 1689 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
>> 1690 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
>> 1691 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
>> 1692 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
>> 1693 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
>> 1694 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
>> 1695 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
>> 1696 interconnect-names = "dma-mem", "read-0-hp", "write-0",
>> 1697 "read-1", "read-1-hp", "write-1",
>> 1698 "read-2", "read-2-hp", "write-2",
>> 1699 "read-3", "read-3-hp", "write-3";
>> 1700 };
>> 1701 };
2380 1702
2381 interrupts = <GIC_SPI !! 1703 pcie@14100000 {
2382 <GIC_SPI !! 1704 compatible = "nvidia,tegra194-pcie";
2383 interrupt-names = "in !! 1705 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1706 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
>> 1707 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1708 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1709 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1710 reg-names = "appl", "config", "atu_dma", "dbi";
2384 1711
2385 #interrupt-cells = <1 !! 1712 status = "disabled";
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 1713
2389 nvidia,bpmp = <&bpmp !! 1714 #address-cells = <3>;
>> 1715 #size-cells = <2>;
>> 1716 device_type = "pci";
>> 1717 num-lanes = <1>;
>> 1718 num-viewport = <8>;
>> 1719 linux,pci-domain = <1>;
2390 1720
2391 nvidia,aspm-cmrt-us = !! 1721 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2392 nvidia,aspm-pwr-on-t- !! 1722 clock-names = "core";
2393 nvidia,aspm-l0s-entra <<
2394 1723
2395 bus-range = <0x0 0xff !! 1724 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 1725 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 1726 reset-names = "apb", "core";
2396 1727
2397 ranges = <0x43000000 !! 1728 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2398 <0x02000000 !! 1729 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2399 <0x01000000 !! 1730 interrupt-names = "intr", "msi";
2400 1731
2401 interconnects = <&mc !! 1732 #interrupt-cells = <1>;
2402 <&mc !! 1733 interrupt-map-mask = <0 0 0 0>;
2403 interconnect-names = !! 1734 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 1735
2409 pcie@14120000 { !! 1736 nvidia,bpmp = <&bpmp 1>;
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 1737
2418 status = "disabled"; !! 1738 nvidia,aspm-cmrt-us = <60>;
>> 1739 nvidia,aspm-pwr-on-t-us = <20>;
>> 1740 nvidia,aspm-l0s-entrance-latency-us = <3>;
2419 1741
2420 #address-cells = <3>; !! 1742 bus-range = <0x0 0xff>;
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 1743
2426 clocks = <&bpmp TEGRA !! 1744 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2427 clock-names = "core"; !! 1745 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1746 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2428 1747
2429 resets = <&bpmp TEGRA !! 1748 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2430 <&bpmp TEGRA !! 1749 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2431 reset-names = "apb", !! 1750 interconnect-names = "read", "write";
>> 1751 };
2432 1752
2433 interrupts = <GIC_SPI !! 1753 pcie@14120000 {
2434 <GIC_SPI !! 1754 compatible = "nvidia,tegra194-pcie";
2435 interrupt-names = "in !! 1755 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1756 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
>> 1757 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1758 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1759 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1760 reg-names = "appl", "config", "atu_dma", "dbi";
2436 1761
2437 #interrupt-cells = <1 !! 1762 status = "disabled";
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 1763
2441 nvidia,bpmp = <&bpmp !! 1764 #address-cells = <3>;
>> 1765 #size-cells = <2>;
>> 1766 device_type = "pci";
>> 1767 num-lanes = <1>;
>> 1768 num-viewport = <8>;
>> 1769 linux,pci-domain = <2>;
2442 1770
2443 nvidia,aspm-cmrt-us = !! 1771 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2444 nvidia,aspm-pwr-on-t- !! 1772 clock-names = "core";
2445 nvidia,aspm-l0s-entra <<
2446 1773
2447 bus-range = <0x0 0xff !! 1774 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 1775 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 1776 reset-names = "apb", "core";
2448 1777
2449 ranges = <0x43000000 !! 1778 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2450 <0x02000000 !! 1779 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2451 <0x01000000 !! 1780 interrupt-names = "intr", "msi";
2452 1781
2453 interconnects = <&mc !! 1782 #interrupt-cells = <1>;
2454 <&mc !! 1783 interrupt-map-mask = <0 0 0 0>;
2455 interconnect-names = !! 1784 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 1785
2461 pcie@14140000 { !! 1786 nvidia,bpmp = <&bpmp 2>;
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 1787
2470 status = "disabled"; !! 1788 nvidia,aspm-cmrt-us = <60>;
>> 1789 nvidia,aspm-pwr-on-t-us = <20>;
>> 1790 nvidia,aspm-l0s-entrance-latency-us = <3>;
2471 1791
2472 #address-cells = <3>; !! 1792 bus-range = <0x0 0xff>;
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 1793
2478 clocks = <&bpmp TEGRA !! 1794 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2479 clock-names = "core"; !! 1795 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1796 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2480 1797
2481 resets = <&bpmp TEGRA !! 1798 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2482 <&bpmp TEGRA !! 1799 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2483 reset-names = "apb", !! 1800 interconnect-names = "read", "write";
>> 1801 };
2484 1802
2485 interrupts = <GIC_SPI !! 1803 pcie@14140000 {
2486 <GIC_SPI !! 1804 compatible = "nvidia,tegra194-pcie";
2487 interrupt-names = "in !! 1805 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1806 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
>> 1807 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1808 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1809 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1810 reg-names = "appl", "config", "atu_dma", "dbi";
2488 1811
2489 #interrupt-cells = <1 !! 1812 status = "disabled";
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 1813
2493 nvidia,bpmp = <&bpmp !! 1814 #address-cells = <3>;
>> 1815 #size-cells = <2>;
>> 1816 device_type = "pci";
>> 1817 num-lanes = <1>;
>> 1818 num-viewport = <8>;
>> 1819 linux,pci-domain = <3>;
2494 1820
2495 nvidia,aspm-cmrt-us = !! 1821 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2496 nvidia,aspm-pwr-on-t- !! 1822 clock-names = "core";
2497 nvidia,aspm-l0s-entra <<
2498 1823
2499 bus-range = <0x0 0xff !! 1824 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 1825 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 1826 reset-names = "apb", "core";
2500 1827
2501 ranges = <0x43000000 !! 1828 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2502 <0x02000000 !! 1829 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2503 <0x01000000 !! 1830 interrupt-names = "intr", "msi";
2504 1831
2505 interconnects = <&mc !! 1832 #interrupt-cells = <1>;
2506 <&mc !! 1833 interrupt-map-mask = <0 0 0 0>;
2507 interconnect-names = !! 1834 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 1835
2513 pcie@14160000 { !! 1836 nvidia,bpmp = <&bpmp 3>;
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 1837
2522 status = "disabled"; !! 1838 nvidia,aspm-cmrt-us = <60>;
>> 1839 nvidia,aspm-pwr-on-t-us = <20>;
>> 1840 nvidia,aspm-l0s-entrance-latency-us = <3>;
2523 1841
2524 #address-cells = <3>; !! 1842 bus-range = <0x0 0xff>;
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 1843
2530 clocks = <&bpmp TEGRA !! 1844 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2531 clock-names = "core"; !! 1845 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
>> 1846 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2532 1847
2533 resets = <&bpmp TEGRA !! 1848 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2534 <&bpmp TEGRA !! 1849 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2535 reset-names = "apb", !! 1850 interconnect-names = "read", "write";
>> 1851 };
2536 1852
2537 interrupts = <GIC_SPI !! 1853 pcie@14160000 {
2538 <GIC_SPI !! 1854 compatible = "nvidia,tegra194-pcie";
2539 interrupt-names = "in !! 1855 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 1856 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 1857 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1858 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1859 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1860 reg-names = "appl", "config", "atu_dma", "dbi";
2540 1861
2541 #interrupt-cells = <1 !! 1862 status = "disabled";
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 1863
2545 nvidia,bpmp = <&bpmp !! 1864 #address-cells = <3>;
>> 1865 #size-cells = <2>;
>> 1866 device_type = "pci";
>> 1867 num-lanes = <4>;
>> 1868 num-viewport = <8>;
>> 1869 linux,pci-domain = <4>;
2546 1870
2547 nvidia,aspm-cmrt-us = !! 1871 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2548 nvidia,aspm-pwr-on-t- !! 1872 clock-names = "core";
2549 nvidia,aspm-l0s-entra <<
2550 1873
2551 bus-range = <0x0 0xff !! 1874 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 1875 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1876 reset-names = "apb", "core";
2552 1877
2553 ranges = <0x43000000 !! 1878 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2554 <0x02000000 !! 1879 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2555 <0x01000000 !! 1880 interrupt-names = "intr", "msi";
2556 1881
2557 interconnects = <&mc !! 1882 #interrupt-cells = <1>;
2558 <&mc !! 1883 interrupt-map-mask = <0 0 0 0>;
2559 interconnect-names = !! 1884 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 1885
2565 pcie-ep@14160000 { !! 1886 nvidia,bpmp = <&bpmp 4>;
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 1887
2574 status = "disabled"; !! 1888 nvidia,aspm-cmrt-us = <60>;
>> 1889 nvidia,aspm-pwr-on-t-us = <20>;
>> 1890 nvidia,aspm-l0s-entrance-latency-us = <3>;
2575 1891
2576 num-lanes = <4>; !! 1892 bus-range = <0x0 0xff>;
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 1893
2580 clocks = <&bpmp TEGRA !! 1894 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2581 clock-names = "core"; !! 1895 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 1896 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2582 1897
2583 resets = <&bpmp TEGRA !! 1898 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2584 <&bpmp TEGRA !! 1899 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2585 reset-names = "apb", !! 1900 interconnect-names = "read", "write";
>> 1901 };
2586 1902
2587 interrupts = <GIC_SPI !! 1903 pcie@14180000 {
2588 interrupt-names = "in !! 1904 compatible = "nvidia,tegra194-pcie";
>> 1905 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 1906 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 1907 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1908 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1909 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1910 reg-names = "appl", "config", "atu_dma", "dbi";
2589 1911
2590 nvidia,bpmp = <&bpmp !! 1912 status = "disabled";
2591 1913
2592 nvidia,aspm-cmrt-us = !! 1914 #address-cells = <3>;
2593 nvidia,aspm-pwr-on-t- !! 1915 #size-cells = <2>;
2594 nvidia,aspm-l0s-entra !! 1916 device_type = "pci";
>> 1917 num-lanes = <8>;
>> 1918 num-viewport = <8>;
>> 1919 linux,pci-domain = <0>;
2595 1920
2596 interconnects = <&mc !! 1921 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2597 <&mc !! 1922 clock-names = "core";
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 1923
2604 pcie@14180000 { !! 1924 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2605 compatible = "nvidia, !! 1925 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2606 power-domains = <&bpm !! 1926 reset-names = "apb", "core";
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 1927
2613 status = "disabled"; !! 1928 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1929 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1930 interrupt-names = "intr", "msi";
2614 1931
2615 #address-cells = <3>; !! 1932 #interrupt-cells = <1>;
2616 #size-cells = <2>; !! 1933 interrupt-map-mask = <0 0 0 0>;
2617 device_type = "pci"; !! 1934 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 1935
2621 clocks = <&bpmp TEGRA !! 1936 nvidia,bpmp = <&bpmp 0>;
2622 clock-names = "core"; <<
2623 1937
2624 resets = <&bpmp TEGRA !! 1938 nvidia,aspm-cmrt-us = <60>;
2625 <&bpmp TEGRA !! 1939 nvidia,aspm-pwr-on-t-us = <20>;
2626 reset-names = "apb", !! 1940 nvidia,aspm-l0s-entrance-latency-us = <3>;
2627 1941
2628 interrupts = <GIC_SPI !! 1942 bus-range = <0x0 0xff>;
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 1943
2632 #interrupt-cells = <1 !! 1944 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2633 interrupt-map-mask = !! 1945 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2634 interrupt-map = <0 0 !! 1946 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2635 1947
2636 nvidia,bpmp = <&bpmp !! 1948 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 1949 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 1950 interconnect-names = "read", "write";
>> 1951 };
2637 1952
2638 nvidia,aspm-cmrt-us = !! 1953 pcie@141a0000 {
2639 nvidia,aspm-pwr-on-t- !! 1954 compatible = "nvidia,tegra194-pcie";
2640 nvidia,aspm-l0s-entra !! 1955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 1956 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 1957 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1958 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1959 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1960 reg-names = "appl", "config", "atu_dma", "dbi";
2641 1961
2642 bus-range = <0x0 0xff !! 1962 status = "disabled";
2643 1963
2644 ranges = <0x43000000 !! 1964 #address-cells = <3>;
2645 <0x02000000 !! 1965 #size-cells = <2>;
2646 <0x01000000 !! 1966 device_type = "pci";
>> 1967 num-lanes = <8>;
>> 1968 num-viewport = <8>;
>> 1969 linux,pci-domain = <5>;
2647 1970
2648 interconnects = <&mc !! 1971 pinctrl-names = "default";
2649 <&mc !! 1972 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 1973
2656 pcie-ep@14180000 { !! 1974 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2657 compatible = "nvidia, !! 1975 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2658 power-domains = <&bpm !! 1976 clock-names = "core", "core_m";
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 1977
2665 status = "disabled"; !! 1978 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 1979 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 1980 reset-names = "apb", "core";
2666 1981
2667 num-lanes = <8>; !! 1982 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2668 num-ib-windows = <2>; !! 1983 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2669 num-ob-windows = <8>; !! 1984 interrupt-names = "intr", "msi";
2670 1985
2671 clocks = <&bpmp TEGRA !! 1986 nvidia,bpmp = <&bpmp 5>;
2672 clock-names = "core"; <<
2673 1987
2674 resets = <&bpmp TEGRA !! 1988 #interrupt-cells = <1>;
2675 <&bpmp TEGRA !! 1989 interrupt-map-mask = <0 0 0 0>;
2676 reset-names = "apb", !! 1990 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2677 1991
2678 interrupts = <GIC_SPI !! 1992 nvidia,aspm-cmrt-us = <60>;
2679 interrupt-names = "in !! 1993 nvidia,aspm-pwr-on-t-us = <20>;
>> 1994 nvidia,aspm-l0s-entrance-latency-us = <3>;
2680 1995
2681 nvidia,bpmp = <&bpmp !! 1996 bus-range = <0x0 0xff>;
2682 1997
2683 nvidia,aspm-cmrt-us = !! 1998 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2684 nvidia,aspm-pwr-on-t- !! 1999 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2685 nvidia,aspm-l0s-entra !! 2000 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2686 2001
2687 interconnects = <&mc !! 2002 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2688 <&mc !! 2003 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2689 interconnect-names = !! 2004 interconnect-names = "read", "write";
2690 iommu-map = <0x0 &smm !! 2005 };
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 2006
2695 pcie@141a0000 { !! 2007 pcie_ep@14160000 {
2696 compatible = "nvidia, !! 2008 compatible = "nvidia,tegra194-pcie-ep";
2697 power-domains = <&bpm !! 2009 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2698 reg = <0x00 0x141a000 !! 2010 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2699 <0x00 0x3a00000 !! 2011 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2700 <0x00 0x3a04000 !! 2012 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2701 <0x00 0x3a08000 !! 2013 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2702 reg-names = "appl", " !! 2014 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2703 2015
2704 status = "disabled"; !! 2016 status = "disabled";
2705 2017
2706 #address-cells = <3>; !! 2018 num-lanes = <4>;
2707 #size-cells = <2>; !! 2019 num-ib-windows = <2>;
2708 device_type = "pci"; !! 2020 num-ob-windows = <8>;
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 2021
2712 pinctrl-names = "defa !! 2022 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2713 pinctrl-0 = <&pex_rst !! 2023 clock-names = "core";
2714 2024
2715 clocks = <&bpmp TEGRA !! 2025 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2716 clock-names = "core"; !! 2026 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2027 reset-names = "apb", "core";
2717 2028
2718 resets = <&bpmp TEGRA !! 2029 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2719 <&bpmp TEGRA !! 2030 interrupt-names = "intr";
2720 reset-names = "apb", <<
2721 2031
2722 interrupts = <GIC_SPI !! 2032 nvidia,bpmp = <&bpmp 4>;
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 2033
2726 nvidia,bpmp = <&bpmp !! 2034 nvidia,aspm-cmrt-us = <60>;
>> 2035 nvidia,aspm-pwr-on-t-us = <20>;
>> 2036 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2037 };
2727 2038
2728 #interrupt-cells = <1 !! 2039 pcie_ep@14180000 {
2729 interrupt-map-mask = !! 2040 compatible = "nvidia,tegra194-pcie-ep";
2730 interrupt-map = <0 0 !! 2041 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2042 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2043 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2044 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2045 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2046 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2731 2047
2732 nvidia,aspm-cmrt-us = !! 2048 status = "disabled";
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 2049
2736 bus-range = <0x0 0xff !! 2050 num-lanes = <8>;
>> 2051 num-ib-windows = <2>;
>> 2052 num-ob-windows = <8>;
2737 2053
2738 ranges = <0x43000000 !! 2054 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2739 <0x02000000 !! 2055 clock-names = "core";
2740 <0x01000000 <<
2741 2056
2742 interconnects = <&mc !! 2057 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2743 <&mc !! 2058 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2744 interconnect-names = !! 2059 reset-names = "apb", "core";
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 2060
2750 pcie-ep@141a0000 { !! 2061 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2751 compatible = "nvidia, !! 2062 interrupt-names = "intr";
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 2063
2759 status = "disabled"; !! 2064 nvidia,bpmp = <&bpmp 0>;
2760 2065
2761 num-lanes = <8>; !! 2066 nvidia,aspm-cmrt-us = <60>;
2762 num-ib-windows = <2>; !! 2067 nvidia,aspm-pwr-on-t-us = <20>;
2763 num-ob-windows = <8>; !! 2068 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2069 };
2764 2070
2765 pinctrl-names = "defa !! 2071 pcie_ep@141a0000 {
2766 pinctrl-0 = <&pex_clk !! 2072 compatible = "nvidia,tegra194-pcie-ep";
>> 2073 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2074 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2075 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2076 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2077 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2078 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2767 2079
2768 clocks = <&bpmp TEGRA !! 2080 status = "disabled";
2769 clock-names = "core"; <<
2770 2081
2771 resets = <&bpmp TEGRA !! 2082 num-lanes = <8>;
2772 <&bpmp TEGRA !! 2083 num-ib-windows = <2>;
2773 reset-names = "apb", !! 2084 num-ob-windows = <8>;
2774 2085
2775 interrupts = <GIC_SPI !! 2086 pinctrl-names = "default";
2776 interrupt-names = "in !! 2087 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2777 2088
2778 nvidia,bpmp = <&bpmp !! 2089 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2090 clock-names = "core";
2779 2091
2780 nvidia,aspm-cmrt-us = !! 2092 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2781 nvidia,aspm-pwr-on-t- !! 2093 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2782 nvidia,aspm-l0s-entra !! 2094 reset-names = "apb", "core";
2783 2095
2784 interconnects = <&mc !! 2096 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2785 <&mc !! 2097 interrupt-names = "intr";
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 2098
2792 gpu@17000000 { !! 2099 nvidia,bpmp = <&bpmp 5>;
2793 compatible = "nvidia, <<
2794 reg = <0x0 0x17000000 <<
2795 <0x0 0x18000000 <<
2796 interrupts = <GIC_SPI <<
2797 <GIC_SPI <<
2798 interrupt-names = "st <<
2799 clocks = <&bpmp TEGRA <<
2800 <&bpmp TEGRA <<
2801 <&bpmp TEGRA <<
2802 clock-names = "gpu", <<
2803 resets = <&bpmp TEGRA <<
2804 reset-names = "gpu"; <<
2805 dma-coherent; <<
2806 2100
2807 power-domains = <&bpm !! 2101 nvidia,aspm-cmrt-us = <60>;
2808 interconnects = <&mc !! 2102 nvidia,aspm-pwr-on-t-us = <20>;
2809 <&mc !! 2103 nvidia,aspm-l0s-entrance-latency-us = <3>;
2810 <&mc <<
2811 <&mc <<
2812 <&mc <<
2813 <&mc <<
2814 <&mc <<
2815 <&mc <<
2816 <&mc <<
2817 <&mc <<
2818 <&mc <<
2819 <&mc <<
2820 interconnect-names = <<
2821 <<
2822 <<
2823 <<
2824 }; <<
2825 }; 2104 };
2826 2105
2827 sram@40000000 { 2106 sram@40000000 {
2828 compatible = "nvidia,tegra194 2107 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 2108 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 2109 #address-cells = <1>;
2832 #size-cells = <1>; 2110 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 2111 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 2112
2835 no-memory-wc; <<
2836 <<
2837 cpu_bpmp_tx: sram@4e000 { 2113 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000 2114 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 2115 label = "cpu-bpmp-tx";
2840 pool; 2116 pool;
2841 }; 2117 };
2842 2118
2843 cpu_bpmp_rx: sram@4f000 { 2119 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000 2120 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 2121 label = "cpu-bpmp-rx";
2846 pool; 2122 pool;
2847 }; 2123 };
2848 }; 2124 };
2849 2125
2850 bpmp: bpmp { 2126 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 2127 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 2128 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 2129 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu !! 2130 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2855 #clock-cells = <1>; 2131 #clock-cells = <1>;
2856 #reset-cells = <1>; 2132 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 2133 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 2134 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859 <&mc TEGRA194 2135 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860 <&mc TEGRA194 2136 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861 <&mc TEGRA194 2137 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862 interconnect-names = "read", 2138 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863 iommus = <&smmu TEGRA194_SID_ <<
2864 2139
2865 bpmp_i2c: i2c { 2140 bpmp_i2c: i2c {
2866 compatible = "nvidia, 2141 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 2142 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 2143 #address-cells = <1>;
2869 #size-cells = <0>; 2144 #size-cells = <0>;
2870 }; 2145 };
2871 2146
2872 bpmp_thermal: thermal { 2147 bpmp_thermal: thermal {
2873 compatible = "nvidia, 2148 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 2149 #thermal-sensor-cells = <1>;
2875 }; 2150 };
2876 }; 2151 };
2877 2152
2878 cpus { 2153 cpus {
2879 compatible = "nvidia,tegra194 2154 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>; 2155 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>; 2156 #address-cells = <1>;
2882 #size-cells = <0>; 2157 #size-cells = <0>;
2883 2158
2884 cpu0_0: cpu@0 { 2159 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 2160 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 2161 device_type = "cpu";
2887 reg = <0x000>; 2162 reg = <0x000>;
2888 enable-method = "psci 2163 enable-method = "psci";
2889 i-cache-size = <13107 2164 i-cache-size = <131072>;
2890 i-cache-line-size = < 2165 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 2166 i-cache-sets = <512>;
2892 d-cache-size = <65536 2167 d-cache-size = <65536>;
2893 d-cache-line-size = < 2168 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 2169 d-cache-sets = <256>;
2895 next-level-cache = <& 2170 next-level-cache = <&l2c_0>;
2896 }; 2171 };
2897 2172
2898 cpu0_1: cpu@1 { 2173 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 2174 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 2175 device_type = "cpu";
2901 reg = <0x001>; 2176 reg = <0x001>;
2902 enable-method = "psci 2177 enable-method = "psci";
2903 i-cache-size = <13107 2178 i-cache-size = <131072>;
2904 i-cache-line-size = < 2179 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 2180 i-cache-sets = <512>;
2906 d-cache-size = <65536 2181 d-cache-size = <65536>;
2907 d-cache-line-size = < 2182 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 2183 d-cache-sets = <256>;
2909 next-level-cache = <& 2184 next-level-cache = <&l2c_0>;
2910 }; 2185 };
2911 2186
2912 cpu1_0: cpu@100 { 2187 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 2188 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 2189 device_type = "cpu";
2915 reg = <0x100>; 2190 reg = <0x100>;
2916 enable-method = "psci 2191 enable-method = "psci";
2917 i-cache-size = <13107 2192 i-cache-size = <131072>;
2918 i-cache-line-size = < 2193 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 2194 i-cache-sets = <512>;
2920 d-cache-size = <65536 2195 d-cache-size = <65536>;
2921 d-cache-line-size = < 2196 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 2197 d-cache-sets = <256>;
2923 next-level-cache = <& 2198 next-level-cache = <&l2c_1>;
2924 }; 2199 };
2925 2200
2926 cpu1_1: cpu@101 { 2201 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 2202 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 2203 device_type = "cpu";
2929 reg = <0x101>; 2204 reg = <0x101>;
2930 enable-method = "psci 2205 enable-method = "psci";
2931 i-cache-size = <13107 2206 i-cache-size = <131072>;
2932 i-cache-line-size = < 2207 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 2208 i-cache-sets = <512>;
2934 d-cache-size = <65536 2209 d-cache-size = <65536>;
2935 d-cache-line-size = < 2210 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 2211 d-cache-sets = <256>;
2937 next-level-cache = <& 2212 next-level-cache = <&l2c_1>;
2938 }; 2213 };
2939 2214
2940 cpu2_0: cpu@200 { 2215 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 2216 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 2217 device_type = "cpu";
2943 reg = <0x200>; 2218 reg = <0x200>;
2944 enable-method = "psci 2219 enable-method = "psci";
2945 i-cache-size = <13107 2220 i-cache-size = <131072>;
2946 i-cache-line-size = < 2221 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 2222 i-cache-sets = <512>;
2948 d-cache-size = <65536 2223 d-cache-size = <65536>;
2949 d-cache-line-size = < 2224 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 2225 d-cache-sets = <256>;
2951 next-level-cache = <& 2226 next-level-cache = <&l2c_2>;
2952 }; 2227 };
2953 2228
2954 cpu2_1: cpu@201 { 2229 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 2230 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 2231 device_type = "cpu";
2957 reg = <0x201>; 2232 reg = <0x201>;
2958 enable-method = "psci 2233 enable-method = "psci";
2959 i-cache-size = <13107 2234 i-cache-size = <131072>;
2960 i-cache-line-size = < 2235 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 2236 i-cache-sets = <512>;
2962 d-cache-size = <65536 2237 d-cache-size = <65536>;
2963 d-cache-line-size = < 2238 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 2239 d-cache-sets = <256>;
2965 next-level-cache = <& 2240 next-level-cache = <&l2c_2>;
2966 }; 2241 };
2967 2242
2968 cpu3_0: cpu@300 { 2243 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 2244 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 2245 device_type = "cpu";
2971 reg = <0x300>; 2246 reg = <0x300>;
2972 enable-method = "psci 2247 enable-method = "psci";
2973 i-cache-size = <13107 2248 i-cache-size = <131072>;
2974 i-cache-line-size = < 2249 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 2250 i-cache-sets = <512>;
2976 d-cache-size = <65536 2251 d-cache-size = <65536>;
2977 d-cache-line-size = < 2252 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 2253 d-cache-sets = <256>;
2979 next-level-cache = <& 2254 next-level-cache = <&l2c_3>;
2980 }; 2255 };
2981 2256
2982 cpu3_1: cpu@301 { 2257 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 2258 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 2259 device_type = "cpu";
2985 reg = <0x301>; 2260 reg = <0x301>;
2986 enable-method = "psci 2261 enable-method = "psci";
2987 i-cache-size = <13107 2262 i-cache-size = <131072>;
2988 i-cache-line-size = < 2263 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 2264 i-cache-sets = <512>;
2990 d-cache-size = <65536 2265 d-cache-size = <65536>;
2991 d-cache-line-size = < 2266 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 2267 d-cache-sets = <256>;
2993 next-level-cache = <& 2268 next-level-cache = <&l2c_3>;
2994 }; 2269 };
2995 2270
2996 cpu-map { 2271 cpu-map {
2997 cluster0 { 2272 cluster0 {
2998 core0 { 2273 core0 {
2999 cpu = 2274 cpu = <&cpu0_0>;
3000 }; 2275 };
3001 2276
3002 core1 { 2277 core1 {
3003 cpu = 2278 cpu = <&cpu0_1>;
3004 }; 2279 };
3005 }; 2280 };
3006 2281
3007 cluster1 { 2282 cluster1 {
3008 core0 { 2283 core0 {
3009 cpu = 2284 cpu = <&cpu1_0>;
3010 }; 2285 };
3011 2286
3012 core1 { 2287 core1 {
3013 cpu = 2288 cpu = <&cpu1_1>;
3014 }; 2289 };
3015 }; 2290 };
3016 2291
3017 cluster2 { 2292 cluster2 {
3018 core0 { 2293 core0 {
3019 cpu = 2294 cpu = <&cpu2_0>;
3020 }; 2295 };
3021 2296
3022 core1 { 2297 core1 {
3023 cpu = 2298 cpu = <&cpu2_1>;
3024 }; 2299 };
3025 }; 2300 };
3026 2301
3027 cluster3 { 2302 cluster3 {
3028 core0 { 2303 core0 {
3029 cpu = 2304 cpu = <&cpu3_0>;
3030 }; 2305 };
3031 2306
3032 core1 { 2307 core1 {
3033 cpu = 2308 cpu = <&cpu3_1>;
3034 }; 2309 };
3035 }; 2310 };
3036 }; 2311 };
3037 2312
3038 l2c_0: l2-cache0 { 2313 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 2314 cache-size = <2097152>;
3042 cache-line-size = <64 2315 cache-line-size = <64>;
3043 cache-sets = <2048>; 2316 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 2317 next-level-cache = <&l3c>;
3046 }; 2318 };
3047 2319
3048 l2c_1: l2-cache1 { 2320 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 2321 cache-size = <2097152>;
3052 cache-line-size = <64 2322 cache-line-size = <64>;
3053 cache-sets = <2048>; 2323 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 2324 next-level-cache = <&l3c>;
3056 }; 2325 };
3057 2326
3058 l2c_2: l2-cache2 { 2327 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 2328 cache-size = <2097152>;
3062 cache-line-size = <64 2329 cache-line-size = <64>;
3063 cache-sets = <2048>; 2330 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 2331 next-level-cache = <&l3c>;
3066 }; 2332 };
3067 2333
3068 l2c_3: l2-cache3 { 2334 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 2335 cache-size = <2097152>;
3072 cache-line-size = <64 2336 cache-line-size = <64>;
3073 cache-sets = <2048>; 2337 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 2338 next-level-cache = <&l3c>;
3076 }; 2339 };
3077 2340
3078 l3c: l3-cache { 2341 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 2342 cache-size = <4194304>;
3082 cache-line-size = <64 2343 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 2344 cache-sets = <4096>;
3085 }; 2345 };
3086 }; 2346 };
3087 2347
3088 pmu { 2348 pmu {
3089 compatible = "nvidia,carmel-p !! 2349 compatible = "arm,armv8-pmuv3";
3090 interrupts = <GIC_SPI 384 IRQ 2350 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 385 IRQ 2351 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 386 IRQ 2352 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 387 IRQ 2353 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 388 IRQ 2354 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 389 IRQ 2355 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 390 IRQ 2356 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 391 IRQ 2357 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3098 interrupt-affinity = <&cpu0_0 2358 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3099 &cpu2_0 2359 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3100 }; 2360 };
3101 2361
3102 psci { 2362 psci {
3103 compatible = "arm,psci-1.0"; 2363 compatible = "arm,psci-1.0";
3104 status = "okay"; 2364 status = "okay";
3105 method = "smc"; 2365 method = "smc";
3106 }; 2366 };
3107 2367
3108 tcu: serial { <<
3109 compatible = "nvidia,tegra194 <<
3110 mboxes = <&hsp_top0 TEGRA_HSP <<
3111 <&hsp_aon TEGRA_HSP_ <<
3112 mbox-names = "rx", "tx"; <<
3113 }; <<
3114 <<
3115 sound { 2368 sound {
3116 status = "disabled"; 2369 status = "disabled";
3117 2370
3118 clocks = <&bpmp TEGRA194_CLK_ 2371 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_ 2372 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120 clock-names = "pll_a", "plla_ 2373 clock-names = "pll_a", "plla_out0";
3121 assigned-clocks = <&bpmp TEGR 2374 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGR 2375 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGR 2376 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124 assigned-clock-parents = <0>, 2377 assigned-clock-parents = <0>,
3125 <&bp 2378 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bp 2379 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3127 /* 2380 /*
3128 * PLLA supports dynamic ramp 2381 * PLLA supports dynamic ramp. Below initial rate is chosen
3129 * for this to work and oscil 2382 * for this to work and oscillate between base rates required
3130 * for 8x and 11.025x sample 2383 * for 8x and 11.025x sample rate streams.
3131 */ 2384 */
3132 assigned-clock-rates = <25800 2385 assigned-clock-rates = <258000000>;
3133 }; 2386 };
3134 2387
>> 2388 tcu: tcu {
>> 2389 compatible = "nvidia,tegra194-tcu";
>> 2390 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
>> 2391 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
>> 2392 mbox-names = "rx", "tx";
>> 2393 };
>> 2394
3135 thermal-zones { 2395 thermal-zones {
3136 cpu-thermal { !! 2396 cpu {
3137 thermal-sensors = <&{ !! 2397 thermal-sensors = <&{/bpmp/thermal}
>> 2398 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 2399 status = "disabled";
3139 }; 2400 };
3140 2401
3141 gpu-thermal { !! 2402 gpu {
3142 thermal-sensors = <&{ !! 2403 thermal-sensors = <&{/bpmp/thermal}
>> 2404 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 2405 status = "disabled";
3144 }; 2406 };
3145 2407
3146 aux-thermal { !! 2408 aux {
3147 thermal-sensors = <&{ !! 2409 thermal-sensors = <&{/bpmp/thermal}
>> 2410 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 2411 status = "disabled";
3149 }; 2412 };
3150 2413
3151 pllx-thermal { !! 2414 pllx {
3152 thermal-sensors = <&{ !! 2415 thermal-sensors = <&{/bpmp/thermal}
>> 2416 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 2417 status = "disabled";
3154 }; 2418 };
3155 2419
3156 ao-thermal { !! 2420 ao {
3157 thermal-sensors = <&{ !! 2421 thermal-sensors = <&{/bpmp/thermal}
>> 2422 TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 2423 status = "disabled";
3159 }; 2424 };
3160 2425
3161 tj-thermal { !! 2426 tj {
3162 thermal-sensors = <&{ !! 2427 thermal-sensors = <&{/bpmp/thermal}
>> 2428 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 2429 status = "disabled";
3164 }; 2430 };
3165 }; 2431 };
3166 2432
3167 timer { 2433 timer {
3168 compatible = "arm,armv8-timer 2434 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 2435 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 2436 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 2437 <GIC_PPI 14
3172 (GIC_CPU_MASK 2438 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 2439 <GIC_PPI 11
3174 (GIC_CPU_MASK 2440 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 2441 <GIC_PPI 10
3176 (GIC_CPU_MASK 2442 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 2443 interrupt-parent = <&gic>;
3178 always-on; 2444 always-on;
3179 }; 2445 };
3180 }; 2446 };
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