1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 7 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 8 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 10 #include <dt-bindings/memory/tegra194-mc.h>
12 11
13 / { 12 / {
14 compatible = "nvidia,tegra194"; 13 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
16 #address-cells = <2>; 15 #address-cells = <2>;
17 #size-cells = <2>; 16 #size-cells = <2>;
18 17
19 /* control backbone */ 18 /* control backbone */
20 bus@0 { 19 bus@0 {
21 compatible = "simple-bus"; 20 compatible = "simple-bus";
>> 21 #address-cells = <1>;
>> 22 #size-cells = <1>;
>> 23 ranges = <0x0 0x0 0x0 0x40000000>;
22 24
23 #address-cells = <2>; !! 25 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 26 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 27 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 28 <0x0010f000 0x1000>;
31 }; 29 };
32 30
33 gpio: gpio@2200000 { 31 gpio: gpio@2200000 {
34 compatible = "nvidia,t 32 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 33 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 34 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 35 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI <<
40 <GIC_SPI <<
41 <GIC_SPI <<
42 <GIC_SPI <<
43 <GIC_SPI <<
44 <GIC_SPI <<
45 <GIC_SPI <<
46 <GIC_SPI 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI <<
48 <GIC_SPI <<
49 <GIC_SPI <<
50 <GIC_SPI <<
51 <GIC_SPI <<
52 <GIC_SPI <<
53 <GIC_SPI <<
54 <GIC_SPI 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI <<
56 <GIC_SPI <<
57 <GIC_SPI <<
58 <GIC_SPI <<
59 <GIC_SPI <<
60 <GIC_SPI <<
61 <GIC_SPI <<
62 <GIC_SPI 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI <<
64 <GIC_SPI <<
65 <GIC_SPI <<
66 <GIC_SPI <<
67 <GIC_SPI <<
68 <GIC_SPI <<
69 <GIC_SPI <<
70 <GIC_SPI 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI !! 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
72 <GIC_SPI <<
73 <GIC_SPI <<
74 <GIC_SPI <<
75 <GIC_SPI <<
76 <GIC_SPI <<
77 <GIC_SPI <<
78 <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 #interrupt-cells = <2> 42 #interrupt-cells = <2>;
87 interrupt-controller; 43 interrupt-controller;
88 #gpio-cells = <2>; 44 #gpio-cells = <2>;
89 gpio-controller; 45 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 46 };
141 47
142 ethernet@2490000 { 48 ethernet@2490000 {
143 compatible = "nvidia,t 49 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 50 "nvidia,tegra186-eqos",
145 "snps,dwc 51 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 52 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 56 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 57 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 60 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 61 reset-names = "eqos";
156 interconnects = <&mc T 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
157 <&mc T 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
158 interconnect-names = " 64 interconnect-names = "dma-mem", "write";
159 iommus = <&smmu TEGRA1 65 iommus = <&smmu TEGRA194_SID_EQOS>;
160 status = "disabled"; 66 status = "disabled";
161 67
162 snps,write-requests = 68 snps,write-requests = <1>;
163 snps,read-requests = < 69 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 70 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 71 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 72 snps,rxpbl = <8>;
167 }; 73 };
168 74
169 gpcdma: dma-controller@2600000 <<
170 compatible = "nvidia,t <<
171 "nvidia,t <<
172 reg = <0x0 0x2600000 0 <<
173 resets = <&bpmp TEGRA1 <<
174 reset-names = "gpcdma" <<
175 interrupts = <GIC_SPI <<
176 <GIC_SPI <<
177 <GIC_SPI <<
178 <GIC_SPI <<
179 <GIC_SPI <<
180 <GIC_SPI <<
181 <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 #dma-cells = <1>; <<
208 iommus = <&smmu TEGRA1 <<
209 dma-coherent; <<
210 dma-channel-mask = <0x <<
211 status = "okay"; <<
212 }; <<
213 <<
214 aconnect@2900000 { 75 aconnect@2900000 {
215 compatible = "nvidia,t 76 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 77 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 78 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 79 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 80 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 81 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 82 #address-cells = <1>;
>> 83 #size-cells = <1>;
>> 84 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 85 status = "disabled";
222 86
223 #address-cells = <2>; !! 87 adma: dma-controller@2930000 {
224 #size-cells = <2>; !! 88 compatible = "nvidia,tegra194-adma",
225 ranges = <0x0 0x029000 !! 89 "nvidia,tegra186-adma";
>> 90 reg = <0x02930000 0x20000>;
>> 91 interrupt-parent = <&agic>;
>> 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 124 #dma-cells = <1>;
>> 125 clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> 126 clock-names = "d_audio";
>> 127 status = "disabled";
>> 128 };
>> 129
>> 130 agic: interrupt-controller@2a40000 {
>> 131 compatible = "nvidia,tegra194-agic",
>> 132 "nvidia,tegra210-agic";
>> 133 #interrupt-cells = <3>;
>> 134 interrupt-controller;
>> 135 reg = <0x02a41000 0x1000>,
>> 136 <0x02a42000 0x2000>;
>> 137 interrupts = <GIC_SPI 145
>> 138 (GIC_CPU_MASK_SIMPLE(4) |
>> 139 IRQ_TYPE_LEVEL_HIGH)>;
>> 140 clocks = <&bpmp TEGRA194_CLK_APE>;
>> 141 clock-names = "clk";
>> 142 status = "disabled";
>> 143 };
226 144
227 tegra_ahub: ahub@29008 145 tegra_ahub: ahub@2900800 {
228 compatible = " 146 compatible = "nvidia,tegra194-ahub",
229 " 147 "nvidia,tegra186-ahub";
230 reg = <0x0 0x0 !! 148 reg = <0x02900800 0x800>;
231 clocks = <&bpm 149 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = 150 clock-names = "ahub";
233 assigned-clock 151 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock !! 152 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
235 assigned-clock !! 153 #address-cells = <1>;
>> 154 #size-cells = <1>;
>> 155 ranges = <0x02900800 0x02900800 0x11800>;
236 status = "disa 156 status = "disabled";
237 157
238 #address-cells !! 158 tegra_admaif: admaif@290f000 {
239 #size-cells = !! 159 compatible = "nvidia,tegra194-admaif",
240 ranges = <0x0 !! 160 "nvidia,tegra186-admaif";
>> 161 reg = <0x0290f000 0x1000>;
>> 162 dmas = <&adma 1>, <&adma 1>,
>> 163 <&adma 2>, <&adma 2>,
>> 164 <&adma 3>, <&adma 3>,
>> 165 <&adma 4>, <&adma 4>,
>> 166 <&adma 5>, <&adma 5>,
>> 167 <&adma 6>, <&adma 6>,
>> 168 <&adma 7>, <&adma 7>,
>> 169 <&adma 8>, <&adma 8>,
>> 170 <&adma 9>, <&adma 9>,
>> 171 <&adma 10>, <&adma 10>,
>> 172 <&adma 11>, <&adma 11>,
>> 173 <&adma 12>, <&adma 12>,
>> 174 <&adma 13>, <&adma 13>,
>> 175 <&adma 14>, <&adma 14>,
>> 176 <&adma 15>, <&adma 15>,
>> 177 <&adma 16>, <&adma 16>,
>> 178 <&adma 17>, <&adma 17>,
>> 179 <&adma 18>, <&adma 18>,
>> 180 <&adma 19>, <&adma 19>,
>> 181 <&adma 20>, <&adma 20>;
>> 182 dma-names = "rx1", "tx1",
>> 183 "rx2", "tx2",
>> 184 "rx3", "tx3",
>> 185 "rx4", "tx4",
>> 186 "rx5", "tx5",
>> 187 "rx6", "tx6",
>> 188 "rx7", "tx7",
>> 189 "rx8", "tx8",
>> 190 "rx9", "tx9",
>> 191 "rx10", "tx10",
>> 192 "rx11", "tx11",
>> 193 "rx12", "tx12",
>> 194 "rx13", "tx13",
>> 195 "rx14", "tx14",
>> 196 "rx15", "tx15",
>> 197 "rx16", "tx16",
>> 198 "rx17", "tx17",
>> 199 "rx18", "tx18",
>> 200 "rx19", "tx19",
>> 201 "rx20", "tx20";
>> 202 status = "disabled";
>> 203 };
241 204
242 tegra_i2s1: i2 205 tegra_i2s1: i2s@2901000 {
243 compat 206 compatible = "nvidia,tegra194-i2s",
244 207 "nvidia,tegra210-i2s";
245 reg = !! 208 reg = <0x2901000 0x100>;
246 clocks 209 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 210 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock- 211 clock-names = "i2s", "sync_input";
249 assign 212 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assign 213 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assign 214 assigned-clock-rates = <1536000>;
252 sound- 215 sound-name-prefix = "I2S1";
253 status 216 status = "disabled";
254 }; 217 };
255 218
256 tegra_i2s2: i2 219 tegra_i2s2: i2s@2901100 {
257 compat 220 compatible = "nvidia,tegra194-i2s",
258 221 "nvidia,tegra210-i2s";
259 reg = !! 222 reg = <0x2901100 0x100>;
260 clocks 223 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 224 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock- 225 clock-names = "i2s", "sync_input";
263 assign 226 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assign 227 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assign 228 assigned-clock-rates = <1536000>;
266 sound- 229 sound-name-prefix = "I2S2";
267 status 230 status = "disabled";
268 }; 231 };
269 232
270 tegra_i2s3: i2 233 tegra_i2s3: i2s@2901200 {
271 compat 234 compatible = "nvidia,tegra194-i2s",
272 235 "nvidia,tegra210-i2s";
273 reg = !! 236 reg = <0x2901200 0x100>;
274 clocks 237 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 238 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock- 239 clock-names = "i2s", "sync_input";
277 assign 240 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assign 241 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assign 242 assigned-clock-rates = <1536000>;
280 sound- 243 sound-name-prefix = "I2S3";
281 status 244 status = "disabled";
282 }; 245 };
283 246
284 tegra_i2s4: i2 247 tegra_i2s4: i2s@2901300 {
285 compat 248 compatible = "nvidia,tegra194-i2s",
286 249 "nvidia,tegra210-i2s";
287 reg = !! 250 reg = <0x2901300 0x100>;
288 clocks 251 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 252 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock- 253 clock-names = "i2s", "sync_input";
291 assign 254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assign 255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assign 256 assigned-clock-rates = <1536000>;
294 sound- 257 sound-name-prefix = "I2S4";
295 status 258 status = "disabled";
296 }; 259 };
297 260
298 tegra_i2s5: i2 261 tegra_i2s5: i2s@2901400 {
299 compat 262 compatible = "nvidia,tegra194-i2s",
300 263 "nvidia,tegra210-i2s";
301 reg = !! 264 reg = <0x2901400 0x100>;
302 clocks 265 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 266 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock- 267 clock-names = "i2s", "sync_input";
305 assign 268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assign 269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assign 270 assigned-clock-rates = <1536000>;
308 sound- 271 sound-name-prefix = "I2S5";
309 status 272 status = "disabled";
310 }; 273 };
311 274
312 tegra_i2s6: i2 275 tegra_i2s6: i2s@2901500 {
313 compat 276 compatible = "nvidia,tegra194-i2s",
314 277 "nvidia,tegra210-i2s";
315 reg = !! 278 reg = <0x2901500 0x100>;
316 clocks 279 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 280 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock- 281 clock-names = "i2s", "sync_input";
319 assign 282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assign 283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assign 284 assigned-clock-rates = <1536000>;
322 sound- 285 sound-name-prefix = "I2S6";
323 status 286 status = "disabled";
324 }; 287 };
325 288
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d 289 tegra_dmic1: dmic@2904000 {
419 compat 290 compatible = "nvidia,tegra194-dmic",
420 291 "nvidia,tegra210-dmic";
421 reg = !! 292 reg = <0x2904000 0x100>;
422 clocks 293 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock- 294 clock-names = "dmic";
424 assign 295 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assign 296 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assign 297 assigned-clock-rates = <3072000>;
427 sound- 298 sound-name-prefix = "DMIC1";
428 status 299 status = "disabled";
429 }; 300 };
430 301
431 tegra_dmic2: d 302 tegra_dmic2: dmic@2904100 {
432 compat 303 compatible = "nvidia,tegra194-dmic",
433 304 "nvidia,tegra210-dmic";
434 reg = !! 305 reg = <0x2904100 0x100>;
435 clocks 306 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock- 307 clock-names = "dmic";
437 assign 308 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assign 309 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assign 310 assigned-clock-rates = <3072000>;
440 sound- 311 sound-name-prefix = "DMIC2";
441 status 312 status = "disabled";
442 }; 313 };
443 314
444 tegra_dmic3: d 315 tegra_dmic3: dmic@2904200 {
445 compat 316 compatible = "nvidia,tegra194-dmic",
446 317 "nvidia,tegra210-dmic";
447 reg = !! 318 reg = <0x2904200 0x100>;
448 clocks 319 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock- 320 clock-names = "dmic";
450 assign 321 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assign 322 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assign 323 assigned-clock-rates = <3072000>;
453 sound- 324 sound-name-prefix = "DMIC3";
454 status 325 status = "disabled";
455 }; 326 };
456 327
457 tegra_dmic4: d 328 tegra_dmic4: dmic@2904300 {
458 compat 329 compatible = "nvidia,tegra194-dmic",
459 330 "nvidia,tegra210-dmic";
460 reg = !! 331 reg = <0x2904300 0x100>;
461 clocks 332 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock- 333 clock-names = "dmic";
463 assign 334 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assign 335 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assign 336 assigned-clock-rates = <3072000>;
466 sound- 337 sound-name-prefix = "DMIC4";
467 status 338 status = "disabled";
468 }; 339 };
469 340
470 tegra_dspk1: d 341 tegra_dspk1: dspk@2905000 {
471 compat 342 compatible = "nvidia,tegra194-dspk",
472 343 "nvidia,tegra186-dspk";
473 reg = !! 344 reg = <0x2905000 0x100>;
474 clocks 345 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock- 346 clock-names = "dspk";
476 assign 347 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assign 348 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assign 349 assigned-clock-rates = <12288000>;
479 sound- 350 sound-name-prefix = "DSPK1";
480 status 351 status = "disabled";
481 }; 352 };
482 353
483 tegra_dspk2: d 354 tegra_dspk2: dspk@2905100 {
484 compat 355 compatible = "nvidia,tegra194-dspk",
485 356 "nvidia,tegra186-dspk";
486 reg = !! 357 reg = <0x2905100 0x100>;
487 clocks 358 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock- 359 clock-names = "dspk";
489 assign 360 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assign 361 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assign 362 assigned-clock-rates = <12288000>;
492 sound- 363 sound-name-prefix = "DSPK2";
493 status 364 status = "disabled";
494 }; 365 };
>> 366 };
>> 367 };
495 368
496 tegra_ope1: pr !! 369 pinmux: pinmux@2430000 {
497 compat !! 370 compatible = "nvidia,tegra194-pinmux";
498 !! 371 reg = <0x2430000 0x17000>,
499 reg = !! 372 <0xc300000 0x4000>;
500 sound- <<
501 status <<
502 <<
503 #addre <<
504 #size- <<
505 ranges <<
506 <<
507 equali <<
508 <<
509 <<
510 <<
511 }; <<
512 <<
513 dynami <<
514 <<
515 <<
516 <<
517 }; <<
518 }; <<
519 <<
520 tegra_mvc1: mv <<
521 compat <<
522 <<
523 reg = <<
524 sound- <<
525 status <<
526 }; <<
527 <<
528 tegra_mvc2: mv <<
529 compat <<
530 <<
531 reg = <<
532 sound- <<
533 status <<
534 }; <<
535 <<
536 tegra_amixer: <<
537 compat <<
538 <<
539 reg = <<
540 sound- <<
541 status <<
542 }; <<
543 373
544 tegra_admaif: !! 374 status = "okay";
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 375
595 tegra_asrc: as !! 376 pex_rst_c5_out_state: pex_rst_c5_out {
596 compat !! 377 pex_rst {
597 !! 378 nvidia,pins = "pex_l5_rst_n_pgg1";
598 reg = !! 379 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
599 sound- !! 380 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
600 status !! 381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
>> 382 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
>> 383 nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> 384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
601 }; 385 };
602 }; 386 };
603 387
604 adma: dma-controller@2 !! 388 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
605 compatible = " !! 389 clkreq {
606 " !! 390 nvidia,pins = "pex_l5_clkreq_n_pgg0";
607 reg = <0x0 0x0 !! 391 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
608 interrupt-pare !! 392 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
609 interrupts = !! 393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
610 !! 394 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
611 !! 395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
612 !! 396 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 !! 397 };
614 <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; <<
646 <<
647 agic: interrupt-contro <<
648 compatible = " <<
649 " <<
650 #interrupt-cel <<
651 interrupt-cont <<
652 reg = <0x0 0x0 <<
653 <0x0 0x0 <<
654 interrupts = < <<
655 <<
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; 398 };
661 }; 399 };
662 400
663 mc: memory-controller@2c00000 401 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 402 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 403 reg = <0x02c00000 0x100000>,
666 <0x0 0x02c10000 !! 404 <0x02b80000 0x040000>,
667 <0x0 0x02c20000 !! 405 <0x01700000 0x100000>;
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI 406 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
687 #interconnect-cells = 407 #interconnect-cells = <1>;
688 status = "disabled"; 408 status = "disabled";
689 409
690 #address-cells = <2>; 410 #address-cells = <2>;
691 #size-cells = <2>; 411 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 412
693 <0x0 0x02b800 !! 413 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 414 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 415 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 416
696 /* 417 /*
697 * Bit 39 of addresses 418 * Bit 39 of addresses passing through the memory
698 * controller selects 419 * controller selects the XBAR format used when memory
699 * is accessed. This i 420 * is accessed. This is used to transparently access
700 * memory in the XBAR 421 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 422 * (bit 39 set) or Tegra (bit 39 clear).
702 * 423 *
703 * As a consequence, t 424 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 425 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 426 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 427 * devices require access to the XBAR switch, their
707 * drivers must set th 428 * drivers must set this bit explicitly.
708 * 429 *
709 * Limit the DMA range 430 * Limit the DMA range for memory clients to [38:0].
710 */ 431 */
711 dma-ranges = <0x0 0x0 !! 432 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 433
713 emc: external-memory-c 434 emc: external-memory-controller@2c60000 {
714 compatible = " 435 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 436 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 437 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < <<
718 clocks = <&bpm 438 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 439 clock-names = "emc";
720 440
721 #interconnect- 441 #interconnect-cells = <0>;
722 442
723 nvidia,bpmp = 443 nvidia,bpmp = <&bpmp>;
724 }; 444 };
725 }; 445 };
726 446
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 447 uarta: serial@3100000 {
744 compatible = "nvidia,t 448 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 449 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 450 reg-shift = <2>;
747 interrupts = <GIC_SPI 451 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 452 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 453 clock-names = "serial";
749 resets = <&bpmp TEGRA1 454 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 455 reset-names = "serial";
750 status = "disabled"; 456 status = "disabled";
751 }; 457 };
752 458
753 uartb: serial@3110000 { 459 uartb: serial@3110000 {
754 compatible = "nvidia,t 460 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 461 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 462 reg-shift = <2>;
757 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 464 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 465 clock-names = "serial";
759 resets = <&bpmp TEGRA1 466 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 467 reset-names = "serial";
760 status = "disabled"; 468 status = "disabled";
761 }; 469 };
762 470
763 uartd: serial@3130000 { 471 uartd: serial@3130000 {
764 compatible = "nvidia,t 472 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 473 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 474 reg-shift = <2>;
767 interrupts = <GIC_SPI 475 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 476 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 477 clock-names = "serial";
770 resets = <&bpmp TEGRA1 478 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 479 reset-names = "serial";
772 status = "disabled"; 480 status = "disabled";
773 }; 481 };
774 482
775 uarte: serial@3140000 { 483 uarte: serial@3140000 {
776 compatible = "nvidia,t 484 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 485 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 486 reg-shift = <2>;
779 interrupts = <GIC_SPI 487 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 488 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 489 clock-names = "serial";
782 resets = <&bpmp TEGRA1 490 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 491 reset-names = "serial";
784 status = "disabled"; 492 status = "disabled";
785 }; 493 };
786 494
787 uartf: serial@3150000 { 495 uartf: serial@3150000 {
788 compatible = "nvidia,t 496 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 497 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 498 reg-shift = <2>;
791 interrupts = <GIC_SPI 499 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 500 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 501 clock-names = "serial";
794 resets = <&bpmp TEGRA1 502 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 503 reset-names = "serial";
796 status = "disabled"; 504 status = "disabled";
797 }; 505 };
798 506
799 gen1_i2c: i2c@3160000 { 507 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 508 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 509 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 511 #address-cells = <1>;
804 #size-cells = <0>; 512 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 513 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 514 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 515 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 516 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 517 status = "disabled";
812 }; 518 };
813 519
814 uarth: serial@3170000 { 520 uarth: serial@3170000 {
815 compatible = "nvidia,t 521 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 522 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 523 reg-shift = <2>;
818 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 525 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 526 clock-names = "serial";
821 resets = <&bpmp TEGRA1 527 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 528 reset-names = "serial";
823 status = "disabled"; 529 status = "disabled";
824 }; 530 };
825 531
826 cam_i2c: i2c@3180000 { 532 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 533 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 534 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 536 #address-cells = <1>;
831 #size-cells = <0>; 537 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 538 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 539 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 540 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 541 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 542 status = "disabled";
839 }; 543 };
840 544
841 /* shares pads with dpaux1 */ 545 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 546 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 547 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 548 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 549 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 550 #address-cells = <1>;
847 #size-cells = <0>; 551 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 552 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 553 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 554 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 555 reset-names = "i2c";
852 pinctrl-0 = <&state_dp 556 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dp 557 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "defau 558 pinctrl-names = "default", "idle";
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 559 status = "disabled";
858 }; 560 };
859 561
860 /* shares pads with dpaux0 */ 562 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 563 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 564 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 565 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 567 #address-cells = <1>;
866 #size-cells = <0>; 568 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 569 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 570 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 571 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 572 reset-names = "i2c";
871 pinctrl-0 = <&state_dp 573 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dp 574 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "defau 575 pinctrl-names = "default", "idle";
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 576 status = "disabled";
877 }; 577 };
878 578
879 /* shares pads with dpaux2 */ 579 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 { 580 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t 581 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 582 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 583 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 584 #address-cells = <1>;
885 #size-cells = <0>; 585 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 586 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 587 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 588 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 589 reset-names = "i2c";
890 pinctrl-0 = <&state_dp 590 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dp 591 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "defau 592 pinctrl-names = "default", "idle";
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 593 status = "disabled";
896 }; 594 };
897 595
898 /* shares pads with dpaux3 */ 596 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 { 597 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t 598 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 599 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 600 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 601 #address-cells = <1>;
904 #size-cells = <0>; 602 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 603 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 604 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 605 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 606 reset-names = "i2c";
909 pinctrl-0 = <&state_dp 607 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dp 608 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "defau 609 pinctrl-names = "default", "idle";
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; 610 status = "disabled";
915 }; 611 };
916 612
917 spi@3270000 { 613 spi@3270000 {
918 compatible = "nvidia,t 614 compatible = "nvidia,tegra194-qspi";
919 reg = <0x0 0x3270000 0 !! 615 reg = <0x3270000 0x1000>;
920 interrupts = <GIC_SPI 616 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
921 #address-cells = <1>; 617 #address-cells = <1>;
922 #size-cells = <0>; 618 #size-cells = <0>;
923 clocks = <&bpmp TEGRA1 619 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA1 620 <&bpmp TEGRA194_CLK_QSPI0_PM>;
925 clock-names = "qspi", 621 clock-names = "qspi", "qspi_out";
926 resets = <&bpmp TEGRA1 622 resets = <&bpmp TEGRA194_RESET_QSPI0>;
>> 623 reset-names = "qspi";
>> 624 status = "disabled";
>> 625 };
>> 626
>> 627 spi@3300000 {
>> 628 compatible = "nvidia,tegra194-qspi";
>> 629 reg = <0x3300000 0x1000>;
>> 630 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>> 631 #address-cells = <1>;
>> 632 #size-cells = <0>;
>> 633 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
>> 634 <&bpmp TEGRA194_CLK_QSPI1_PM>;
>> 635 clock-names = "qspi", "qspi_out";
>> 636 resets = <&bpmp TEGRA194_RESET_QSPI1>;
>> 637 reset-names = "qspi";
927 status = "disabled"; 638 status = "disabled";
928 }; 639 };
929 640
930 pwm1: pwm@3280000 { 641 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 642 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 643 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 644 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 645 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 646 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 647 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 648 reset-names = "pwm";
937 status = "disabled"; 649 status = "disabled";
938 #pwm-cells = <2>; 650 #pwm-cells = <2>;
939 }; 651 };
940 652
941 pwm2: pwm@3290000 { 653 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 654 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 655 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 656 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 657 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 658 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 659 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 660 reset-names = "pwm";
948 status = "disabled"; 661 status = "disabled";
949 #pwm-cells = <2>; 662 #pwm-cells = <2>;
950 }; 663 };
951 664
952 pwm3: pwm@32a0000 { 665 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 666 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 667 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 668 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 669 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 670 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 671 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 672 reset-names = "pwm";
959 status = "disabled"; 673 status = "disabled";
960 #pwm-cells = <2>; 674 #pwm-cells = <2>;
961 }; 675 };
962 676
963 pwm5: pwm@32c0000 { 677 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 678 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 679 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 680 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 681 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 682 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 683 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 684 reset-names = "pwm";
970 status = "disabled"; 685 status = "disabled";
971 #pwm-cells = <2>; 686 #pwm-cells = <2>;
972 }; 687 };
973 688
974 pwm6: pwm@32d0000 { 689 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 690 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 691 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 692 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 693 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 694 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 695 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 696 reset-names = "pwm";
981 status = "disabled"; 697 status = "disabled";
982 #pwm-cells = <2>; 698 #pwm-cells = <2>;
983 }; 699 };
984 700
985 pwm7: pwm@32e0000 { 701 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 702 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 703 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 704 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 705 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 706 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 707 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 708 reset-names = "pwm";
992 status = "disabled"; 709 status = "disabled";
993 #pwm-cells = <2>; 710 #pwm-cells = <2>;
994 }; 711 };
995 712
996 pwm8: pwm@32f0000 { 713 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 714 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 715 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 716 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 717 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 718 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 719 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 720 reset-names = "pwm";
1003 status = "disabled"; 721 status = "disabled";
1004 #pwm-cells = <2>; 722 #pwm-cells = <2>;
1005 }; 723 };
1006 724
1007 spi@3300000 { <<
1008 compatible = "nvidia, <<
1009 reg = <0x0 0x3300000 <<
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { 725 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia, 726 compatible = "nvidia,tegra194-sdhci";
1022 reg = <0x0 0x03400000 !! 727 reg = <0x03400000 0x10000>;
1023 interrupts = <GIC_SPI 728 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA 729 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA 730 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci" 731 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 732 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 733 reset-names = "sdhci";
1034 interconnects = <&mc 734 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035 <&mc 735 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036 interconnect-names = 736 interconnect-names = "dma-mem", "write";
1037 iommus = <&smmu TEGRA 737 iommus = <&smmu TEGRA194_SID_SDMMC1>;
1038 pinctrl-names = "sdmm <<
1039 pinctrl-0 = <&sdmmc1_ <<
1040 pinctrl-1 = <&sdmmc1_ <<
1041 nvidia,pad-autocal-pu 738 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 739 <0x07>;
1043 nvidia,pad-autocal-pu 740 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 741 <0x07>;
1045 nvidia,pad-autocal-pu 742 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 743 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 744 <0x07>;
1048 nvidia,pad-autocal-pu 745 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 746 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 747 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 748 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; <<
1053 sd-uhs-sdr50; <<
1054 sd-uhs-ddr50; <<
1055 sd-uhs-sdr104; <<
1056 status = "disabled"; 749 status = "disabled";
1057 }; 750 };
1058 751
1059 sdmmc3: mmc@3440000 { 752 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia, 753 compatible = "nvidia,tegra194-sdhci";
1061 reg = <0x0 0x03440000 !! 754 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 755 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA 756 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA 757 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci" 758 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 759 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 760 reset-names = "sdhci";
1073 interconnects = <&mc 761 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074 <&mc 762 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075 interconnect-names = 763 interconnect-names = "dma-mem", "write";
1076 iommus = <&smmu TEGRA 764 iommus = <&smmu TEGRA194_SID_SDMMC3>;
1077 pinctrl-names = "sdmm <<
1078 pinctrl-0 = <&sdmmc3_ <<
1079 pinctrl-1 = <&sdmmc3_ <<
1080 nvidia,pad-autocal-pu 765 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 766 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 767 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 768 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 769 <0x07>;
1085 nvidia,pad-autocal-pu 770 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 771 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 772 <0x07>;
1088 nvidia,pad-autocal-pu 773 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 774 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 775 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 776 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; <<
1093 sd-uhs-sdr50; <<
1094 sd-uhs-ddr50; <<
1095 sd-uhs-sdr104; <<
1096 status = "disabled"; 777 status = "disabled";
1097 }; 778 };
1098 779
1099 sdmmc4: mmc@3460000 { 780 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia, 781 compatible = "nvidia,tegra194-sdhci";
1101 reg = <0x0 0x03460000 !! 782 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 783 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA 784 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA 785 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci" 786 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&b 787 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 788 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 789 assigned-clock-parents =
1109 <&b 790 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 791 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 792 reset-names = "sdhci";
1112 interconnects = <&mc 793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113 <&mc 794 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114 interconnect-names = 795 interconnect-names = "dma-mem", "write";
1115 iommus = <&smmu TEGRA 796 iommus = <&smmu TEGRA194_SID_SDMMC4>;
1116 nvidia,pad-autocal-pu 797 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 798 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 799 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 800 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 801 <0x0a>;
1121 nvidia,pad-autocal-pu 802 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 803 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 804 <0x0a>;
1124 nvidia,default-tap = 805 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 806 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 807 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; <<
1128 mmc-ddr-1_8v; <<
1129 mmc-hs200-1_8v; <<
1130 mmc-hs400-1_8v; <<
1131 mmc-hs400-enhanced-st <<
1132 supports-cqe; 808 supports-cqe;
1133 status = "disabled"; 809 status = "disabled";
1134 }; 810 };
1135 811
1136 hda@3510000 { 812 hda@3510000 {
1137 compatible = "nvidia, !! 813 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 814 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 815 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 816 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA 817 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA 818 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", 819 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA 820 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA 821 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", 822 reset-names = "hda", "hda2hdmi";
1147 power-domains = <&bpm 823 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc 824 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149 <&mc 825 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150 interconnect-names = 826 interconnect-names = "dma-mem", "write";
1151 iommus = <&smmu TEGRA 827 iommus = <&smmu TEGRA194_SID_HDA>;
1152 status = "disabled"; 828 status = "disabled";
1153 }; 829 };
1154 830
1155 xusb_padctl: padctl@3520000 { 831 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia, 832 compatible = "nvidia,tegra194-xusb-padctl";
1157 reg = <0x0 0x03520000 !! 833 reg = <0x03520000 0x1000>,
1158 <0x0 0x03540000 !! 834 <0x03540000 0x1000>;
1159 reg-names = "padctl", 835 reg-names = "padctl", "ao";
1160 interrupts = <GIC_SPI 836 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161 837
1162 resets = <&bpmp TEGRA 838 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl 839 reset-names = "padctl";
1164 840
1165 status = "disabled"; 841 status = "disabled";
1166 842
1167 pads { 843 pads {
1168 usb2 { 844 usb2 {
1169 clock 845 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock 846 clock-names = "trk";
1171 847
1172 lanes 848 lanes {
1173 849 usb2-0 {
1174 850 nvidia,function = "xusb";
1175 851 status = "disabled";
1176 852 #phy-cells = <0>;
1177 853 };
1178 854
1179 855 usb2-1 {
1180 856 nvidia,function = "xusb";
1181 857 status = "disabled";
1182 858 #phy-cells = <0>;
1183 859 };
1184 860
1185 861 usb2-2 {
1186 862 nvidia,function = "xusb";
1187 863 status = "disabled";
1188 864 #phy-cells = <0>;
1189 865 };
1190 866
1191 867 usb2-3 {
1192 868 nvidia,function = "xusb";
1193 869 status = "disabled";
1194 870 #phy-cells = <0>;
1195 871 };
1196 }; 872 };
1197 }; 873 };
1198 874
1199 usb3 { 875 usb3 {
1200 lanes 876 lanes {
1201 877 usb3-0 {
1202 878 nvidia,function = "xusb";
1203 879 status = "disabled";
1204 880 #phy-cells = <0>;
1205 881 };
1206 882
1207 883 usb3-1 {
1208 884 nvidia,function = "xusb";
1209 885 status = "disabled";
1210 886 #phy-cells = <0>;
1211 887 };
1212 888
1213 889 usb3-2 {
1214 890 nvidia,function = "xusb";
1215 891 status = "disabled";
1216 892 #phy-cells = <0>;
1217 893 };
1218 894
1219 895 usb3-3 {
1220 896 nvidia,function = "xusb";
1221 897 status = "disabled";
1222 898 #phy-cells = <0>;
1223 899 };
1224 }; 900 };
1225 }; 901 };
1226 }; 902 };
1227 903
1228 ports { 904 ports {
1229 usb2-0 { 905 usb2-0 {
1230 statu 906 status = "disabled";
1231 }; 907 };
1232 908
1233 usb2-1 { 909 usb2-1 {
1234 statu 910 status = "disabled";
1235 }; 911 };
1236 912
1237 usb2-2 { 913 usb2-2 {
1238 statu 914 status = "disabled";
1239 }; 915 };
1240 916
1241 usb2-3 { 917 usb2-3 {
1242 statu 918 status = "disabled";
1243 }; 919 };
1244 920
1245 usb3-0 { 921 usb3-0 {
1246 statu 922 status = "disabled";
1247 }; 923 };
1248 924
1249 usb3-1 { 925 usb3-1 {
1250 statu 926 status = "disabled";
1251 }; 927 };
1252 928
1253 usb3-2 { 929 usb3-2 {
1254 statu 930 status = "disabled";
1255 }; 931 };
1256 932
1257 usb3-3 { 933 usb3-3 {
1258 statu 934 status = "disabled";
1259 }; 935 };
1260 }; 936 };
1261 }; 937 };
1262 938
1263 usb@3550000 { 939 usb@3550000 {
1264 compatible = "nvidia, 940 compatible = "nvidia,tegra194-xudc";
1265 reg = <0x0 0x03550000 !! 941 reg = <0x03550000 0x8000>,
1266 <0x0 0x03558000 !! 942 <0x03558000 0x1000>;
1267 reg-names = "base", " 943 reg-names = "base", "fpci";
1268 interrupts = <GIC_SPI 944 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&bpmp TEGRA 945 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA 946 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA 947 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA 948 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", 949 clock-names = "dev", "ss", "ss_src", "fs_src";
1274 interconnects = <&mc 950 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1275 <&mc 951 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1276 interconnect-names = 952 interconnect-names = "dma-mem", "write";
1277 iommus = <&smmu TEGRA 953 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1278 power-domains = <&bpm 954 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpm 955 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = 956 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = 957 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent; <<
1283 status = "disabled"; 958 status = "disabled";
1284 }; 959 };
1285 960
1286 usb@3610000 { 961 usb@3610000 {
1287 compatible = "nvidia, 962 compatible = "nvidia,tegra194-xusb";
1288 reg = <0x0 0x03610000 !! 963 reg = <0x03610000 0x40000>,
1289 <0x0 0x03600000 !! 964 <0x03600000 0x10000>;
1290 reg-names = "hcd", "f 965 reg-names = "hcd", "fpci";
1291 966
1292 interrupts = <GIC_SPI 967 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 968 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294 969
1295 clocks = <&bpmp TEGRA 970 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA 971 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA 972 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA 973 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA 974 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA 975 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA 976 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA 977 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA 978 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_h 979 clock-names = "xusb_host", "xusb_falcon_src",
1305 "xusb_s 980 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306 "xusb_f 981 "xusb_fs_src", "pll_u_480m", "clk_m",
1307 "pll_e" 982 "pll_e";
1308 interconnects = <&mc 983 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1309 <&mc 984 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1310 interconnect-names = 985 interconnect-names = "dma-mem", "write";
1311 iommus = <&smmu TEGRA 986 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1312 987
1313 power-domains = <&bpm 988 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpm 989 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = 990 power-domain-names = "xusb_host", "xusb_ss";
1316 991
1317 nvidia,xusb-padctl = 992 nvidia,xusb-padctl = <&xusb_padctl>;
1318 status = "disabled"; 993 status = "disabled";
1319 }; 994 };
1320 995
1321 fuse@3820000 { 996 fuse@3820000 {
1322 compatible = "nvidia, 997 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 998 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 999 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 1000 clock-names = "fuse";
1326 }; 1001 };
1327 1002
1328 gic: interrupt-controller@388 1003 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 1004 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 1005 #interrupt-cells = <3>;
1331 interrupt-controller; 1006 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 1007 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 1008 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 1009 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 1010 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 1011 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 1012 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 1013 interrupt-parent = <&gic>;
1339 }; 1014 };
1340 1015
1341 cec@3960000 { 1016 cec@3960000 {
1342 compatible = "nvidia, 1017 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 1018 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 1019 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 1020 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 1021 clock-names = "cec";
1347 status = "disabled"; 1022 status = "disabled";
1348 }; 1023 };
1349 1024
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 1025 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, !! 1026 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1362 reg = <0x0 0x03c00000 !! 1027 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 1028 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1029 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1030 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1031 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1032 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1033 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1034 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1035 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1036 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 1037 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 1038 "shared3", "shared4", "shared5", "shared6",
1374 "sh 1039 "shared7";
1375 #mbox-cells = <2>; 1040 #mbox-cells = <2>;
1376 }; 1041 };
1377 1042
1378 p2u_hsio_0: phy@3e10000 { 1043 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 1044 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 1045 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 1046 reg-names = "ctl";
1382 1047
1383 #phy-cells = <0>; 1048 #phy-cells = <0>;
1384 }; 1049 };
1385 1050
1386 p2u_hsio_1: phy@3e20000 { 1051 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 1052 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 1053 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 1054 reg-names = "ctl";
1390 1055
1391 #phy-cells = <0>; 1056 #phy-cells = <0>;
1392 }; 1057 };
1393 1058
1394 p2u_hsio_2: phy@3e30000 { 1059 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 1060 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 1061 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 1062 reg-names = "ctl";
1398 1063
1399 #phy-cells = <0>; 1064 #phy-cells = <0>;
1400 }; 1065 };
1401 1066
1402 p2u_hsio_3: phy@3e40000 { 1067 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 1068 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 1069 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 1070 reg-names = "ctl";
1406 1071
1407 #phy-cells = <0>; 1072 #phy-cells = <0>;
1408 }; 1073 };
1409 1074
1410 p2u_hsio_4: phy@3e50000 { 1075 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 1076 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 1077 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 1078 reg-names = "ctl";
1414 1079
1415 #phy-cells = <0>; 1080 #phy-cells = <0>;
1416 }; 1081 };
1417 1082
1418 p2u_hsio_5: phy@3e60000 { 1083 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 1084 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 1085 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 1086 reg-names = "ctl";
1422 1087
1423 #phy-cells = <0>; 1088 #phy-cells = <0>;
1424 }; 1089 };
1425 1090
1426 p2u_hsio_6: phy@3e70000 { 1091 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 1092 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 1093 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 1094 reg-names = "ctl";
1430 1095
1431 #phy-cells = <0>; 1096 #phy-cells = <0>;
1432 }; 1097 };
1433 1098
1434 p2u_hsio_7: phy@3e80000 { 1099 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 1100 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 1101 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 1102 reg-names = "ctl";
1438 1103
1439 #phy-cells = <0>; 1104 #phy-cells = <0>;
1440 }; 1105 };
1441 1106
1442 p2u_hsio_8: phy@3e90000 { 1107 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 1108 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 1109 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 1110 reg-names = "ctl";
1446 1111
1447 #phy-cells = <0>; 1112 #phy-cells = <0>;
1448 }; 1113 };
1449 1114
1450 p2u_hsio_9: phy@3ea0000 { 1115 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 1116 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 1117 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 1118 reg-names = "ctl";
1454 1119
1455 #phy-cells = <0>; 1120 #phy-cells = <0>;
1456 }; 1121 };
1457 1122
1458 p2u_nvhs_0: phy@3eb0000 { 1123 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 1124 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 1125 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 1126 reg-names = "ctl";
1462 1127
1463 #phy-cells = <0>; 1128 #phy-cells = <0>;
1464 }; 1129 };
1465 1130
1466 p2u_nvhs_1: phy@3ec0000 { 1131 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 1132 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 1133 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 1134 reg-names = "ctl";
1470 1135
1471 #phy-cells = <0>; 1136 #phy-cells = <0>;
1472 }; 1137 };
1473 1138
1474 p2u_nvhs_2: phy@3ed0000 { 1139 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 1140 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 1141 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 1142 reg-names = "ctl";
1478 1143
1479 #phy-cells = <0>; 1144 #phy-cells = <0>;
1480 }; 1145 };
1481 1146
1482 p2u_nvhs_3: phy@3ee0000 { 1147 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 1148 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 1149 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 1150 reg-names = "ctl";
1486 1151
1487 #phy-cells = <0>; 1152 #phy-cells = <0>;
1488 }; 1153 };
1489 1154
1490 p2u_nvhs_4: phy@3ef0000 { 1155 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 1156 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 1157 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 1158 reg-names = "ctl";
1494 1159
1495 #phy-cells = <0>; 1160 #phy-cells = <0>;
1496 }; 1161 };
1497 1162
1498 p2u_nvhs_5: phy@3f00000 { 1163 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 1164 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 1165 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 1166 reg-names = "ctl";
1502 1167
1503 #phy-cells = <0>; 1168 #phy-cells = <0>;
1504 }; 1169 };
1505 1170
1506 p2u_nvhs_6: phy@3f10000 { 1171 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 1172 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 1173 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 1174 reg-names = "ctl";
1510 1175
1511 #phy-cells = <0>; 1176 #phy-cells = <0>;
1512 }; 1177 };
1513 1178
1514 p2u_nvhs_7: phy@3f20000 { 1179 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 1180 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 1181 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 1182 reg-names = "ctl";
1518 1183
1519 #phy-cells = <0>; 1184 #phy-cells = <0>;
1520 }; 1185 };
1521 1186
1522 p2u_hsio_10: phy@3f30000 { 1187 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 1188 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 1189 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 1190 reg-names = "ctl";
1526 1191
1527 #phy-cells = <0>; 1192 #phy-cells = <0>;
1528 }; 1193 };
1529 1194
1530 p2u_hsio_11: phy@3f40000 { 1195 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 1196 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 1197 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 1198 reg-names = "ctl";
1534 1199
1535 #phy-cells = <0>; 1200 #phy-cells = <0>;
1536 }; 1201 };
1537 1202
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 1203 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, !! 1204 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1560 reg = <0x0 0x0c150000 !! 1205 reg = <0x0c150000 0x90000>;
1561 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 1207 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 1208 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 1209 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1210 /*
1566 * Shared interrupt 0 1211 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 1212 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 1213 */
1569 interrupt-names = "sh 1214 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 1215 #mbox-cells = <2>;
1571 }; 1216 };
1572 1217
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 1218 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 1219 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 1220 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 1221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 1222 #address-cells = <1>;
1588 #size-cells = <0>; 1223 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 1224 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 1225 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 1226 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 1227 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 1228 status = "disabled";
1596 }; 1229 };
1597 1230
1598 gen8_i2c: i2c@c250000 { 1231 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 1232 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 1233 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 1235 #address-cells = <1>;
1603 #size-cells = <0>; 1236 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 1237 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 1238 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 1239 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 1240 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 1241 status = "disabled";
1611 }; 1242 };
1612 1243
1613 uartc: serial@c280000 { 1244 uartc: serial@c280000 {
1614 compatible = "nvidia, 1245 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 1246 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 1247 reg-shift = <2>;
1617 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 1249 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 1250 clock-names = "serial";
1620 resets = <&bpmp TEGRA 1251 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 1252 reset-names = "serial";
1622 status = "disabled"; 1253 status = "disabled";
1623 }; 1254 };
1624 1255
1625 uartg: serial@c290000 { 1256 uartg: serial@c290000 {
1626 compatible = "nvidia, 1257 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 1258 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 1259 reg-shift = <2>;
1629 interrupts = <GIC_SPI 1260 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 1261 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 1262 clock-names = "serial";
1632 resets = <&bpmp TEGRA 1263 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 1264 reset-names = "serial";
1634 status = "disabled"; 1265 status = "disabled";
1635 }; 1266 };
1636 1267
1637 rtc: rtc@c2a0000 { 1268 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 1269 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 1270 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 1271 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 1272 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 1273 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 1274 clock-names = "rtc";
1644 status = "disabled"; 1275 status = "disabled";
1645 }; 1276 };
1646 1277
1647 gpio_aon: gpio@c2f0000 { 1278 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 1279 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 1280 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 1281 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 1282 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI !! 1283 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1653 <GIC_SPI <<
1654 <GIC_SPI <<
1655 <GIC_SPI <<
1656 gpio-controller; 1284 gpio-controller;
1657 #gpio-cells = <2>; 1285 #gpio-cells = <2>;
1658 interrupt-controller; 1286 interrupt-controller;
1659 #interrupt-cells = <2 1287 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 1288 };
1669 1289
1670 pwm4: pwm@c340000 { 1290 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 1291 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 1292 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 1293 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 1294 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 1295 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 1296 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 1297 reset-names = "pwm";
1677 status = "disabled"; 1298 status = "disabled";
1678 #pwm-cells = <2>; 1299 #pwm-cells = <2>;
1679 }; 1300 };
1680 1301
1681 pmc: pmc@c360000 { 1302 pmc: pmc@c360000 {
1682 compatible = "nvidia, 1303 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 1304 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 1305 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 1306 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 1307 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 1308 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 1309 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 1310
1690 #interrupt-cells = <2 1311 #interrupt-cells = <2>;
1691 interrupt-controller; 1312 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v <<
1699 pins = "sdmmc <<
1700 power-source <<
1701 }; <<
1702 <<
1703 sdmmc3_1v8: sdmmc3-1v <<
1704 pins = "sdmmc <<
1705 power-source <<
1706 }; <<
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v <<
1709 pins = "sdmmc <<
1710 power-source <<
1711 }; <<
1712 }; <<
1713 <<
1714 aon-noc@c600000 { <<
1715 compatible = "nvidia, <<
1716 reg = <0x0 0xc600000 <<
1717 interrupts = <GIC_SPI <<
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 <<
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; <<
1732 <<
1733 iommu@10000000 { <<
1734 compatible = "nvidia, <<
1735 reg = <0x0 0x10000000 <<
1736 interrupts = <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 <GIC_SPI <<
1747 <GIC_SPI <<
1748 <GIC_SPI <<
1749 <GIC_SPI <<
1750 <GIC_SPI <<
1751 <GIC_SPI <<
1752 <GIC_SPI <<
1753 <GIC_SPI <<
1754 <GIC_SPI <<
1755 <GIC_SPI <<
1756 <GIC_SPI <<
1757 <GIC_SPI <<
1758 <GIC_SPI <<
1759 <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 <GIC_SPI <<
1770 <GIC_SPI <<
1771 <GIC_SPI <<
1772 <GIC_SPI <<
1773 <GIC_SPI <<
1774 <GIC_SPI <<
1775 <GIC_SPI <<
1776 <GIC_SPI <<
1777 <GIC_SPI <<
1778 <GIC_SPI <<
1779 <GIC_SPI <<
1780 <GIC_SPI <<
1781 <GIC_SPI <<
1782 <GIC_SPI <<
1783 <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 <GIC_SPI <<
1792 <GIC_SPI <<
1793 <GIC_SPI <<
1794 <GIC_SPI <<
1795 <GIC_SPI <<
1796 <GIC_SPI <<
1797 <GIC_SPI <<
1798 <GIC_SPI <<
1799 <GIC_SPI <<
1800 <GIC_SPI <<
1801 stream-match-mask = < <<
1802 #global-interrupts = <<
1803 #iommu-cells = <1>; <<
1804 <<
1805 nvidia,memory-control <<
1806 status = "disabled"; <<
1807 }; 1313 };
1808 1314
1809 smmu: iommu@12000000 { 1315 smmu: iommu@12000000 {
1810 compatible = "nvidia, 1316 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1811 reg = <0x0 0x12000000 !! 1317 reg = <0x12000000 0x800000>,
1812 <0x0 0x11000000 !! 1318 <0x11000000 0x800000>;
1813 interrupts = <GIC_SPI 1319 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1320 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1321 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1322 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1323 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1324 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1325 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1326 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1327 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1328 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1329 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1330 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1331 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1332 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1333 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1334 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1335 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1336 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1337 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 1339 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 1340 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 1341 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 1342 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 1343 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 1344 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 1345 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 1346 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 1347 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 1348 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 1349 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 1350 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 1351 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 1352 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 1353 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 1354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 1355 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 1356 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 1357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 1358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 1359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 1360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 1361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 1362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 1363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 1364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 1365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 1366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 1367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 1368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 1369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 1370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 1371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 1372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 1373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 1375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 1376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1379 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 1381 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 1382 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1879 stream-match-mask = < 1385 stream-match-mask = <0x7f80>;
1880 #global-interrupts = 1386 #global-interrupts = <2>;
1881 #iommu-cells = <1>; 1387 #iommu-cells = <1>;
1882 1388
1883 nvidia,memory-control 1389 nvidia,memory-controller = <&mc>;
1884 status = "okay"; 1390 status = "okay";
1885 }; 1391 };
1886 1392
1887 host1x@13e00000 { 1393 host1x@13e00000 {
1888 compatible = "nvidia, 1394 compatible = "nvidia,tegra194-host1x";
1889 reg = <0x0 0x13e00000 !! 1395 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 1396 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 1397 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 1398 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1399 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy 1400 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA 1401 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 1402 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 1403 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 1404 reset-names = "host1x";
1899 1405
1900 #address-cells = <2>; !! 1406 #address-cells = <1>;
1901 #size-cells = <2>; !! 1407 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 1408
>> 1409 ranges = <0x15000000 0x15000000 0x01000000>;
1904 interconnects = <&mc 1410 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905 interconnect-names = 1411 interconnect-names = "dma-mem";
1906 iommus = <&smmu TEGRA 1412 iommus = <&smmu TEGRA194_SID_HOST1X>;
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 <<
1919 nvdec@15140000 { <<
1920 compatible = <<
1921 reg = <0x0 0x <<
1922 clocks = <&bp <<
1923 clock-names = <<
1924 resets = <&bp <<
1925 reset-names = <<
1926 <<
1927 power-domains <<
1928 interconnects <<
1929 <<
1930 <<
1931 interconnect- <<
1932 iommus = <&sm <<
1933 dma-coherent; <<
1934 <<
1935 nvidia,host1x <<
1936 }; <<
1937 1413
1938 display-hub@15200000 1414 display-hub@15200000 {
1939 compatible = 1415 compatible = "nvidia,tegra194-display";
1940 reg = <0x0 0x !! 1416 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 1417 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 1418 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 1419 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 1420 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 1421 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 1422 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 1423 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 1424 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 1425 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 1426 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 1427 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 1428 clock-names = "disp", "hub";
1953 status = "dis 1429 status = "disabled";
1954 1430
1955 power-domains 1431 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 1432
1957 #address-cell !! 1433 #address-cells = <1>;
1958 #size-cells = !! 1434 #size-cells = <1>;
1959 ranges = <0x0 !! 1435
>> 1436 ranges = <0x15200000 0x15200000 0x40000>;
1960 1437
1961 display@15200 1438 display@15200000 {
1962 compa 1439 compatible = "nvidia,tegra194-dc";
1963 reg = !! 1440 reg = <0x15200000 0x10000>;
1964 inter 1441 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 1442 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 1443 clock-names = "dc";
1967 reset 1444 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 1445 reset-names = "dc";
1969 1446
1970 power 1447 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter 1448 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 1449 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 inter 1450 interconnect-names = "dma-mem", "read-1";
1974 1451
1975 nvidi 1452 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 1453 nvidia,head = <0>;
1977 }; 1454 };
1978 1455
1979 display@15210 1456 display@15210000 {
1980 compa 1457 compatible = "nvidia,tegra194-dc";
1981 reg = !! 1458 reg = <0x15210000 0x10000>;
1982 inter 1459 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 1460 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 1461 clock-names = "dc";
1985 reset 1462 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 1463 reset-names = "dc";
1987 1464
1988 power 1465 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter 1466 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 1467 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 inter 1468 interconnect-names = "dma-mem", "read-1";
1992 1469
1993 nvidi 1470 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 1471 nvidia,head = <1>;
1995 }; 1472 };
1996 1473
1997 display@15220 1474 display@15220000 {
1998 compa 1475 compatible = "nvidia,tegra194-dc";
1999 reg = !! 1476 reg = <0x15220000 0x10000>;
2000 inter 1477 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 1478 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 1479 clock-names = "dc";
2003 reset 1480 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 1481 reset-names = "dc";
2005 1482
2006 power 1483 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter 1484 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008 1485 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009 inter 1486 interconnect-names = "dma-mem", "read-1";
2010 1487
2011 nvidi 1488 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 1489 nvidia,head = <2>;
2013 }; 1490 };
2014 1491
2015 display@15230 1492 display@15230000 {
2016 compa 1493 compatible = "nvidia,tegra194-dc";
2017 reg = !! 1494 reg = <0x15230000 0x10000>;
2018 inter 1495 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 1496 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 1497 clock-names = "dc";
2021 reset 1498 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 1499 reset-names = "dc";
2023 1500
2024 power 1501 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter 1502 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026 1503 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027 inter 1504 interconnect-names = "dma-mem", "read-1";
2028 1505
2029 nvidi 1506 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 1507 nvidia,head = <3>;
2031 }; 1508 };
2032 }; 1509 };
2033 1510
2034 vic@15340000 { 1511 vic@15340000 {
2035 compatible = 1512 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 1513 reg = <0x15340000 0x00040000>;
2037 interrupts = 1514 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 1515 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 1516 clock-names = "vic";
2040 resets = <&bp 1517 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 1518 reset-names = "vic";
2042 1519
2043 power-domains 1520 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects 1521 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045 1522 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046 interconnect- 1523 interconnect-names = "dma-mem", "write";
2047 iommus = <&sm 1524 iommus = <&smmu TEGRA194_SID_VIC>;
2048 dma-coherent; <<
2049 }; <<
2050 <<
2051 nvjpg@15380000 { <<
2052 compatible = <<
2053 reg = <0x0 0x <<
2054 clocks = <&bp <<
2055 clock-names = <<
2056 resets = <&bp <<
2057 reset-names = <<
2058 <<
2059 power-domains <<
2060 interconnects <<
2061 <<
2062 interconnect- <<
2063 iommus = <&sm <<
2064 dma-coherent; <<
2065 }; <<
2066 <<
2067 nvdec@15480000 { <<
2068 compatible = <<
2069 reg = <0x0 0x <<
2070 clocks = <&bp <<
2071 clock-names = <<
2072 resets = <&bp <<
2073 reset-names = <<
2074 <<
2075 power-domains <<
2076 interconnects <<
2077 <<
2078 <<
2079 interconnect- <<
2080 iommus = <&sm <<
2081 dma-coherent; <<
2082 <<
2083 nvidia,host1x <<
2084 }; <<
2085 <<
2086 nvenc@154c0000 { <<
2087 compatible = <<
2088 reg = <0x0 0x <<
2089 clocks = <&bp <<
2090 clock-names = <<
2091 resets = <&bp <<
2092 reset-names = <<
2093 <<
2094 power-domains <<
2095 interconnects <<
2096 <<
2097 <<
2098 interconnect- <<
2099 iommus = <&sm <<
2100 dma-coherent; <<
2101 <<
2102 nvidia,host1x <<
2103 }; 1525 };
2104 1526
2105 dpaux0: dpaux@155c000 1527 dpaux0: dpaux@155c0000 {
2106 compatible = 1528 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 1529 reg = <0x155c0000 0x10000>;
2108 interrupts = 1530 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 1531 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 1532 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 1533 clock-names = "dpaux", "parent";
2112 resets = <&bp 1534 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 1535 reset-names = "dpaux";
2114 status = "dis 1536 status = "disabled";
2115 1537
2116 power-domains 1538 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 1539
2118 state_dpaux0_ 1540 state_dpaux0_aux: pinmux-aux {
2119 group 1541 groups = "dpaux-io";
2120 funct 1542 function = "aux";
2121 }; 1543 };
2122 1544
2123 state_dpaux0_ 1545 state_dpaux0_i2c: pinmux-i2c {
2124 group 1546 groups = "dpaux-io";
2125 funct 1547 function = "i2c";
2126 }; 1548 };
2127 1549
2128 state_dpaux0_ 1550 state_dpaux0_off: pinmux-off {
2129 group 1551 groups = "dpaux-io";
2130 funct 1552 function = "off";
2131 }; 1553 };
2132 1554
2133 i2c-bus { 1555 i2c-bus {
2134 #addr 1556 #address-cells = <1>;
2135 #size 1557 #size-cells = <0>;
2136 }; 1558 };
2137 }; 1559 };
2138 1560
2139 dpaux1: dpaux@155d000 1561 dpaux1: dpaux@155d0000 {
2140 compatible = 1562 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1563 reg = <0x155d0000 0x10000>;
2142 interrupts = 1564 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1565 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1566 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1567 clock-names = "dpaux", "parent";
2146 resets = <&bp 1568 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 1569 reset-names = "dpaux";
2148 status = "dis 1570 status = "disabled";
2149 1571
2150 power-domains 1572 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 1573
2152 state_dpaux1_ 1574 state_dpaux1_aux: pinmux-aux {
2153 group 1575 groups = "dpaux-io";
2154 funct 1576 function = "aux";
2155 }; 1577 };
2156 1578
2157 state_dpaux1_ 1579 state_dpaux1_i2c: pinmux-i2c {
2158 group 1580 groups = "dpaux-io";
2159 funct 1581 function = "i2c";
2160 }; 1582 };
2161 1583
2162 state_dpaux1_ 1584 state_dpaux1_off: pinmux-off {
2163 group 1585 groups = "dpaux-io";
2164 funct 1586 function = "off";
2165 }; 1587 };
2166 1588
2167 i2c-bus { 1589 i2c-bus {
2168 #addr 1590 #address-cells = <1>;
2169 #size 1591 #size-cells = <0>;
2170 }; 1592 };
2171 }; 1593 };
2172 1594
2173 dpaux2: dpaux@155e000 1595 dpaux2: dpaux@155e0000 {
2174 compatible = 1596 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 1597 reg = <0x155e0000 0x10000>;
2176 interrupts = 1598 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 1599 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 1600 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 1601 clock-names = "dpaux", "parent";
2180 resets = <&bp 1602 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 1603 reset-names = "dpaux";
2182 status = "dis 1604 status = "disabled";
2183 1605
2184 power-domains 1606 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 1607
2186 state_dpaux2_ 1608 state_dpaux2_aux: pinmux-aux {
2187 group 1609 groups = "dpaux-io";
2188 funct 1610 function = "aux";
2189 }; 1611 };
2190 1612
2191 state_dpaux2_ 1613 state_dpaux2_i2c: pinmux-i2c {
2192 group 1614 groups = "dpaux-io";
2193 funct 1615 function = "i2c";
2194 }; 1616 };
2195 1617
2196 state_dpaux2_ 1618 state_dpaux2_off: pinmux-off {
2197 group 1619 groups = "dpaux-io";
2198 funct 1620 function = "off";
2199 }; 1621 };
2200 1622
2201 i2c-bus { 1623 i2c-bus {
2202 #addr 1624 #address-cells = <1>;
2203 #size 1625 #size-cells = <0>;
2204 }; 1626 };
2205 }; 1627 };
2206 1628
2207 dpaux3: dpaux@155f000 1629 dpaux3: dpaux@155f0000 {
2208 compatible = 1630 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 1631 reg = <0x155f0000 0x10000>;
2210 interrupts = 1632 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 1633 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 1634 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 1635 clock-names = "dpaux", "parent";
2214 resets = <&bp 1636 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 1637 reset-names = "dpaux";
2216 status = "dis 1638 status = "disabled";
2217 1639
2218 power-domains 1640 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 1641
2220 state_dpaux3_ 1642 state_dpaux3_aux: pinmux-aux {
2221 group 1643 groups = "dpaux-io";
2222 funct 1644 function = "aux";
2223 }; 1645 };
2224 1646
2225 state_dpaux3_ 1647 state_dpaux3_i2c: pinmux-i2c {
2226 group 1648 groups = "dpaux-io";
2227 funct 1649 function = "i2c";
2228 }; 1650 };
2229 1651
2230 state_dpaux3_ 1652 state_dpaux3_off: pinmux-off {
2231 group 1653 groups = "dpaux-io";
2232 funct 1654 function = "off";
2233 }; 1655 };
2234 1656
2235 i2c-bus { 1657 i2c-bus {
2236 #addr 1658 #address-cells = <1>;
2237 #size 1659 #size-cells = <0>;
2238 }; 1660 };
2239 }; 1661 };
2240 1662
2241 nvenc@15a80000 { <<
2242 compatible = <<
2243 reg = <0x0 0x <<
2244 clocks = <&bp <<
2245 clock-names = <<
2246 resets = <&bp <<
2247 reset-names = <<
2248 <<
2249 power-domains <<
2250 interconnects <<
2251 <<
2252 <<
2253 interconnect- <<
2254 iommus = <&sm <<
2255 dma-coherent; <<
2256 <<
2257 nvidia,host1x <<
2258 }; <<
2259 <<
2260 sor0: sor@15b00000 { 1663 sor0: sor@15b00000 {
2261 compatible = 1664 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 1665 reg = <0x15b00000 0x40000>;
2263 interrupts = 1666 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 1667 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 1668 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 1669 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 1670 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 1671 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 1672 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 1673 clock-names = "sor", "out", "parent", "dp", "safe",
2271 1674 "pad";
2272 resets = <&bp 1675 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 1676 reset-names = "sor";
2274 pinctrl-0 = < 1677 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 1678 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 1679 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 1680 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 1681 status = "disabled";
2279 1682
2280 power-domains 1683 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 1684 nvidia,interface = <0>;
2282 }; 1685 };
2283 1686
2284 sor1: sor@15b40000 { 1687 sor1: sor@15b40000 {
2285 compatible = 1688 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 1689 reg = <0x15b40000 0x40000>;
2287 interrupts = 1690 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 1691 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 1692 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 1693 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 1694 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 1695 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 1696 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 1697 clock-names = "sor", "out", "parent", "dp", "safe",
2295 1698 "pad";
2296 resets = <&bp 1699 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 1700 reset-names = "sor";
2298 pinctrl-0 = < 1701 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 1702 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 1703 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 1704 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 1705 status = "disabled";
2303 1706
2304 power-domains 1707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 1708 nvidia,interface = <1>;
2306 }; 1709 };
2307 1710
2308 sor2: sor@15b80000 { 1711 sor2: sor@15b80000 {
2309 compatible = 1712 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 1713 reg = <0x15b80000 0x40000>;
2311 interrupts = 1714 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 1715 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 1716 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 1717 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 1718 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 1719 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 1720 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 1721 clock-names = "sor", "out", "parent", "dp", "safe",
2319 1722 "pad";
2320 resets = <&bp 1723 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 1724 reset-names = "sor";
2322 pinctrl-0 = < 1725 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 1726 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 1727 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 1728 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 1729 status = "disabled";
2327 1730
2328 power-domains 1731 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 1732 nvidia,interface = <2>;
2330 }; 1733 };
2331 1734
2332 sor3: sor@15bc0000 { 1735 sor3: sor@15bc0000 {
2333 compatible = 1736 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 1737 reg = <0x15bc0000 0x40000>;
2335 interrupts = 1738 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 1739 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 1740 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 1741 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 1742 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 1743 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 1744 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 1745 clock-names = "sor", "out", "parent", "dp", "safe",
2343 1746 "pad";
2344 resets = <&bp 1747 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 1748 reset-names = "sor";
2346 pinctrl-0 = < 1749 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 1750 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 1751 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 1752 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 1753 status = "disabled";
2351 1754
2352 power-domains 1755 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 1756 nvidia,interface = <3>;
2354 }; 1757 };
2355 }; 1758 };
2356 1759
2357 pcie@14100000 { <<
2358 compatible = "nvidia, <<
2359 power-domains = <&bpm <<
2360 reg = <0x00 0x1410000 <<
2361 <0x00 0x3000000 <<
2362 <0x00 0x3004000 <<
2363 <0x00 0x3008000 <<
2364 reg-names = "appl", " <<
2365 <<
2366 status = "disabled"; <<
2367 <<
2368 #address-cells = <3>; <<
2369 #size-cells = <2>; <<
2370 device_type = "pci"; <<
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 <<
2377 resets = <&bpmp TEGRA <<
2378 <&bpmp TEGRA <<
2379 reset-names = "apb", <<
2380 <<
2381 interrupts = <GIC_SPI <<
2382 <GIC_SPI <<
2383 interrupt-names = "in <<
2384 <<
2385 #interrupt-cells = <1 <<
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 <<
2389 nvidia,bpmp = <&bpmp <<
2390 <<
2391 nvidia,aspm-cmrt-us = <<
2392 nvidia,aspm-pwr-on-t- <<
2393 nvidia,aspm-l0s-entra <<
2394 <<
2395 bus-range = <0x0 0xff <<
2396 <<
2397 ranges = <0x43000000 <<
2398 <0x02000000 <<
2399 <0x01000000 <<
2400 <<
2401 interconnects = <&mc <<
2402 <&mc <<
2403 interconnect-names = <<
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 <<
2409 pcie@14120000 { <<
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 <<
2418 status = "disabled"; <<
2419 <<
2420 #address-cells = <3>; <<
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 <<
2426 clocks = <&bpmp TEGRA <<
2427 clock-names = "core"; <<
2428 <<
2429 resets = <&bpmp TEGRA <<
2430 <&bpmp TEGRA <<
2431 reset-names = "apb", <<
2432 <<
2433 interrupts = <GIC_SPI <<
2434 <GIC_SPI <<
2435 interrupt-names = "in <<
2436 <<
2437 #interrupt-cells = <1 <<
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 <<
2441 nvidia,bpmp = <&bpmp <<
2442 <<
2443 nvidia,aspm-cmrt-us = <<
2444 nvidia,aspm-pwr-on-t- <<
2445 nvidia,aspm-l0s-entra <<
2446 <<
2447 bus-range = <0x0 0xff <<
2448 <<
2449 ranges = <0x43000000 <<
2450 <0x02000000 <<
2451 <0x01000000 <<
2452 <<
2453 interconnects = <&mc <<
2454 <&mc <<
2455 interconnect-names = <<
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 <<
2461 pcie@14140000 { <<
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 <<
2470 status = "disabled"; <<
2471 <<
2472 #address-cells = <3>; <<
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 <<
2478 clocks = <&bpmp TEGRA <<
2479 clock-names = "core"; <<
2480 <<
2481 resets = <&bpmp TEGRA <<
2482 <&bpmp TEGRA <<
2483 reset-names = "apb", <<
2484 <<
2485 interrupts = <GIC_SPI <<
2486 <GIC_SPI <<
2487 interrupt-names = "in <<
2488 <<
2489 #interrupt-cells = <1 <<
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 <<
2493 nvidia,bpmp = <&bpmp <<
2494 <<
2495 nvidia,aspm-cmrt-us = <<
2496 nvidia,aspm-pwr-on-t- <<
2497 nvidia,aspm-l0s-entra <<
2498 <<
2499 bus-range = <0x0 0xff <<
2500 <<
2501 ranges = <0x43000000 <<
2502 <0x02000000 <<
2503 <0x01000000 <<
2504 <<
2505 interconnects = <&mc <<
2506 <&mc <<
2507 interconnect-names = <<
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 <<
2513 pcie@14160000 { <<
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 <<
2522 status = "disabled"; <<
2523 <<
2524 #address-cells = <3>; <<
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 <<
2530 clocks = <&bpmp TEGRA <<
2531 clock-names = "core"; <<
2532 <<
2533 resets = <&bpmp TEGRA <<
2534 <&bpmp TEGRA <<
2535 reset-names = "apb", <<
2536 <<
2537 interrupts = <GIC_SPI <<
2538 <GIC_SPI <<
2539 interrupt-names = "in <<
2540 <<
2541 #interrupt-cells = <1 <<
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 <<
2545 nvidia,bpmp = <&bpmp <<
2546 <<
2547 nvidia,aspm-cmrt-us = <<
2548 nvidia,aspm-pwr-on-t- <<
2549 nvidia,aspm-l0s-entra <<
2550 <<
2551 bus-range = <0x0 0xff <<
2552 <<
2553 ranges = <0x43000000 <<
2554 <0x02000000 <<
2555 <0x01000000 <<
2556 <<
2557 interconnects = <&mc <<
2558 <&mc <<
2559 interconnect-names = <<
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 <<
2565 pcie-ep@14160000 { <<
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 <<
2574 status = "disabled"; <<
2575 <<
2576 num-lanes = <4>; <<
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 <<
2580 clocks = <&bpmp TEGRA <<
2581 clock-names = "core"; <<
2582 <<
2583 resets = <&bpmp TEGRA <<
2584 <&bpmp TEGRA <<
2585 reset-names = "apb", <<
2586 <<
2587 interrupts = <GIC_SPI <<
2588 interrupt-names = "in <<
2589 <<
2590 nvidia,bpmp = <&bpmp <<
2591 <<
2592 nvidia,aspm-cmrt-us = <<
2593 nvidia,aspm-pwr-on-t- <<
2594 nvidia,aspm-l0s-entra <<
2595 <<
2596 interconnects = <&mc <<
2597 <&mc <<
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 <<
2604 pcie@14180000 { <<
2605 compatible = "nvidia, <<
2606 power-domains = <&bpm <<
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 <<
2613 status = "disabled"; <<
2614 <<
2615 #address-cells = <3>; <<
2616 #size-cells = <2>; <<
2617 device_type = "pci"; <<
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 <<
2621 clocks = <&bpmp TEGRA <<
2622 clock-names = "core"; <<
2623 <<
2624 resets = <&bpmp TEGRA <<
2625 <&bpmp TEGRA <<
2626 reset-names = "apb", <<
2627 <<
2628 interrupts = <GIC_SPI <<
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 <<
2632 #interrupt-cells = <1 <<
2633 interrupt-map-mask = <<
2634 interrupt-map = <0 0 <<
2635 <<
2636 nvidia,bpmp = <&bpmp <<
2637 <<
2638 nvidia,aspm-cmrt-us = <<
2639 nvidia,aspm-pwr-on-t- <<
2640 nvidia,aspm-l0s-entra <<
2641 <<
2642 bus-range = <0x0 0xff <<
2643 <<
2644 ranges = <0x43000000 <<
2645 <0x02000000 <<
2646 <0x01000000 <<
2647 <<
2648 interconnects = <&mc <<
2649 <&mc <<
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 <<
2656 pcie-ep@14180000 { <<
2657 compatible = "nvidia, <<
2658 power-domains = <&bpm <<
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 <<
2665 status = "disabled"; <<
2666 <<
2667 num-lanes = <8>; <<
2668 num-ib-windows = <2>; <<
2669 num-ob-windows = <8>; <<
2670 <<
2671 clocks = <&bpmp TEGRA <<
2672 clock-names = "core"; <<
2673 <<
2674 resets = <&bpmp TEGRA <<
2675 <&bpmp TEGRA <<
2676 reset-names = "apb", <<
2677 <<
2678 interrupts = <GIC_SPI <<
2679 interrupt-names = "in <<
2680 <<
2681 nvidia,bpmp = <&bpmp <<
2682 <<
2683 nvidia,aspm-cmrt-us = <<
2684 nvidia,aspm-pwr-on-t- <<
2685 nvidia,aspm-l0s-entra <<
2686 <<
2687 interconnects = <&mc <<
2688 <&mc <<
2689 interconnect-names = <<
2690 iommu-map = <0x0 &smm <<
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 <<
2695 pcie@141a0000 { <<
2696 compatible = "nvidia, <<
2697 power-domains = <&bpm <<
2698 reg = <0x00 0x141a000 <<
2699 <0x00 0x3a00000 <<
2700 <0x00 0x3a04000 <<
2701 <0x00 0x3a08000 <<
2702 reg-names = "appl", " <<
2703 <<
2704 status = "disabled"; <<
2705 <<
2706 #address-cells = <3>; <<
2707 #size-cells = <2>; <<
2708 device_type = "pci"; <<
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 <<
2712 pinctrl-names = "defa <<
2713 pinctrl-0 = <&pex_rst <<
2714 <<
2715 clocks = <&bpmp TEGRA <<
2716 clock-names = "core"; <<
2717 <<
2718 resets = <&bpmp TEGRA <<
2719 <&bpmp TEGRA <<
2720 reset-names = "apb", <<
2721 <<
2722 interrupts = <GIC_SPI <<
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 <<
2726 nvidia,bpmp = <&bpmp <<
2727 <<
2728 #interrupt-cells = <1 <<
2729 interrupt-map-mask = <<
2730 interrupt-map = <0 0 <<
2731 <<
2732 nvidia,aspm-cmrt-us = <<
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 <<
2736 bus-range = <0x0 0xff <<
2737 <<
2738 ranges = <0x43000000 <<
2739 <0x02000000 <<
2740 <0x01000000 <<
2741 <<
2742 interconnects = <&mc <<
2743 <&mc <<
2744 interconnect-names = <<
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 <<
2750 pcie-ep@141a0000 { <<
2751 compatible = "nvidia, <<
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 <<
2759 status = "disabled"; <<
2760 <<
2761 num-lanes = <8>; <<
2762 num-ib-windows = <2>; <<
2763 num-ob-windows = <8>; <<
2764 <<
2765 pinctrl-names = "defa <<
2766 pinctrl-0 = <&pex_clk <<
2767 <<
2768 clocks = <&bpmp TEGRA <<
2769 clock-names = "core"; <<
2770 <<
2771 resets = <&bpmp TEGRA <<
2772 <&bpmp TEGRA <<
2773 reset-names = "apb", <<
2774 <<
2775 interrupts = <GIC_SPI <<
2776 interrupt-names = "in <<
2777 <<
2778 nvidia,bpmp = <&bpmp <<
2779 <<
2780 nvidia,aspm-cmrt-us = <<
2781 nvidia,aspm-pwr-on-t- <<
2782 nvidia,aspm-l0s-entra <<
2783 <<
2784 interconnects = <&mc <<
2785 <&mc <<
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 <<
2792 gpu@17000000 { 1760 gpu@17000000 {
2793 compatible = "nvidia, 1761 compatible = "nvidia,gv11b";
2794 reg = <0x0 0x17000000 !! 1762 reg = <0x17000000 0x1000000>,
2795 <0x0 0x18000000 !! 1763 <0x18000000 0x1000000>;
2796 interrupts = <GIC_SPI 1764 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 1765 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2798 interrupt-names = "st 1766 interrupt-names = "stall", "nonstall";
2799 clocks = <&bpmp TEGRA 1767 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800 <&bpmp TEGRA 1768 <&bpmp TEGRA194_CLK_GPU_PWR>,
2801 <&bpmp TEGRA 1769 <&bpmp TEGRA194_CLK_FUSE>;
2802 clock-names = "gpu", 1770 clock-names = "gpu", "pwr", "fuse";
2803 resets = <&bpmp TEGRA 1771 resets = <&bpmp TEGRA194_RESET_GPU>;
2804 reset-names = "gpu"; 1772 reset-names = "gpu";
2805 dma-coherent; 1773 dma-coherent;
2806 1774
2807 power-domains = <&bpm 1775 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2808 interconnects = <&mc 1776 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2809 <&mc 1777 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2810 <&mc 1778 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2811 <&mc 1779 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2812 <&mc 1780 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2813 <&mc 1781 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2814 <&mc 1782 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2815 <&mc 1783 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2816 <&mc 1784 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2817 <&mc 1785 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2818 <&mc 1786 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2819 <&mc 1787 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2820 interconnect-names = 1788 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2821 1789 "read-1", "read-1-hp", "write-1",
2822 1790 "read-2", "read-2-hp", "write-2",
2823 1791 "read-3", "read-3-hp", "write-3";
2824 }; 1792 };
2825 }; 1793 };
2826 1794
>> 1795 pcie@14100000 {
>> 1796 compatible = "nvidia,tegra194-pcie";
>> 1797 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1798 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
>> 1799 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1800 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1801 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1802 reg-names = "appl", "config", "atu_dma", "dbi";
>> 1803
>> 1804 status = "disabled";
>> 1805
>> 1806 #address-cells = <3>;
>> 1807 #size-cells = <2>;
>> 1808 device_type = "pci";
>> 1809 num-lanes = <1>;
>> 1810 num-viewport = <8>;
>> 1811 linux,pci-domain = <1>;
>> 1812
>> 1813 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
>> 1814 clock-names = "core";
>> 1815
>> 1816 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 1817 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 1818 reset-names = "apb", "core";
>> 1819
>> 1820 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1821 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1822 interrupt-names = "intr", "msi";
>> 1823
>> 1824 #interrupt-cells = <1>;
>> 1825 interrupt-map-mask = <0 0 0 0>;
>> 1826 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 1827
>> 1828 nvidia,bpmp = <&bpmp 1>;
>> 1829
>> 1830 nvidia,aspm-cmrt-us = <60>;
>> 1831 nvidia,aspm-pwr-on-t-us = <20>;
>> 1832 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1833
>> 1834 bus-range = <0x0 0xff>;
>> 1835
>> 1836 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 1837 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1838 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 1839
>> 1840 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
>> 1841 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
>> 1842 interconnect-names = "dma-mem", "write";
>> 1843 iommus = <&smmu TEGRA194_SID_PCIE1>;
>> 1844 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
>> 1845 iommu-map-mask = <0x0>;
>> 1846 dma-coherent;
>> 1847 };
>> 1848
>> 1849 pcie@14120000 {
>> 1850 compatible = "nvidia,tegra194-pcie";
>> 1851 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1852 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
>> 1853 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1854 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1855 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1856 reg-names = "appl", "config", "atu_dma", "dbi";
>> 1857
>> 1858 status = "disabled";
>> 1859
>> 1860 #address-cells = <3>;
>> 1861 #size-cells = <2>;
>> 1862 device_type = "pci";
>> 1863 num-lanes = <1>;
>> 1864 num-viewport = <8>;
>> 1865 linux,pci-domain = <2>;
>> 1866
>> 1867 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
>> 1868 clock-names = "core";
>> 1869
>> 1870 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 1871 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 1872 reset-names = "apb", "core";
>> 1873
>> 1874 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1875 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1876 interrupt-names = "intr", "msi";
>> 1877
>> 1878 #interrupt-cells = <1>;
>> 1879 interrupt-map-mask = <0 0 0 0>;
>> 1880 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 1881
>> 1882 nvidia,bpmp = <&bpmp 2>;
>> 1883
>> 1884 nvidia,aspm-cmrt-us = <60>;
>> 1885 nvidia,aspm-pwr-on-t-us = <20>;
>> 1886 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1887
>> 1888 bus-range = <0x0 0xff>;
>> 1889
>> 1890 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 1891 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 1892 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 1893
>> 1894 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
>> 1895 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
>> 1896 interconnect-names = "dma-mem", "write";
>> 1897 iommus = <&smmu TEGRA194_SID_PCIE2>;
>> 1898 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
>> 1899 iommu-map-mask = <0x0>;
>> 1900 dma-coherent;
>> 1901 };
>> 1902
>> 1903 pcie@14140000 {
>> 1904 compatible = "nvidia,tegra194-pcie";
>> 1905 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1906 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
>> 1907 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1908 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1909 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1910 reg-names = "appl", "config", "atu_dma", "dbi";
>> 1911
>> 1912 status = "disabled";
>> 1913
>> 1914 #address-cells = <3>;
>> 1915 #size-cells = <2>;
>> 1916 device_type = "pci";
>> 1917 num-lanes = <1>;
>> 1918 num-viewport = <8>;
>> 1919 linux,pci-domain = <3>;
>> 1920
>> 1921 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
>> 1922 clock-names = "core";
>> 1923
>> 1924 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 1925 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 1926 reset-names = "apb", "core";
>> 1927
>> 1928 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1929 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1930 interrupt-names = "intr", "msi";
>> 1931
>> 1932 #interrupt-cells = <1>;
>> 1933 interrupt-map-mask = <0 0 0 0>;
>> 1934 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>> 1935
>> 1936 nvidia,bpmp = <&bpmp 3>;
>> 1937
>> 1938 nvidia,aspm-cmrt-us = <60>;
>> 1939 nvidia,aspm-pwr-on-t-us = <20>;
>> 1940 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1941
>> 1942 bus-range = <0x0 0xff>;
>> 1943
>> 1944 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 1945 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
>> 1946 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 1947
>> 1948 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
>> 1949 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
>> 1950 interconnect-names = "dma-mem", "write";
>> 1951 iommus = <&smmu TEGRA194_SID_PCIE3>;
>> 1952 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
>> 1953 iommu-map-mask = <0x0>;
>> 1954 dma-coherent;
>> 1955 };
>> 1956
>> 1957 pcie@14160000 {
>> 1958 compatible = "nvidia,tegra194-pcie";
>> 1959 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 1960 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 1961 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
>> 1962 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 1963 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1964 reg-names = "appl", "config", "atu_dma", "dbi";
>> 1965
>> 1966 status = "disabled";
>> 1967
>> 1968 #address-cells = <3>;
>> 1969 #size-cells = <2>;
>> 1970 device_type = "pci";
>> 1971 num-lanes = <4>;
>> 1972 num-viewport = <8>;
>> 1973 linux,pci-domain = <4>;
>> 1974
>> 1975 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 1976 clock-names = "core";
>> 1977
>> 1978 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 1979 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1980 reset-names = "apb", "core";
>> 1981
>> 1982 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1983 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1984 interrupt-names = "intr", "msi";
>> 1985
>> 1986 #interrupt-cells = <1>;
>> 1987 interrupt-map-mask = <0 0 0 0>;
>> 1988 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 1989
>> 1990 nvidia,bpmp = <&bpmp 4>;
>> 1991
>> 1992 nvidia,aspm-cmrt-us = <60>;
>> 1993 nvidia,aspm-pwr-on-t-us = <20>;
>> 1994 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1995
>> 1996 bus-range = <0x0 0xff>;
>> 1997
>> 1998 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 1999 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2000 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2001
>> 2002 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2003 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2004 interconnect-names = "dma-mem", "write";
>> 2005 iommus = <&smmu TEGRA194_SID_PCIE4>;
>> 2006 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2007 iommu-map-mask = <0x0>;
>> 2008 dma-coherent;
>> 2009 };
>> 2010
>> 2011 pcie@14180000 {
>> 2012 compatible = "nvidia,tegra194-pcie";
>> 2013 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2014 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2015 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2016 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2017 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2018 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2019
>> 2020 status = "disabled";
>> 2021
>> 2022 #address-cells = <3>;
>> 2023 #size-cells = <2>;
>> 2024 device_type = "pci";
>> 2025 num-lanes = <8>;
>> 2026 num-viewport = <8>;
>> 2027 linux,pci-domain = <0>;
>> 2028
>> 2029 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2030 clock-names = "core";
>> 2031
>> 2032 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2033 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2034 reset-names = "apb", "core";
>> 2035
>> 2036 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2037 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2038 interrupt-names = "intr", "msi";
>> 2039
>> 2040 #interrupt-cells = <1>;
>> 2041 interrupt-map-mask = <0 0 0 0>;
>> 2042 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 2043
>> 2044 nvidia,bpmp = <&bpmp 0>;
>> 2045
>> 2046 nvidia,aspm-cmrt-us = <60>;
>> 2047 nvidia,aspm-pwr-on-t-us = <20>;
>> 2048 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2049
>> 2050 bus-range = <0x0 0xff>;
>> 2051
>> 2052 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2053 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2054 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2055
>> 2056 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2057 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2058 interconnect-names = "dma-mem", "write";
>> 2059 iommus = <&smmu TEGRA194_SID_PCIE0>;
>> 2060 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2061 iommu-map-mask = <0x0>;
>> 2062 dma-coherent;
>> 2063 };
>> 2064
>> 2065 pcie@141a0000 {
>> 2066 compatible = "nvidia,tegra194-pcie";
>> 2067 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2068 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2069 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2070 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2071 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2072 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2073
>> 2074 status = "disabled";
>> 2075
>> 2076 #address-cells = <3>;
>> 2077 #size-cells = <2>;
>> 2078 device_type = "pci";
>> 2079 num-lanes = <8>;
>> 2080 num-viewport = <8>;
>> 2081 linux,pci-domain = <5>;
>> 2082
>> 2083 pinctrl-names = "default";
>> 2084 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> 2085
>> 2086 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
>> 2087 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
>> 2088 clock-names = "core", "core_m";
>> 2089
>> 2090 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2091 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2092 reset-names = "apb", "core";
>> 2093
>> 2094 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2095 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2096 interrupt-names = "intr", "msi";
>> 2097
>> 2098 nvidia,bpmp = <&bpmp 5>;
>> 2099
>> 2100 #interrupt-cells = <1>;
>> 2101 interrupt-map-mask = <0 0 0 0>;
>> 2102 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
>> 2103
>> 2104 nvidia,aspm-cmrt-us = <60>;
>> 2105 nvidia,aspm-pwr-on-t-us = <20>;
>> 2106 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2107
>> 2108 bus-range = <0x0 0xff>;
>> 2109
>> 2110 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2111 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2112 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2113
>> 2114 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2115 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2116 interconnect-names = "dma-mem", "write";
>> 2117 iommus = <&smmu TEGRA194_SID_PCIE5>;
>> 2118 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2119 iommu-map-mask = <0x0>;
>> 2120 dma-coherent;
>> 2121 };
>> 2122
>> 2123 pcie_ep@14160000 {
>> 2124 compatible = "nvidia,tegra194-pcie-ep";
>> 2125 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 2126 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 2127 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2128 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2129 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2130 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2131
>> 2132 status = "disabled";
>> 2133
>> 2134 num-lanes = <4>;
>> 2135 num-ib-windows = <2>;
>> 2136 num-ob-windows = <8>;
>> 2137
>> 2138 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 2139 clock-names = "core";
>> 2140
>> 2141 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 2142 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2143 reset-names = "apb", "core";
>> 2144
>> 2145 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2146 interrupt-names = "intr";
>> 2147
>> 2148 nvidia,bpmp = <&bpmp 4>;
>> 2149
>> 2150 nvidia,aspm-cmrt-us = <60>;
>> 2151 nvidia,aspm-pwr-on-t-us = <20>;
>> 2152 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2153
>> 2154 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2155 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2156 interconnect-names = "dma-mem", "write";
>> 2157 iommus = <&smmu TEGRA194_SID_PCIE4>;
>> 2158 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2159 iommu-map-mask = <0x0>;
>> 2160 dma-coherent;
>> 2161 };
>> 2162
>> 2163 pcie_ep@14180000 {
>> 2164 compatible = "nvidia,tegra194-pcie-ep";
>> 2165 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2166 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2167 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2168 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2169 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2170 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2171
>> 2172 status = "disabled";
>> 2173
>> 2174 num-lanes = <8>;
>> 2175 num-ib-windows = <2>;
>> 2176 num-ob-windows = <8>;
>> 2177
>> 2178 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2179 clock-names = "core";
>> 2180
>> 2181 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2182 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2183 reset-names = "apb", "core";
>> 2184
>> 2185 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2186 interrupt-names = "intr";
>> 2187
>> 2188 nvidia,bpmp = <&bpmp 0>;
>> 2189
>> 2190 nvidia,aspm-cmrt-us = <60>;
>> 2191 nvidia,aspm-pwr-on-t-us = <20>;
>> 2192 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2193
>> 2194 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2195 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2196 interconnect-names = "dma-mem", "write";
>> 2197 iommus = <&smmu TEGRA194_SID_PCIE0>;
>> 2198 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2199 iommu-map-mask = <0x0>;
>> 2200 dma-coherent;
>> 2201 };
>> 2202
>> 2203 pcie_ep@141a0000 {
>> 2204 compatible = "nvidia,tegra194-pcie-ep";
>> 2205 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2206 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2207 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2208 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2209 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2210 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2211
>> 2212 status = "disabled";
>> 2213
>> 2214 num-lanes = <8>;
>> 2215 num-ib-windows = <2>;
>> 2216 num-ob-windows = <8>;
>> 2217
>> 2218 pinctrl-names = "default";
>> 2219 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> 2220
>> 2221 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2222 clock-names = "core";
>> 2223
>> 2224 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2225 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2226 reset-names = "apb", "core";
>> 2227
>> 2228 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2229 interrupt-names = "intr";
>> 2230
>> 2231 nvidia,bpmp = <&bpmp 5>;
>> 2232
>> 2233 nvidia,aspm-cmrt-us = <60>;
>> 2234 nvidia,aspm-pwr-on-t-us = <20>;
>> 2235 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2236
>> 2237 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2238 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2239 interconnect-names = "dma-mem", "write";
>> 2240 iommus = <&smmu TEGRA194_SID_PCIE5>;
>> 2241 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2242 iommu-map-mask = <0x0>;
>> 2243 dma-coherent;
>> 2244 };
>> 2245
2827 sram@40000000 { 2246 sram@40000000 {
2828 compatible = "nvidia,tegra194 2247 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 2248 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 2249 #address-cells = <1>;
2832 #size-cells = <1>; 2250 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 2251 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 <<
2835 no-memory-wc; 2252 no-memory-wc;
2836 2253
2837 cpu_bpmp_tx: sram@4e000 { 2254 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000 2255 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 2256 label = "cpu-bpmp-tx";
2840 pool; 2257 pool;
2841 }; 2258 };
2842 2259
2843 cpu_bpmp_rx: sram@4f000 { 2260 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000 2261 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 2262 label = "cpu-bpmp-rx";
2846 pool; 2263 pool;
2847 }; 2264 };
2848 }; 2265 };
2849 2266
2850 bpmp: bpmp { 2267 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 2268 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 2269 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 2270 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu 2271 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2855 #clock-cells = <1>; 2272 #clock-cells = <1>;
2856 #reset-cells = <1>; 2273 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 2274 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 2275 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859 <&mc TEGRA194 2276 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860 <&mc TEGRA194 2277 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861 <&mc TEGRA194 2278 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862 interconnect-names = "read", 2279 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863 iommus = <&smmu TEGRA194_SID_ 2280 iommus = <&smmu TEGRA194_SID_BPMP>;
2864 2281
2865 bpmp_i2c: i2c { 2282 bpmp_i2c: i2c {
2866 compatible = "nvidia, 2283 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 2284 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 2285 #address-cells = <1>;
2869 #size-cells = <0>; 2286 #size-cells = <0>;
2870 }; 2287 };
2871 2288
2872 bpmp_thermal: thermal { 2289 bpmp_thermal: thermal {
2873 compatible = "nvidia, 2290 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 2291 #thermal-sensor-cells = <1>;
2875 }; 2292 };
2876 }; 2293 };
2877 2294
2878 cpus { 2295 cpus {
2879 compatible = "nvidia,tegra194 2296 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>; 2297 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>; 2298 #address-cells = <1>;
2882 #size-cells = <0>; 2299 #size-cells = <0>;
2883 2300
2884 cpu0_0: cpu@0 { 2301 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 2302 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 2303 device_type = "cpu";
2887 reg = <0x000>; 2304 reg = <0x000>;
2888 enable-method = "psci 2305 enable-method = "psci";
2889 i-cache-size = <13107 2306 i-cache-size = <131072>;
2890 i-cache-line-size = < 2307 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 2308 i-cache-sets = <512>;
2892 d-cache-size = <65536 2309 d-cache-size = <65536>;
2893 d-cache-line-size = < 2310 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 2311 d-cache-sets = <256>;
2895 next-level-cache = <& 2312 next-level-cache = <&l2c_0>;
2896 }; 2313 };
2897 2314
2898 cpu0_1: cpu@1 { 2315 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 2316 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 2317 device_type = "cpu";
2901 reg = <0x001>; 2318 reg = <0x001>;
2902 enable-method = "psci 2319 enable-method = "psci";
2903 i-cache-size = <13107 2320 i-cache-size = <131072>;
2904 i-cache-line-size = < 2321 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 2322 i-cache-sets = <512>;
2906 d-cache-size = <65536 2323 d-cache-size = <65536>;
2907 d-cache-line-size = < 2324 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 2325 d-cache-sets = <256>;
2909 next-level-cache = <& 2326 next-level-cache = <&l2c_0>;
2910 }; 2327 };
2911 2328
2912 cpu1_0: cpu@100 { 2329 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 2330 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 2331 device_type = "cpu";
2915 reg = <0x100>; 2332 reg = <0x100>;
2916 enable-method = "psci 2333 enable-method = "psci";
2917 i-cache-size = <13107 2334 i-cache-size = <131072>;
2918 i-cache-line-size = < 2335 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 2336 i-cache-sets = <512>;
2920 d-cache-size = <65536 2337 d-cache-size = <65536>;
2921 d-cache-line-size = < 2338 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 2339 d-cache-sets = <256>;
2923 next-level-cache = <& 2340 next-level-cache = <&l2c_1>;
2924 }; 2341 };
2925 2342
2926 cpu1_1: cpu@101 { 2343 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 2344 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 2345 device_type = "cpu";
2929 reg = <0x101>; 2346 reg = <0x101>;
2930 enable-method = "psci 2347 enable-method = "psci";
2931 i-cache-size = <13107 2348 i-cache-size = <131072>;
2932 i-cache-line-size = < 2349 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 2350 i-cache-sets = <512>;
2934 d-cache-size = <65536 2351 d-cache-size = <65536>;
2935 d-cache-line-size = < 2352 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 2353 d-cache-sets = <256>;
2937 next-level-cache = <& 2354 next-level-cache = <&l2c_1>;
2938 }; 2355 };
2939 2356
2940 cpu2_0: cpu@200 { 2357 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 2358 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 2359 device_type = "cpu";
2943 reg = <0x200>; 2360 reg = <0x200>;
2944 enable-method = "psci 2361 enable-method = "psci";
2945 i-cache-size = <13107 2362 i-cache-size = <131072>;
2946 i-cache-line-size = < 2363 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 2364 i-cache-sets = <512>;
2948 d-cache-size = <65536 2365 d-cache-size = <65536>;
2949 d-cache-line-size = < 2366 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 2367 d-cache-sets = <256>;
2951 next-level-cache = <& 2368 next-level-cache = <&l2c_2>;
2952 }; 2369 };
2953 2370
2954 cpu2_1: cpu@201 { 2371 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 2372 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 2373 device_type = "cpu";
2957 reg = <0x201>; 2374 reg = <0x201>;
2958 enable-method = "psci 2375 enable-method = "psci";
2959 i-cache-size = <13107 2376 i-cache-size = <131072>;
2960 i-cache-line-size = < 2377 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 2378 i-cache-sets = <512>;
2962 d-cache-size = <65536 2379 d-cache-size = <65536>;
2963 d-cache-line-size = < 2380 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 2381 d-cache-sets = <256>;
2965 next-level-cache = <& 2382 next-level-cache = <&l2c_2>;
2966 }; 2383 };
2967 2384
2968 cpu3_0: cpu@300 { 2385 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 2386 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 2387 device_type = "cpu";
2971 reg = <0x300>; 2388 reg = <0x300>;
2972 enable-method = "psci 2389 enable-method = "psci";
2973 i-cache-size = <13107 2390 i-cache-size = <131072>;
2974 i-cache-line-size = < 2391 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 2392 i-cache-sets = <512>;
2976 d-cache-size = <65536 2393 d-cache-size = <65536>;
2977 d-cache-line-size = < 2394 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 2395 d-cache-sets = <256>;
2979 next-level-cache = <& 2396 next-level-cache = <&l2c_3>;
2980 }; 2397 };
2981 2398
2982 cpu3_1: cpu@301 { 2399 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 2400 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 2401 device_type = "cpu";
2985 reg = <0x301>; 2402 reg = <0x301>;
2986 enable-method = "psci 2403 enable-method = "psci";
2987 i-cache-size = <13107 2404 i-cache-size = <131072>;
2988 i-cache-line-size = < 2405 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 2406 i-cache-sets = <512>;
2990 d-cache-size = <65536 2407 d-cache-size = <65536>;
2991 d-cache-line-size = < 2408 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 2409 d-cache-sets = <256>;
2993 next-level-cache = <& 2410 next-level-cache = <&l2c_3>;
2994 }; 2411 };
2995 2412
2996 cpu-map { 2413 cpu-map {
2997 cluster0 { 2414 cluster0 {
2998 core0 { 2415 core0 {
2999 cpu = 2416 cpu = <&cpu0_0>;
3000 }; 2417 };
3001 2418
3002 core1 { 2419 core1 {
3003 cpu = 2420 cpu = <&cpu0_1>;
3004 }; 2421 };
3005 }; 2422 };
3006 2423
3007 cluster1 { 2424 cluster1 {
3008 core0 { 2425 core0 {
3009 cpu = 2426 cpu = <&cpu1_0>;
3010 }; 2427 };
3011 2428
3012 core1 { 2429 core1 {
3013 cpu = 2430 cpu = <&cpu1_1>;
3014 }; 2431 };
3015 }; 2432 };
3016 2433
3017 cluster2 { 2434 cluster2 {
3018 core0 { 2435 core0 {
3019 cpu = 2436 cpu = <&cpu2_0>;
3020 }; 2437 };
3021 2438
3022 core1 { 2439 core1 {
3023 cpu = 2440 cpu = <&cpu2_1>;
3024 }; 2441 };
3025 }; 2442 };
3026 2443
3027 cluster3 { 2444 cluster3 {
3028 core0 { 2445 core0 {
3029 cpu = 2446 cpu = <&cpu3_0>;
3030 }; 2447 };
3031 2448
3032 core1 { 2449 core1 {
3033 cpu = 2450 cpu = <&cpu3_1>;
3034 }; 2451 };
3035 }; 2452 };
3036 }; 2453 };
3037 2454
3038 l2c_0: l2-cache0 { 2455 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 2456 cache-size = <2097152>;
3042 cache-line-size = <64 2457 cache-line-size = <64>;
3043 cache-sets = <2048>; 2458 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 2459 next-level-cache = <&l3c>;
3046 }; 2460 };
3047 2461
3048 l2c_1: l2-cache1 { 2462 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 2463 cache-size = <2097152>;
3052 cache-line-size = <64 2464 cache-line-size = <64>;
3053 cache-sets = <2048>; 2465 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 2466 next-level-cache = <&l3c>;
3056 }; 2467 };
3057 2468
3058 l2c_2: l2-cache2 { 2469 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 2470 cache-size = <2097152>;
3062 cache-line-size = <64 2471 cache-line-size = <64>;
3063 cache-sets = <2048>; 2472 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 2473 next-level-cache = <&l3c>;
3066 }; 2474 };
3067 2475
3068 l2c_3: l2-cache3 { 2476 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 2477 cache-size = <2097152>;
3072 cache-line-size = <64 2478 cache-line-size = <64>;
3073 cache-sets = <2048>; 2479 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 2480 next-level-cache = <&l3c>;
3076 }; 2481 };
3077 2482
3078 l3c: l3-cache { 2483 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 2484 cache-size = <4194304>;
3082 cache-line-size = <64 2485 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 2486 cache-sets = <4096>;
3085 }; 2487 };
3086 }; 2488 };
3087 2489
3088 pmu { 2490 pmu {
3089 compatible = "nvidia,carmel-p !! 2491 compatible = "arm,armv8-pmuv3";
3090 interrupts = <GIC_SPI 384 IRQ 2492 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 385 IRQ 2493 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 386 IRQ 2494 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 387 IRQ 2495 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 388 IRQ 2496 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 389 IRQ 2497 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 390 IRQ 2498 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 391 IRQ 2499 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3098 interrupt-affinity = <&cpu0_0 2500 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3099 &cpu2_0 2501 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3100 }; 2502 };
3101 2503
3102 psci { 2504 psci {
3103 compatible = "arm,psci-1.0"; 2505 compatible = "arm,psci-1.0";
3104 status = "okay"; 2506 status = "okay";
3105 method = "smc"; 2507 method = "smc";
3106 }; 2508 };
3107 2509
3108 tcu: serial { <<
3109 compatible = "nvidia,tegra194 <<
3110 mboxes = <&hsp_top0 TEGRA_HSP <<
3111 <&hsp_aon TEGRA_HSP_ <<
3112 mbox-names = "rx", "tx"; <<
3113 }; <<
3114 <<
3115 sound { 2510 sound {
3116 status = "disabled"; 2511 status = "disabled";
3117 2512
3118 clocks = <&bpmp TEGRA194_CLK_ 2513 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_ 2514 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120 clock-names = "pll_a", "plla_ 2515 clock-names = "pll_a", "plla_out0";
3121 assigned-clocks = <&bpmp TEGR 2516 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGR 2517 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGR 2518 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124 assigned-clock-parents = <0>, 2519 assigned-clock-parents = <0>,
3125 <&bp 2520 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bp 2521 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3127 /* 2522 /*
3128 * PLLA supports dynamic ramp 2523 * PLLA supports dynamic ramp. Below initial rate is chosen
3129 * for this to work and oscil 2524 * for this to work and oscillate between base rates required
3130 * for 8x and 11.025x sample 2525 * for 8x and 11.025x sample rate streams.
3131 */ 2526 */
3132 assigned-clock-rates = <25800 2527 assigned-clock-rates = <258000000>;
>> 2528
>> 2529 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
>> 2530 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
>> 2531 interconnect-names = "dma-mem", "write";
>> 2532 iommus = <&smmu TEGRA194_SID_APE>;
>> 2533 };
>> 2534
>> 2535 tcu: tcu {
>> 2536 compatible = "nvidia,tegra194-tcu";
>> 2537 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
>> 2538 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
>> 2539 mbox-names = "rx", "tx";
3133 }; 2540 };
3134 2541
3135 thermal-zones { 2542 thermal-zones {
3136 cpu-thermal { !! 2543 cpu {
3137 thermal-sensors = <&{ !! 2544 thermal-sensors = <&{/bpmp/thermal}
>> 2545 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 2546 status = "disabled";
3139 }; 2547 };
3140 2548
3141 gpu-thermal { !! 2549 gpu {
3142 thermal-sensors = <&{ !! 2550 thermal-sensors = <&{/bpmp/thermal}
>> 2551 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 2552 status = "disabled";
3144 }; 2553 };
3145 2554
3146 aux-thermal { !! 2555 aux {
3147 thermal-sensors = <&{ !! 2556 thermal-sensors = <&{/bpmp/thermal}
>> 2557 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 2558 status = "disabled";
3149 }; 2559 };
3150 2560
3151 pllx-thermal { !! 2561 pllx {
3152 thermal-sensors = <&{ !! 2562 thermal-sensors = <&{/bpmp/thermal}
>> 2563 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 2564 status = "disabled";
3154 }; 2565 };
3155 2566
3156 ao-thermal { !! 2567 ao {
3157 thermal-sensors = <&{ !! 2568 thermal-sensors = <&{/bpmp/thermal}
>> 2569 TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 2570 status = "disabled";
3159 }; 2571 };
3160 2572
3161 tj-thermal { !! 2573 tj {
3162 thermal-sensors = <&{ !! 2574 thermal-sensors = <&{/bpmp/thermal}
>> 2575 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 2576 status = "disabled";
3164 }; 2577 };
3165 }; 2578 };
3166 2579
3167 timer { 2580 timer {
3168 compatible = "arm,armv8-timer 2581 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 2582 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 2583 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 2584 <GIC_PPI 14
3172 (GIC_CPU_MASK 2585 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 2586 <GIC_PPI 11
3174 (GIC_CPU_MASK 2587 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 2588 <GIC_PPI 10
3176 (GIC_CPU_MASK 2589 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 2590 interrupt-parent = <&gic>;
3178 always-on; 2591 always-on;
3179 }; 2592 };
3180 }; 2593 };
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