1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 11 #include <dt-bindings/memory/tegra194-mc.h>
12 12
13 / { 13 / {
14 compatible = "nvidia,tegra194"; 14 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 /* control backbone */ 19 /* control backbone */
20 bus@0 { 20 bus@0 {
21 compatible = "simple-bus"; 21 compatible = "simple-bus";
>> 22 #address-cells = <1>;
>> 23 #size-cells = <1>;
>> 24 ranges = <0x0 0x0 0x0 0x40000000>;
22 25
23 #address-cells = <2>; !! 26 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 27 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 28 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 29 <0x0010f000 0x1000>;
31 }; 30 };
32 31
33 gpio: gpio@2200000 { 32 gpio: gpio@2200000 {
34 compatible = "nvidia,t 33 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 34 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 35 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 36 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
86 #interrupt-cells = <2> 85 #interrupt-cells = <2>;
87 interrupt-controller; 86 interrupt-controller;
88 #gpio-cells = <2>; 87 #gpio-cells = <2>;
89 gpio-controller; 88 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 89 };
141 90
142 ethernet@2490000 { 91 ethernet@2490000 {
143 compatible = "nvidia,t 92 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 93 "nvidia,tegra186-eqos",
145 "snps,dwc 94 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 95 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 98 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 99 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 100 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 103 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 104 reset-names = "eqos";
156 interconnects = <&mc T 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
157 <&mc T 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
158 interconnect-names = " 107 interconnect-names = "dma-mem", "write";
159 iommus = <&smmu TEGRA1 108 iommus = <&smmu TEGRA194_SID_EQOS>;
160 status = "disabled"; 109 status = "disabled";
161 110
162 snps,write-requests = 111 snps,write-requests = <1>;
163 snps,read-requests = < 112 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 113 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 114 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 115 snps,rxpbl = <8>;
167 }; 116 };
168 117
169 gpcdma: dma-controller@2600000 118 gpcdma: dma-controller@2600000 {
170 compatible = "nvidia,t 119 compatible = "nvidia,tegra194-gpcdma",
171 "nvidia,t 120 "nvidia,tegra186-gpcdma";
172 reg = <0x0 0x2600000 0 !! 121 reg = <0x2600000 0x210000>;
173 resets = <&bpmp TEGRA1 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
174 reset-names = "gpcdma" 123 reset-names = "gpcdma";
175 interrupts = <GIC_SPI !! 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI <<
177 <GIC_SPI 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
207 #dma-cells = <1>; 155 #dma-cells = <1>;
208 iommus = <&smmu TEGRA1 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
209 dma-coherent; 157 dma-coherent;
210 dma-channel-mask = <0x <<
211 status = "okay"; 158 status = "okay";
212 }; 159 };
213 160
214 aconnect@2900000 { 161 aconnect@2900000 {
215 compatible = "nvidia,t 162 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 163 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 164 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 165 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 166 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 168 #address-cells = <1>;
>> 169 #size-cells = <1>;
>> 170 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 171 status = "disabled";
222 172
223 #address-cells = <2>; !! 173 adma: dma-controller@2930000 {
224 #size-cells = <2>; !! 174 compatible = "nvidia,tegra194-adma",
225 ranges = <0x0 0x029000 !! 175 "nvidia,tegra186-adma";
>> 176 reg = <0x02930000 0x20000>;
>> 177 interrupt-parent = <&agic>;
>> 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 210 #dma-cells = <1>;
>> 211 clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> 212 clock-names = "d_audio";
>> 213 status = "disabled";
>> 214 };
>> 215
>> 216 agic: interrupt-controller@2a40000 {
>> 217 compatible = "nvidia,tegra194-agic",
>> 218 "nvidia,tegra210-agic";
>> 219 #interrupt-cells = <3>;
>> 220 interrupt-controller;
>> 221 reg = <0x02a41000 0x1000>,
>> 222 <0x02a42000 0x2000>;
>> 223 interrupts = <GIC_SPI 145
>> 224 (GIC_CPU_MASK_SIMPLE(4) |
>> 225 IRQ_TYPE_LEVEL_HIGH)>;
>> 226 clocks = <&bpmp TEGRA194_CLK_APE>;
>> 227 clock-names = "clk";
>> 228 status = "disabled";
>> 229 };
226 230
227 tegra_ahub: ahub@29008 231 tegra_ahub: ahub@2900800 {
228 compatible = " 232 compatible = "nvidia,tegra194-ahub",
229 " 233 "nvidia,tegra186-ahub";
230 reg = <0x0 0x0 !! 234 reg = <0x02900800 0x800>;
231 clocks = <&bpm 235 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = 236 clock-names = "ahub";
233 assigned-clock 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock !! 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
235 assigned-clock !! 239 #address-cells = <1>;
>> 240 #size-cells = <1>;
>> 241 ranges = <0x02900800 0x02900800 0x11800>;
236 status = "disa 242 status = "disabled";
237 243
238 #address-cells !! 244 tegra_admaif: admaif@290f000 {
239 #size-cells = !! 245 compatible = "nvidia,tegra194-admaif",
240 ranges = <0x0 !! 246 "nvidia,tegra186-admaif";
>> 247 reg = <0x0290f000 0x1000>;
>> 248 dmas = <&adma 1>, <&adma 1>,
>> 249 <&adma 2>, <&adma 2>,
>> 250 <&adma 3>, <&adma 3>,
>> 251 <&adma 4>, <&adma 4>,
>> 252 <&adma 5>, <&adma 5>,
>> 253 <&adma 6>, <&adma 6>,
>> 254 <&adma 7>, <&adma 7>,
>> 255 <&adma 8>, <&adma 8>,
>> 256 <&adma 9>, <&adma 9>,
>> 257 <&adma 10>, <&adma 10>,
>> 258 <&adma 11>, <&adma 11>,
>> 259 <&adma 12>, <&adma 12>,
>> 260 <&adma 13>, <&adma 13>,
>> 261 <&adma 14>, <&adma 14>,
>> 262 <&adma 15>, <&adma 15>,
>> 263 <&adma 16>, <&adma 16>,
>> 264 <&adma 17>, <&adma 17>,
>> 265 <&adma 18>, <&adma 18>,
>> 266 <&adma 19>, <&adma 19>,
>> 267 <&adma 20>, <&adma 20>;
>> 268 dma-names = "rx1", "tx1",
>> 269 "rx2", "tx2",
>> 270 "rx3", "tx3",
>> 271 "rx4", "tx4",
>> 272 "rx5", "tx5",
>> 273 "rx6", "tx6",
>> 274 "rx7", "tx7",
>> 275 "rx8", "tx8",
>> 276 "rx9", "tx9",
>> 277 "rx10", "tx10",
>> 278 "rx11", "tx11",
>> 279 "rx12", "tx12",
>> 280 "rx13", "tx13",
>> 281 "rx14", "tx14",
>> 282 "rx15", "tx15",
>> 283 "rx16", "tx16",
>> 284 "rx17", "tx17",
>> 285 "rx18", "tx18",
>> 286 "rx19", "tx19",
>> 287 "rx20", "tx20";
>> 288 status = "disabled";
>> 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
>> 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
>> 291 interconnect-names = "dma-mem", "write";
>> 292 iommus = <&smmu TEGRA194_SID_APE>;
>> 293 };
241 294
242 tegra_i2s1: i2 295 tegra_i2s1: i2s@2901000 {
243 compat 296 compatible = "nvidia,tegra194-i2s",
244 297 "nvidia,tegra210-i2s";
245 reg = !! 298 reg = <0x2901000 0x100>;
246 clocks 299 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock- 301 clock-names = "i2s", "sync_input";
249 assign 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assign 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assign 304 assigned-clock-rates = <1536000>;
252 sound- 305 sound-name-prefix = "I2S1";
253 status 306 status = "disabled";
254 }; 307 };
255 308
256 tegra_i2s2: i2 309 tegra_i2s2: i2s@2901100 {
257 compat 310 compatible = "nvidia,tegra194-i2s",
258 311 "nvidia,tegra210-i2s";
259 reg = !! 312 reg = <0x2901100 0x100>;
260 clocks 313 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock- 315 clock-names = "i2s", "sync_input";
263 assign 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assign 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assign 318 assigned-clock-rates = <1536000>;
266 sound- 319 sound-name-prefix = "I2S2";
267 status 320 status = "disabled";
268 }; 321 };
269 322
270 tegra_i2s3: i2 323 tegra_i2s3: i2s@2901200 {
271 compat 324 compatible = "nvidia,tegra194-i2s",
272 325 "nvidia,tegra210-i2s";
273 reg = !! 326 reg = <0x2901200 0x100>;
274 clocks 327 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock- 329 clock-names = "i2s", "sync_input";
277 assign 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assign 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assign 332 assigned-clock-rates = <1536000>;
280 sound- 333 sound-name-prefix = "I2S3";
281 status 334 status = "disabled";
282 }; 335 };
283 336
284 tegra_i2s4: i2 337 tegra_i2s4: i2s@2901300 {
285 compat 338 compatible = "nvidia,tegra194-i2s",
286 339 "nvidia,tegra210-i2s";
287 reg = !! 340 reg = <0x2901300 0x100>;
288 clocks 341 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock- 343 clock-names = "i2s", "sync_input";
291 assign 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assign 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assign 346 assigned-clock-rates = <1536000>;
294 sound- 347 sound-name-prefix = "I2S4";
295 status 348 status = "disabled";
296 }; 349 };
297 350
298 tegra_i2s5: i2 351 tegra_i2s5: i2s@2901400 {
299 compat 352 compatible = "nvidia,tegra194-i2s",
300 353 "nvidia,tegra210-i2s";
301 reg = !! 354 reg = <0x2901400 0x100>;
302 clocks 355 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock- 357 clock-names = "i2s", "sync_input";
305 assign 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assign 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assign 360 assigned-clock-rates = <1536000>;
308 sound- 361 sound-name-prefix = "I2S5";
309 status 362 status = "disabled";
310 }; 363 };
311 364
312 tegra_i2s6: i2 365 tegra_i2s6: i2s@2901500 {
313 compat 366 compatible = "nvidia,tegra194-i2s",
314 367 "nvidia,tegra210-i2s";
315 reg = !! 368 reg = <0x2901500 0x100>;
316 clocks 369 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock- 371 clock-names = "i2s", "sync_input";
319 assign 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assign 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assign 374 assigned-clock-rates = <1536000>;
322 sound- 375 sound-name-prefix = "I2S6";
323 status 376 status = "disabled";
324 }; 377 };
325 378
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d 379 tegra_dmic1: dmic@2904000 {
419 compat 380 compatible = "nvidia,tegra194-dmic",
420 381 "nvidia,tegra210-dmic";
421 reg = !! 382 reg = <0x2904000 0x100>;
422 clocks 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock- 384 clock-names = "dmic";
424 assign 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assign 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assign 387 assigned-clock-rates = <3072000>;
427 sound- 388 sound-name-prefix = "DMIC1";
428 status 389 status = "disabled";
429 }; 390 };
430 391
431 tegra_dmic2: d 392 tegra_dmic2: dmic@2904100 {
432 compat 393 compatible = "nvidia,tegra194-dmic",
433 394 "nvidia,tegra210-dmic";
434 reg = !! 395 reg = <0x2904100 0x100>;
435 clocks 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock- 397 clock-names = "dmic";
437 assign 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assign 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assign 400 assigned-clock-rates = <3072000>;
440 sound- 401 sound-name-prefix = "DMIC2";
441 status 402 status = "disabled";
442 }; 403 };
443 404
444 tegra_dmic3: d 405 tegra_dmic3: dmic@2904200 {
445 compat 406 compatible = "nvidia,tegra194-dmic",
446 407 "nvidia,tegra210-dmic";
447 reg = !! 408 reg = <0x2904200 0x100>;
448 clocks 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock- 410 clock-names = "dmic";
450 assign 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assign 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assign 413 assigned-clock-rates = <3072000>;
453 sound- 414 sound-name-prefix = "DMIC3";
454 status 415 status = "disabled";
455 }; 416 };
456 417
457 tegra_dmic4: d 418 tegra_dmic4: dmic@2904300 {
458 compat 419 compatible = "nvidia,tegra194-dmic",
459 420 "nvidia,tegra210-dmic";
460 reg = !! 421 reg = <0x2904300 0x100>;
461 clocks 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock- 423 clock-names = "dmic";
463 assign 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assign 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assign 426 assigned-clock-rates = <3072000>;
466 sound- 427 sound-name-prefix = "DMIC4";
467 status 428 status = "disabled";
468 }; 429 };
469 430
470 tegra_dspk1: d 431 tegra_dspk1: dspk@2905000 {
471 compat 432 compatible = "nvidia,tegra194-dspk",
472 433 "nvidia,tegra186-dspk";
473 reg = !! 434 reg = <0x2905000 0x100>;
474 clocks 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock- 436 clock-names = "dspk";
476 assign 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assign 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assign 439 assigned-clock-rates = <12288000>;
479 sound- 440 sound-name-prefix = "DSPK1";
480 status 441 status = "disabled";
481 }; 442 };
482 443
483 tegra_dspk2: d 444 tegra_dspk2: dspk@2905100 {
484 compat 445 compatible = "nvidia,tegra194-dspk",
485 446 "nvidia,tegra186-dspk";
486 reg = !! 447 reg = <0x2905100 0x100>;
487 clocks 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock- 449 clock-names = "dspk";
489 assign 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assign 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assign 452 assigned-clock-rates = <12288000>;
492 sound- 453 sound-name-prefix = "DSPK2";
493 status 454 status = "disabled";
494 }; 455 };
495 456
496 tegra_ope1: pr !! 457 tegra_sfc1: sfc@2902000 {
497 compat !! 458 compatible = "nvidia,tegra194-sfc",
498 !! 459 "nvidia,tegra210-sfc";
499 reg = !! 460 reg = <0x2902000 0x200>;
500 sound- !! 461 sound-name-prefix = "SFC1";
501 status 462 status = "disabled";
>> 463 };
502 464
503 #addre !! 465 tegra_sfc2: sfc@2902200 {
504 #size- !! 466 compatible = "nvidia,tegra194-sfc",
505 ranges !! 467 "nvidia,tegra210-sfc";
506 !! 468 reg = <0x2902200 0x200>;
507 equali !! 469 sound-name-prefix = "SFC2";
508 !! 470 status = "disabled";
509 !! 471 };
510 <<
511 }; <<
512 472
513 dynami !! 473 tegra_sfc3: sfc@2902400 {
514 !! 474 compatible = "nvidia,tegra194-sfc",
515 !! 475 "nvidia,tegra210-sfc";
516 !! 476 reg = <0x2902400 0x200>;
517 }; !! 477 sound-name-prefix = "SFC3";
>> 478 status = "disabled";
>> 479 };
>> 480
>> 481 tegra_sfc4: sfc@2902600 {
>> 482 compatible = "nvidia,tegra194-sfc",
>> 483 "nvidia,tegra210-sfc";
>> 484 reg = <0x2902600 0x200>;
>> 485 sound-name-prefix = "SFC4";
>> 486 status = "disabled";
518 }; 487 };
519 488
520 tegra_mvc1: mv 489 tegra_mvc1: mvc@290a000 {
521 compat 490 compatible = "nvidia,tegra194-mvc",
522 491 "nvidia,tegra210-mvc";
523 reg = !! 492 reg = <0x290a000 0x200>;
524 sound- 493 sound-name-prefix = "MVC1";
525 status 494 status = "disabled";
526 }; 495 };
527 496
528 tegra_mvc2: mv 497 tegra_mvc2: mvc@290a200 {
529 compat 498 compatible = "nvidia,tegra194-mvc",
530 499 "nvidia,tegra210-mvc";
531 reg = !! 500 reg = <0x290a200 0x200>;
532 sound- 501 sound-name-prefix = "MVC2";
533 status 502 status = "disabled";
534 }; 503 };
535 504
536 tegra_amixer: !! 505 tegra_amx1: amx@2903000 {
537 compat !! 506 compatible = "nvidia,tegra194-amx";
538 !! 507 reg = <0x2903000 0x100>;
539 reg = !! 508 sound-name-prefix = "AMX1";
540 sound- <<
541 status 509 status = "disabled";
542 }; 510 };
543 511
544 tegra_admaif: !! 512 tegra_amx2: amx@2903100 {
545 compat !! 513 compatible = "nvidia,tegra194-amx";
546 !! 514 reg = <0x2903100 0x100>;
547 reg = !! 515 sound-name-prefix = "AMX2";
548 dmas = !! 516 status = "disabled";
549 !! 517 };
550 !! 518
551 !! 519 tegra_amx3: amx@2903200 {
552 !! 520 compatible = "nvidia,tegra194-amx";
553 !! 521 reg = <0x2903200 0x100>;
554 !! 522 sound-name-prefix = "AMX3";
555 !! 523 status = "disabled";
556 !! 524 };
557 !! 525
558 !! 526 tegra_amx4: amx@2903300 {
559 !! 527 compatible = "nvidia,tegra194-amx";
560 !! 528 reg = <0x2903300 0x100>;
561 !! 529 sound-name-prefix = "AMX4";
562 !! 530 status = "disabled";
563 !! 531 };
564 !! 532
565 !! 533 tegra_adx1: adx@2903800 {
566 !! 534 compatible = "nvidia,tegra194-adx",
567 !! 535 "nvidia,tegra210-adx";
568 dma-na !! 536 reg = <0x2903800 0x100>;
569 !! 537 sound-name-prefix = "ADX1";
570 !! 538 status = "disabled";
571 !! 539 };
572 !! 540
573 !! 541 tegra_adx2: adx@2903900 {
574 !! 542 compatible = "nvidia,tegra194-adx",
575 !! 543 "nvidia,tegra210-adx";
576 !! 544 reg = <0x2903900 0x100>;
577 !! 545 sound-name-prefix = "ADX2";
578 !! 546 status = "disabled";
579 !! 547 };
580 !! 548
581 !! 549 tegra_adx3: adx@2903a00 {
582 !! 550 compatible = "nvidia,tegra194-adx",
583 !! 551 "nvidia,tegra210-adx";
584 !! 552 reg = <0x2903a00 0x100>;
585 !! 553 sound-name-prefix = "ADX3";
586 !! 554 status = "disabled";
587 !! 555 };
>> 556
>> 557 tegra_adx4: adx@2903b00 {
>> 558 compatible = "nvidia,tegra194-adx",
>> 559 "nvidia,tegra210-adx";
>> 560 reg = <0x2903b00 0x100>;
>> 561 sound-name-prefix = "ADX4";
588 status 562 status = "disabled";
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; 563 };
594 564
595 tegra_asrc: as !! 565 tegra_amixer: amixer@290bb00 {
596 compat !! 566 compatible = "nvidia,tegra194-amixer",
597 !! 567 "nvidia,tegra210-amixer";
598 reg = !! 568 reg = <0x290bb00 0x800>;
599 sound- !! 569 sound-name-prefix = "MIXER1";
600 status 570 status = "disabled";
601 }; 571 };
602 }; 572 };
>> 573 };
603 574
604 adma: dma-controller@2 !! 575 pinmux: pinmux@2430000 {
605 compatible = " !! 576 compatible = "nvidia,tegra194-pinmux";
606 " !! 577 reg = <0x2430000 0x17000>,
607 reg = <0x0 0x0 !! 578 <0xc300000 0x4000>;
608 interrupt-pare !! 579
609 interrupts = !! 580 status = "okay";
610 !! 581
611 !! 582 pex_rst_c5_out_state: pex_rst_c5_out {
612 !! 583 pex_rst {
613 !! 584 nvidia,pins = "pex_l5_rst_n_pgg1";
614 !! 585 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
615 !! 586 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
616 !! 587 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
617 !! 588 nvidia,tristate = <TEGRA_PIN_DISABLE>;
618 !! 589 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619 !! 590 };
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; 591 };
646 592
647 agic: interrupt-contro !! 593 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
648 compatible = " !! 594 clkreq {
649 " !! 595 nvidia,pins = "pex_l5_clkreq_n_pgg0";
650 #interrupt-cel !! 596 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
651 interrupt-cont !! 597 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652 reg = <0x0 0x0 !! 598 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
653 <0x0 0x0 !! 599 nvidia,tristate = <TEGRA_PIN_DISABLE>;
654 interrupts = < !! 600 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655 !! 601 };
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; 602 };
661 }; 603 };
662 604
663 mc: memory-controller@2c00000 605 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 606 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 607 reg = <0x02c00000 0x100000>,
666 <0x0 0x02c10000 !! 608 <0x02b80000 0x040000>,
667 <0x0 0x02c20000 !! 609 <0x01700000 0x100000>;
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI 610 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
687 #interconnect-cells = 611 #interconnect-cells = <1>;
688 status = "disabled"; 612 status = "disabled";
689 613
690 #address-cells = <2>; 614 #address-cells = <2>;
691 #size-cells = <2>; 615 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 616
693 <0x0 0x02b800 !! 617 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 618 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 619 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 620
696 /* 621 /*
697 * Bit 39 of addresses 622 * Bit 39 of addresses passing through the memory
698 * controller selects 623 * controller selects the XBAR format used when memory
699 * is accessed. This i 624 * is accessed. This is used to transparently access
700 * memory in the XBAR 625 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 626 * (bit 39 set) or Tegra (bit 39 clear).
702 * 627 *
703 * As a consequence, t 628 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 629 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 630 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 631 * devices require access to the XBAR switch, their
707 * drivers must set th 632 * drivers must set this bit explicitly.
708 * 633 *
709 * Limit the DMA range 634 * Limit the DMA range for memory clients to [38:0].
710 */ 635 */
711 dma-ranges = <0x0 0x0 !! 636 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 637
713 emc: external-memory-c 638 emc: external-memory-controller@2c60000 {
714 compatible = " 639 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 640 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 641 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < 642 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&bpm 643 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 644 clock-names = "emc";
720 645
721 #interconnect- 646 #interconnect-cells = <0>;
722 647
723 nvidia,bpmp = 648 nvidia,bpmp = <&bpmp>;
724 }; 649 };
725 }; 650 };
726 651
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 652 uarta: serial@3100000 {
744 compatible = "nvidia,t 653 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 654 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 655 reg-shift = <2>;
747 interrupts = <GIC_SPI 656 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 657 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 658 clock-names = "serial";
749 resets = <&bpmp TEGRA1 659 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 660 reset-names = "serial";
750 status = "disabled"; 661 status = "disabled";
751 }; 662 };
752 663
753 uartb: serial@3110000 { 664 uartb: serial@3110000 {
754 compatible = "nvidia,t 665 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 666 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 667 reg-shift = <2>;
757 interrupts = <GIC_SPI 668 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 669 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 670 clock-names = "serial";
759 resets = <&bpmp TEGRA1 671 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 672 reset-names = "serial";
760 status = "disabled"; 673 status = "disabled";
761 }; 674 };
762 675
763 uartd: serial@3130000 { 676 uartd: serial@3130000 {
764 compatible = "nvidia,t 677 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 678 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 679 reg-shift = <2>;
767 interrupts = <GIC_SPI 680 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 681 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 682 clock-names = "serial";
770 resets = <&bpmp TEGRA1 683 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 684 reset-names = "serial";
772 status = "disabled"; 685 status = "disabled";
773 }; 686 };
774 687
775 uarte: serial@3140000 { 688 uarte: serial@3140000 {
776 compatible = "nvidia,t 689 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 690 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 691 reg-shift = <2>;
779 interrupts = <GIC_SPI 692 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 693 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 694 clock-names = "serial";
782 resets = <&bpmp TEGRA1 695 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 696 reset-names = "serial";
784 status = "disabled"; 697 status = "disabled";
785 }; 698 };
786 699
787 uartf: serial@3150000 { 700 uartf: serial@3150000 {
788 compatible = "nvidia,t 701 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 702 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 703 reg-shift = <2>;
791 interrupts = <GIC_SPI 704 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 705 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 706 clock-names = "serial";
794 resets = <&bpmp TEGRA1 707 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 708 reset-names = "serial";
796 status = "disabled"; 709 status = "disabled";
797 }; 710 };
798 711
799 gen1_i2c: i2c@3160000 { 712 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 713 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 714 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 715 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 716 #address-cells = <1>;
804 #size-cells = <0>; 717 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 718 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 719 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 720 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 721 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 722 status = "disabled";
812 }; 723 };
813 724
814 uarth: serial@3170000 { 725 uarth: serial@3170000 {
815 compatible = "nvidia,t 726 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 727 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 728 reg-shift = <2>;
818 interrupts = <GIC_SPI 729 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 730 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 731 clock-names = "serial";
821 resets = <&bpmp TEGRA1 732 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 733 reset-names = "serial";
823 status = "disabled"; 734 status = "disabled";
824 }; 735 };
825 736
826 cam_i2c: i2c@3180000 { 737 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 738 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 739 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 741 #address-cells = <1>;
831 #size-cells = <0>; 742 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 743 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 744 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 745 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 746 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 747 status = "disabled";
839 }; 748 };
840 749
841 /* shares pads with dpaux1 */ 750 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 751 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 752 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 753 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 754 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 755 #address-cells = <1>;
847 #size-cells = <0>; 756 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 757 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 758 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 759 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 760 reset-names = "i2c";
852 pinctrl-0 = <&state_dp 761 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dp 762 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "defau 763 pinctrl-names = "default", "idle";
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 764 status = "disabled";
858 }; 765 };
859 766
860 /* shares pads with dpaux0 */ 767 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 768 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 769 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 770 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 771 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 772 #address-cells = <1>;
866 #size-cells = <0>; 773 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 774 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 775 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 776 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 777 reset-names = "i2c";
871 pinctrl-0 = <&state_dp 778 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dp 779 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "defau 780 pinctrl-names = "default", "idle";
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 781 status = "disabled";
877 }; 782 };
878 783
879 /* shares pads with dpaux2 */ 784 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 { 785 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t 786 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 787 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 788 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 789 #address-cells = <1>;
885 #size-cells = <0>; 790 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 791 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 792 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 793 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 794 reset-names = "i2c";
890 pinctrl-0 = <&state_dp 795 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dp 796 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "defau 797 pinctrl-names = "default", "idle";
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 798 status = "disabled";
896 }; 799 };
897 800
898 /* shares pads with dpaux3 */ 801 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 { 802 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t 803 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 804 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 806 #address-cells = <1>;
904 #size-cells = <0>; 807 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 808 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 809 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 810 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 811 reset-names = "i2c";
909 pinctrl-0 = <&state_dp 812 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dp 813 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "defau 814 pinctrl-names = "default", "idle";
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; 815 status = "disabled";
915 }; 816 };
916 817
917 spi@3270000 { 818 spi@3270000 {
918 compatible = "nvidia,t 819 compatible = "nvidia,tegra194-qspi";
919 reg = <0x0 0x3270000 0 !! 820 reg = <0x3270000 0x1000>;
920 interrupts = <GIC_SPI 821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
921 #address-cells = <1>; 822 #address-cells = <1>;
922 #size-cells = <0>; 823 #size-cells = <0>;
923 clocks = <&bpmp TEGRA1 824 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA1 825 <&bpmp TEGRA194_CLK_QSPI0_PM>;
925 clock-names = "qspi", 826 clock-names = "qspi", "qspi_out";
926 resets = <&bpmp TEGRA1 827 resets = <&bpmp TEGRA194_RESET_QSPI0>;
>> 828 reset-names = "qspi";
>> 829 status = "disabled";
>> 830 };
>> 831
>> 832 spi@3300000 {
>> 833 compatible = "nvidia,tegra194-qspi";
>> 834 reg = <0x3300000 0x1000>;
>> 835 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>> 836 #address-cells = <1>;
>> 837 #size-cells = <0>;
>> 838 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
>> 839 <&bpmp TEGRA194_CLK_QSPI1_PM>;
>> 840 clock-names = "qspi", "qspi_out";
>> 841 resets = <&bpmp TEGRA194_RESET_QSPI1>;
>> 842 reset-names = "qspi";
927 status = "disabled"; 843 status = "disabled";
928 }; 844 };
929 845
930 pwm1: pwm@3280000 { 846 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 847 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 848 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 849 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 850 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 851 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 852 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 853 reset-names = "pwm";
937 status = "disabled"; 854 status = "disabled";
938 #pwm-cells = <2>; 855 #pwm-cells = <2>;
939 }; 856 };
940 857
941 pwm2: pwm@3290000 { 858 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 859 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 860 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 861 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 862 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 863 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 864 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 865 reset-names = "pwm";
948 status = "disabled"; 866 status = "disabled";
949 #pwm-cells = <2>; 867 #pwm-cells = <2>;
950 }; 868 };
951 869
952 pwm3: pwm@32a0000 { 870 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 871 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 872 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 873 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 874 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 875 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 876 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 877 reset-names = "pwm";
959 status = "disabled"; 878 status = "disabled";
960 #pwm-cells = <2>; 879 #pwm-cells = <2>;
961 }; 880 };
962 881
963 pwm5: pwm@32c0000 { 882 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 883 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 884 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 885 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 886 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 887 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 888 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 889 reset-names = "pwm";
970 status = "disabled"; 890 status = "disabled";
971 #pwm-cells = <2>; 891 #pwm-cells = <2>;
972 }; 892 };
973 893
974 pwm6: pwm@32d0000 { 894 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 895 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 896 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 897 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 898 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 899 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 900 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 901 reset-names = "pwm";
981 status = "disabled"; 902 status = "disabled";
982 #pwm-cells = <2>; 903 #pwm-cells = <2>;
983 }; 904 };
984 905
985 pwm7: pwm@32e0000 { 906 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 907 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 908 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 909 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 910 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 911 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 912 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 913 reset-names = "pwm";
992 status = "disabled"; 914 status = "disabled";
993 #pwm-cells = <2>; 915 #pwm-cells = <2>;
994 }; 916 };
995 917
996 pwm8: pwm@32f0000 { 918 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 919 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 920 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 921 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 922 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 923 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 924 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 925 reset-names = "pwm";
1003 status = "disabled"; 926 status = "disabled";
1004 #pwm-cells = <2>; 927 #pwm-cells = <2>;
1005 }; 928 };
1006 929
1007 spi@3300000 { <<
1008 compatible = "nvidia, <<
1009 reg = <0x0 0x3300000 <<
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { 930 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia, 931 compatible = "nvidia,tegra194-sdhci";
1022 reg = <0x0 0x03400000 !! 932 reg = <0x03400000 0x10000>;
1023 interrupts = <GIC_SPI 933 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA 934 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA 935 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci" 936 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 937 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 938 reset-names = "sdhci";
1034 interconnects = <&mc 939 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035 <&mc 940 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036 interconnect-names = 941 interconnect-names = "dma-mem", "write";
1037 iommus = <&smmu TEGRA 942 iommus = <&smmu TEGRA194_SID_SDMMC1>;
1038 pinctrl-names = "sdmm 943 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1039 pinctrl-0 = <&sdmmc1_ 944 pinctrl-0 = <&sdmmc1_3v3>;
1040 pinctrl-1 = <&sdmmc1_ 945 pinctrl-1 = <&sdmmc1_1v8>;
1041 nvidia,pad-autocal-pu 946 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 947 <0x07>;
1043 nvidia,pad-autocal-pu 948 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 949 <0x07>;
1045 nvidia,pad-autocal-pu 950 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 951 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 952 <0x07>;
1048 nvidia,pad-autocal-pu 953 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 954 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 955 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 956 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; 957 sd-uhs-sdr25;
1053 sd-uhs-sdr50; 958 sd-uhs-sdr50;
1054 sd-uhs-ddr50; 959 sd-uhs-ddr50;
1055 sd-uhs-sdr104; 960 sd-uhs-sdr104;
1056 status = "disabled"; 961 status = "disabled";
1057 }; 962 };
1058 963
1059 sdmmc3: mmc@3440000 { 964 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia, 965 compatible = "nvidia,tegra194-sdhci";
1061 reg = <0x0 0x03440000 !! 966 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 967 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA 968 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA 969 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci" 970 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 971 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 972 reset-names = "sdhci";
1073 interconnects = <&mc 973 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074 <&mc 974 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075 interconnect-names = 975 interconnect-names = "dma-mem", "write";
1076 iommus = <&smmu TEGRA 976 iommus = <&smmu TEGRA194_SID_SDMMC3>;
1077 pinctrl-names = "sdmm 977 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1078 pinctrl-0 = <&sdmmc3_ 978 pinctrl-0 = <&sdmmc3_3v3>;
1079 pinctrl-1 = <&sdmmc3_ 979 pinctrl-1 = <&sdmmc3_1v8>;
1080 nvidia,pad-autocal-pu 980 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 981 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 982 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 983 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 984 <0x07>;
1085 nvidia,pad-autocal-pu 985 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 986 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 987 <0x07>;
1088 nvidia,pad-autocal-pu 988 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 989 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 990 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 991 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; 992 sd-uhs-sdr25;
1093 sd-uhs-sdr50; 993 sd-uhs-sdr50;
1094 sd-uhs-ddr50; 994 sd-uhs-ddr50;
1095 sd-uhs-sdr104; 995 sd-uhs-sdr104;
1096 status = "disabled"; 996 status = "disabled";
1097 }; 997 };
1098 998
1099 sdmmc4: mmc@3460000 { 999 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia, 1000 compatible = "nvidia,tegra194-sdhci";
1101 reg = <0x0 0x03460000 !! 1001 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 1002 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA 1003 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA 1004 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci" 1005 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&b 1006 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 1007 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 1008 assigned-clock-parents =
1109 <&b 1009 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 1010 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 1011 reset-names = "sdhci";
1112 interconnects = <&mc 1012 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113 <&mc 1013 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114 interconnect-names = 1014 interconnect-names = "dma-mem", "write";
1115 iommus = <&smmu TEGRA 1015 iommus = <&smmu TEGRA194_SID_SDMMC4>;
1116 nvidia,pad-autocal-pu 1016 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 1017 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 1018 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 1019 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 1020 <0x0a>;
1121 nvidia,pad-autocal-pu 1021 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 1022 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 1023 <0x0a>;
1124 nvidia,default-tap = 1024 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 1025 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 1026 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; 1027 cap-mmc-highspeed;
1128 mmc-ddr-1_8v; 1028 mmc-ddr-1_8v;
1129 mmc-hs200-1_8v; 1029 mmc-hs200-1_8v;
1130 mmc-hs400-1_8v; 1030 mmc-hs400-1_8v;
1131 mmc-hs400-enhanced-st 1031 mmc-hs400-enhanced-strobe;
1132 supports-cqe; 1032 supports-cqe;
1133 status = "disabled"; 1033 status = "disabled";
1134 }; 1034 };
1135 1035
1136 hda@3510000 { 1036 hda@3510000 {
1137 compatible = "nvidia, !! 1037 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 1038 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 1039 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 1040 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA 1041 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA 1042 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", 1043 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA 1044 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA 1045 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", 1046 reset-names = "hda", "hda2hdmi";
1147 power-domains = <&bpm 1047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc 1048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149 <&mc 1049 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150 interconnect-names = 1050 interconnect-names = "dma-mem", "write";
1151 iommus = <&smmu TEGRA 1051 iommus = <&smmu TEGRA194_SID_HDA>;
1152 status = "disabled"; 1052 status = "disabled";
1153 }; 1053 };
1154 1054
1155 xusb_padctl: padctl@3520000 { 1055 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia, 1056 compatible = "nvidia,tegra194-xusb-padctl";
1157 reg = <0x0 0x03520000 !! 1057 reg = <0x03520000 0x1000>,
1158 <0x0 0x03540000 !! 1058 <0x03540000 0x1000>;
1159 reg-names = "padctl", 1059 reg-names = "padctl", "ao";
1160 interrupts = <GIC_SPI 1060 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161 1061
1162 resets = <&bpmp TEGRA 1062 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl 1063 reset-names = "padctl";
1164 1064
1165 status = "disabled"; 1065 status = "disabled";
1166 1066
1167 pads { 1067 pads {
1168 usb2 { 1068 usb2 {
1169 clock 1069 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock 1070 clock-names = "trk";
1171 1071
1172 lanes 1072 lanes {
1173 1073 usb2-0 {
1174 1074 nvidia,function = "xusb";
1175 1075 status = "disabled";
1176 1076 #phy-cells = <0>;
1177 1077 };
1178 1078
1179 1079 usb2-1 {
1180 1080 nvidia,function = "xusb";
1181 1081 status = "disabled";
1182 1082 #phy-cells = <0>;
1183 1083 };
1184 1084
1185 1085 usb2-2 {
1186 1086 nvidia,function = "xusb";
1187 1087 status = "disabled";
1188 1088 #phy-cells = <0>;
1189 1089 };
1190 1090
1191 1091 usb2-3 {
1192 1092 nvidia,function = "xusb";
1193 1093 status = "disabled";
1194 1094 #phy-cells = <0>;
1195 1095 };
1196 }; 1096 };
1197 }; 1097 };
1198 1098
1199 usb3 { 1099 usb3 {
1200 lanes 1100 lanes {
1201 1101 usb3-0 {
1202 1102 nvidia,function = "xusb";
1203 1103 status = "disabled";
1204 1104 #phy-cells = <0>;
1205 1105 };
1206 1106
1207 1107 usb3-1 {
1208 1108 nvidia,function = "xusb";
1209 1109 status = "disabled";
1210 1110 #phy-cells = <0>;
1211 1111 };
1212 1112
1213 1113 usb3-2 {
1214 1114 nvidia,function = "xusb";
1215 1115 status = "disabled";
1216 1116 #phy-cells = <0>;
1217 1117 };
1218 1118
1219 1119 usb3-3 {
1220 1120 nvidia,function = "xusb";
1221 1121 status = "disabled";
1222 1122 #phy-cells = <0>;
1223 1123 };
1224 }; 1124 };
1225 }; 1125 };
1226 }; 1126 };
1227 1127
1228 ports { 1128 ports {
1229 usb2-0 { 1129 usb2-0 {
1230 statu 1130 status = "disabled";
1231 }; 1131 };
1232 1132
1233 usb2-1 { 1133 usb2-1 {
1234 statu 1134 status = "disabled";
1235 }; 1135 };
1236 1136
1237 usb2-2 { 1137 usb2-2 {
1238 statu 1138 status = "disabled";
1239 }; 1139 };
1240 1140
1241 usb2-3 { 1141 usb2-3 {
1242 statu 1142 status = "disabled";
1243 }; 1143 };
1244 1144
1245 usb3-0 { 1145 usb3-0 {
1246 statu 1146 status = "disabled";
1247 }; 1147 };
1248 1148
1249 usb3-1 { 1149 usb3-1 {
1250 statu 1150 status = "disabled";
1251 }; 1151 };
1252 1152
1253 usb3-2 { 1153 usb3-2 {
1254 statu 1154 status = "disabled";
1255 }; 1155 };
1256 1156
1257 usb3-3 { 1157 usb3-3 {
1258 statu 1158 status = "disabled";
1259 }; 1159 };
1260 }; 1160 };
1261 }; 1161 };
1262 1162
1263 usb@3550000 { 1163 usb@3550000 {
1264 compatible = "nvidia, 1164 compatible = "nvidia,tegra194-xudc";
1265 reg = <0x0 0x03550000 !! 1165 reg = <0x03550000 0x8000>,
1266 <0x0 0x03558000 !! 1166 <0x03558000 0x1000>;
1267 reg-names = "base", " 1167 reg-names = "base", "fpci";
1268 interrupts = <GIC_SPI 1168 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&bpmp TEGRA 1169 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA 1170 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA 1171 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA 1172 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", 1173 clock-names = "dev", "ss", "ss_src", "fs_src";
1274 interconnects = <&mc 1174 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1275 <&mc 1175 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1276 interconnect-names = 1176 interconnect-names = "dma-mem", "write";
1277 iommus = <&smmu TEGRA 1177 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1278 power-domains = <&bpm 1178 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpm 1179 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = 1180 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = 1181 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent; <<
1283 status = "disabled"; 1182 status = "disabled";
1284 }; 1183 };
1285 1184
1286 usb@3610000 { 1185 usb@3610000 {
1287 compatible = "nvidia, 1186 compatible = "nvidia,tegra194-xusb";
1288 reg = <0x0 0x03610000 !! 1187 reg = <0x03610000 0x40000>,
1289 <0x0 0x03600000 !! 1188 <0x03600000 0x10000>;
1290 reg-names = "hcd", "f 1189 reg-names = "hcd", "fpci";
1291 1190
1292 interrupts = <GIC_SPI 1191 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 1192 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294 1193
1295 clocks = <&bpmp TEGRA 1194 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA 1195 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA 1196 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA 1197 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA 1198 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA 1199 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA 1200 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA 1201 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA 1202 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_h 1203 clock-names = "xusb_host", "xusb_falcon_src",
1305 "xusb_s 1204 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306 "xusb_f 1205 "xusb_fs_src", "pll_u_480m", "clk_m",
1307 "pll_e" 1206 "pll_e";
1308 interconnects = <&mc 1207 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1309 <&mc 1208 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1310 interconnect-names = 1209 interconnect-names = "dma-mem", "write";
1311 iommus = <&smmu TEGRA 1210 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1312 1211
1313 power-domains = <&bpm 1212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpm 1213 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = 1214 power-domain-names = "xusb_host", "xusb_ss";
1316 1215
1317 nvidia,xusb-padctl = 1216 nvidia,xusb-padctl = <&xusb_padctl>;
1318 status = "disabled"; 1217 status = "disabled";
1319 }; 1218 };
1320 1219
1321 fuse@3820000 { 1220 fuse@3820000 {
1322 compatible = "nvidia, 1221 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 1222 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 1223 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 1224 clock-names = "fuse";
1326 }; 1225 };
1327 1226
1328 gic: interrupt-controller@388 1227 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 1228 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 1229 #interrupt-cells = <3>;
1331 interrupt-controller; 1230 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 1231 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 1232 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 1233 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 1234 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 1235 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 1236 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 1237 interrupt-parent = <&gic>;
1339 }; 1238 };
1340 1239
1341 cec@3960000 { 1240 cec@3960000 {
1342 compatible = "nvidia, 1241 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 1242 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 1244 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 1245 clock-names = "cec";
1347 status = "disabled"; 1246 status = "disabled";
1348 }; 1247 };
1349 1248
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 1249 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, 1250 compatible = "nvidia,tegra194-hsp";
1362 reg = <0x0 0x03c00000 !! 1251 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 1252 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1253 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1254 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1255 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1256 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1257 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1258 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1259 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1260 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 1261 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 1262 "shared3", "shared4", "shared5", "shared6",
1374 "sh 1263 "shared7";
1375 #mbox-cells = <2>; 1264 #mbox-cells = <2>;
1376 }; 1265 };
1377 1266
1378 p2u_hsio_0: phy@3e10000 { 1267 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 1268 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 1269 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 1270 reg-names = "ctl";
1382 1271
1383 #phy-cells = <0>; 1272 #phy-cells = <0>;
1384 }; 1273 };
1385 1274
1386 p2u_hsio_1: phy@3e20000 { 1275 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 1276 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 1277 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 1278 reg-names = "ctl";
1390 1279
1391 #phy-cells = <0>; 1280 #phy-cells = <0>;
1392 }; 1281 };
1393 1282
1394 p2u_hsio_2: phy@3e30000 { 1283 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 1284 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 1285 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 1286 reg-names = "ctl";
1398 1287
1399 #phy-cells = <0>; 1288 #phy-cells = <0>;
1400 }; 1289 };
1401 1290
1402 p2u_hsio_3: phy@3e40000 { 1291 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 1292 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 1293 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 1294 reg-names = "ctl";
1406 1295
1407 #phy-cells = <0>; 1296 #phy-cells = <0>;
1408 }; 1297 };
1409 1298
1410 p2u_hsio_4: phy@3e50000 { 1299 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 1300 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 1301 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 1302 reg-names = "ctl";
1414 1303
1415 #phy-cells = <0>; 1304 #phy-cells = <0>;
1416 }; 1305 };
1417 1306
1418 p2u_hsio_5: phy@3e60000 { 1307 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 1308 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 1309 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 1310 reg-names = "ctl";
1422 1311
1423 #phy-cells = <0>; 1312 #phy-cells = <0>;
1424 }; 1313 };
1425 1314
1426 p2u_hsio_6: phy@3e70000 { 1315 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 1316 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 1317 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 1318 reg-names = "ctl";
1430 1319
1431 #phy-cells = <0>; 1320 #phy-cells = <0>;
1432 }; 1321 };
1433 1322
1434 p2u_hsio_7: phy@3e80000 { 1323 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 1324 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 1325 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 1326 reg-names = "ctl";
1438 1327
1439 #phy-cells = <0>; 1328 #phy-cells = <0>;
1440 }; 1329 };
1441 1330
1442 p2u_hsio_8: phy@3e90000 { 1331 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 1332 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 1333 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 1334 reg-names = "ctl";
1446 1335
1447 #phy-cells = <0>; 1336 #phy-cells = <0>;
1448 }; 1337 };
1449 1338
1450 p2u_hsio_9: phy@3ea0000 { 1339 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 1340 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 1341 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 1342 reg-names = "ctl";
1454 1343
1455 #phy-cells = <0>; 1344 #phy-cells = <0>;
1456 }; 1345 };
1457 1346
1458 p2u_nvhs_0: phy@3eb0000 { 1347 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 1348 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 1349 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 1350 reg-names = "ctl";
1462 1351
1463 #phy-cells = <0>; 1352 #phy-cells = <0>;
1464 }; 1353 };
1465 1354
1466 p2u_nvhs_1: phy@3ec0000 { 1355 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 1356 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 1357 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 1358 reg-names = "ctl";
1470 1359
1471 #phy-cells = <0>; 1360 #phy-cells = <0>;
1472 }; 1361 };
1473 1362
1474 p2u_nvhs_2: phy@3ed0000 { 1363 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 1364 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 1365 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 1366 reg-names = "ctl";
1478 1367
1479 #phy-cells = <0>; 1368 #phy-cells = <0>;
1480 }; 1369 };
1481 1370
1482 p2u_nvhs_3: phy@3ee0000 { 1371 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 1372 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 1373 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 1374 reg-names = "ctl";
1486 1375
1487 #phy-cells = <0>; 1376 #phy-cells = <0>;
1488 }; 1377 };
1489 1378
1490 p2u_nvhs_4: phy@3ef0000 { 1379 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 1380 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 1381 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 1382 reg-names = "ctl";
1494 1383
1495 #phy-cells = <0>; 1384 #phy-cells = <0>;
1496 }; 1385 };
1497 1386
1498 p2u_nvhs_5: phy@3f00000 { 1387 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 1388 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 1389 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 1390 reg-names = "ctl";
1502 1391
1503 #phy-cells = <0>; 1392 #phy-cells = <0>;
1504 }; 1393 };
1505 1394
1506 p2u_nvhs_6: phy@3f10000 { 1395 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 1396 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 1397 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 1398 reg-names = "ctl";
1510 1399
1511 #phy-cells = <0>; 1400 #phy-cells = <0>;
1512 }; 1401 };
1513 1402
1514 p2u_nvhs_7: phy@3f20000 { 1403 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 1404 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 1405 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 1406 reg-names = "ctl";
1518 1407
1519 #phy-cells = <0>; 1408 #phy-cells = <0>;
1520 }; 1409 };
1521 1410
1522 p2u_hsio_10: phy@3f30000 { 1411 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 1412 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 1413 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 1414 reg-names = "ctl";
1526 1415
1527 #phy-cells = <0>; 1416 #phy-cells = <0>;
1528 }; 1417 };
1529 1418
1530 p2u_hsio_11: phy@3f40000 { 1419 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 1420 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 1421 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 1422 reg-names = "ctl";
1534 1423
1535 #phy-cells = <0>; 1424 #phy-cells = <0>;
1536 }; 1425 };
1537 1426
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 1427 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, 1428 compatible = "nvidia,tegra194-hsp";
1560 reg = <0x0 0x0c150000 !! 1429 reg = <0x0c150000 0x90000>;
1561 interrupts = <GIC_SPI 1430 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 1431 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 1432 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 1433 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1434 /*
1566 * Shared interrupt 0 1435 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 1436 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 1437 */
1569 interrupt-names = "sh 1438 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 1439 #mbox-cells = <2>;
1571 }; 1440 };
1572 1441
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 1442 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 1443 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 1444 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 1445 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 1446 #address-cells = <1>;
1588 #size-cells = <0>; 1447 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 1448 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 1449 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 1450 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 1451 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 1452 status = "disabled";
1596 }; 1453 };
1597 1454
1598 gen8_i2c: i2c@c250000 { 1455 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 1456 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 1457 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 1458 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 1459 #address-cells = <1>;
1603 #size-cells = <0>; 1460 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 1461 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 1462 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 1463 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 1464 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 1465 status = "disabled";
1611 }; 1466 };
1612 1467
1613 uartc: serial@c280000 { 1468 uartc: serial@c280000 {
1614 compatible = "nvidia, 1469 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 1470 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 1471 reg-shift = <2>;
1617 interrupts = <GIC_SPI 1472 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 1473 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 1474 clock-names = "serial";
1620 resets = <&bpmp TEGRA 1475 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 1476 reset-names = "serial";
1622 status = "disabled"; 1477 status = "disabled";
1623 }; 1478 };
1624 1479
1625 uartg: serial@c290000 { 1480 uartg: serial@c290000 {
1626 compatible = "nvidia, 1481 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 1482 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 1483 reg-shift = <2>;
1629 interrupts = <GIC_SPI 1484 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 1485 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 1486 clock-names = "serial";
1632 resets = <&bpmp TEGRA 1487 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 1488 reset-names = "serial";
1634 status = "disabled"; 1489 status = "disabled";
1635 }; 1490 };
1636 1491
1637 rtc: rtc@c2a0000 { 1492 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 1493 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 1494 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 1495 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 1496 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 1497 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 1498 clock-names = "rtc";
1644 status = "disabled"; 1499 status = "disabled";
1645 }; 1500 };
1646 1501
1647 gpio_aon: gpio@c2f0000 { 1502 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 1503 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 1504 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 1505 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 1506 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI 1507 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 1508 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 1509 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 1510 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1656 gpio-controller; 1511 gpio-controller;
1657 #gpio-cells = <2>; 1512 #gpio-cells = <2>;
1658 interrupt-controller; 1513 interrupt-controller;
1659 #interrupt-cells = <2 1514 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 1515 };
1669 1516
1670 pwm4: pwm@c340000 { 1517 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 1518 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 1519 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 1520 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 1521 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 1522 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 1523 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 1524 reset-names = "pwm";
1677 status = "disabled"; 1525 status = "disabled";
1678 #pwm-cells = <2>; 1526 #pwm-cells = <2>;
1679 }; 1527 };
1680 1528
1681 pmc: pmc@c360000 { 1529 pmc: pmc@c360000 {
1682 compatible = "nvidia, 1530 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 1531 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 1532 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 1533 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 1534 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 1535 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 1536 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 1537
1690 #interrupt-cells = <2 1538 #interrupt-cells = <2>;
1691 interrupt-controller; 1539 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v 1540 sdmmc1_3v3: sdmmc1-3v3 {
1699 pins = "sdmmc 1541 pins = "sdmmc1-hv";
1700 power-source 1542 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1701 }; 1543 };
1702 1544
1703 sdmmc3_1v8: sdmmc3-1v !! 1545 sdmmc1_1v8: sdmmc1-1v8 {
1704 pins = "sdmmc !! 1546 pins = "sdmmc1-hv";
1705 power-source 1547 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1706 }; 1548 };
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v 1549 sdmmc3_3v3: sdmmc3-3v3 {
1709 pins = "sdmmc 1550 pins = "sdmmc3-hv";
1710 power-source 1551 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1711 }; 1552 };
1712 }; <<
1713 1553
1714 aon-noc@c600000 { !! 1554 sdmmc3_1v8: sdmmc3-1v8 {
1715 compatible = "nvidia, !! 1555 pins = "sdmmc3-hv";
1716 reg = <0x0 0xc600000 !! 1556 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1717 interrupts = <GIC_SPI !! 1557 };
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 1558
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; 1559 };
1732 1560
1733 iommu@10000000 { 1561 iommu@10000000 {
1734 compatible = "nvidia, 1562 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1735 reg = <0x0 0x10000000 !! 1563 reg = <0x10000000 0x800000>;
1736 interrupts = <GIC_SPI 1564 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1566 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1567 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1569 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1570 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 1571 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1572 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1573 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1746 <GIC_SPI 1574 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 1575 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 1576 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 1577 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1750 <GIC_SPI 1578 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1751 <GIC_SPI 1579 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1752 <GIC_SPI 1580 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 1581 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 1582 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 1583 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 1584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 1585 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 1586 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 1587 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1588 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1591 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1592 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1593 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1594 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1596 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 1597 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 1598 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1771 <GIC_SPI 1599 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1772 <GIC_SPI 1600 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1773 <GIC_SPI 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1774 <GIC_SPI 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1776 <GIC_SPI 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1801 stream-match-mask = < 1629 stream-match-mask = <0x7f80>;
1802 #global-interrupts = 1630 #global-interrupts = <1>;
1803 #iommu-cells = <1>; 1631 #iommu-cells = <1>;
1804 1632
1805 nvidia,memory-control 1633 nvidia,memory-controller = <&mc>;
1806 status = "disabled"; 1634 status = "disabled";
1807 }; 1635 };
1808 1636
1809 smmu: iommu@12000000 { 1637 smmu: iommu@12000000 {
1810 compatible = "nvidia, 1638 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1811 reg = <0x0 0x12000000 !! 1639 reg = <0x12000000 0x800000>,
1812 <0x0 0x11000000 !! 1640 <0x11000000 0x800000>;
1813 interrupts = <GIC_SPI 1641 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1642 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1649 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1650 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1651 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1652 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1653 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1654 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1655 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1656 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1657 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1659 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1660 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 1661 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 1662 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 1663 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 1664 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 1665 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 1666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 1667 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 1668 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 1669 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 1670 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 1671 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 1672 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 1673 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 1674 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 1675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 1676 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 1677 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 1678 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1879 stream-match-mask = < 1707 stream-match-mask = <0x7f80>;
1880 #global-interrupts = 1708 #global-interrupts = <2>;
1881 #iommu-cells = <1>; 1709 #iommu-cells = <1>;
1882 1710
1883 nvidia,memory-control 1711 nvidia,memory-controller = <&mc>;
1884 status = "okay"; 1712 status = "okay";
1885 }; 1713 };
1886 1714
1887 host1x@13e00000 { 1715 host1x@13e00000 {
1888 compatible = "nvidia, 1716 compatible = "nvidia,tegra194-host1x";
1889 reg = <0x0 0x13e00000 !! 1717 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 1718 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 1719 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 1720 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1721 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy 1722 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA 1723 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 1724 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 1725 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 1726 reset-names = "host1x";
1899 1727
1900 #address-cells = <2>; !! 1728 #address-cells = <1>;
1901 #size-cells = <2>; !! 1729 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 1730
>> 1731 ranges = <0x15000000 0x15000000 0x01000000>;
1904 interconnects = <&mc 1732 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905 interconnect-names = 1733 interconnect-names = "dma-mem";
1906 iommus = <&smmu TEGRA 1734 iommus = <&smmu TEGRA194_SID_HOST1X>;
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 1735
1919 nvdec@15140000 { 1736 nvdec@15140000 {
1920 compatible = 1737 compatible = "nvidia,tegra194-nvdec";
1921 reg = <0x0 0x !! 1738 reg = <0x15140000 0x00040000>;
1922 clocks = <&bp 1739 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1923 clock-names = 1740 clock-names = "nvdec";
1924 resets = <&bp 1741 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1925 reset-names = 1742 reset-names = "nvdec";
1926 1743
1927 power-domains 1744 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1928 interconnects 1745 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1929 1746 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1930 1747 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1931 interconnect- 1748 interconnect-names = "dma-mem", "read-1", "write";
1932 iommus = <&sm 1749 iommus = <&smmu TEGRA194_SID_NVDEC1>;
1933 dma-coherent; 1750 dma-coherent;
1934 1751
1935 nvidia,host1x 1752 nvidia,host1x-class = <0xf5>;
1936 }; 1753 };
1937 1754
1938 display-hub@15200000 1755 display-hub@15200000 {
1939 compatible = 1756 compatible = "nvidia,tegra194-display";
1940 reg = <0x0 0x !! 1757 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 1758 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 1759 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 1760 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 1761 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 1762 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 1763 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 1764 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 1765 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 1766 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 1767 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 1768 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 1769 clock-names = "disp", "hub";
1953 status = "dis 1770 status = "disabled";
1954 1771
1955 power-domains 1772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 1773
1957 #address-cell !! 1774 #address-cells = <1>;
1958 #size-cells = !! 1775 #size-cells = <1>;
1959 ranges = <0x0 !! 1776
>> 1777 ranges = <0x15200000 0x15200000 0x40000>;
1960 1778
1961 display@15200 1779 display@15200000 {
1962 compa 1780 compatible = "nvidia,tegra194-dc";
1963 reg = !! 1781 reg = <0x15200000 0x10000>;
1964 inter 1782 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 1783 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 1784 clock-names = "dc";
1967 reset 1785 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 1786 reset-names = "dc";
1969 1787
1970 power 1788 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter 1789 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 1790 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 inter 1791 interconnect-names = "dma-mem", "read-1";
1974 1792
1975 nvidi 1793 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 1794 nvidia,head = <0>;
1977 }; 1795 };
1978 1796
1979 display@15210 1797 display@15210000 {
1980 compa 1798 compatible = "nvidia,tegra194-dc";
1981 reg = !! 1799 reg = <0x15210000 0x10000>;
1982 inter 1800 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 1801 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 1802 clock-names = "dc";
1985 reset 1803 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 1804 reset-names = "dc";
1987 1805
1988 power 1806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter 1807 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 1808 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 inter 1809 interconnect-names = "dma-mem", "read-1";
1992 1810
1993 nvidi 1811 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 1812 nvidia,head = <1>;
1995 }; 1813 };
1996 1814
1997 display@15220 1815 display@15220000 {
1998 compa 1816 compatible = "nvidia,tegra194-dc";
1999 reg = !! 1817 reg = <0x15220000 0x10000>;
2000 inter 1818 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 1819 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 1820 clock-names = "dc";
2003 reset 1821 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 1822 reset-names = "dc";
2005 1823
2006 power 1824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter 1825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008 1826 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009 inter 1827 interconnect-names = "dma-mem", "read-1";
2010 1828
2011 nvidi 1829 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 1830 nvidia,head = <2>;
2013 }; 1831 };
2014 1832
2015 display@15230 1833 display@15230000 {
2016 compa 1834 compatible = "nvidia,tegra194-dc";
2017 reg = !! 1835 reg = <0x15230000 0x10000>;
2018 inter 1836 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 1837 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 1838 clock-names = "dc";
2021 reset 1839 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 1840 reset-names = "dc";
2023 1841
2024 power 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027 inter 1845 interconnect-names = "dma-mem", "read-1";
2028 1846
2029 nvidi 1847 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 1848 nvidia,head = <3>;
2031 }; 1849 };
2032 }; 1850 };
2033 1851
2034 vic@15340000 { 1852 vic@15340000 {
2035 compatible = 1853 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 1854 reg = <0x15340000 0x00040000>;
2037 interrupts = 1855 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 1856 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 1857 clock-names = "vic";
2040 resets = <&bp 1858 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 1859 reset-names = "vic";
2042 1860
2043 power-domains 1861 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects 1862 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045 1863 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046 interconnect- 1864 interconnect-names = "dma-mem", "write";
2047 iommus = <&sm 1865 iommus = <&smmu TEGRA194_SID_VIC>;
2048 dma-coherent; 1866 dma-coherent;
2049 }; 1867 };
2050 1868
2051 nvjpg@15380000 { 1869 nvjpg@15380000 {
2052 compatible = 1870 compatible = "nvidia,tegra194-nvjpg";
2053 reg = <0x0 0x !! 1871 reg = <0x15380000 0x40000>;
2054 clocks = <&bp 1872 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2055 clock-names = 1873 clock-names = "nvjpg";
2056 resets = <&bp 1874 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2057 reset-names = 1875 reset-names = "nvjpg";
2058 1876
2059 power-domains 1877 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2060 interconnects 1878 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
2061 1879 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
2062 interconnect- 1880 interconnect-names = "dma-mem", "write";
2063 iommus = <&sm 1881 iommus = <&smmu TEGRA194_SID_NVJPG>;
2064 dma-coherent; 1882 dma-coherent;
2065 }; 1883 };
2066 1884
2067 nvdec@15480000 { 1885 nvdec@15480000 {
2068 compatible = 1886 compatible = "nvidia,tegra194-nvdec";
2069 reg = <0x0 0x !! 1887 reg = <0x15480000 0x00040000>;
2070 clocks = <&bp 1888 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2071 clock-names = 1889 clock-names = "nvdec";
2072 resets = <&bp 1890 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2073 reset-names = 1891 reset-names = "nvdec";
2074 1892
2075 power-domains 1893 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2076 interconnects 1894 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
2077 1895 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
2078 1896 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
2079 interconnect- 1897 interconnect-names = "dma-mem", "read-1", "write";
2080 iommus = <&sm 1898 iommus = <&smmu TEGRA194_SID_NVDEC>;
2081 dma-coherent; 1899 dma-coherent;
2082 1900
2083 nvidia,host1x 1901 nvidia,host1x-class = <0xf0>;
2084 }; 1902 };
2085 1903
2086 nvenc@154c0000 { 1904 nvenc@154c0000 {
2087 compatible = 1905 compatible = "nvidia,tegra194-nvenc";
2088 reg = <0x0 0x !! 1906 reg = <0x154c0000 0x40000>;
2089 clocks = <&bp 1907 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2090 clock-names = 1908 clock-names = "nvenc";
2091 resets = <&bp 1909 resets = <&bpmp TEGRA194_RESET_NVENC>;
2092 reset-names = 1910 reset-names = "nvenc";
2093 1911
2094 power-domains 1912 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2095 interconnects 1913 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
2096 1914 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
2097 1915 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
2098 interconnect- 1916 interconnect-names = "dma-mem", "read-1", "write";
2099 iommus = <&sm 1917 iommus = <&smmu TEGRA194_SID_NVENC>;
2100 dma-coherent; 1918 dma-coherent;
2101 1919
2102 nvidia,host1x 1920 nvidia,host1x-class = <0x21>;
2103 }; 1921 };
2104 1922
2105 dpaux0: dpaux@155c000 1923 dpaux0: dpaux@155c0000 {
2106 compatible = 1924 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 1925 reg = <0x155c0000 0x10000>;
2108 interrupts = 1926 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 1927 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 1928 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 1929 clock-names = "dpaux", "parent";
2112 resets = <&bp 1930 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 1931 reset-names = "dpaux";
2114 status = "dis 1932 status = "disabled";
2115 1933
2116 power-domains 1934 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 1935
2118 state_dpaux0_ 1936 state_dpaux0_aux: pinmux-aux {
2119 group 1937 groups = "dpaux-io";
2120 funct 1938 function = "aux";
2121 }; 1939 };
2122 1940
2123 state_dpaux0_ 1941 state_dpaux0_i2c: pinmux-i2c {
2124 group 1942 groups = "dpaux-io";
2125 funct 1943 function = "i2c";
2126 }; 1944 };
2127 1945
2128 state_dpaux0_ 1946 state_dpaux0_off: pinmux-off {
2129 group 1947 groups = "dpaux-io";
2130 funct 1948 function = "off";
2131 }; 1949 };
2132 1950
2133 i2c-bus { 1951 i2c-bus {
2134 #addr 1952 #address-cells = <1>;
2135 #size 1953 #size-cells = <0>;
2136 }; 1954 };
2137 }; 1955 };
2138 1956
2139 dpaux1: dpaux@155d000 1957 dpaux1: dpaux@155d0000 {
2140 compatible = 1958 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1959 reg = <0x155d0000 0x10000>;
2142 interrupts = 1960 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1961 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1962 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1963 clock-names = "dpaux", "parent";
2146 resets = <&bp 1964 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 1965 reset-names = "dpaux";
2148 status = "dis 1966 status = "disabled";
2149 1967
2150 power-domains 1968 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 1969
2152 state_dpaux1_ 1970 state_dpaux1_aux: pinmux-aux {
2153 group 1971 groups = "dpaux-io";
2154 funct 1972 function = "aux";
2155 }; 1973 };
2156 1974
2157 state_dpaux1_ 1975 state_dpaux1_i2c: pinmux-i2c {
2158 group 1976 groups = "dpaux-io";
2159 funct 1977 function = "i2c";
2160 }; 1978 };
2161 1979
2162 state_dpaux1_ 1980 state_dpaux1_off: pinmux-off {
2163 group 1981 groups = "dpaux-io";
2164 funct 1982 function = "off";
2165 }; 1983 };
2166 1984
2167 i2c-bus { 1985 i2c-bus {
2168 #addr 1986 #address-cells = <1>;
2169 #size 1987 #size-cells = <0>;
2170 }; 1988 };
2171 }; 1989 };
2172 1990
2173 dpaux2: dpaux@155e000 1991 dpaux2: dpaux@155e0000 {
2174 compatible = 1992 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 1993 reg = <0x155e0000 0x10000>;
2176 interrupts = 1994 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 1995 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 1996 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 1997 clock-names = "dpaux", "parent";
2180 resets = <&bp 1998 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 1999 reset-names = "dpaux";
2182 status = "dis 2000 status = "disabled";
2183 2001
2184 power-domains 2002 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 2003
2186 state_dpaux2_ 2004 state_dpaux2_aux: pinmux-aux {
2187 group 2005 groups = "dpaux-io";
2188 funct 2006 function = "aux";
2189 }; 2007 };
2190 2008
2191 state_dpaux2_ 2009 state_dpaux2_i2c: pinmux-i2c {
2192 group 2010 groups = "dpaux-io";
2193 funct 2011 function = "i2c";
2194 }; 2012 };
2195 2013
2196 state_dpaux2_ 2014 state_dpaux2_off: pinmux-off {
2197 group 2015 groups = "dpaux-io";
2198 funct 2016 function = "off";
2199 }; 2017 };
2200 2018
2201 i2c-bus { 2019 i2c-bus {
2202 #addr 2020 #address-cells = <1>;
2203 #size 2021 #size-cells = <0>;
2204 }; 2022 };
2205 }; 2023 };
2206 2024
2207 dpaux3: dpaux@155f000 2025 dpaux3: dpaux@155f0000 {
2208 compatible = 2026 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 2027 reg = <0x155f0000 0x10000>;
2210 interrupts = 2028 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 2029 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 2030 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 2031 clock-names = "dpaux", "parent";
2214 resets = <&bp 2032 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 2033 reset-names = "dpaux";
2216 status = "dis 2034 status = "disabled";
2217 2035
2218 power-domains 2036 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 2037
2220 state_dpaux3_ 2038 state_dpaux3_aux: pinmux-aux {
2221 group 2039 groups = "dpaux-io";
2222 funct 2040 function = "aux";
2223 }; 2041 };
2224 2042
2225 state_dpaux3_ 2043 state_dpaux3_i2c: pinmux-i2c {
2226 group 2044 groups = "dpaux-io";
2227 funct 2045 function = "i2c";
2228 }; 2046 };
2229 2047
2230 state_dpaux3_ 2048 state_dpaux3_off: pinmux-off {
2231 group 2049 groups = "dpaux-io";
2232 funct 2050 function = "off";
2233 }; 2051 };
2234 2052
2235 i2c-bus { 2053 i2c-bus {
2236 #addr 2054 #address-cells = <1>;
2237 #size 2055 #size-cells = <0>;
2238 }; 2056 };
2239 }; 2057 };
2240 2058
2241 nvenc@15a80000 { 2059 nvenc@15a80000 {
2242 compatible = 2060 compatible = "nvidia,tegra194-nvenc";
2243 reg = <0x0 0x !! 2061 reg = <0x15a80000 0x00040000>;
2244 clocks = <&bp 2062 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2245 clock-names = 2063 clock-names = "nvenc";
2246 resets = <&bp 2064 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2247 reset-names = 2065 reset-names = "nvenc";
2248 2066
2249 power-domains 2067 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2250 interconnects 2068 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2251 2069 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2252 2070 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2253 interconnect- 2071 interconnect-names = "dma-mem", "read-1", "write";
2254 iommus = <&sm 2072 iommus = <&smmu TEGRA194_SID_NVENC1>;
2255 dma-coherent; 2073 dma-coherent;
2256 2074
2257 nvidia,host1x 2075 nvidia,host1x-class = <0x22>;
2258 }; 2076 };
2259 2077
2260 sor0: sor@15b00000 { 2078 sor0: sor@15b00000 {
2261 compatible = 2079 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 2080 reg = <0x15b00000 0x40000>;
2263 interrupts = 2081 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 2082 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 2083 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 2084 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 2085 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 2086 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 2087 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 2088 clock-names = "sor", "out", "parent", "dp", "safe",
2271 2089 "pad";
2272 resets = <&bp 2090 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 2091 reset-names = "sor";
2274 pinctrl-0 = < 2092 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 2093 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 2094 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 2095 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 2096 status = "disabled";
2279 2097
2280 power-domains 2098 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 2099 nvidia,interface = <0>;
2282 }; 2100 };
2283 2101
2284 sor1: sor@15b40000 { 2102 sor1: sor@15b40000 {
2285 compatible = 2103 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 2104 reg = <0x15b40000 0x40000>;
2287 interrupts = 2105 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 2106 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 2107 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 2108 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 2109 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 2110 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 2111 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 2112 clock-names = "sor", "out", "parent", "dp", "safe",
2295 2113 "pad";
2296 resets = <&bp 2114 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 2115 reset-names = "sor";
2298 pinctrl-0 = < 2116 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 2117 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 2118 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 2119 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 2120 status = "disabled";
2303 2121
2304 power-domains 2122 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 2123 nvidia,interface = <1>;
2306 }; 2124 };
2307 2125
2308 sor2: sor@15b80000 { 2126 sor2: sor@15b80000 {
2309 compatible = 2127 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 2128 reg = <0x15b80000 0x40000>;
2311 interrupts = 2129 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 2130 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 2131 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 2132 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 2133 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 2134 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 2135 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 2136 clock-names = "sor", "out", "parent", "dp", "safe",
2319 2137 "pad";
2320 resets = <&bp 2138 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 2139 reset-names = "sor";
2322 pinctrl-0 = < 2140 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 2141 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 2142 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 2143 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 2144 status = "disabled";
2327 2145
2328 power-domains 2146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 2147 nvidia,interface = <2>;
2330 }; 2148 };
2331 2149
2332 sor3: sor@15bc0000 { 2150 sor3: sor@15bc0000 {
2333 compatible = 2151 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 2152 reg = <0x15bc0000 0x40000>;
2335 interrupts = 2153 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 2154 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 2155 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 2156 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 2157 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 2158 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 2159 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 2160 clock-names = "sor", "out", "parent", "dp", "safe",
2343 2161 "pad";
2344 resets = <&bp 2162 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 2163 reset-names = "sor";
2346 pinctrl-0 = < 2164 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 2165 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 2166 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 2167 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 2168 status = "disabled";
2351 2169
2352 power-domains 2170 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 2171 nvidia,interface = <3>;
2354 }; 2172 };
2355 }; 2173 };
2356 2174
2357 pcie@14100000 { <<
2358 compatible = "nvidia, <<
2359 power-domains = <&bpm <<
2360 reg = <0x00 0x1410000 <<
2361 <0x00 0x3000000 <<
2362 <0x00 0x3004000 <<
2363 <0x00 0x3008000 <<
2364 reg-names = "appl", " <<
2365 <<
2366 status = "disabled"; <<
2367 <<
2368 #address-cells = <3>; <<
2369 #size-cells = <2>; <<
2370 device_type = "pci"; <<
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 <<
2377 resets = <&bpmp TEGRA <<
2378 <&bpmp TEGRA <<
2379 reset-names = "apb", <<
2380 <<
2381 interrupts = <GIC_SPI <<
2382 <GIC_SPI <<
2383 interrupt-names = "in <<
2384 <<
2385 #interrupt-cells = <1 <<
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 <<
2389 nvidia,bpmp = <&bpmp <<
2390 <<
2391 nvidia,aspm-cmrt-us = <<
2392 nvidia,aspm-pwr-on-t- <<
2393 nvidia,aspm-l0s-entra <<
2394 <<
2395 bus-range = <0x0 0xff <<
2396 <<
2397 ranges = <0x43000000 <<
2398 <0x02000000 <<
2399 <0x01000000 <<
2400 <<
2401 interconnects = <&mc <<
2402 <&mc <<
2403 interconnect-names = <<
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 <<
2409 pcie@14120000 { <<
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 <<
2418 status = "disabled"; <<
2419 <<
2420 #address-cells = <3>; <<
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 <<
2426 clocks = <&bpmp TEGRA <<
2427 clock-names = "core"; <<
2428 <<
2429 resets = <&bpmp TEGRA <<
2430 <&bpmp TEGRA <<
2431 reset-names = "apb", <<
2432 <<
2433 interrupts = <GIC_SPI <<
2434 <GIC_SPI <<
2435 interrupt-names = "in <<
2436 <<
2437 #interrupt-cells = <1 <<
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 <<
2441 nvidia,bpmp = <&bpmp <<
2442 <<
2443 nvidia,aspm-cmrt-us = <<
2444 nvidia,aspm-pwr-on-t- <<
2445 nvidia,aspm-l0s-entra <<
2446 <<
2447 bus-range = <0x0 0xff <<
2448 <<
2449 ranges = <0x43000000 <<
2450 <0x02000000 <<
2451 <0x01000000 <<
2452 <<
2453 interconnects = <&mc <<
2454 <&mc <<
2455 interconnect-names = <<
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 <<
2461 pcie@14140000 { <<
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 <<
2470 status = "disabled"; <<
2471 <<
2472 #address-cells = <3>; <<
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 <<
2478 clocks = <&bpmp TEGRA <<
2479 clock-names = "core"; <<
2480 <<
2481 resets = <&bpmp TEGRA <<
2482 <&bpmp TEGRA <<
2483 reset-names = "apb", <<
2484 <<
2485 interrupts = <GIC_SPI <<
2486 <GIC_SPI <<
2487 interrupt-names = "in <<
2488 <<
2489 #interrupt-cells = <1 <<
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 <<
2493 nvidia,bpmp = <&bpmp <<
2494 <<
2495 nvidia,aspm-cmrt-us = <<
2496 nvidia,aspm-pwr-on-t- <<
2497 nvidia,aspm-l0s-entra <<
2498 <<
2499 bus-range = <0x0 0xff <<
2500 <<
2501 ranges = <0x43000000 <<
2502 <0x02000000 <<
2503 <0x01000000 <<
2504 <<
2505 interconnects = <&mc <<
2506 <&mc <<
2507 interconnect-names = <<
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 <<
2513 pcie@14160000 { <<
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 <<
2522 status = "disabled"; <<
2523 <<
2524 #address-cells = <3>; <<
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 <<
2530 clocks = <&bpmp TEGRA <<
2531 clock-names = "core"; <<
2532 <<
2533 resets = <&bpmp TEGRA <<
2534 <&bpmp TEGRA <<
2535 reset-names = "apb", <<
2536 <<
2537 interrupts = <GIC_SPI <<
2538 <GIC_SPI <<
2539 interrupt-names = "in <<
2540 <<
2541 #interrupt-cells = <1 <<
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 <<
2545 nvidia,bpmp = <&bpmp <<
2546 <<
2547 nvidia,aspm-cmrt-us = <<
2548 nvidia,aspm-pwr-on-t- <<
2549 nvidia,aspm-l0s-entra <<
2550 <<
2551 bus-range = <0x0 0xff <<
2552 <<
2553 ranges = <0x43000000 <<
2554 <0x02000000 <<
2555 <0x01000000 <<
2556 <<
2557 interconnects = <&mc <<
2558 <&mc <<
2559 interconnect-names = <<
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 <<
2565 pcie-ep@14160000 { <<
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 <<
2574 status = "disabled"; <<
2575 <<
2576 num-lanes = <4>; <<
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 <<
2580 clocks = <&bpmp TEGRA <<
2581 clock-names = "core"; <<
2582 <<
2583 resets = <&bpmp TEGRA <<
2584 <&bpmp TEGRA <<
2585 reset-names = "apb", <<
2586 <<
2587 interrupts = <GIC_SPI <<
2588 interrupt-names = "in <<
2589 <<
2590 nvidia,bpmp = <&bpmp <<
2591 <<
2592 nvidia,aspm-cmrt-us = <<
2593 nvidia,aspm-pwr-on-t- <<
2594 nvidia,aspm-l0s-entra <<
2595 <<
2596 interconnects = <&mc <<
2597 <&mc <<
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 <<
2604 pcie@14180000 { <<
2605 compatible = "nvidia, <<
2606 power-domains = <&bpm <<
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 <<
2613 status = "disabled"; <<
2614 <<
2615 #address-cells = <3>; <<
2616 #size-cells = <2>; <<
2617 device_type = "pci"; <<
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 <<
2621 clocks = <&bpmp TEGRA <<
2622 clock-names = "core"; <<
2623 <<
2624 resets = <&bpmp TEGRA <<
2625 <&bpmp TEGRA <<
2626 reset-names = "apb", <<
2627 <<
2628 interrupts = <GIC_SPI <<
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 <<
2632 #interrupt-cells = <1 <<
2633 interrupt-map-mask = <<
2634 interrupt-map = <0 0 <<
2635 <<
2636 nvidia,bpmp = <&bpmp <<
2637 <<
2638 nvidia,aspm-cmrt-us = <<
2639 nvidia,aspm-pwr-on-t- <<
2640 nvidia,aspm-l0s-entra <<
2641 <<
2642 bus-range = <0x0 0xff <<
2643 <<
2644 ranges = <0x43000000 <<
2645 <0x02000000 <<
2646 <0x01000000 <<
2647 <<
2648 interconnects = <&mc <<
2649 <&mc <<
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 <<
2656 pcie-ep@14180000 { <<
2657 compatible = "nvidia, <<
2658 power-domains = <&bpm <<
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 <<
2665 status = "disabled"; <<
2666 <<
2667 num-lanes = <8>; <<
2668 num-ib-windows = <2>; <<
2669 num-ob-windows = <8>; <<
2670 <<
2671 clocks = <&bpmp TEGRA <<
2672 clock-names = "core"; <<
2673 <<
2674 resets = <&bpmp TEGRA <<
2675 <&bpmp TEGRA <<
2676 reset-names = "apb", <<
2677 <<
2678 interrupts = <GIC_SPI <<
2679 interrupt-names = "in <<
2680 <<
2681 nvidia,bpmp = <&bpmp <<
2682 <<
2683 nvidia,aspm-cmrt-us = <<
2684 nvidia,aspm-pwr-on-t- <<
2685 nvidia,aspm-l0s-entra <<
2686 <<
2687 interconnects = <&mc <<
2688 <&mc <<
2689 interconnect-names = <<
2690 iommu-map = <0x0 &smm <<
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 <<
2695 pcie@141a0000 { <<
2696 compatible = "nvidia, <<
2697 power-domains = <&bpm <<
2698 reg = <0x00 0x141a000 <<
2699 <0x00 0x3a00000 <<
2700 <0x00 0x3a04000 <<
2701 <0x00 0x3a08000 <<
2702 reg-names = "appl", " <<
2703 <<
2704 status = "disabled"; <<
2705 <<
2706 #address-cells = <3>; <<
2707 #size-cells = <2>; <<
2708 device_type = "pci"; <<
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 <<
2712 pinctrl-names = "defa <<
2713 pinctrl-0 = <&pex_rst <<
2714 <<
2715 clocks = <&bpmp TEGRA <<
2716 clock-names = "core"; <<
2717 <<
2718 resets = <&bpmp TEGRA <<
2719 <&bpmp TEGRA <<
2720 reset-names = "apb", <<
2721 <<
2722 interrupts = <GIC_SPI <<
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 <<
2726 nvidia,bpmp = <&bpmp <<
2727 <<
2728 #interrupt-cells = <1 <<
2729 interrupt-map-mask = <<
2730 interrupt-map = <0 0 <<
2731 <<
2732 nvidia,aspm-cmrt-us = <<
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 <<
2736 bus-range = <0x0 0xff <<
2737 <<
2738 ranges = <0x43000000 <<
2739 <0x02000000 <<
2740 <0x01000000 <<
2741 <<
2742 interconnects = <&mc <<
2743 <&mc <<
2744 interconnect-names = <<
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 <<
2750 pcie-ep@141a0000 { <<
2751 compatible = "nvidia, <<
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 <<
2759 status = "disabled"; <<
2760 <<
2761 num-lanes = <8>; <<
2762 num-ib-windows = <2>; <<
2763 num-ob-windows = <8>; <<
2764 <<
2765 pinctrl-names = "defa <<
2766 pinctrl-0 = <&pex_clk <<
2767 <<
2768 clocks = <&bpmp TEGRA <<
2769 clock-names = "core"; <<
2770 <<
2771 resets = <&bpmp TEGRA <<
2772 <&bpmp TEGRA <<
2773 reset-names = "apb", <<
2774 <<
2775 interrupts = <GIC_SPI <<
2776 interrupt-names = "in <<
2777 <<
2778 nvidia,bpmp = <&bpmp <<
2779 <<
2780 nvidia,aspm-cmrt-us = <<
2781 nvidia,aspm-pwr-on-t- <<
2782 nvidia,aspm-l0s-entra <<
2783 <<
2784 interconnects = <&mc <<
2785 <&mc <<
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 <<
2792 gpu@17000000 { 2175 gpu@17000000 {
2793 compatible = "nvidia, 2176 compatible = "nvidia,gv11b";
2794 reg = <0x0 0x17000000 !! 2177 reg = <0x17000000 0x1000000>,
2795 <0x0 0x18000000 !! 2178 <0x18000000 0x1000000>;
2796 interrupts = <GIC_SPI 2179 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 2180 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2798 interrupt-names = "st 2181 interrupt-names = "stall", "nonstall";
2799 clocks = <&bpmp TEGRA 2182 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800 <&bpmp TEGRA 2183 <&bpmp TEGRA194_CLK_GPU_PWR>,
2801 <&bpmp TEGRA 2184 <&bpmp TEGRA194_CLK_FUSE>;
2802 clock-names = "gpu", 2185 clock-names = "gpu", "pwr", "fuse";
2803 resets = <&bpmp TEGRA 2186 resets = <&bpmp TEGRA194_RESET_GPU>;
2804 reset-names = "gpu"; 2187 reset-names = "gpu";
2805 dma-coherent; 2188 dma-coherent;
2806 2189
2807 power-domains = <&bpm 2190 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2808 interconnects = <&mc 2191 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2809 <&mc 2192 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2810 <&mc 2193 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2811 <&mc 2194 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2812 <&mc 2195 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2813 <&mc 2196 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2814 <&mc 2197 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2815 <&mc 2198 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2816 <&mc 2199 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2817 <&mc 2200 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2818 <&mc 2201 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2819 <&mc 2202 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2820 interconnect-names = 2203 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2821 2204 "read-1", "read-1-hp", "write-1",
2822 2205 "read-2", "read-2-hp", "write-2",
2823 2206 "read-3", "read-3-hp", "write-3";
2824 }; 2207 };
2825 }; 2208 };
2826 2209
>> 2210 pcie@14100000 {
>> 2211 compatible = "nvidia,tegra194-pcie";
>> 2212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2213 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
>> 2214 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2215 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2216 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2217 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2218
>> 2219 status = "disabled";
>> 2220
>> 2221 #address-cells = <3>;
>> 2222 #size-cells = <2>;
>> 2223 device_type = "pci";
>> 2224 num-lanes = <1>;
>> 2225 linux,pci-domain = <1>;
>> 2226
>> 2227 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
>> 2228 clock-names = "core";
>> 2229
>> 2230 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 2231 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 2232 reset-names = "apb", "core";
>> 2233
>> 2234 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2235 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2236 interrupt-names = "intr", "msi";
>> 2237
>> 2238 #interrupt-cells = <1>;
>> 2239 interrupt-map-mask = <0 0 0 0>;
>> 2240 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 2241
>> 2242 nvidia,bpmp = <&bpmp 1>;
>> 2243
>> 2244 nvidia,aspm-cmrt-us = <60>;
>> 2245 nvidia,aspm-pwr-on-t-us = <20>;
>> 2246 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2247
>> 2248 bus-range = <0x0 0xff>;
>> 2249
>> 2250 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2251 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 2252 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2253
>> 2254 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
>> 2255 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
>> 2256 interconnect-names = "dma-mem", "write";
>> 2257 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
>> 2258 iommu-map-mask = <0x0>;
>> 2259 dma-coherent;
>> 2260 };
>> 2261
>> 2262 pcie@14120000 {
>> 2263 compatible = "nvidia,tegra194-pcie";
>> 2264 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2265 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
>> 2266 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2267 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2268 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2269 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2270
>> 2271 status = "disabled";
>> 2272
>> 2273 #address-cells = <3>;
>> 2274 #size-cells = <2>;
>> 2275 device_type = "pci";
>> 2276 num-lanes = <1>;
>> 2277 linux,pci-domain = <2>;
>> 2278
>> 2279 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
>> 2280 clock-names = "core";
>> 2281
>> 2282 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 2283 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 2284 reset-names = "apb", "core";
>> 2285
>> 2286 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2287 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2288 interrupt-names = "intr", "msi";
>> 2289
>> 2290 #interrupt-cells = <1>;
>> 2291 interrupt-map-mask = <0 0 0 0>;
>> 2292 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 2293
>> 2294 nvidia,bpmp = <&bpmp 2>;
>> 2295
>> 2296 nvidia,aspm-cmrt-us = <60>;
>> 2297 nvidia,aspm-pwr-on-t-us = <20>;
>> 2298 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2299
>> 2300 bus-range = <0x0 0xff>;
>> 2301
>> 2302 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2303 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 2304 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2305
>> 2306 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
>> 2307 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
>> 2308 interconnect-names = "dma-mem", "write";
>> 2309 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
>> 2310 iommu-map-mask = <0x0>;
>> 2311 dma-coherent;
>> 2312 };
>> 2313
>> 2314 pcie@14140000 {
>> 2315 compatible = "nvidia,tegra194-pcie";
>> 2316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2317 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
>> 2318 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2319 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2320 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2321 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2322
>> 2323 status = "disabled";
>> 2324
>> 2325 #address-cells = <3>;
>> 2326 #size-cells = <2>;
>> 2327 device_type = "pci";
>> 2328 num-lanes = <1>;
>> 2329 linux,pci-domain = <3>;
>> 2330
>> 2331 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
>> 2332 clock-names = "core";
>> 2333
>> 2334 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 2335 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 2336 reset-names = "apb", "core";
>> 2337
>> 2338 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2339 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2340 interrupt-names = "intr", "msi";
>> 2341
>> 2342 #interrupt-cells = <1>;
>> 2343 interrupt-map-mask = <0 0 0 0>;
>> 2344 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>> 2345
>> 2346 nvidia,bpmp = <&bpmp 3>;
>> 2347
>> 2348 nvidia,aspm-cmrt-us = <60>;
>> 2349 nvidia,aspm-pwr-on-t-us = <20>;
>> 2350 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2351
>> 2352 bus-range = <0x0 0xff>;
>> 2353
>> 2354 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2355 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
>> 2356 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2357
>> 2358 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
>> 2359 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
>> 2360 interconnect-names = "dma-mem", "write";
>> 2361 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
>> 2362 iommu-map-mask = <0x0>;
>> 2363 dma-coherent;
>> 2364 };
>> 2365
>> 2366 pcie@14160000 {
>> 2367 compatible = "nvidia,tegra194-pcie";
>> 2368 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 2369 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 2370 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2371 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2372 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2373 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2374
>> 2375 status = "disabled";
>> 2376
>> 2377 #address-cells = <3>;
>> 2378 #size-cells = <2>;
>> 2379 device_type = "pci";
>> 2380 num-lanes = <4>;
>> 2381 linux,pci-domain = <4>;
>> 2382
>> 2383 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 2384 clock-names = "core";
>> 2385
>> 2386 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 2387 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2388 reset-names = "apb", "core";
>> 2389
>> 2390 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2391 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2392 interrupt-names = "intr", "msi";
>> 2393
>> 2394 #interrupt-cells = <1>;
>> 2395 interrupt-map-mask = <0 0 0 0>;
>> 2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 2397
>> 2398 nvidia,bpmp = <&bpmp 4>;
>> 2399
>> 2400 nvidia,aspm-cmrt-us = <60>;
>> 2401 nvidia,aspm-pwr-on-t-us = <20>;
>> 2402 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2403
>> 2404 bus-range = <0x0 0xff>;
>> 2405
>> 2406 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2407 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2408 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2409
>> 2410 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2411 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2412 interconnect-names = "dma-mem", "write";
>> 2413 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2414 iommu-map-mask = <0x0>;
>> 2415 dma-coherent;
>> 2416 };
>> 2417
>> 2418 pcie@14180000 {
>> 2419 compatible = "nvidia,tegra194-pcie";
>> 2420 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2421 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2422 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2423 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2424 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2425 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2426
>> 2427 status = "disabled";
>> 2428
>> 2429 #address-cells = <3>;
>> 2430 #size-cells = <2>;
>> 2431 device_type = "pci";
>> 2432 num-lanes = <8>;
>> 2433 linux,pci-domain = <0>;
>> 2434
>> 2435 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2436 clock-names = "core";
>> 2437
>> 2438 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2439 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2440 reset-names = "apb", "core";
>> 2441
>> 2442 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2443 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2444 interrupt-names = "intr", "msi";
>> 2445
>> 2446 #interrupt-cells = <1>;
>> 2447 interrupt-map-mask = <0 0 0 0>;
>> 2448 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 2449
>> 2450 nvidia,bpmp = <&bpmp 0>;
>> 2451
>> 2452 nvidia,aspm-cmrt-us = <60>;
>> 2453 nvidia,aspm-pwr-on-t-us = <20>;
>> 2454 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2455
>> 2456 bus-range = <0x0 0xff>;
>> 2457
>> 2458 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2459 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2460 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2461
>> 2462 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2463 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2464 interconnect-names = "dma-mem", "write";
>> 2465 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2466 iommu-map-mask = <0x0>;
>> 2467 dma-coherent;
>> 2468 };
>> 2469
>> 2470 pcie@141a0000 {
>> 2471 compatible = "nvidia,tegra194-pcie";
>> 2472 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2473 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2474 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2475 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2476 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2477 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2478
>> 2479 status = "disabled";
>> 2480
>> 2481 #address-cells = <3>;
>> 2482 #size-cells = <2>;
>> 2483 device_type = "pci";
>> 2484 num-lanes = <8>;
>> 2485 linux,pci-domain = <5>;
>> 2486
>> 2487 pinctrl-names = "default";
>> 2488 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> 2489
>> 2490 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2491 clock-names = "core";
>> 2492
>> 2493 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2494 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2495 reset-names = "apb", "core";
>> 2496
>> 2497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2498 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2499 interrupt-names = "intr", "msi";
>> 2500
>> 2501 nvidia,bpmp = <&bpmp 5>;
>> 2502
>> 2503 #interrupt-cells = <1>;
>> 2504 interrupt-map-mask = <0 0 0 0>;
>> 2505 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
>> 2506
>> 2507 nvidia,aspm-cmrt-us = <60>;
>> 2508 nvidia,aspm-pwr-on-t-us = <20>;
>> 2509 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2510
>> 2511 bus-range = <0x0 0xff>;
>> 2512
>> 2513 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2514 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2515 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2516
>> 2517 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2518 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2519 interconnect-names = "dma-mem", "write";
>> 2520 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2521 iommu-map-mask = <0x0>;
>> 2522 dma-coherent;
>> 2523 };
>> 2524
>> 2525 pcie-ep@14160000 {
>> 2526 compatible = "nvidia,tegra194-pcie-ep";
>> 2527 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 2528 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 2529 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2530 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2531 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2532 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2533
>> 2534 status = "disabled";
>> 2535
>> 2536 num-lanes = <4>;
>> 2537 num-ib-windows = <2>;
>> 2538 num-ob-windows = <8>;
>> 2539
>> 2540 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 2541 clock-names = "core";
>> 2542
>> 2543 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 2544 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2545 reset-names = "apb", "core";
>> 2546
>> 2547 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2548 interrupt-names = "intr";
>> 2549
>> 2550 nvidia,bpmp = <&bpmp 4>;
>> 2551
>> 2552 nvidia,aspm-cmrt-us = <60>;
>> 2553 nvidia,aspm-pwr-on-t-us = <20>;
>> 2554 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2555
>> 2556 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2557 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2558 interconnect-names = "dma-mem", "write";
>> 2559 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2560 iommu-map-mask = <0x0>;
>> 2561 dma-coherent;
>> 2562 };
>> 2563
>> 2564 pcie-ep@14180000 {
>> 2565 compatible = "nvidia,tegra194-pcie-ep";
>> 2566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2567 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2568 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2569 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2570 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2571 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2572
>> 2573 status = "disabled";
>> 2574
>> 2575 num-lanes = <8>;
>> 2576 num-ib-windows = <2>;
>> 2577 num-ob-windows = <8>;
>> 2578
>> 2579 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2580 clock-names = "core";
>> 2581
>> 2582 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2583 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2584 reset-names = "apb", "core";
>> 2585
>> 2586 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2587 interrupt-names = "intr";
>> 2588
>> 2589 nvidia,bpmp = <&bpmp 0>;
>> 2590
>> 2591 nvidia,aspm-cmrt-us = <60>;
>> 2592 nvidia,aspm-pwr-on-t-us = <20>;
>> 2593 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2594
>> 2595 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2596 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2597 interconnect-names = "dma-mem", "write";
>> 2598 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2599 iommu-map-mask = <0x0>;
>> 2600 dma-coherent;
>> 2601 };
>> 2602
>> 2603 pcie-ep@141a0000 {
>> 2604 compatible = "nvidia,tegra194-pcie-ep";
>> 2605 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2606 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2607 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2608 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2609 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2610 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2611
>> 2612 status = "disabled";
>> 2613
>> 2614 num-lanes = <8>;
>> 2615 num-ib-windows = <2>;
>> 2616 num-ob-windows = <8>;
>> 2617
>> 2618 pinctrl-names = "default";
>> 2619 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> 2620
>> 2621 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2622 clock-names = "core";
>> 2623
>> 2624 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2625 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2626 reset-names = "apb", "core";
>> 2627
>> 2628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2629 interrupt-names = "intr";
>> 2630
>> 2631 nvidia,bpmp = <&bpmp 5>;
>> 2632
>> 2633 nvidia,aspm-cmrt-us = <60>;
>> 2634 nvidia,aspm-pwr-on-t-us = <20>;
>> 2635 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2636
>> 2637 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2638 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2639 interconnect-names = "dma-mem", "write";
>> 2640 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2641 iommu-map-mask = <0x0>;
>> 2642 dma-coherent;
>> 2643 };
>> 2644
2827 sram@40000000 { 2645 sram@40000000 {
2828 compatible = "nvidia,tegra194 2646 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 2647 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 2648 #address-cells = <1>;
2832 #size-cells = <1>; 2649 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 2650 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 <<
2835 no-memory-wc; 2651 no-memory-wc;
2836 2652
2837 cpu_bpmp_tx: sram@4e000 { 2653 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000 2654 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 2655 label = "cpu-bpmp-tx";
2840 pool; 2656 pool;
2841 }; 2657 };
2842 2658
2843 cpu_bpmp_rx: sram@4f000 { 2659 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000 2660 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 2661 label = "cpu-bpmp-rx";
2846 pool; 2662 pool;
2847 }; 2663 };
2848 }; 2664 };
2849 2665
2850 bpmp: bpmp { 2666 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 2667 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 2668 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 2669 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu 2670 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2855 #clock-cells = <1>; 2671 #clock-cells = <1>;
2856 #reset-cells = <1>; 2672 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 2673 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 2674 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859 <&mc TEGRA194 2675 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860 <&mc TEGRA194 2676 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861 <&mc TEGRA194 2677 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862 interconnect-names = "read", 2678 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863 iommus = <&smmu TEGRA194_SID_ 2679 iommus = <&smmu TEGRA194_SID_BPMP>;
2864 2680
2865 bpmp_i2c: i2c { 2681 bpmp_i2c: i2c {
2866 compatible = "nvidia, 2682 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 2683 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 2684 #address-cells = <1>;
2869 #size-cells = <0>; 2685 #size-cells = <0>;
2870 }; 2686 };
2871 2687
2872 bpmp_thermal: thermal { 2688 bpmp_thermal: thermal {
2873 compatible = "nvidia, 2689 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 2690 #thermal-sensor-cells = <1>;
2875 }; 2691 };
2876 }; 2692 };
2877 2693
2878 cpus { 2694 cpus {
2879 compatible = "nvidia,tegra194 2695 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>; 2696 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>; 2697 #address-cells = <1>;
2882 #size-cells = <0>; 2698 #size-cells = <0>;
2883 2699
2884 cpu0_0: cpu@0 { 2700 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 2701 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 2702 device_type = "cpu";
2887 reg = <0x000>; 2703 reg = <0x000>;
2888 enable-method = "psci 2704 enable-method = "psci";
2889 i-cache-size = <13107 2705 i-cache-size = <131072>;
2890 i-cache-line-size = < 2706 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 2707 i-cache-sets = <512>;
2892 d-cache-size = <65536 2708 d-cache-size = <65536>;
2893 d-cache-line-size = < 2709 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 2710 d-cache-sets = <256>;
2895 next-level-cache = <& 2711 next-level-cache = <&l2c_0>;
2896 }; 2712 };
2897 2713
2898 cpu0_1: cpu@1 { 2714 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 2715 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 2716 device_type = "cpu";
2901 reg = <0x001>; 2717 reg = <0x001>;
2902 enable-method = "psci 2718 enable-method = "psci";
2903 i-cache-size = <13107 2719 i-cache-size = <131072>;
2904 i-cache-line-size = < 2720 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 2721 i-cache-sets = <512>;
2906 d-cache-size = <65536 2722 d-cache-size = <65536>;
2907 d-cache-line-size = < 2723 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 2724 d-cache-sets = <256>;
2909 next-level-cache = <& 2725 next-level-cache = <&l2c_0>;
2910 }; 2726 };
2911 2727
2912 cpu1_0: cpu@100 { 2728 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 2729 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 2730 device_type = "cpu";
2915 reg = <0x100>; 2731 reg = <0x100>;
2916 enable-method = "psci 2732 enable-method = "psci";
2917 i-cache-size = <13107 2733 i-cache-size = <131072>;
2918 i-cache-line-size = < 2734 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 2735 i-cache-sets = <512>;
2920 d-cache-size = <65536 2736 d-cache-size = <65536>;
2921 d-cache-line-size = < 2737 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 2738 d-cache-sets = <256>;
2923 next-level-cache = <& 2739 next-level-cache = <&l2c_1>;
2924 }; 2740 };
2925 2741
2926 cpu1_1: cpu@101 { 2742 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 2743 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 2744 device_type = "cpu";
2929 reg = <0x101>; 2745 reg = <0x101>;
2930 enable-method = "psci 2746 enable-method = "psci";
2931 i-cache-size = <13107 2747 i-cache-size = <131072>;
2932 i-cache-line-size = < 2748 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 2749 i-cache-sets = <512>;
2934 d-cache-size = <65536 2750 d-cache-size = <65536>;
2935 d-cache-line-size = < 2751 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 2752 d-cache-sets = <256>;
2937 next-level-cache = <& 2753 next-level-cache = <&l2c_1>;
2938 }; 2754 };
2939 2755
2940 cpu2_0: cpu@200 { 2756 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 2757 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 2758 device_type = "cpu";
2943 reg = <0x200>; 2759 reg = <0x200>;
2944 enable-method = "psci 2760 enable-method = "psci";
2945 i-cache-size = <13107 2761 i-cache-size = <131072>;
2946 i-cache-line-size = < 2762 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 2763 i-cache-sets = <512>;
2948 d-cache-size = <65536 2764 d-cache-size = <65536>;
2949 d-cache-line-size = < 2765 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 2766 d-cache-sets = <256>;
2951 next-level-cache = <& 2767 next-level-cache = <&l2c_2>;
2952 }; 2768 };
2953 2769
2954 cpu2_1: cpu@201 { 2770 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 2771 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 2772 device_type = "cpu";
2957 reg = <0x201>; 2773 reg = <0x201>;
2958 enable-method = "psci 2774 enable-method = "psci";
2959 i-cache-size = <13107 2775 i-cache-size = <131072>;
2960 i-cache-line-size = < 2776 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 2777 i-cache-sets = <512>;
2962 d-cache-size = <65536 2778 d-cache-size = <65536>;
2963 d-cache-line-size = < 2779 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 2780 d-cache-sets = <256>;
2965 next-level-cache = <& 2781 next-level-cache = <&l2c_2>;
2966 }; 2782 };
2967 2783
2968 cpu3_0: cpu@300 { 2784 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 2785 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 2786 device_type = "cpu";
2971 reg = <0x300>; 2787 reg = <0x300>;
2972 enable-method = "psci 2788 enable-method = "psci";
2973 i-cache-size = <13107 2789 i-cache-size = <131072>;
2974 i-cache-line-size = < 2790 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 2791 i-cache-sets = <512>;
2976 d-cache-size = <65536 2792 d-cache-size = <65536>;
2977 d-cache-line-size = < 2793 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 2794 d-cache-sets = <256>;
2979 next-level-cache = <& 2795 next-level-cache = <&l2c_3>;
2980 }; 2796 };
2981 2797
2982 cpu3_1: cpu@301 { 2798 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 2799 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 2800 device_type = "cpu";
2985 reg = <0x301>; 2801 reg = <0x301>;
2986 enable-method = "psci 2802 enable-method = "psci";
2987 i-cache-size = <13107 2803 i-cache-size = <131072>;
2988 i-cache-line-size = < 2804 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 2805 i-cache-sets = <512>;
2990 d-cache-size = <65536 2806 d-cache-size = <65536>;
2991 d-cache-line-size = < 2807 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 2808 d-cache-sets = <256>;
2993 next-level-cache = <& 2809 next-level-cache = <&l2c_3>;
2994 }; 2810 };
2995 2811
2996 cpu-map { 2812 cpu-map {
2997 cluster0 { 2813 cluster0 {
2998 core0 { 2814 core0 {
2999 cpu = 2815 cpu = <&cpu0_0>;
3000 }; 2816 };
3001 2817
3002 core1 { 2818 core1 {
3003 cpu = 2819 cpu = <&cpu0_1>;
3004 }; 2820 };
3005 }; 2821 };
3006 2822
3007 cluster1 { 2823 cluster1 {
3008 core0 { 2824 core0 {
3009 cpu = 2825 cpu = <&cpu1_0>;
3010 }; 2826 };
3011 2827
3012 core1 { 2828 core1 {
3013 cpu = 2829 cpu = <&cpu1_1>;
3014 }; 2830 };
3015 }; 2831 };
3016 2832
3017 cluster2 { 2833 cluster2 {
3018 core0 { 2834 core0 {
3019 cpu = 2835 cpu = <&cpu2_0>;
3020 }; 2836 };
3021 2837
3022 core1 { 2838 core1 {
3023 cpu = 2839 cpu = <&cpu2_1>;
3024 }; 2840 };
3025 }; 2841 };
3026 2842
3027 cluster3 { 2843 cluster3 {
3028 core0 { 2844 core0 {
3029 cpu = 2845 cpu = <&cpu3_0>;
3030 }; 2846 };
3031 2847
3032 core1 { 2848 core1 {
3033 cpu = 2849 cpu = <&cpu3_1>;
3034 }; 2850 };
3035 }; 2851 };
3036 }; 2852 };
3037 2853
3038 l2c_0: l2-cache0 { 2854 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 2855 cache-size = <2097152>;
3042 cache-line-size = <64 2856 cache-line-size = <64>;
3043 cache-sets = <2048>; 2857 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 2858 next-level-cache = <&l3c>;
3046 }; 2859 };
3047 2860
3048 l2c_1: l2-cache1 { 2861 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 2862 cache-size = <2097152>;
3052 cache-line-size = <64 2863 cache-line-size = <64>;
3053 cache-sets = <2048>; 2864 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 2865 next-level-cache = <&l3c>;
3056 }; 2866 };
3057 2867
3058 l2c_2: l2-cache2 { 2868 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 2869 cache-size = <2097152>;
3062 cache-line-size = <64 2870 cache-line-size = <64>;
3063 cache-sets = <2048>; 2871 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 2872 next-level-cache = <&l3c>;
3066 }; 2873 };
3067 2874
3068 l2c_3: l2-cache3 { 2875 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 2876 cache-size = <2097152>;
3072 cache-line-size = <64 2877 cache-line-size = <64>;
3073 cache-sets = <2048>; 2878 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 2879 next-level-cache = <&l3c>;
3076 }; 2880 };
3077 2881
3078 l3c: l3-cache { 2882 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 2883 cache-size = <4194304>;
3082 cache-line-size = <64 2884 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 2885 cache-sets = <4096>;
3085 }; 2886 };
3086 }; 2887 };
3087 2888
3088 pmu { 2889 pmu {
3089 compatible = "nvidia,carmel-p 2890 compatible = "nvidia,carmel-pmu";
3090 interrupts = <GIC_SPI 384 IRQ 2891 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 385 IRQ 2892 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 386 IRQ 2893 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 387 IRQ 2894 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 388 IRQ 2895 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 389 IRQ 2896 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 390 IRQ 2897 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 391 IRQ 2898 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3098 interrupt-affinity = <&cpu0_0 2899 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3099 &cpu2_0 2900 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3100 }; 2901 };
3101 2902
3102 psci { 2903 psci {
3103 compatible = "arm,psci-1.0"; 2904 compatible = "arm,psci-1.0";
3104 status = "okay"; 2905 status = "okay";
3105 method = "smc"; 2906 method = "smc";
3106 }; 2907 };
3107 2908
3108 tcu: serial { <<
3109 compatible = "nvidia,tegra194 <<
3110 mboxes = <&hsp_top0 TEGRA_HSP <<
3111 <&hsp_aon TEGRA_HSP_ <<
3112 mbox-names = "rx", "tx"; <<
3113 }; <<
3114 <<
3115 sound { 2909 sound {
3116 status = "disabled"; 2910 status = "disabled";
3117 2911
3118 clocks = <&bpmp TEGRA194_CLK_ 2912 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_ 2913 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120 clock-names = "pll_a", "plla_ 2914 clock-names = "pll_a", "plla_out0";
3121 assigned-clocks = <&bpmp TEGR 2915 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGR 2916 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGR 2917 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124 assigned-clock-parents = <0>, 2918 assigned-clock-parents = <0>,
3125 <&bp 2919 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bp 2920 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3127 /* 2921 /*
3128 * PLLA supports dynamic ramp 2922 * PLLA supports dynamic ramp. Below initial rate is chosen
3129 * for this to work and oscil 2923 * for this to work and oscillate between base rates required
3130 * for 8x and 11.025x sample 2924 * for 8x and 11.025x sample rate streams.
3131 */ 2925 */
3132 assigned-clock-rates = <25800 2926 assigned-clock-rates = <258000000>;
>> 2927 };
>> 2928
>> 2929 tcu: serial {
>> 2930 compatible = "nvidia,tegra194-tcu";
>> 2931 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
>> 2932 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
>> 2933 mbox-names = "rx", "tx";
3133 }; 2934 };
3134 2935
3135 thermal-zones { 2936 thermal-zones {
3136 cpu-thermal { 2937 cpu-thermal {
3137 thermal-sensors = <&{ 2938 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 2939 status = "disabled";
3139 }; 2940 };
3140 2941
3141 gpu-thermal { 2942 gpu-thermal {
3142 thermal-sensors = <&{ 2943 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 2944 status = "disabled";
3144 }; 2945 };
3145 2946
3146 aux-thermal { 2947 aux-thermal {
3147 thermal-sensors = <&{ 2948 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 2949 status = "disabled";
3149 }; 2950 };
3150 2951
3151 pllx-thermal { 2952 pllx-thermal {
3152 thermal-sensors = <&{ 2953 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 2954 status = "disabled";
3154 }; 2955 };
3155 2956
3156 ao-thermal { 2957 ao-thermal {
3157 thermal-sensors = <&{ 2958 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 2959 status = "disabled";
3159 }; 2960 };
3160 2961
3161 tj-thermal { 2962 tj-thermal {
3162 thermal-sensors = <&{ 2963 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 2964 status = "disabled";
3164 }; 2965 };
3165 }; 2966 };
3166 2967
3167 timer { 2968 timer {
3168 compatible = "arm,armv8-timer 2969 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 2970 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 2971 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 2972 <GIC_PPI 14
3172 (GIC_CPU_MASK 2973 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 2974 <GIC_PPI 11
3174 (GIC_CPU_MASK 2975 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 2976 <GIC_PPI 10
3176 (GIC_CPU_MASK 2977 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 2978 interrupt-parent = <&gic>;
3178 always-on; 2979 always-on;
3179 }; 2980 };
3180 }; 2981 };
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