1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 11 #include <dt-bindings/memory/tegra194-mc.h>
12 12
13 / { 13 / {
14 compatible = "nvidia,tegra194"; 14 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 /* control backbone */ 19 /* control backbone */
20 bus@0 { 20 bus@0 {
21 compatible = "simple-bus"; 21 compatible = "simple-bus";
>> 22 #address-cells = <1>;
>> 23 #size-cells = <1>;
>> 24 ranges = <0x0 0x0 0x0 0x40000000>;
22 25
23 #address-cells = <2>; !! 26 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 27 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 28 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 29 <0x0010f000 0x1000>;
31 }; 30 };
32 31
33 gpio: gpio@2200000 { 32 gpio: gpio@2200000 {
34 compatible = "nvidia,t 33 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 34 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 35 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 36 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
86 #interrupt-cells = <2> 85 #interrupt-cells = <2>;
87 interrupt-controller; 86 interrupt-controller;
88 #gpio-cells = <2>; 87 #gpio-cells = <2>;
89 gpio-controller; 88 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 89 };
141 90
142 ethernet@2490000 { 91 ethernet@2490000 {
143 compatible = "nvidia,t 92 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 93 "nvidia,tegra186-eqos",
145 "snps,dwc 94 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 95 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 98 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 99 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 100 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 103 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 104 reset-names = "eqos";
156 interconnects = <&mc T 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
157 <&mc T 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
158 interconnect-names = " 107 interconnect-names = "dma-mem", "write";
159 iommus = <&smmu TEGRA1 108 iommus = <&smmu TEGRA194_SID_EQOS>;
160 status = "disabled"; 109 status = "disabled";
161 110
162 snps,write-requests = 111 snps,write-requests = <1>;
163 snps,read-requests = < 112 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 113 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 114 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 115 snps,rxpbl = <8>;
167 }; 116 };
168 117
169 gpcdma: dma-controller@2600000 118 gpcdma: dma-controller@2600000 {
170 compatible = "nvidia,t 119 compatible = "nvidia,tegra194-gpcdma",
171 "nvidia,t 120 "nvidia,tegra186-gpcdma";
172 reg = <0x0 0x2600000 0 !! 121 reg = <0x2600000 0x210000>;
173 resets = <&bpmp TEGRA1 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
174 reset-names = "gpcdma" 123 reset-names = "gpcdma";
175 interrupts = <GIC_SPI !! 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI <<
177 <GIC_SPI 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
207 #dma-cells = <1>; 155 #dma-cells = <1>;
208 iommus = <&smmu TEGRA1 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
209 dma-coherent; 157 dma-coherent;
210 dma-channel-mask = <0x <<
211 status = "okay"; 158 status = "okay";
212 }; 159 };
213 160
214 aconnect@2900000 { 161 aconnect@2900000 {
215 compatible = "nvidia,t 162 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 163 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 164 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 165 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 166 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 168 #address-cells = <1>;
>> 169 #size-cells = <1>;
>> 170 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 171 status = "disabled";
222 172
223 #address-cells = <2>; !! 173 adma: dma-controller@2930000 {
224 #size-cells = <2>; !! 174 compatible = "nvidia,tegra194-adma",
225 ranges = <0x0 0x029000 !! 175 "nvidia,tegra186-adma";
>> 176 reg = <0x02930000 0x20000>;
>> 177 interrupt-parent = <&agic>;
>> 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> 210 #dma-cells = <1>;
>> 211 clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> 212 clock-names = "d_audio";
>> 213 status = "disabled";
>> 214 };
>> 215
>> 216 agic: interrupt-controller@2a40000 {
>> 217 compatible = "nvidia,tegra194-agic",
>> 218 "nvidia,tegra210-agic";
>> 219 #interrupt-cells = <3>;
>> 220 interrupt-controller;
>> 221 reg = <0x02a41000 0x1000>,
>> 222 <0x02a42000 0x2000>;
>> 223 interrupts = <GIC_SPI 145
>> 224 (GIC_CPU_MASK_SIMPLE(4) |
>> 225 IRQ_TYPE_LEVEL_HIGH)>;
>> 226 clocks = <&bpmp TEGRA194_CLK_APE>;
>> 227 clock-names = "clk";
>> 228 status = "disabled";
>> 229 };
226 230
227 tegra_ahub: ahub@29008 231 tegra_ahub: ahub@2900800 {
228 compatible = " 232 compatible = "nvidia,tegra194-ahub",
229 " 233 "nvidia,tegra186-ahub";
230 reg = <0x0 0x0 !! 234 reg = <0x02900800 0x800>;
231 clocks = <&bpm 235 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = 236 clock-names = "ahub";
233 assigned-clock 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock !! 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
235 assigned-clock !! 239 #address-cells = <1>;
>> 240 #size-cells = <1>;
>> 241 ranges = <0x02900800 0x02900800 0x11800>;
236 status = "disa 242 status = "disabled";
237 243
238 #address-cells !! 244 tegra_admaif: admaif@290f000 {
239 #size-cells = !! 245 compatible = "nvidia,tegra194-admaif",
240 ranges = <0x0 !! 246 "nvidia,tegra186-admaif";
>> 247 reg = <0x0290f000 0x1000>;
>> 248 dmas = <&adma 1>, <&adma 1>,
>> 249 <&adma 2>, <&adma 2>,
>> 250 <&adma 3>, <&adma 3>,
>> 251 <&adma 4>, <&adma 4>,
>> 252 <&adma 5>, <&adma 5>,
>> 253 <&adma 6>, <&adma 6>,
>> 254 <&adma 7>, <&adma 7>,
>> 255 <&adma 8>, <&adma 8>,
>> 256 <&adma 9>, <&adma 9>,
>> 257 <&adma 10>, <&adma 10>,
>> 258 <&adma 11>, <&adma 11>,
>> 259 <&adma 12>, <&adma 12>,
>> 260 <&adma 13>, <&adma 13>,
>> 261 <&adma 14>, <&adma 14>,
>> 262 <&adma 15>, <&adma 15>,
>> 263 <&adma 16>, <&adma 16>,
>> 264 <&adma 17>, <&adma 17>,
>> 265 <&adma 18>, <&adma 18>,
>> 266 <&adma 19>, <&adma 19>,
>> 267 <&adma 20>, <&adma 20>;
>> 268 dma-names = "rx1", "tx1",
>> 269 "rx2", "tx2",
>> 270 "rx3", "tx3",
>> 271 "rx4", "tx4",
>> 272 "rx5", "tx5",
>> 273 "rx6", "tx6",
>> 274 "rx7", "tx7",
>> 275 "rx8", "tx8",
>> 276 "rx9", "tx9",
>> 277 "rx10", "tx10",
>> 278 "rx11", "tx11",
>> 279 "rx12", "tx12",
>> 280 "rx13", "tx13",
>> 281 "rx14", "tx14",
>> 282 "rx15", "tx15",
>> 283 "rx16", "tx16",
>> 284 "rx17", "tx17",
>> 285 "rx18", "tx18",
>> 286 "rx19", "tx19",
>> 287 "rx20", "tx20";
>> 288 status = "disabled";
>> 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
>> 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
>> 291 interconnect-names = "dma-mem", "write";
>> 292 iommus = <&smmu TEGRA194_SID_APE>;
>> 293 };
241 294
242 tegra_i2s1: i2 295 tegra_i2s1: i2s@2901000 {
243 compat 296 compatible = "nvidia,tegra194-i2s",
244 297 "nvidia,tegra210-i2s";
245 reg = !! 298 reg = <0x2901000 0x100>;
246 clocks 299 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock- 301 clock-names = "i2s", "sync_input";
249 assign 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assign 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assign 304 assigned-clock-rates = <1536000>;
252 sound- 305 sound-name-prefix = "I2S1";
253 status 306 status = "disabled";
254 }; 307 };
255 308
256 tegra_i2s2: i2 309 tegra_i2s2: i2s@2901100 {
257 compat 310 compatible = "nvidia,tegra194-i2s",
258 311 "nvidia,tegra210-i2s";
259 reg = !! 312 reg = <0x2901100 0x100>;
260 clocks 313 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock- 315 clock-names = "i2s", "sync_input";
263 assign 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assign 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assign 318 assigned-clock-rates = <1536000>;
266 sound- 319 sound-name-prefix = "I2S2";
267 status 320 status = "disabled";
268 }; 321 };
269 322
270 tegra_i2s3: i2 323 tegra_i2s3: i2s@2901200 {
271 compat 324 compatible = "nvidia,tegra194-i2s",
272 325 "nvidia,tegra210-i2s";
273 reg = !! 326 reg = <0x2901200 0x100>;
274 clocks 327 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock- 329 clock-names = "i2s", "sync_input";
277 assign 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assign 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assign 332 assigned-clock-rates = <1536000>;
280 sound- 333 sound-name-prefix = "I2S3";
281 status 334 status = "disabled";
282 }; 335 };
283 336
284 tegra_i2s4: i2 337 tegra_i2s4: i2s@2901300 {
285 compat 338 compatible = "nvidia,tegra194-i2s",
286 339 "nvidia,tegra210-i2s";
287 reg = !! 340 reg = <0x2901300 0x100>;
288 clocks 341 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock- 343 clock-names = "i2s", "sync_input";
291 assign 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assign 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assign 346 assigned-clock-rates = <1536000>;
294 sound- 347 sound-name-prefix = "I2S4";
295 status 348 status = "disabled";
296 }; 349 };
297 350
298 tegra_i2s5: i2 351 tegra_i2s5: i2s@2901400 {
299 compat 352 compatible = "nvidia,tegra194-i2s",
300 353 "nvidia,tegra210-i2s";
301 reg = !! 354 reg = <0x2901400 0x100>;
302 clocks 355 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock- 357 clock-names = "i2s", "sync_input";
305 assign 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assign 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assign 360 assigned-clock-rates = <1536000>;
308 sound- 361 sound-name-prefix = "I2S5";
309 status 362 status = "disabled";
310 }; 363 };
311 364
312 tegra_i2s6: i2 365 tegra_i2s6: i2s@2901500 {
313 compat 366 compatible = "nvidia,tegra194-i2s",
314 367 "nvidia,tegra210-i2s";
315 reg = !! 368 reg = <0x2901500 0x100>;
316 clocks 369 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock- 371 clock-names = "i2s", "sync_input";
319 assign 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assign 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assign 374 assigned-clock-rates = <1536000>;
322 sound- 375 sound-name-prefix = "I2S6";
323 status 376 status = "disabled";
324 }; 377 };
325 378
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d 379 tegra_dmic1: dmic@2904000 {
419 compat 380 compatible = "nvidia,tegra194-dmic",
420 381 "nvidia,tegra210-dmic";
421 reg = !! 382 reg = <0x2904000 0x100>;
422 clocks 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock- 384 clock-names = "dmic";
424 assign 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assign 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assign 387 assigned-clock-rates = <3072000>;
427 sound- 388 sound-name-prefix = "DMIC1";
428 status 389 status = "disabled";
429 }; 390 };
430 391
431 tegra_dmic2: d 392 tegra_dmic2: dmic@2904100 {
432 compat 393 compatible = "nvidia,tegra194-dmic",
433 394 "nvidia,tegra210-dmic";
434 reg = !! 395 reg = <0x2904100 0x100>;
435 clocks 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock- 397 clock-names = "dmic";
437 assign 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assign 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assign 400 assigned-clock-rates = <3072000>;
440 sound- 401 sound-name-prefix = "DMIC2";
441 status 402 status = "disabled";
442 }; 403 };
443 404
444 tegra_dmic3: d 405 tegra_dmic3: dmic@2904200 {
445 compat 406 compatible = "nvidia,tegra194-dmic",
446 407 "nvidia,tegra210-dmic";
447 reg = !! 408 reg = <0x2904200 0x100>;
448 clocks 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock- 410 clock-names = "dmic";
450 assign 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assign 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assign 413 assigned-clock-rates = <3072000>;
453 sound- 414 sound-name-prefix = "DMIC3";
454 status 415 status = "disabled";
455 }; 416 };
456 417
457 tegra_dmic4: d 418 tegra_dmic4: dmic@2904300 {
458 compat 419 compatible = "nvidia,tegra194-dmic",
459 420 "nvidia,tegra210-dmic";
460 reg = !! 421 reg = <0x2904300 0x100>;
461 clocks 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock- 423 clock-names = "dmic";
463 assign 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assign 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assign 426 assigned-clock-rates = <3072000>;
466 sound- 427 sound-name-prefix = "DMIC4";
467 status 428 status = "disabled";
468 }; 429 };
469 430
470 tegra_dspk1: d 431 tegra_dspk1: dspk@2905000 {
471 compat 432 compatible = "nvidia,tegra194-dspk",
472 433 "nvidia,tegra186-dspk";
473 reg = !! 434 reg = <0x2905000 0x100>;
474 clocks 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock- 436 clock-names = "dspk";
476 assign 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assign 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assign 439 assigned-clock-rates = <12288000>;
479 sound- 440 sound-name-prefix = "DSPK1";
480 status 441 status = "disabled";
481 }; 442 };
482 443
483 tegra_dspk2: d 444 tegra_dspk2: dspk@2905100 {
484 compat 445 compatible = "nvidia,tegra194-dspk",
485 446 "nvidia,tegra186-dspk";
486 reg = !! 447 reg = <0x2905100 0x100>;
487 clocks 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock- 449 clock-names = "dspk";
489 assign 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assign 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assign 452 assigned-clock-rates = <12288000>;
492 sound- 453 sound-name-prefix = "DSPK2";
493 status 454 status = "disabled";
494 }; 455 };
495 456
496 tegra_ope1: pr !! 457 tegra_sfc1: sfc@2902000 {
497 compat !! 458 compatible = "nvidia,tegra194-sfc",
498 !! 459 "nvidia,tegra210-sfc";
499 reg = !! 460 reg = <0x2902000 0x200>;
500 sound- !! 461 sound-name-prefix = "SFC1";
501 status 462 status = "disabled";
>> 463 };
502 464
503 #addre !! 465 tegra_sfc2: sfc@2902200 {
504 #size- !! 466 compatible = "nvidia,tegra194-sfc",
505 ranges !! 467 "nvidia,tegra210-sfc";
506 !! 468 reg = <0x2902200 0x200>;
507 equali !! 469 sound-name-prefix = "SFC2";
508 !! 470 status = "disabled";
509 !! 471 };
510 <<
511 }; <<
512 472
513 dynami !! 473 tegra_sfc3: sfc@2902400 {
514 !! 474 compatible = "nvidia,tegra194-sfc",
515 !! 475 "nvidia,tegra210-sfc";
516 !! 476 reg = <0x2902400 0x200>;
517 }; !! 477 sound-name-prefix = "SFC3";
>> 478 status = "disabled";
>> 479 };
>> 480
>> 481 tegra_sfc4: sfc@2902600 {
>> 482 compatible = "nvidia,tegra194-sfc",
>> 483 "nvidia,tegra210-sfc";
>> 484 reg = <0x2902600 0x200>;
>> 485 sound-name-prefix = "SFC4";
>> 486 status = "disabled";
518 }; 487 };
519 488
520 tegra_mvc1: mv 489 tegra_mvc1: mvc@290a000 {
521 compat 490 compatible = "nvidia,tegra194-mvc",
522 491 "nvidia,tegra210-mvc";
523 reg = !! 492 reg = <0x290a000 0x200>;
524 sound- 493 sound-name-prefix = "MVC1";
525 status 494 status = "disabled";
526 }; 495 };
527 496
528 tegra_mvc2: mv 497 tegra_mvc2: mvc@290a200 {
529 compat 498 compatible = "nvidia,tegra194-mvc",
530 499 "nvidia,tegra210-mvc";
531 reg = !! 500 reg = <0x290a200 0x200>;
532 sound- 501 sound-name-prefix = "MVC2";
533 status 502 status = "disabled";
534 }; 503 };
535 504
>> 505 tegra_amx1: amx@2903000 {
>> 506 compatible = "nvidia,tegra194-amx";
>> 507 reg = <0x2903000 0x100>;
>> 508 sound-name-prefix = "AMX1";
>> 509 status = "disabled";
>> 510 };
>> 511
>> 512 tegra_amx2: amx@2903100 {
>> 513 compatible = "nvidia,tegra194-amx";
>> 514 reg = <0x2903100 0x100>;
>> 515 sound-name-prefix = "AMX2";
>> 516 status = "disabled";
>> 517 };
>> 518
>> 519 tegra_amx3: amx@2903200 {
>> 520 compatible = "nvidia,tegra194-amx";
>> 521 reg = <0x2903200 0x100>;
>> 522 sound-name-prefix = "AMX3";
>> 523 status = "disabled";
>> 524 };
>> 525
>> 526 tegra_amx4: amx@2903300 {
>> 527 compatible = "nvidia,tegra194-amx";
>> 528 reg = <0x2903300 0x100>;
>> 529 sound-name-prefix = "AMX4";
>> 530 status = "disabled";
>> 531 };
>> 532
>> 533 tegra_adx1: adx@2903800 {
>> 534 compatible = "nvidia,tegra194-adx",
>> 535 "nvidia,tegra210-adx";
>> 536 reg = <0x2903800 0x100>;
>> 537 sound-name-prefix = "ADX1";
>> 538 status = "disabled";
>> 539 };
>> 540
>> 541 tegra_adx2: adx@2903900 {
>> 542 compatible = "nvidia,tegra194-adx",
>> 543 "nvidia,tegra210-adx";
>> 544 reg = <0x2903900 0x100>;
>> 545 sound-name-prefix = "ADX2";
>> 546 status = "disabled";
>> 547 };
>> 548
>> 549 tegra_adx3: adx@2903a00 {
>> 550 compatible = "nvidia,tegra194-adx",
>> 551 "nvidia,tegra210-adx";
>> 552 reg = <0x2903a00 0x100>;
>> 553 sound-name-prefix = "ADX3";
>> 554 status = "disabled";
>> 555 };
>> 556
>> 557 tegra_adx4: adx@2903b00 {
>> 558 compatible = "nvidia,tegra194-adx",
>> 559 "nvidia,tegra210-adx";
>> 560 reg = <0x2903b00 0x100>;
>> 561 sound-name-prefix = "ADX4";
>> 562 status = "disabled";
>> 563 };
>> 564
536 tegra_amixer: 565 tegra_amixer: amixer@290bb00 {
537 compat 566 compatible = "nvidia,tegra194-amixer",
538 567 "nvidia,tegra210-amixer";
539 reg = !! 568 reg = <0x290bb00 0x800>;
540 sound- 569 sound-name-prefix = "MIXER1";
541 status 570 status = "disabled";
542 }; 571 };
543 572
544 tegra_admaif: <<
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 <<
595 tegra_asrc: as 573 tegra_asrc: asrc@2910000 {
596 compat 574 compatible = "nvidia,tegra194-asrc",
597 575 "nvidia,tegra186-asrc";
598 reg = !! 576 reg = <0x2910000 0x2000>;
599 sound- 577 sound-name-prefix = "ASRC1";
600 status 578 status = "disabled";
601 }; 579 };
602 }; 580 };
>> 581 };
603 582
604 adma: dma-controller@2 !! 583 pinmux: pinmux@2430000 {
605 compatible = " !! 584 compatible = "nvidia,tegra194-pinmux";
606 " !! 585 reg = <0x2430000 0x17000>,
607 reg = <0x0 0x0 !! 586 <0xc300000 0x4000>;
608 interrupt-pare !! 587
609 interrupts = !! 588 status = "okay";
610 !! 589
611 !! 590 pex_rst_c5_out_state: pex_rst_c5_out {
612 !! 591 pex_rst {
613 !! 592 nvidia,pins = "pex_l5_rst_n_pgg1";
614 !! 593 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
615 !! 594 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
616 !! 595 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
617 !! 596 nvidia,tristate = <TEGRA_PIN_DISABLE>;
618 !! 597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619 !! 598 };
620 <<
621 <<
622 <<
623 <<
624 <<
625 <<
626 <<
627 <<
628 <<
629 <<
630 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 <<
637 <<
638 <<
639 <<
640 <<
641 #dma-cells = < <<
642 clocks = <&bpm <<
643 clock-names = <<
644 status = "disa <<
645 }; 599 };
646 600
647 agic: interrupt-contro !! 601 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
648 compatible = " !! 602 clkreq {
649 " !! 603 nvidia,pins = "pex_l5_clkreq_n_pgg0";
650 #interrupt-cel !! 604 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
651 interrupt-cont !! 605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652 reg = <0x0 0x0 !! 606 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
653 <0x0 0x0 !! 607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
654 interrupts = < !! 608 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655 !! 609 };
656 <<
657 clocks = <&bpm <<
658 clock-names = <<
659 status = "disa <<
660 }; 610 };
661 }; 611 };
662 612
663 mc: memory-controller@2c00000 613 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 614 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 615 reg = <0x02c00000 0x10000>, /* MC-SID */
666 <0x0 0x02c10000 !! 616 <0x02c10000 0x10000>, /* MC Broadcast*/
667 <0x0 0x02c20000 !! 617 <0x02c20000 0x10000>, /* MC0 */
668 <0x0 0x02c30000 !! 618 <0x02c30000 0x10000>, /* MC1 */
669 <0x0 0x02c40000 !! 619 <0x02c40000 0x10000>, /* MC2 */
670 <0x0 0x02c50000 !! 620 <0x02c50000 0x10000>, /* MC3 */
671 <0x0 0x02b80000 !! 621 <0x02b80000 0x10000>, /* MC4 */
672 <0x0 0x02b90000 !! 622 <0x02b90000 0x10000>, /* MC5 */
673 <0x0 0x02ba0000 !! 623 <0x02ba0000 0x10000>, /* MC6 */
674 <0x0 0x02bb0000 !! 624 <0x02bb0000 0x10000>, /* MC7 */
675 <0x0 0x01700000 !! 625 <0x01700000 0x10000>, /* MC8 */
676 <0x0 0x01710000 !! 626 <0x01710000 0x10000>, /* MC9 */
677 <0x0 0x01720000 !! 627 <0x01720000 0x10000>, /* MC10 */
678 <0x0 0x01730000 !! 628 <0x01730000 0x10000>, /* MC11 */
679 <0x0 0x01740000 !! 629 <0x01740000 0x10000>, /* MC12 */
680 <0x0 0x01750000 !! 630 <0x01750000 0x10000>, /* MC13 */
681 <0x0 0x01760000 !! 631 <0x01760000 0x10000>, /* MC14 */
682 <0x0 0x01770000 !! 632 <0x01770000 0x10000>; /* MC15 */
683 reg-names = "sid", "br 633 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
684 "ch4", "ch 634 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
685 "ch11", "c 635 "ch11", "ch12", "ch13", "ch14", "ch15";
686 interrupts = <GIC_SPI 636 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
687 #interconnect-cells = 637 #interconnect-cells = <1>;
688 status = "disabled"; 638 status = "disabled";
689 639
690 #address-cells = <2>; 640 #address-cells = <2>;
691 #size-cells = <2>; 641 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 642
693 <0x0 0x02b800 !! 643 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 644 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 645 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 646
696 /* 647 /*
697 * Bit 39 of addresses 648 * Bit 39 of addresses passing through the memory
698 * controller selects 649 * controller selects the XBAR format used when memory
699 * is accessed. This i 650 * is accessed. This is used to transparently access
700 * memory in the XBAR 651 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 652 * (bit 39 set) or Tegra (bit 39 clear).
702 * 653 *
703 * As a consequence, t 654 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 655 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 656 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 657 * devices require access to the XBAR switch, their
707 * drivers must set th 658 * drivers must set this bit explicitly.
708 * 659 *
709 * Limit the DMA range 660 * Limit the DMA range for memory clients to [38:0].
710 */ 661 */
711 dma-ranges = <0x0 0x0 !! 662 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 663
713 emc: external-memory-c 664 emc: external-memory-controller@2c60000 {
714 compatible = " 665 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 666 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 667 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < 668 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&bpm 669 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 670 clock-names = "emc";
720 671
721 #interconnect- 672 #interconnect-cells = <0>;
722 673
723 nvidia,bpmp = 674 nvidia,bpmp = <&bpmp>;
724 }; 675 };
725 }; 676 };
726 677
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 678 uarta: serial@3100000 {
744 compatible = "nvidia,t 679 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 680 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 681 reg-shift = <2>;
747 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 683 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 684 clock-names = "serial";
749 resets = <&bpmp TEGRA1 685 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 686 reset-names = "serial";
750 status = "disabled"; 687 status = "disabled";
751 }; 688 };
752 689
753 uartb: serial@3110000 { 690 uartb: serial@3110000 {
754 compatible = "nvidia,t 691 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 692 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 693 reg-shift = <2>;
757 interrupts = <GIC_SPI 694 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 695 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 696 clock-names = "serial";
759 resets = <&bpmp TEGRA1 697 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 698 reset-names = "serial";
760 status = "disabled"; 699 status = "disabled";
761 }; 700 };
762 701
763 uartd: serial@3130000 { 702 uartd: serial@3130000 {
764 compatible = "nvidia,t 703 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 704 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 705 reg-shift = <2>;
767 interrupts = <GIC_SPI 706 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 707 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 708 clock-names = "serial";
770 resets = <&bpmp TEGRA1 709 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 710 reset-names = "serial";
772 status = "disabled"; 711 status = "disabled";
773 }; 712 };
774 713
775 uarte: serial@3140000 { 714 uarte: serial@3140000 {
776 compatible = "nvidia,t 715 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 716 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 717 reg-shift = <2>;
779 interrupts = <GIC_SPI 718 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 719 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 720 clock-names = "serial";
782 resets = <&bpmp TEGRA1 721 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 722 reset-names = "serial";
784 status = "disabled"; 723 status = "disabled";
785 }; 724 };
786 725
787 uartf: serial@3150000 { 726 uartf: serial@3150000 {
788 compatible = "nvidia,t 727 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 728 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 729 reg-shift = <2>;
791 interrupts = <GIC_SPI 730 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 731 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 732 clock-names = "serial";
794 resets = <&bpmp TEGRA1 733 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 734 reset-names = "serial";
796 status = "disabled"; 735 status = "disabled";
797 }; 736 };
798 737
799 gen1_i2c: i2c@3160000 { 738 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 739 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 740 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 741 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 742 #address-cells = <1>;
804 #size-cells = <0>; 743 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 744 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 745 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 746 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 747 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 748 status = "disabled";
812 }; 749 };
813 750
814 uarth: serial@3170000 { 751 uarth: serial@3170000 {
815 compatible = "nvidia,t 752 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 753 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 754 reg-shift = <2>;
818 interrupts = <GIC_SPI 755 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 756 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 757 clock-names = "serial";
821 resets = <&bpmp TEGRA1 758 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 759 reset-names = "serial";
823 status = "disabled"; 760 status = "disabled";
824 }; 761 };
825 762
826 cam_i2c: i2c@3180000 { 763 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 764 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 765 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 767 #address-cells = <1>;
831 #size-cells = <0>; 768 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 769 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 770 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 771 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 772 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 773 status = "disabled";
839 }; 774 };
840 775
841 /* shares pads with dpaux1 */ 776 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 777 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 778 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 779 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 781 #address-cells = <1>;
847 #size-cells = <0>; 782 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 783 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 784 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 785 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 786 reset-names = "i2c";
852 pinctrl-0 = <&state_dp 787 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dp 788 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "defau 789 pinctrl-names = "default", "idle";
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 790 status = "disabled";
858 }; 791 };
859 792
860 /* shares pads with dpaux0 */ 793 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 794 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 795 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 796 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 797 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 798 #address-cells = <1>;
866 #size-cells = <0>; 799 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 800 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 801 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 802 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 803 reset-names = "i2c";
871 pinctrl-0 = <&state_dp 804 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dp 805 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "defau 806 pinctrl-names = "default", "idle";
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 807 status = "disabled";
877 }; 808 };
878 809
879 /* shares pads with dpaux2 */ 810 /* shares pads with dpaux2 */
880 dp_aux_ch2_i2c: i2c@31c0000 { 811 dp_aux_ch2_i2c: i2c@31c0000 {
881 compatible = "nvidia,t 812 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 813 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 815 #address-cells = <1>;
885 #size-cells = <0>; 816 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 817 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 818 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 819 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 820 reset-names = "i2c";
890 pinctrl-0 = <&state_dp 821 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dp 822 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "defau 823 pinctrl-names = "default", "idle";
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 824 status = "disabled";
896 }; 825 };
897 826
898 /* shares pads with dpaux3 */ 827 /* shares pads with dpaux3 */
899 dp_aux_ch3_i2c: i2c@31e0000 { 828 dp_aux_ch3_i2c: i2c@31e0000 {
900 compatible = "nvidia,t 829 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 830 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 831 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 832 #address-cells = <1>;
904 #size-cells = <0>; 833 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 834 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 835 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 836 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 837 reset-names = "i2c";
909 pinctrl-0 = <&state_dp 838 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dp 839 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "defau 840 pinctrl-names = "default", "idle";
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; 841 status = "disabled";
915 }; 842 };
916 843
917 spi@3270000 { 844 spi@3270000 {
918 compatible = "nvidia,t 845 compatible = "nvidia,tegra194-qspi";
919 reg = <0x0 0x3270000 0 !! 846 reg = <0x3270000 0x1000>;
920 interrupts = <GIC_SPI 847 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
921 #address-cells = <1>; 848 #address-cells = <1>;
922 #size-cells = <0>; 849 #size-cells = <0>;
923 clocks = <&bpmp TEGRA1 850 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA1 851 <&bpmp TEGRA194_CLK_QSPI0_PM>;
925 clock-names = "qspi", 852 clock-names = "qspi", "qspi_out";
926 resets = <&bpmp TEGRA1 853 resets = <&bpmp TEGRA194_RESET_QSPI0>;
>> 854 reset-names = "qspi";
>> 855 status = "disabled";
>> 856 };
>> 857
>> 858 spi@3300000 {
>> 859 compatible = "nvidia,tegra194-qspi";
>> 860 reg = <0x3300000 0x1000>;
>> 861 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>> 862 #address-cells = <1>;
>> 863 #size-cells = <0>;
>> 864 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
>> 865 <&bpmp TEGRA194_CLK_QSPI1_PM>;
>> 866 clock-names = "qspi", "qspi_out";
>> 867 resets = <&bpmp TEGRA194_RESET_QSPI1>;
>> 868 reset-names = "qspi";
927 status = "disabled"; 869 status = "disabled";
928 }; 870 };
929 871
930 pwm1: pwm@3280000 { 872 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 873 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 874 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 875 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 876 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 877 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 878 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 879 reset-names = "pwm";
937 status = "disabled"; 880 status = "disabled";
938 #pwm-cells = <2>; 881 #pwm-cells = <2>;
939 }; 882 };
940 883
941 pwm2: pwm@3290000 { 884 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 885 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 886 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 887 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 888 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 889 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 890 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 891 reset-names = "pwm";
948 status = "disabled"; 892 status = "disabled";
949 #pwm-cells = <2>; 893 #pwm-cells = <2>;
950 }; 894 };
951 895
952 pwm3: pwm@32a0000 { 896 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 897 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 898 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 899 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 900 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 901 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 902 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 903 reset-names = "pwm";
959 status = "disabled"; 904 status = "disabled";
960 #pwm-cells = <2>; 905 #pwm-cells = <2>;
961 }; 906 };
962 907
963 pwm5: pwm@32c0000 { 908 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 909 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 910 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 911 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 912 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 913 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 914 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 915 reset-names = "pwm";
970 status = "disabled"; 916 status = "disabled";
971 #pwm-cells = <2>; 917 #pwm-cells = <2>;
972 }; 918 };
973 919
974 pwm6: pwm@32d0000 { 920 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 921 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 922 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 923 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 924 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 925 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 926 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 927 reset-names = "pwm";
981 status = "disabled"; 928 status = "disabled";
982 #pwm-cells = <2>; 929 #pwm-cells = <2>;
983 }; 930 };
984 931
985 pwm7: pwm@32e0000 { 932 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 933 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 934 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 935 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 936 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 937 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 938 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 939 reset-names = "pwm";
992 status = "disabled"; 940 status = "disabled";
993 #pwm-cells = <2>; 941 #pwm-cells = <2>;
994 }; 942 };
995 943
996 pwm8: pwm@32f0000 { 944 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 945 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 946 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 947 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 948 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 949 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 950 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 951 reset-names = "pwm";
1003 status = "disabled"; 952 status = "disabled";
1004 #pwm-cells = <2>; 953 #pwm-cells = <2>;
1005 }; 954 };
1006 955
1007 spi@3300000 { <<
1008 compatible = "nvidia, <<
1009 reg = <0x0 0x3300000 <<
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { 956 sdmmc1: mmc@3400000 {
1021 compatible = "nvidia, 957 compatible = "nvidia,tegra194-sdhci";
1022 reg = <0x0 0x03400000 !! 958 reg = <0x03400000 0x10000>;
1023 interrupts = <GIC_SPI 959 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA 960 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA 961 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci" 962 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&b 963 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1028 <&b 964 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1029 assigned-clock-parent 965 assigned-clock-parents =
1030 <&b 966 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1031 <&b 967 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1032 resets = <&bpmp TEGRA 968 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 969 reset-names = "sdhci";
1034 interconnects = <&mc 970 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035 <&mc 971 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036 interconnect-names = 972 interconnect-names = "dma-mem", "write";
1037 iommus = <&smmu TEGRA 973 iommus = <&smmu TEGRA194_SID_SDMMC1>;
1038 pinctrl-names = "sdmm 974 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1039 pinctrl-0 = <&sdmmc1_ 975 pinctrl-0 = <&sdmmc1_3v3>;
1040 pinctrl-1 = <&sdmmc1_ 976 pinctrl-1 = <&sdmmc1_1v8>;
1041 nvidia,pad-autocal-pu 977 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 978 <0x07>;
1043 nvidia,pad-autocal-pu 979 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 980 <0x07>;
1045 nvidia,pad-autocal-pu 981 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 982 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 983 <0x07>;
1048 nvidia,pad-autocal-pu 984 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 985 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 986 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 987 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; 988 sd-uhs-sdr25;
1053 sd-uhs-sdr50; 989 sd-uhs-sdr50;
1054 sd-uhs-ddr50; 990 sd-uhs-ddr50;
1055 sd-uhs-sdr104; 991 sd-uhs-sdr104;
1056 status = "disabled"; 992 status = "disabled";
1057 }; 993 };
1058 994
1059 sdmmc3: mmc@3440000 { 995 sdmmc3: mmc@3440000 {
1060 compatible = "nvidia, 996 compatible = "nvidia,tegra194-sdhci";
1061 reg = <0x0 0x03440000 !! 997 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 998 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA 999 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA 1000 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci" 1001 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&b 1002 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1067 <&b 1003 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1068 assigned-clock-parent 1004 assigned-clock-parents =
1069 <&b 1005 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1070 <&b 1006 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1071 resets = <&bpmp TEGRA 1007 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 1008 reset-names = "sdhci";
1073 interconnects = <&mc 1009 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074 <&mc 1010 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075 interconnect-names = 1011 interconnect-names = "dma-mem", "write";
1076 iommus = <&smmu TEGRA 1012 iommus = <&smmu TEGRA194_SID_SDMMC3>;
1077 pinctrl-names = "sdmm 1013 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1078 pinctrl-0 = <&sdmmc3_ 1014 pinctrl-0 = <&sdmmc3_3v3>;
1079 pinctrl-1 = <&sdmmc3_ 1015 pinctrl-1 = <&sdmmc3_1v8>;
1080 nvidia,pad-autocal-pu 1016 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 1017 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 1018 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 1019 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 1020 <0x07>;
1085 nvidia,pad-autocal-pu 1021 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 1022 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 1023 <0x07>;
1088 nvidia,pad-autocal-pu 1024 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 1025 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 1026 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 1027 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; 1028 sd-uhs-sdr25;
1093 sd-uhs-sdr50; 1029 sd-uhs-sdr50;
1094 sd-uhs-ddr50; 1030 sd-uhs-ddr50;
1095 sd-uhs-sdr104; 1031 sd-uhs-sdr104;
1096 status = "disabled"; 1032 status = "disabled";
1097 }; 1033 };
1098 1034
1099 sdmmc4: mmc@3460000 { 1035 sdmmc4: mmc@3460000 {
1100 compatible = "nvidia, 1036 compatible = "nvidia,tegra194-sdhci";
1101 reg = <0x0 0x03460000 !! 1037 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 1038 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA 1039 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA 1040 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci" 1041 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&b 1042 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 1043 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 1044 assigned-clock-parents =
1109 <&b 1045 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 1046 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 1047 reset-names = "sdhci";
1112 interconnects = <&mc 1048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113 <&mc 1049 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114 interconnect-names = 1050 interconnect-names = "dma-mem", "write";
1115 iommus = <&smmu TEGRA 1051 iommus = <&smmu TEGRA194_SID_SDMMC4>;
1116 nvidia,pad-autocal-pu 1052 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 1053 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 1054 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 1055 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 1056 <0x0a>;
1121 nvidia,pad-autocal-pu 1057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 1059 <0x0a>;
1124 nvidia,default-tap = 1060 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 1061 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 1062 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; 1063 cap-mmc-highspeed;
1128 mmc-ddr-1_8v; 1064 mmc-ddr-1_8v;
1129 mmc-hs200-1_8v; 1065 mmc-hs200-1_8v;
1130 mmc-hs400-1_8v; 1066 mmc-hs400-1_8v;
1131 mmc-hs400-enhanced-st 1067 mmc-hs400-enhanced-strobe;
1132 supports-cqe; 1068 supports-cqe;
1133 status = "disabled"; 1069 status = "disabled";
1134 }; 1070 };
1135 1071
1136 hda@3510000 { 1072 hda@3510000 {
1137 compatible = "nvidia, !! 1073 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 1074 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 1075 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 1076 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA 1077 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA 1078 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", 1079 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA 1080 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA 1081 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", 1082 reset-names = "hda", "hda2hdmi";
1147 power-domains = <&bpm 1083 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc 1084 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149 <&mc 1085 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150 interconnect-names = 1086 interconnect-names = "dma-mem", "write";
1151 iommus = <&smmu TEGRA 1087 iommus = <&smmu TEGRA194_SID_HDA>;
1152 status = "disabled"; 1088 status = "disabled";
1153 }; 1089 };
1154 1090
1155 xusb_padctl: padctl@3520000 { 1091 xusb_padctl: padctl@3520000 {
1156 compatible = "nvidia, 1092 compatible = "nvidia,tegra194-xusb-padctl";
1157 reg = <0x0 0x03520000 !! 1093 reg = <0x03520000 0x1000>,
1158 <0x0 0x03540000 !! 1094 <0x03540000 0x1000>;
1159 reg-names = "padctl", 1095 reg-names = "padctl", "ao";
1160 interrupts = <GIC_SPI 1096 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161 1097
1162 resets = <&bpmp TEGRA 1098 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl 1099 reset-names = "padctl";
1164 1100
1165 status = "disabled"; 1101 status = "disabled";
1166 1102
1167 pads { 1103 pads {
1168 usb2 { 1104 usb2 {
1169 clock 1105 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock 1106 clock-names = "trk";
1171 1107
1172 lanes 1108 lanes {
1173 1109 usb2-0 {
1174 1110 nvidia,function = "xusb";
1175 1111 status = "disabled";
1176 1112 #phy-cells = <0>;
1177 1113 };
1178 1114
1179 1115 usb2-1 {
1180 1116 nvidia,function = "xusb";
1181 1117 status = "disabled";
1182 1118 #phy-cells = <0>;
1183 1119 };
1184 1120
1185 1121 usb2-2 {
1186 1122 nvidia,function = "xusb";
1187 1123 status = "disabled";
1188 1124 #phy-cells = <0>;
1189 1125 };
1190 1126
1191 1127 usb2-3 {
1192 1128 nvidia,function = "xusb";
1193 1129 status = "disabled";
1194 1130 #phy-cells = <0>;
1195 1131 };
1196 }; 1132 };
1197 }; 1133 };
1198 1134
1199 usb3 { 1135 usb3 {
1200 lanes 1136 lanes {
1201 1137 usb3-0 {
1202 1138 nvidia,function = "xusb";
1203 1139 status = "disabled";
1204 1140 #phy-cells = <0>;
1205 1141 };
1206 1142
1207 1143 usb3-1 {
1208 1144 nvidia,function = "xusb";
1209 1145 status = "disabled";
1210 1146 #phy-cells = <0>;
1211 1147 };
1212 1148
1213 1149 usb3-2 {
1214 1150 nvidia,function = "xusb";
1215 1151 status = "disabled";
1216 1152 #phy-cells = <0>;
1217 1153 };
1218 1154
1219 1155 usb3-3 {
1220 1156 nvidia,function = "xusb";
1221 1157 status = "disabled";
1222 1158 #phy-cells = <0>;
1223 1159 };
1224 }; 1160 };
1225 }; 1161 };
1226 }; 1162 };
1227 1163
1228 ports { 1164 ports {
1229 usb2-0 { 1165 usb2-0 {
1230 statu 1166 status = "disabled";
1231 }; 1167 };
1232 1168
1233 usb2-1 { 1169 usb2-1 {
1234 statu 1170 status = "disabled";
1235 }; 1171 };
1236 1172
1237 usb2-2 { 1173 usb2-2 {
1238 statu 1174 status = "disabled";
1239 }; 1175 };
1240 1176
1241 usb2-3 { 1177 usb2-3 {
1242 statu 1178 status = "disabled";
1243 }; 1179 };
1244 1180
1245 usb3-0 { 1181 usb3-0 {
1246 statu 1182 status = "disabled";
1247 }; 1183 };
1248 1184
1249 usb3-1 { 1185 usb3-1 {
1250 statu 1186 status = "disabled";
1251 }; 1187 };
1252 1188
1253 usb3-2 { 1189 usb3-2 {
1254 statu 1190 status = "disabled";
1255 }; 1191 };
1256 1192
1257 usb3-3 { 1193 usb3-3 {
1258 statu 1194 status = "disabled";
1259 }; 1195 };
1260 }; 1196 };
1261 }; 1197 };
1262 1198
1263 usb@3550000 { 1199 usb@3550000 {
1264 compatible = "nvidia, 1200 compatible = "nvidia,tegra194-xudc";
1265 reg = <0x0 0x03550000 !! 1201 reg = <0x03550000 0x8000>,
1266 <0x0 0x03558000 !! 1202 <0x03558000 0x1000>;
1267 reg-names = "base", " 1203 reg-names = "base", "fpci";
1268 interrupts = <GIC_SPI 1204 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&bpmp TEGRA 1205 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA 1206 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA 1207 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA 1208 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", 1209 clock-names = "dev", "ss", "ss_src", "fs_src";
1274 interconnects = <&mc 1210 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1275 <&mc 1211 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1276 interconnect-names = 1212 interconnect-names = "dma-mem", "write";
1277 iommus = <&smmu TEGRA 1213 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1278 power-domains = <&bpm 1214 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpm 1215 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = 1216 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = 1217 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent; <<
1283 status = "disabled"; 1218 status = "disabled";
1284 }; 1219 };
1285 1220
1286 usb@3610000 { 1221 usb@3610000 {
1287 compatible = "nvidia, 1222 compatible = "nvidia,tegra194-xusb";
1288 reg = <0x0 0x03610000 !! 1223 reg = <0x03610000 0x40000>,
1289 <0x0 0x03600000 !! 1224 <0x03600000 0x10000>;
1290 reg-names = "hcd", "f 1225 reg-names = "hcd", "fpci";
1291 1226
1292 interrupts = <GIC_SPI 1227 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 1228 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294 1229
1295 clocks = <&bpmp TEGRA 1230 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA 1231 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA 1232 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA 1233 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA 1234 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA 1235 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA 1236 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA 1237 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA 1238 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_h 1239 clock-names = "xusb_host", "xusb_falcon_src",
1305 "xusb_s 1240 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306 "xusb_f 1241 "xusb_fs_src", "pll_u_480m", "clk_m",
1307 "pll_e" 1242 "pll_e";
1308 interconnects = <&mc 1243 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1309 <&mc 1244 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1310 interconnect-names = 1245 interconnect-names = "dma-mem", "write";
1311 iommus = <&smmu TEGRA 1246 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1312 1247
1313 power-domains = <&bpm 1248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpm 1249 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = 1250 power-domain-names = "xusb_host", "xusb_ss";
1316 1251
1317 nvidia,xusb-padctl = 1252 nvidia,xusb-padctl = <&xusb_padctl>;
1318 status = "disabled"; 1253 status = "disabled";
1319 }; 1254 };
1320 1255
1321 fuse@3820000 { 1256 fuse@3820000 {
1322 compatible = "nvidia, 1257 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 1258 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 1259 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 1260 clock-names = "fuse";
1326 }; 1261 };
1327 1262
1328 gic: interrupt-controller@388 1263 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 1264 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 1265 #interrupt-cells = <3>;
1331 interrupt-controller; 1266 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 1267 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 1268 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 1269 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 1270 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 1271 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 1272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 1273 interrupt-parent = <&gic>;
1339 }; 1274 };
1340 1275
1341 cec@3960000 { 1276 cec@3960000 {
1342 compatible = "nvidia, 1277 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 1278 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 1279 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 1280 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 1281 clock-names = "cec";
1347 status = "disabled"; 1282 status = "disabled";
1348 }; 1283 };
1349 1284
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 1285 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, 1286 compatible = "nvidia,tegra194-hsp";
1362 reg = <0x0 0x03c00000 !! 1287 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 1288 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1289 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1290 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1291 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1292 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1293 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1294 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1295 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1296 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 1297 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 1298 "shared3", "shared4", "shared5", "shared6",
1374 "sh 1299 "shared7";
1375 #mbox-cells = <2>; 1300 #mbox-cells = <2>;
1376 }; 1301 };
1377 1302
1378 p2u_hsio_0: phy@3e10000 { 1303 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 1304 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 1305 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 1306 reg-names = "ctl";
1382 1307
1383 #phy-cells = <0>; 1308 #phy-cells = <0>;
1384 }; 1309 };
1385 1310
1386 p2u_hsio_1: phy@3e20000 { 1311 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 1312 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 1313 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 1314 reg-names = "ctl";
1390 1315
1391 #phy-cells = <0>; 1316 #phy-cells = <0>;
1392 }; 1317 };
1393 1318
1394 p2u_hsio_2: phy@3e30000 { 1319 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 1320 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 1321 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 1322 reg-names = "ctl";
1398 1323
1399 #phy-cells = <0>; 1324 #phy-cells = <0>;
1400 }; 1325 };
1401 1326
1402 p2u_hsio_3: phy@3e40000 { 1327 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 1328 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 1329 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 1330 reg-names = "ctl";
1406 1331
1407 #phy-cells = <0>; 1332 #phy-cells = <0>;
1408 }; 1333 };
1409 1334
1410 p2u_hsio_4: phy@3e50000 { 1335 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 1336 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 1337 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 1338 reg-names = "ctl";
1414 1339
1415 #phy-cells = <0>; 1340 #phy-cells = <0>;
1416 }; 1341 };
1417 1342
1418 p2u_hsio_5: phy@3e60000 { 1343 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 1344 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 1345 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 1346 reg-names = "ctl";
1422 1347
1423 #phy-cells = <0>; 1348 #phy-cells = <0>;
1424 }; 1349 };
1425 1350
1426 p2u_hsio_6: phy@3e70000 { 1351 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 1352 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 1353 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 1354 reg-names = "ctl";
1430 1355
1431 #phy-cells = <0>; 1356 #phy-cells = <0>;
1432 }; 1357 };
1433 1358
1434 p2u_hsio_7: phy@3e80000 { 1359 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 1360 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 1361 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 1362 reg-names = "ctl";
1438 1363
1439 #phy-cells = <0>; 1364 #phy-cells = <0>;
1440 }; 1365 };
1441 1366
1442 p2u_hsio_8: phy@3e90000 { 1367 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 1368 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 1369 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 1370 reg-names = "ctl";
1446 1371
1447 #phy-cells = <0>; 1372 #phy-cells = <0>;
1448 }; 1373 };
1449 1374
1450 p2u_hsio_9: phy@3ea0000 { 1375 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 1376 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 1377 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 1378 reg-names = "ctl";
1454 1379
1455 #phy-cells = <0>; 1380 #phy-cells = <0>;
1456 }; 1381 };
1457 1382
1458 p2u_nvhs_0: phy@3eb0000 { 1383 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 1384 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 1385 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 1386 reg-names = "ctl";
1462 1387
1463 #phy-cells = <0>; 1388 #phy-cells = <0>;
1464 }; 1389 };
1465 1390
1466 p2u_nvhs_1: phy@3ec0000 { 1391 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 1392 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 1393 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 1394 reg-names = "ctl";
1470 1395
1471 #phy-cells = <0>; 1396 #phy-cells = <0>;
1472 }; 1397 };
1473 1398
1474 p2u_nvhs_2: phy@3ed0000 { 1399 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 1400 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 1401 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 1402 reg-names = "ctl";
1478 1403
1479 #phy-cells = <0>; 1404 #phy-cells = <0>;
1480 }; 1405 };
1481 1406
1482 p2u_nvhs_3: phy@3ee0000 { 1407 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 1408 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 1409 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 1410 reg-names = "ctl";
1486 1411
1487 #phy-cells = <0>; 1412 #phy-cells = <0>;
1488 }; 1413 };
1489 1414
1490 p2u_nvhs_4: phy@3ef0000 { 1415 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 1416 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 1417 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 1418 reg-names = "ctl";
1494 1419
1495 #phy-cells = <0>; 1420 #phy-cells = <0>;
1496 }; 1421 };
1497 1422
1498 p2u_nvhs_5: phy@3f00000 { 1423 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 1424 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 1425 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 1426 reg-names = "ctl";
1502 1427
1503 #phy-cells = <0>; 1428 #phy-cells = <0>;
1504 }; 1429 };
1505 1430
1506 p2u_nvhs_6: phy@3f10000 { 1431 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 1432 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 1433 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 1434 reg-names = "ctl";
1510 1435
1511 #phy-cells = <0>; 1436 #phy-cells = <0>;
1512 }; 1437 };
1513 1438
1514 p2u_nvhs_7: phy@3f20000 { 1439 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 1440 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 1441 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 1442 reg-names = "ctl";
1518 1443
1519 #phy-cells = <0>; 1444 #phy-cells = <0>;
1520 }; 1445 };
1521 1446
1522 p2u_hsio_10: phy@3f30000 { 1447 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 1448 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 1449 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 1450 reg-names = "ctl";
1526 1451
1527 #phy-cells = <0>; 1452 #phy-cells = <0>;
1528 }; 1453 };
1529 1454
1530 p2u_hsio_11: phy@3f40000 { 1455 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 1456 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 1457 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 1458 reg-names = "ctl";
1534 1459
1535 #phy-cells = <0>; 1460 #phy-cells = <0>;
1536 }; 1461 };
1537 1462
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 1463 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, 1464 compatible = "nvidia,tegra194-hsp";
1560 reg = <0x0 0x0c150000 !! 1465 reg = <0x0c150000 0x90000>;
1561 interrupts = <GIC_SPI 1466 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 1467 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 1468 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 1469 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 1470 /*
1566 * Shared interrupt 0 1471 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 1472 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 1473 */
1569 interrupt-names = "sh 1474 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 1475 #mbox-cells = <2>;
1571 }; 1476 };
1572 1477
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 1478 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 1479 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 1480 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 1481 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 1482 #address-cells = <1>;
1588 #size-cells = <0>; 1483 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 1484 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 1485 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 1486 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 1487 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 1488 status = "disabled";
1596 }; 1489 };
1597 1490
1598 gen8_i2c: i2c@c250000 { 1491 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 1492 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 1493 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 1494 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 1495 #address-cells = <1>;
1603 #size-cells = <0>; 1496 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 1497 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 1498 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 1499 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 1500 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 1501 status = "disabled";
1611 }; 1502 };
1612 1503
1613 uartc: serial@c280000 { 1504 uartc: serial@c280000 {
1614 compatible = "nvidia, 1505 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 1506 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 1507 reg-shift = <2>;
1617 interrupts = <GIC_SPI 1508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 1509 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 1510 clock-names = "serial";
1620 resets = <&bpmp TEGRA 1511 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 1512 reset-names = "serial";
1622 status = "disabled"; 1513 status = "disabled";
1623 }; 1514 };
1624 1515
1625 uartg: serial@c290000 { 1516 uartg: serial@c290000 {
1626 compatible = "nvidia, 1517 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 1518 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 1519 reg-shift = <2>;
1629 interrupts = <GIC_SPI 1520 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 1521 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 1522 clock-names = "serial";
1632 resets = <&bpmp TEGRA 1523 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 1524 reset-names = "serial";
1634 status = "disabled"; 1525 status = "disabled";
1635 }; 1526 };
1636 1527
1637 rtc: rtc@c2a0000 { 1528 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 1529 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 1530 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 1531 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 1532 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 1533 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 1534 clock-names = "rtc";
1644 status = "disabled"; 1535 status = "disabled";
1645 }; 1536 };
1646 1537
1647 gpio_aon: gpio@c2f0000 { 1538 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 1539 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 1540 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 1541 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 1542 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI 1543 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 1544 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 1545 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 1546 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1656 gpio-controller; 1547 gpio-controller;
1657 #gpio-cells = <2>; 1548 #gpio-cells = <2>;
1658 interrupt-controller; 1549 interrupt-controller;
1659 #interrupt-cells = <2 1550 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 1551 };
1669 1552
1670 pwm4: pwm@c340000 { 1553 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 1554 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 1555 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 1556 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 1557 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 1558 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 1559 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 1560 reset-names = "pwm";
1677 status = "disabled"; 1561 status = "disabled";
1678 #pwm-cells = <2>; 1562 #pwm-cells = <2>;
1679 }; 1563 };
1680 1564
1681 pmc: pmc@c360000 { 1565 pmc: pmc@c360000 {
1682 compatible = "nvidia, 1566 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 1567 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 1568 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 1569 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 1570 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 1571 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 1572 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 1573
1690 #interrupt-cells = <2 1574 #interrupt-cells = <2>;
1691 interrupt-controller; 1575 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v 1576 sdmmc1_3v3: sdmmc1-3v3 {
1699 pins = "sdmmc 1577 pins = "sdmmc1-hv";
1700 power-source 1578 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1701 }; 1579 };
1702 1580
1703 sdmmc3_1v8: sdmmc3-1v !! 1581 sdmmc1_1v8: sdmmc1-1v8 {
1704 pins = "sdmmc !! 1582 pins = "sdmmc1-hv";
1705 power-source 1583 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1706 }; 1584 };
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v 1585 sdmmc3_3v3: sdmmc3-3v3 {
1709 pins = "sdmmc 1586 pins = "sdmmc3-hv";
1710 power-source 1587 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1711 }; 1588 };
1712 }; <<
1713 1589
1714 aon-noc@c600000 { !! 1590 sdmmc3_1v8: sdmmc3-1v8 {
1715 compatible = "nvidia, !! 1591 pins = "sdmmc3-hv";
1716 reg = <0x0 0xc600000 !! 1592 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1717 interrupts = <GIC_SPI !! 1593 };
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 1594
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; 1595 };
1732 1596
1733 iommu@10000000 { 1597 iommu@10000000 {
1734 compatible = "nvidia, 1598 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1735 reg = <0x0 0x10000000 !! 1599 reg = <0x10000000 0x800000>;
1736 interrupts = <GIC_SPI 1600 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1601 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1602 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1603 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1604 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1605 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1606 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 1607 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1608 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1609 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1746 <GIC_SPI 1610 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 1611 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 1612 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 1613 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1750 <GIC_SPI 1614 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1751 <GIC_SPI 1615 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1752 <GIC_SPI 1616 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 1617 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1771 <GIC_SPI 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1772 <GIC_SPI 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1773 <GIC_SPI 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1774 <GIC_SPI 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1776 <GIC_SPI 1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 1647 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 1648 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 1649 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 1650 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 1651 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 1652 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 1653 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 1654 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 1655 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 1656 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 1657 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1801 stream-match-mask = < 1665 stream-match-mask = <0x7f80>;
1802 #global-interrupts = 1666 #global-interrupts = <1>;
1803 #iommu-cells = <1>; 1667 #iommu-cells = <1>;
1804 1668
1805 nvidia,memory-control 1669 nvidia,memory-controller = <&mc>;
1806 status = "disabled"; 1670 status = "disabled";
1807 }; 1671 };
1808 1672
1809 smmu: iommu@12000000 { 1673 smmu: iommu@12000000 {
1810 compatible = "nvidia, 1674 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1811 reg = <0x0 0x12000000 !! 1675 reg = <0x12000000 0x800000>,
1812 <0x0 0x11000000 !! 1676 <0x11000000 0x800000>;
1813 interrupts = <GIC_SPI 1677 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1678 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1679 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1680 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1682 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1683 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1684 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1686 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1687 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1689 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1690 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1691 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1692 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1693 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1695 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1696 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 1697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 1698 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 1699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 1700 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 1701 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 1707 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 1708 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 1709 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 1710 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 1711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 1712 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 1713 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 1714 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 1715 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 1716 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 1717 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 1718 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 1719 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 1720 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 1721 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 1722 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 1723 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 1724 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 1725 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 1726 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 1727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 1728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 1729 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 1730 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 1731 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 1733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 1734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 1735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 1736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 1737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 1738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 1739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 1740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 1741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 1742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1879 stream-match-mask = < 1743 stream-match-mask = <0x7f80>;
1880 #global-interrupts = 1744 #global-interrupts = <2>;
1881 #iommu-cells = <1>; 1745 #iommu-cells = <1>;
1882 1746
1883 nvidia,memory-control 1747 nvidia,memory-controller = <&mc>;
1884 status = "okay"; 1748 status = "okay";
1885 }; 1749 };
1886 1750
1887 host1x@13e00000 { 1751 host1x@13e00000 {
1888 compatible = "nvidia, 1752 compatible = "nvidia,tegra194-host1x";
1889 reg = <0x0 0x13e00000 !! 1753 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 1754 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 1755 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 1756 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 1757 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy 1758 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA 1759 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 1760 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 1761 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 1762 reset-names = "host1x";
1899 1763
1900 #address-cells = <2>; !! 1764 #address-cells = <1>;
1901 #size-cells = <2>; !! 1765 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 1766
>> 1767 ranges = <0x15000000 0x15000000 0x01000000>;
1904 interconnects = <&mc 1768 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905 interconnect-names = 1769 interconnect-names = "dma-mem";
1906 iommus = <&smmu TEGRA 1770 iommus = <&smmu TEGRA194_SID_HOST1X>;
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 1771
1919 nvdec@15140000 { 1772 nvdec@15140000 {
1920 compatible = 1773 compatible = "nvidia,tegra194-nvdec";
1921 reg = <0x0 0x !! 1774 reg = <0x15140000 0x00040000>;
1922 clocks = <&bp 1775 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1923 clock-names = 1776 clock-names = "nvdec";
1924 resets = <&bp 1777 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1925 reset-names = 1778 reset-names = "nvdec";
1926 1779
1927 power-domains 1780 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1928 interconnects 1781 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1929 1782 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1930 1783 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1931 interconnect- 1784 interconnect-names = "dma-mem", "read-1", "write";
1932 iommus = <&sm 1785 iommus = <&smmu TEGRA194_SID_NVDEC1>;
1933 dma-coherent; 1786 dma-coherent;
1934 1787
1935 nvidia,host1x 1788 nvidia,host1x-class = <0xf5>;
1936 }; 1789 };
1937 1790
1938 display-hub@15200000 1791 display-hub@15200000 {
1939 compatible = 1792 compatible = "nvidia,tegra194-display";
1940 reg = <0x0 0x !! 1793 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 1794 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 1795 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 1796 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 1797 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 1798 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 1799 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 1800 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 1801 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 1802 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 1803 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 1804 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 1805 clock-names = "disp", "hub";
1953 status = "dis 1806 status = "disabled";
1954 1807
1955 power-domains 1808 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 1809
1957 #address-cell !! 1810 #address-cells = <1>;
1958 #size-cells = !! 1811 #size-cells = <1>;
1959 ranges = <0x0 !! 1812
>> 1813 ranges = <0x15200000 0x15200000 0x40000>;
1960 1814
1961 display@15200 1815 display@15200000 {
1962 compa 1816 compatible = "nvidia,tegra194-dc";
1963 reg = !! 1817 reg = <0x15200000 0x10000>;
1964 inter 1818 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 1819 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 1820 clock-names = "dc";
1967 reset 1821 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 1822 reset-names = "dc";
1969 1823
1970 power 1824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter 1825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 1826 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 inter 1827 interconnect-names = "dma-mem", "read-1";
1974 1828
1975 nvidi 1829 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 1830 nvidia,head = <0>;
1977 }; 1831 };
1978 1832
1979 display@15210 1833 display@15210000 {
1980 compa 1834 compatible = "nvidia,tegra194-dc";
1981 reg = !! 1835 reg = <0x15210000 0x10000>;
1982 inter 1836 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 1837 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 1838 clock-names = "dc";
1985 reset 1839 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 1840 reset-names = "dc";
1987 1841
1988 power 1842 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter 1843 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 1844 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 inter 1845 interconnect-names = "dma-mem", "read-1";
1992 1846
1993 nvidi 1847 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 1848 nvidia,head = <1>;
1995 }; 1849 };
1996 1850
1997 display@15220 1851 display@15220000 {
1998 compa 1852 compatible = "nvidia,tegra194-dc";
1999 reg = !! 1853 reg = <0x15220000 0x10000>;
2000 inter 1854 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 1855 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 1856 clock-names = "dc";
2003 reset 1857 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 1858 reset-names = "dc";
2005 1859
2006 power 1860 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter 1861 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008 1862 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009 inter 1863 interconnect-names = "dma-mem", "read-1";
2010 1864
2011 nvidi 1865 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 1866 nvidia,head = <2>;
2013 }; 1867 };
2014 1868
2015 display@15230 1869 display@15230000 {
2016 compa 1870 compatible = "nvidia,tegra194-dc";
2017 reg = !! 1871 reg = <0x15230000 0x10000>;
2018 inter 1872 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 1873 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 1874 clock-names = "dc";
2021 reset 1875 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 1876 reset-names = "dc";
2023 1877
2024 power 1878 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter 1879 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026 1880 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027 inter 1881 interconnect-names = "dma-mem", "read-1";
2028 1882
2029 nvidi 1883 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 1884 nvidia,head = <3>;
2031 }; 1885 };
2032 }; 1886 };
2033 1887
2034 vic@15340000 { 1888 vic@15340000 {
2035 compatible = 1889 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 1890 reg = <0x15340000 0x00040000>;
2037 interrupts = 1891 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 1892 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 1893 clock-names = "vic";
2040 resets = <&bp 1894 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 1895 reset-names = "vic";
2042 1896
2043 power-domains 1897 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects 1898 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045 1899 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046 interconnect- 1900 interconnect-names = "dma-mem", "write";
2047 iommus = <&sm 1901 iommus = <&smmu TEGRA194_SID_VIC>;
2048 dma-coherent; 1902 dma-coherent;
2049 }; 1903 };
2050 1904
2051 nvjpg@15380000 { 1905 nvjpg@15380000 {
2052 compatible = 1906 compatible = "nvidia,tegra194-nvjpg";
2053 reg = <0x0 0x !! 1907 reg = <0x15380000 0x40000>;
2054 clocks = <&bp 1908 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2055 clock-names = 1909 clock-names = "nvjpg";
2056 resets = <&bp 1910 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2057 reset-names = 1911 reset-names = "nvjpg";
2058 1912
2059 power-domains 1913 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2060 interconnects 1914 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
2061 1915 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
2062 interconnect- 1916 interconnect-names = "dma-mem", "write";
2063 iommus = <&sm 1917 iommus = <&smmu TEGRA194_SID_NVJPG>;
2064 dma-coherent; 1918 dma-coherent;
2065 }; 1919 };
2066 1920
2067 nvdec@15480000 { 1921 nvdec@15480000 {
2068 compatible = 1922 compatible = "nvidia,tegra194-nvdec";
2069 reg = <0x0 0x !! 1923 reg = <0x15480000 0x00040000>;
2070 clocks = <&bp 1924 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2071 clock-names = 1925 clock-names = "nvdec";
2072 resets = <&bp 1926 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2073 reset-names = 1927 reset-names = "nvdec";
2074 1928
2075 power-domains 1929 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2076 interconnects 1930 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
2077 1931 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
2078 1932 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
2079 interconnect- 1933 interconnect-names = "dma-mem", "read-1", "write";
2080 iommus = <&sm 1934 iommus = <&smmu TEGRA194_SID_NVDEC>;
2081 dma-coherent; 1935 dma-coherent;
2082 1936
2083 nvidia,host1x 1937 nvidia,host1x-class = <0xf0>;
2084 }; 1938 };
2085 1939
2086 nvenc@154c0000 { 1940 nvenc@154c0000 {
2087 compatible = 1941 compatible = "nvidia,tegra194-nvenc";
2088 reg = <0x0 0x !! 1942 reg = <0x154c0000 0x40000>;
2089 clocks = <&bp 1943 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2090 clock-names = 1944 clock-names = "nvenc";
2091 resets = <&bp 1945 resets = <&bpmp TEGRA194_RESET_NVENC>;
2092 reset-names = 1946 reset-names = "nvenc";
2093 1947
2094 power-domains 1948 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2095 interconnects 1949 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
2096 1950 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
2097 1951 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
2098 interconnect- 1952 interconnect-names = "dma-mem", "read-1", "write";
2099 iommus = <&sm 1953 iommus = <&smmu TEGRA194_SID_NVENC>;
2100 dma-coherent; 1954 dma-coherent;
2101 1955
2102 nvidia,host1x 1956 nvidia,host1x-class = <0x21>;
2103 }; 1957 };
2104 1958
2105 dpaux0: dpaux@155c000 1959 dpaux0: dpaux@155c0000 {
2106 compatible = 1960 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 1961 reg = <0x155c0000 0x10000>;
2108 interrupts = 1962 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 1963 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 1964 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 1965 clock-names = "dpaux", "parent";
2112 resets = <&bp 1966 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 1967 reset-names = "dpaux";
2114 status = "dis 1968 status = "disabled";
2115 1969
2116 power-domains 1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 1971
2118 state_dpaux0_ 1972 state_dpaux0_aux: pinmux-aux {
2119 group 1973 groups = "dpaux-io";
2120 funct 1974 function = "aux";
2121 }; 1975 };
2122 1976
2123 state_dpaux0_ 1977 state_dpaux0_i2c: pinmux-i2c {
2124 group 1978 groups = "dpaux-io";
2125 funct 1979 function = "i2c";
2126 }; 1980 };
2127 1981
2128 state_dpaux0_ 1982 state_dpaux0_off: pinmux-off {
2129 group 1983 groups = "dpaux-io";
2130 funct 1984 function = "off";
2131 }; 1985 };
2132 1986
2133 i2c-bus { 1987 i2c-bus {
2134 #addr 1988 #address-cells = <1>;
2135 #size 1989 #size-cells = <0>;
2136 }; 1990 };
2137 }; 1991 };
2138 1992
2139 dpaux1: dpaux@155d000 1993 dpaux1: dpaux@155d0000 {
2140 compatible = 1994 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1995 reg = <0x155d0000 0x10000>;
2142 interrupts = 1996 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1997 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1998 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1999 clock-names = "dpaux", "parent";
2146 resets = <&bp 2000 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 2001 reset-names = "dpaux";
2148 status = "dis 2002 status = "disabled";
2149 2003
2150 power-domains 2004 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 2005
2152 state_dpaux1_ 2006 state_dpaux1_aux: pinmux-aux {
2153 group 2007 groups = "dpaux-io";
2154 funct 2008 function = "aux";
2155 }; 2009 };
2156 2010
2157 state_dpaux1_ 2011 state_dpaux1_i2c: pinmux-i2c {
2158 group 2012 groups = "dpaux-io";
2159 funct 2013 function = "i2c";
2160 }; 2014 };
2161 2015
2162 state_dpaux1_ 2016 state_dpaux1_off: pinmux-off {
2163 group 2017 groups = "dpaux-io";
2164 funct 2018 function = "off";
2165 }; 2019 };
2166 2020
2167 i2c-bus { 2021 i2c-bus {
2168 #addr 2022 #address-cells = <1>;
2169 #size 2023 #size-cells = <0>;
2170 }; 2024 };
2171 }; 2025 };
2172 2026
2173 dpaux2: dpaux@155e000 2027 dpaux2: dpaux@155e0000 {
2174 compatible = 2028 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 2029 reg = <0x155e0000 0x10000>;
2176 interrupts = 2030 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 2031 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 2032 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 2033 clock-names = "dpaux", "parent";
2180 resets = <&bp 2034 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 2035 reset-names = "dpaux";
2182 status = "dis 2036 status = "disabled";
2183 2037
2184 power-domains 2038 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 2039
2186 state_dpaux2_ 2040 state_dpaux2_aux: pinmux-aux {
2187 group 2041 groups = "dpaux-io";
2188 funct 2042 function = "aux";
2189 }; 2043 };
2190 2044
2191 state_dpaux2_ 2045 state_dpaux2_i2c: pinmux-i2c {
2192 group 2046 groups = "dpaux-io";
2193 funct 2047 function = "i2c";
2194 }; 2048 };
2195 2049
2196 state_dpaux2_ 2050 state_dpaux2_off: pinmux-off {
2197 group 2051 groups = "dpaux-io";
2198 funct 2052 function = "off";
2199 }; 2053 };
2200 2054
2201 i2c-bus { 2055 i2c-bus {
2202 #addr 2056 #address-cells = <1>;
2203 #size 2057 #size-cells = <0>;
2204 }; 2058 };
2205 }; 2059 };
2206 2060
2207 dpaux3: dpaux@155f000 2061 dpaux3: dpaux@155f0000 {
2208 compatible = 2062 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 2063 reg = <0x155f0000 0x10000>;
2210 interrupts = 2064 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 2065 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 2066 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 2067 clock-names = "dpaux", "parent";
2214 resets = <&bp 2068 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 2069 reset-names = "dpaux";
2216 status = "dis 2070 status = "disabled";
2217 2071
2218 power-domains 2072 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 2073
2220 state_dpaux3_ 2074 state_dpaux3_aux: pinmux-aux {
2221 group 2075 groups = "dpaux-io";
2222 funct 2076 function = "aux";
2223 }; 2077 };
2224 2078
2225 state_dpaux3_ 2079 state_dpaux3_i2c: pinmux-i2c {
2226 group 2080 groups = "dpaux-io";
2227 funct 2081 function = "i2c";
2228 }; 2082 };
2229 2083
2230 state_dpaux3_ 2084 state_dpaux3_off: pinmux-off {
2231 group 2085 groups = "dpaux-io";
2232 funct 2086 function = "off";
2233 }; 2087 };
2234 2088
2235 i2c-bus { 2089 i2c-bus {
2236 #addr 2090 #address-cells = <1>;
2237 #size 2091 #size-cells = <0>;
2238 }; 2092 };
2239 }; 2093 };
2240 2094
2241 nvenc@15a80000 { 2095 nvenc@15a80000 {
2242 compatible = 2096 compatible = "nvidia,tegra194-nvenc";
2243 reg = <0x0 0x !! 2097 reg = <0x15a80000 0x00040000>;
2244 clocks = <&bp 2098 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2245 clock-names = 2099 clock-names = "nvenc";
2246 resets = <&bp 2100 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2247 reset-names = 2101 reset-names = "nvenc";
2248 2102
2249 power-domains 2103 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2250 interconnects 2104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2251 2105 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2252 2106 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2253 interconnect- 2107 interconnect-names = "dma-mem", "read-1", "write";
2254 iommus = <&sm 2108 iommus = <&smmu TEGRA194_SID_NVENC1>;
2255 dma-coherent; 2109 dma-coherent;
2256 2110
2257 nvidia,host1x 2111 nvidia,host1x-class = <0x22>;
2258 }; 2112 };
2259 2113
2260 sor0: sor@15b00000 { 2114 sor0: sor@15b00000 {
2261 compatible = 2115 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 2116 reg = <0x15b00000 0x40000>;
2263 interrupts = 2117 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 2118 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 2119 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 2120 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 2121 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 2122 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 2123 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 2124 clock-names = "sor", "out", "parent", "dp", "safe",
2271 2125 "pad";
2272 resets = <&bp 2126 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 2127 reset-names = "sor";
2274 pinctrl-0 = < 2128 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 2129 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 2130 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 2131 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 2132 status = "disabled";
2279 2133
2280 power-domains 2134 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 2135 nvidia,interface = <0>;
2282 }; 2136 };
2283 2137
2284 sor1: sor@15b40000 { 2138 sor1: sor@15b40000 {
2285 compatible = 2139 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 2140 reg = <0x15b40000 0x40000>;
2287 interrupts = 2141 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 2142 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 2143 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 2144 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 2145 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 2146 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 2147 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 2148 clock-names = "sor", "out", "parent", "dp", "safe",
2295 2149 "pad";
2296 resets = <&bp 2150 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 2151 reset-names = "sor";
2298 pinctrl-0 = < 2152 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 2153 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 2154 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 2155 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 2156 status = "disabled";
2303 2157
2304 power-domains 2158 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 2159 nvidia,interface = <1>;
2306 }; 2160 };
2307 2161
2308 sor2: sor@15b80000 { 2162 sor2: sor@15b80000 {
2309 compatible = 2163 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 2164 reg = <0x15b80000 0x40000>;
2311 interrupts = 2165 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 2166 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 2167 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 2168 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 2169 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 2170 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 2171 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 2172 clock-names = "sor", "out", "parent", "dp", "safe",
2319 2173 "pad";
2320 resets = <&bp 2174 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 2175 reset-names = "sor";
2322 pinctrl-0 = < 2176 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 2177 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 2178 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 2179 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 2180 status = "disabled";
2327 2181
2328 power-domains 2182 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 2183 nvidia,interface = <2>;
2330 }; 2184 };
2331 2185
2332 sor3: sor@15bc0000 { 2186 sor3: sor@15bc0000 {
2333 compatible = 2187 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 2188 reg = <0x15bc0000 0x40000>;
2335 interrupts = 2189 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 2190 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 2191 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 2192 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 2193 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 2194 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 2195 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 2196 clock-names = "sor", "out", "parent", "dp", "safe",
2343 2197 "pad";
2344 resets = <&bp 2198 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 2199 reset-names = "sor";
2346 pinctrl-0 = < 2200 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 2201 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 2202 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 2203 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 2204 status = "disabled";
2351 2205
2352 power-domains 2206 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 2207 nvidia,interface = <3>;
2354 }; 2208 };
2355 }; 2209 };
2356 2210
2357 pcie@14100000 { <<
2358 compatible = "nvidia, <<
2359 power-domains = <&bpm <<
2360 reg = <0x00 0x1410000 <<
2361 <0x00 0x3000000 <<
2362 <0x00 0x3004000 <<
2363 <0x00 0x3008000 <<
2364 reg-names = "appl", " <<
2365 <<
2366 status = "disabled"; <<
2367 <<
2368 #address-cells = <3>; <<
2369 #size-cells = <2>; <<
2370 device_type = "pci"; <<
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 <<
2377 resets = <&bpmp TEGRA <<
2378 <&bpmp TEGRA <<
2379 reset-names = "apb", <<
2380 <<
2381 interrupts = <GIC_SPI <<
2382 <GIC_SPI <<
2383 interrupt-names = "in <<
2384 <<
2385 #interrupt-cells = <1 <<
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 <<
2389 nvidia,bpmp = <&bpmp <<
2390 <<
2391 nvidia,aspm-cmrt-us = <<
2392 nvidia,aspm-pwr-on-t- <<
2393 nvidia,aspm-l0s-entra <<
2394 <<
2395 bus-range = <0x0 0xff <<
2396 <<
2397 ranges = <0x43000000 <<
2398 <0x02000000 <<
2399 <0x01000000 <<
2400 <<
2401 interconnects = <&mc <<
2402 <&mc <<
2403 interconnect-names = <<
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 <<
2409 pcie@14120000 { <<
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 <<
2418 status = "disabled"; <<
2419 <<
2420 #address-cells = <3>; <<
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 <<
2426 clocks = <&bpmp TEGRA <<
2427 clock-names = "core"; <<
2428 <<
2429 resets = <&bpmp TEGRA <<
2430 <&bpmp TEGRA <<
2431 reset-names = "apb", <<
2432 <<
2433 interrupts = <GIC_SPI <<
2434 <GIC_SPI <<
2435 interrupt-names = "in <<
2436 <<
2437 #interrupt-cells = <1 <<
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 <<
2441 nvidia,bpmp = <&bpmp <<
2442 <<
2443 nvidia,aspm-cmrt-us = <<
2444 nvidia,aspm-pwr-on-t- <<
2445 nvidia,aspm-l0s-entra <<
2446 <<
2447 bus-range = <0x0 0xff <<
2448 <<
2449 ranges = <0x43000000 <<
2450 <0x02000000 <<
2451 <0x01000000 <<
2452 <<
2453 interconnects = <&mc <<
2454 <&mc <<
2455 interconnect-names = <<
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 <<
2461 pcie@14140000 { <<
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 <<
2470 status = "disabled"; <<
2471 <<
2472 #address-cells = <3>; <<
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 <<
2478 clocks = <&bpmp TEGRA <<
2479 clock-names = "core"; <<
2480 <<
2481 resets = <&bpmp TEGRA <<
2482 <&bpmp TEGRA <<
2483 reset-names = "apb", <<
2484 <<
2485 interrupts = <GIC_SPI <<
2486 <GIC_SPI <<
2487 interrupt-names = "in <<
2488 <<
2489 #interrupt-cells = <1 <<
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 <<
2493 nvidia,bpmp = <&bpmp <<
2494 <<
2495 nvidia,aspm-cmrt-us = <<
2496 nvidia,aspm-pwr-on-t- <<
2497 nvidia,aspm-l0s-entra <<
2498 <<
2499 bus-range = <0x0 0xff <<
2500 <<
2501 ranges = <0x43000000 <<
2502 <0x02000000 <<
2503 <0x01000000 <<
2504 <<
2505 interconnects = <&mc <<
2506 <&mc <<
2507 interconnect-names = <<
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 <<
2513 pcie@14160000 { <<
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 <<
2522 status = "disabled"; <<
2523 <<
2524 #address-cells = <3>; <<
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 <<
2530 clocks = <&bpmp TEGRA <<
2531 clock-names = "core"; <<
2532 <<
2533 resets = <&bpmp TEGRA <<
2534 <&bpmp TEGRA <<
2535 reset-names = "apb", <<
2536 <<
2537 interrupts = <GIC_SPI <<
2538 <GIC_SPI <<
2539 interrupt-names = "in <<
2540 <<
2541 #interrupt-cells = <1 <<
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 <<
2545 nvidia,bpmp = <&bpmp <<
2546 <<
2547 nvidia,aspm-cmrt-us = <<
2548 nvidia,aspm-pwr-on-t- <<
2549 nvidia,aspm-l0s-entra <<
2550 <<
2551 bus-range = <0x0 0xff <<
2552 <<
2553 ranges = <0x43000000 <<
2554 <0x02000000 <<
2555 <0x01000000 <<
2556 <<
2557 interconnects = <&mc <<
2558 <&mc <<
2559 interconnect-names = <<
2560 iommu-map = <0x0 &smm <<
2561 iommu-map-mask = <0x0 <<
2562 dma-coherent; <<
2563 }; <<
2564 <<
2565 pcie-ep@14160000 { <<
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 <<
2574 status = "disabled"; <<
2575 <<
2576 num-lanes = <4>; <<
2577 num-ib-windows = <2>; <<
2578 num-ob-windows = <8>; <<
2579 <<
2580 clocks = <&bpmp TEGRA <<
2581 clock-names = "core"; <<
2582 <<
2583 resets = <&bpmp TEGRA <<
2584 <&bpmp TEGRA <<
2585 reset-names = "apb", <<
2586 <<
2587 interrupts = <GIC_SPI <<
2588 interrupt-names = "in <<
2589 <<
2590 nvidia,bpmp = <&bpmp <<
2591 <<
2592 nvidia,aspm-cmrt-us = <<
2593 nvidia,aspm-pwr-on-t- <<
2594 nvidia,aspm-l0s-entra <<
2595 <<
2596 interconnects = <&mc <<
2597 <&mc <<
2598 interconnect-names = <<
2599 iommu-map = <0x0 &smm <<
2600 iommu-map-mask = <0x0 <<
2601 dma-coherent; <<
2602 }; <<
2603 <<
2604 pcie@14180000 { <<
2605 compatible = "nvidia, <<
2606 power-domains = <&bpm <<
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 <<
2613 status = "disabled"; <<
2614 <<
2615 #address-cells = <3>; <<
2616 #size-cells = <2>; <<
2617 device_type = "pci"; <<
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 <<
2621 clocks = <&bpmp TEGRA <<
2622 clock-names = "core"; <<
2623 <<
2624 resets = <&bpmp TEGRA <<
2625 <&bpmp TEGRA <<
2626 reset-names = "apb", <<
2627 <<
2628 interrupts = <GIC_SPI <<
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 <<
2632 #interrupt-cells = <1 <<
2633 interrupt-map-mask = <<
2634 interrupt-map = <0 0 <<
2635 <<
2636 nvidia,bpmp = <&bpmp <<
2637 <<
2638 nvidia,aspm-cmrt-us = <<
2639 nvidia,aspm-pwr-on-t- <<
2640 nvidia,aspm-l0s-entra <<
2641 <<
2642 bus-range = <0x0 0xff <<
2643 <<
2644 ranges = <0x43000000 <<
2645 <0x02000000 <<
2646 <0x01000000 <<
2647 <<
2648 interconnects = <&mc <<
2649 <&mc <<
2650 interconnect-names = <<
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 <<
2656 pcie-ep@14180000 { <<
2657 compatible = "nvidia, <<
2658 power-domains = <&bpm <<
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 <<
2665 status = "disabled"; <<
2666 <<
2667 num-lanes = <8>; <<
2668 num-ib-windows = <2>; <<
2669 num-ob-windows = <8>; <<
2670 <<
2671 clocks = <&bpmp TEGRA <<
2672 clock-names = "core"; <<
2673 <<
2674 resets = <&bpmp TEGRA <<
2675 <&bpmp TEGRA <<
2676 reset-names = "apb", <<
2677 <<
2678 interrupts = <GIC_SPI <<
2679 interrupt-names = "in <<
2680 <<
2681 nvidia,bpmp = <&bpmp <<
2682 <<
2683 nvidia,aspm-cmrt-us = <<
2684 nvidia,aspm-pwr-on-t- <<
2685 nvidia,aspm-l0s-entra <<
2686 <<
2687 interconnects = <&mc <<
2688 <&mc <<
2689 interconnect-names = <<
2690 iommu-map = <0x0 &smm <<
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 <<
2695 pcie@141a0000 { <<
2696 compatible = "nvidia, <<
2697 power-domains = <&bpm <<
2698 reg = <0x00 0x141a000 <<
2699 <0x00 0x3a00000 <<
2700 <0x00 0x3a04000 <<
2701 <0x00 0x3a08000 <<
2702 reg-names = "appl", " <<
2703 <<
2704 status = "disabled"; <<
2705 <<
2706 #address-cells = <3>; <<
2707 #size-cells = <2>; <<
2708 device_type = "pci"; <<
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 <<
2712 pinctrl-names = "defa <<
2713 pinctrl-0 = <&pex_rst <<
2714 <<
2715 clocks = <&bpmp TEGRA <<
2716 clock-names = "core"; <<
2717 <<
2718 resets = <&bpmp TEGRA <<
2719 <&bpmp TEGRA <<
2720 reset-names = "apb", <<
2721 <<
2722 interrupts = <GIC_SPI <<
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 <<
2726 nvidia,bpmp = <&bpmp <<
2727 <<
2728 #interrupt-cells = <1 <<
2729 interrupt-map-mask = <<
2730 interrupt-map = <0 0 <<
2731 <<
2732 nvidia,aspm-cmrt-us = <<
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 <<
2736 bus-range = <0x0 0xff <<
2737 <<
2738 ranges = <0x43000000 <<
2739 <0x02000000 <<
2740 <0x01000000 <<
2741 <<
2742 interconnects = <&mc <<
2743 <&mc <<
2744 interconnect-names = <<
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 <<
2750 pcie-ep@141a0000 { <<
2751 compatible = "nvidia, <<
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 <<
2759 status = "disabled"; <<
2760 <<
2761 num-lanes = <8>; <<
2762 num-ib-windows = <2>; <<
2763 num-ob-windows = <8>; <<
2764 <<
2765 pinctrl-names = "defa <<
2766 pinctrl-0 = <&pex_clk <<
2767 <<
2768 clocks = <&bpmp TEGRA <<
2769 clock-names = "core"; <<
2770 <<
2771 resets = <&bpmp TEGRA <<
2772 <&bpmp TEGRA <<
2773 reset-names = "apb", <<
2774 <<
2775 interrupts = <GIC_SPI <<
2776 interrupt-names = "in <<
2777 <<
2778 nvidia,bpmp = <&bpmp <<
2779 <<
2780 nvidia,aspm-cmrt-us = <<
2781 nvidia,aspm-pwr-on-t- <<
2782 nvidia,aspm-l0s-entra <<
2783 <<
2784 interconnects = <&mc <<
2785 <&mc <<
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 <<
2792 gpu@17000000 { 2211 gpu@17000000 {
2793 compatible = "nvidia, 2212 compatible = "nvidia,gv11b";
2794 reg = <0x0 0x17000000 !! 2213 reg = <0x17000000 0x1000000>,
2795 <0x0 0x18000000 !! 2214 <0x18000000 0x1000000>;
2796 interrupts = <GIC_SPI 2215 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 2216 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2798 interrupt-names = "st 2217 interrupt-names = "stall", "nonstall";
2799 clocks = <&bpmp TEGRA 2218 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800 <&bpmp TEGRA 2219 <&bpmp TEGRA194_CLK_GPU_PWR>,
2801 <&bpmp TEGRA 2220 <&bpmp TEGRA194_CLK_FUSE>;
2802 clock-names = "gpu", 2221 clock-names = "gpu", "pwr", "fuse";
2803 resets = <&bpmp TEGRA 2222 resets = <&bpmp TEGRA194_RESET_GPU>;
2804 reset-names = "gpu"; 2223 reset-names = "gpu";
2805 dma-coherent; 2224 dma-coherent;
2806 2225
2807 power-domains = <&bpm 2226 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2808 interconnects = <&mc 2227 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2809 <&mc 2228 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2810 <&mc 2229 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2811 <&mc 2230 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2812 <&mc 2231 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2813 <&mc 2232 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2814 <&mc 2233 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2815 <&mc 2234 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2816 <&mc 2235 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2817 <&mc 2236 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2818 <&mc 2237 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2819 <&mc 2238 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2820 interconnect-names = 2239 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2821 2240 "read-1", "read-1-hp", "write-1",
2822 2241 "read-2", "read-2-hp", "write-2",
2823 2242 "read-3", "read-3-hp", "write-3";
2824 }; 2243 };
2825 }; 2244 };
2826 2245
>> 2246 pcie@14100000 {
>> 2247 compatible = "nvidia,tegra194-pcie";
>> 2248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2249 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
>> 2250 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2251 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2252 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2253 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2254
>> 2255 status = "disabled";
>> 2256
>> 2257 #address-cells = <3>;
>> 2258 #size-cells = <2>;
>> 2259 device_type = "pci";
>> 2260 num-lanes = <1>;
>> 2261 linux,pci-domain = <1>;
>> 2262
>> 2263 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
>> 2264 clock-names = "core";
>> 2265
>> 2266 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 2267 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 2268 reset-names = "apb", "core";
>> 2269
>> 2270 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2271 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2272 interrupt-names = "intr", "msi";
>> 2273
>> 2274 #interrupt-cells = <1>;
>> 2275 interrupt-map-mask = <0 0 0 0>;
>> 2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 2277
>> 2278 nvidia,bpmp = <&bpmp 1>;
>> 2279
>> 2280 nvidia,aspm-cmrt-us = <60>;
>> 2281 nvidia,aspm-pwr-on-t-us = <20>;
>> 2282 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2283
>> 2284 bus-range = <0x0 0xff>;
>> 2285
>> 2286 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2287 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 2288 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2289
>> 2290 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
>> 2291 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
>> 2292 interconnect-names = "dma-mem", "write";
>> 2293 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
>> 2294 iommu-map-mask = <0x0>;
>> 2295 dma-coherent;
>> 2296 };
>> 2297
>> 2298 pcie@14120000 {
>> 2299 compatible = "nvidia,tegra194-pcie";
>> 2300 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2301 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
>> 2302 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2303 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2304 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2305 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2306
>> 2307 status = "disabled";
>> 2308
>> 2309 #address-cells = <3>;
>> 2310 #size-cells = <2>;
>> 2311 device_type = "pci";
>> 2312 num-lanes = <1>;
>> 2313 linux,pci-domain = <2>;
>> 2314
>> 2315 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
>> 2316 clock-names = "core";
>> 2317
>> 2318 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 2319 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 2320 reset-names = "apb", "core";
>> 2321
>> 2322 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2323 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2324 interrupt-names = "intr", "msi";
>> 2325
>> 2326 #interrupt-cells = <1>;
>> 2327 interrupt-map-mask = <0 0 0 0>;
>> 2328 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 2329
>> 2330 nvidia,bpmp = <&bpmp 2>;
>> 2331
>> 2332 nvidia,aspm-cmrt-us = <60>;
>> 2333 nvidia,aspm-pwr-on-t-us = <20>;
>> 2334 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2335
>> 2336 bus-range = <0x0 0xff>;
>> 2337
>> 2338 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2339 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
>> 2340 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2341
>> 2342 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
>> 2343 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
>> 2344 interconnect-names = "dma-mem", "write";
>> 2345 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
>> 2346 iommu-map-mask = <0x0>;
>> 2347 dma-coherent;
>> 2348 };
>> 2349
>> 2350 pcie@14140000 {
>> 2351 compatible = "nvidia,tegra194-pcie";
>> 2352 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 2353 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
>> 2354 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2355 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2356 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2357 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2358
>> 2359 status = "disabled";
>> 2360
>> 2361 #address-cells = <3>;
>> 2362 #size-cells = <2>;
>> 2363 device_type = "pci";
>> 2364 num-lanes = <1>;
>> 2365 linux,pci-domain = <3>;
>> 2366
>> 2367 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
>> 2368 clock-names = "core";
>> 2369
>> 2370 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 2371 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 2372 reset-names = "apb", "core";
>> 2373
>> 2374 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2375 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2376 interrupt-names = "intr", "msi";
>> 2377
>> 2378 #interrupt-cells = <1>;
>> 2379 interrupt-map-mask = <0 0 0 0>;
>> 2380 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>> 2381
>> 2382 nvidia,bpmp = <&bpmp 3>;
>> 2383
>> 2384 nvidia,aspm-cmrt-us = <60>;
>> 2385 nvidia,aspm-pwr-on-t-us = <20>;
>> 2386 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2387
>> 2388 bus-range = <0x0 0xff>;
>> 2389
>> 2390 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
>> 2391 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
>> 2392 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2393
>> 2394 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
>> 2395 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
>> 2396 interconnect-names = "dma-mem", "write";
>> 2397 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
>> 2398 iommu-map-mask = <0x0>;
>> 2399 dma-coherent;
>> 2400 };
>> 2401
>> 2402 pcie@14160000 {
>> 2403 compatible = "nvidia,tegra194-pcie";
>> 2404 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 2405 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 2406 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2407 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2408 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2409 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2410
>> 2411 status = "disabled";
>> 2412
>> 2413 #address-cells = <3>;
>> 2414 #size-cells = <2>;
>> 2415 device_type = "pci";
>> 2416 num-lanes = <4>;
>> 2417 linux,pci-domain = <4>;
>> 2418
>> 2419 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 2420 clock-names = "core";
>> 2421
>> 2422 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 2423 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2424 reset-names = "apb", "core";
>> 2425
>> 2426 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2427 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2428 interrupt-names = "intr", "msi";
>> 2429
>> 2430 #interrupt-cells = <1>;
>> 2431 interrupt-map-mask = <0 0 0 0>;
>> 2432 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 2433
>> 2434 nvidia,bpmp = <&bpmp 4>;
>> 2435
>> 2436 nvidia,aspm-cmrt-us = <60>;
>> 2437 nvidia,aspm-pwr-on-t-us = <20>;
>> 2438 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2439
>> 2440 bus-range = <0x0 0xff>;
>> 2441
>> 2442 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2443 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2444 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2445
>> 2446 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2447 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2448 interconnect-names = "dma-mem", "write";
>> 2449 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2450 iommu-map-mask = <0x0>;
>> 2451 dma-coherent;
>> 2452 };
>> 2453
>> 2454 pcie@14180000 {
>> 2455 compatible = "nvidia,tegra194-pcie";
>> 2456 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2457 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2458 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2459 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2460 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2461 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2462
>> 2463 status = "disabled";
>> 2464
>> 2465 #address-cells = <3>;
>> 2466 #size-cells = <2>;
>> 2467 device_type = "pci";
>> 2468 num-lanes = <8>;
>> 2469 linux,pci-domain = <0>;
>> 2470
>> 2471 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2472 clock-names = "core";
>> 2473
>> 2474 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2475 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2476 reset-names = "apb", "core";
>> 2477
>> 2478 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2480 interrupt-names = "intr", "msi";
>> 2481
>> 2482 #interrupt-cells = <1>;
>> 2483 interrupt-map-mask = <0 0 0 0>;
>> 2484 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 2485
>> 2486 nvidia,bpmp = <&bpmp 0>;
>> 2487
>> 2488 nvidia,aspm-cmrt-us = <60>;
>> 2489 nvidia,aspm-pwr-on-t-us = <20>;
>> 2490 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2491
>> 2492 bus-range = <0x0 0xff>;
>> 2493
>> 2494 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2495 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2496 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2497
>> 2498 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2499 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2500 interconnect-names = "dma-mem", "write";
>> 2501 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2502 iommu-map-mask = <0x0>;
>> 2503 dma-coherent;
>> 2504 };
>> 2505
>> 2506 pcie@141a0000 {
>> 2507 compatible = "nvidia,tegra194-pcie";
>> 2508 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2509 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2510 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
>> 2511 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2512 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 2513 reg-names = "appl", "config", "atu_dma", "dbi";
>> 2514
>> 2515 status = "disabled";
>> 2516
>> 2517 #address-cells = <3>;
>> 2518 #size-cells = <2>;
>> 2519 device_type = "pci";
>> 2520 num-lanes = <8>;
>> 2521 linux,pci-domain = <5>;
>> 2522
>> 2523 pinctrl-names = "default";
>> 2524 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> 2525
>> 2526 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2527 clock-names = "core";
>> 2528
>> 2529 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2530 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2531 reset-names = "apb", "core";
>> 2532
>> 2533 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 2534 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 2535 interrupt-names = "intr", "msi";
>> 2536
>> 2537 nvidia,bpmp = <&bpmp 5>;
>> 2538
>> 2539 #interrupt-cells = <1>;
>> 2540 interrupt-map-mask = <0 0 0 0>;
>> 2541 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
>> 2542
>> 2543 nvidia,aspm-cmrt-us = <60>;
>> 2544 nvidia,aspm-pwr-on-t-us = <20>;
>> 2545 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2546
>> 2547 bus-range = <0x0 0xff>;
>> 2548
>> 2549 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
>> 2550 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
>> 2551 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
>> 2552
>> 2553 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2554 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2555 interconnect-names = "dma-mem", "write";
>> 2556 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2557 iommu-map-mask = <0x0>;
>> 2558 dma-coherent;
>> 2559 };
>> 2560
>> 2561 pcie-ep@14160000 {
>> 2562 compatible = "nvidia,tegra194-pcie-ep";
>> 2563 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>> 2564 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
>> 2565 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2566 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2567 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2568 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2569
>> 2570 status = "disabled";
>> 2571
>> 2572 num-lanes = <4>;
>> 2573 num-ib-windows = <2>;
>> 2574 num-ob-windows = <8>;
>> 2575
>> 2576 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 2577 clock-names = "core";
>> 2578
>> 2579 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 2580 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 2581 reset-names = "apb", "core";
>> 2582
>> 2583 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2584 interrupt-names = "intr";
>> 2585
>> 2586 nvidia,bpmp = <&bpmp 4>;
>> 2587
>> 2588 nvidia,aspm-cmrt-us = <60>;
>> 2589 nvidia,aspm-pwr-on-t-us = <20>;
>> 2590 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2591
>> 2592 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
>> 2593 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
>> 2594 interconnect-names = "dma-mem", "write";
>> 2595 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
>> 2596 iommu-map-mask = <0x0>;
>> 2597 dma-coherent;
>> 2598 };
>> 2599
>> 2600 pcie-ep@14180000 {
>> 2601 compatible = "nvidia,tegra194-pcie-ep";
>> 2602 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 2603 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> 2604 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2605 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2606 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2607 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2608
>> 2609 status = "disabled";
>> 2610
>> 2611 num-lanes = <8>;
>> 2612 num-ib-windows = <2>;
>> 2613 num-ob-windows = <8>;
>> 2614
>> 2615 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 2616 clock-names = "core";
>> 2617
>> 2618 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 2619 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 2620 reset-names = "apb", "core";
>> 2621
>> 2622 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2623 interrupt-names = "intr";
>> 2624
>> 2625 nvidia,bpmp = <&bpmp 0>;
>> 2626
>> 2627 nvidia,aspm-cmrt-us = <60>;
>> 2628 nvidia,aspm-pwr-on-t-us = <20>;
>> 2629 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2630
>> 2631 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
>> 2632 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
>> 2633 interconnect-names = "dma-mem", "write";
>> 2634 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
>> 2635 iommu-map-mask = <0x0>;
>> 2636 dma-coherent;
>> 2637 };
>> 2638
>> 2639 pcie-ep@141a0000 {
>> 2640 compatible = "nvidia,tegra194-pcie-ep";
>> 2641 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 2642 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> 2643 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> 2644 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> 2645 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 2646 reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> 2647
>> 2648 status = "disabled";
>> 2649
>> 2650 num-lanes = <8>;
>> 2651 num-ib-windows = <2>;
>> 2652 num-ob-windows = <8>;
>> 2653
>> 2654 pinctrl-names = "default";
>> 2655 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> 2656
>> 2657 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> 2658 clock-names = "core";
>> 2659
>> 2660 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 2661 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 2662 reset-names = "apb", "core";
>> 2663
>> 2664 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> 2665 interrupt-names = "intr";
>> 2666
>> 2667 nvidia,bpmp = <&bpmp 5>;
>> 2668
>> 2669 nvidia,aspm-cmrt-us = <60>;
>> 2670 nvidia,aspm-pwr-on-t-us = <20>;
>> 2671 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 2672
>> 2673 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
>> 2674 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
>> 2675 interconnect-names = "dma-mem", "write";
>> 2676 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
>> 2677 iommu-map-mask = <0x0>;
>> 2678 dma-coherent;
>> 2679 };
>> 2680
2827 sram@40000000 { 2681 sram@40000000 {
2828 compatible = "nvidia,tegra194 2682 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 2683 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 2684 #address-cells = <1>;
2832 #size-cells = <1>; 2685 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 2686 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 <<
2835 no-memory-wc; 2687 no-memory-wc;
2836 2688
2837 cpu_bpmp_tx: sram@4e000 { 2689 cpu_bpmp_tx: sram@4e000 {
2838 reg = <0x4e000 0x1000 2690 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 2691 label = "cpu-bpmp-tx";
2840 pool; 2692 pool;
2841 }; 2693 };
2842 2694
2843 cpu_bpmp_rx: sram@4f000 { 2695 cpu_bpmp_rx: sram@4f000 {
2844 reg = <0x4f000 0x1000 2696 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 2697 label = "cpu-bpmp-rx";
2846 pool; 2698 pool;
2847 }; 2699 };
2848 }; 2700 };
2849 2701
2850 bpmp: bpmp { 2702 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 2703 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 2704 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 2705 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu 2706 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2855 #clock-cells = <1>; 2707 #clock-cells = <1>;
2856 #reset-cells = <1>; 2708 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 2709 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 2710 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859 <&mc TEGRA194 2711 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860 <&mc TEGRA194 2712 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861 <&mc TEGRA194 2713 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862 interconnect-names = "read", 2714 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863 iommus = <&smmu TEGRA194_SID_ 2715 iommus = <&smmu TEGRA194_SID_BPMP>;
2864 2716
2865 bpmp_i2c: i2c { 2717 bpmp_i2c: i2c {
2866 compatible = "nvidia, 2718 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 2719 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 2720 #address-cells = <1>;
2869 #size-cells = <0>; 2721 #size-cells = <0>;
2870 }; 2722 };
2871 2723
2872 bpmp_thermal: thermal { 2724 bpmp_thermal: thermal {
2873 compatible = "nvidia, 2725 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 2726 #thermal-sensor-cells = <1>;
2875 }; 2727 };
2876 }; 2728 };
2877 2729
2878 cpus { 2730 cpus {
2879 compatible = "nvidia,tegra194 2731 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>; 2732 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>; 2733 #address-cells = <1>;
2882 #size-cells = <0>; 2734 #size-cells = <0>;
2883 2735
2884 cpu0_0: cpu@0 { 2736 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 2737 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 2738 device_type = "cpu";
2887 reg = <0x000>; 2739 reg = <0x000>;
2888 enable-method = "psci 2740 enable-method = "psci";
2889 i-cache-size = <13107 2741 i-cache-size = <131072>;
2890 i-cache-line-size = < 2742 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 2743 i-cache-sets = <512>;
2892 d-cache-size = <65536 2744 d-cache-size = <65536>;
2893 d-cache-line-size = < 2745 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 2746 d-cache-sets = <256>;
2895 next-level-cache = <& 2747 next-level-cache = <&l2c_0>;
2896 }; 2748 };
2897 2749
2898 cpu0_1: cpu@1 { 2750 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 2751 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 2752 device_type = "cpu";
2901 reg = <0x001>; 2753 reg = <0x001>;
2902 enable-method = "psci 2754 enable-method = "psci";
2903 i-cache-size = <13107 2755 i-cache-size = <131072>;
2904 i-cache-line-size = < 2756 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 2757 i-cache-sets = <512>;
2906 d-cache-size = <65536 2758 d-cache-size = <65536>;
2907 d-cache-line-size = < 2759 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 2760 d-cache-sets = <256>;
2909 next-level-cache = <& 2761 next-level-cache = <&l2c_0>;
2910 }; 2762 };
2911 2763
2912 cpu1_0: cpu@100 { 2764 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 2765 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 2766 device_type = "cpu";
2915 reg = <0x100>; 2767 reg = <0x100>;
2916 enable-method = "psci 2768 enable-method = "psci";
2917 i-cache-size = <13107 2769 i-cache-size = <131072>;
2918 i-cache-line-size = < 2770 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 2771 i-cache-sets = <512>;
2920 d-cache-size = <65536 2772 d-cache-size = <65536>;
2921 d-cache-line-size = < 2773 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 2774 d-cache-sets = <256>;
2923 next-level-cache = <& 2775 next-level-cache = <&l2c_1>;
2924 }; 2776 };
2925 2777
2926 cpu1_1: cpu@101 { 2778 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 2779 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 2780 device_type = "cpu";
2929 reg = <0x101>; 2781 reg = <0x101>;
2930 enable-method = "psci 2782 enable-method = "psci";
2931 i-cache-size = <13107 2783 i-cache-size = <131072>;
2932 i-cache-line-size = < 2784 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 2785 i-cache-sets = <512>;
2934 d-cache-size = <65536 2786 d-cache-size = <65536>;
2935 d-cache-line-size = < 2787 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 2788 d-cache-sets = <256>;
2937 next-level-cache = <& 2789 next-level-cache = <&l2c_1>;
2938 }; 2790 };
2939 2791
2940 cpu2_0: cpu@200 { 2792 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 2793 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 2794 device_type = "cpu";
2943 reg = <0x200>; 2795 reg = <0x200>;
2944 enable-method = "psci 2796 enable-method = "psci";
2945 i-cache-size = <13107 2797 i-cache-size = <131072>;
2946 i-cache-line-size = < 2798 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 2799 i-cache-sets = <512>;
2948 d-cache-size = <65536 2800 d-cache-size = <65536>;
2949 d-cache-line-size = < 2801 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 2802 d-cache-sets = <256>;
2951 next-level-cache = <& 2803 next-level-cache = <&l2c_2>;
2952 }; 2804 };
2953 2805
2954 cpu2_1: cpu@201 { 2806 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 2807 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 2808 device_type = "cpu";
2957 reg = <0x201>; 2809 reg = <0x201>;
2958 enable-method = "psci 2810 enable-method = "psci";
2959 i-cache-size = <13107 2811 i-cache-size = <131072>;
2960 i-cache-line-size = < 2812 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 2813 i-cache-sets = <512>;
2962 d-cache-size = <65536 2814 d-cache-size = <65536>;
2963 d-cache-line-size = < 2815 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 2816 d-cache-sets = <256>;
2965 next-level-cache = <& 2817 next-level-cache = <&l2c_2>;
2966 }; 2818 };
2967 2819
2968 cpu3_0: cpu@300 { 2820 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 2821 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 2822 device_type = "cpu";
2971 reg = <0x300>; 2823 reg = <0x300>;
2972 enable-method = "psci 2824 enable-method = "psci";
2973 i-cache-size = <13107 2825 i-cache-size = <131072>;
2974 i-cache-line-size = < 2826 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 2827 i-cache-sets = <512>;
2976 d-cache-size = <65536 2828 d-cache-size = <65536>;
2977 d-cache-line-size = < 2829 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 2830 d-cache-sets = <256>;
2979 next-level-cache = <& 2831 next-level-cache = <&l2c_3>;
2980 }; 2832 };
2981 2833
2982 cpu3_1: cpu@301 { 2834 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 2835 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 2836 device_type = "cpu";
2985 reg = <0x301>; 2837 reg = <0x301>;
2986 enable-method = "psci 2838 enable-method = "psci";
2987 i-cache-size = <13107 2839 i-cache-size = <131072>;
2988 i-cache-line-size = < 2840 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 2841 i-cache-sets = <512>;
2990 d-cache-size = <65536 2842 d-cache-size = <65536>;
2991 d-cache-line-size = < 2843 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 2844 d-cache-sets = <256>;
2993 next-level-cache = <& 2845 next-level-cache = <&l2c_3>;
2994 }; 2846 };
2995 2847
2996 cpu-map { 2848 cpu-map {
2997 cluster0 { 2849 cluster0 {
2998 core0 { 2850 core0 {
2999 cpu = 2851 cpu = <&cpu0_0>;
3000 }; 2852 };
3001 2853
3002 core1 { 2854 core1 {
3003 cpu = 2855 cpu = <&cpu0_1>;
3004 }; 2856 };
3005 }; 2857 };
3006 2858
3007 cluster1 { 2859 cluster1 {
3008 core0 { 2860 core0 {
3009 cpu = 2861 cpu = <&cpu1_0>;
3010 }; 2862 };
3011 2863
3012 core1 { 2864 core1 {
3013 cpu = 2865 cpu = <&cpu1_1>;
3014 }; 2866 };
3015 }; 2867 };
3016 2868
3017 cluster2 { 2869 cluster2 {
3018 core0 { 2870 core0 {
3019 cpu = 2871 cpu = <&cpu2_0>;
3020 }; 2872 };
3021 2873
3022 core1 { 2874 core1 {
3023 cpu = 2875 cpu = <&cpu2_1>;
3024 }; 2876 };
3025 }; 2877 };
3026 2878
3027 cluster3 { 2879 cluster3 {
3028 core0 { 2880 core0 {
3029 cpu = 2881 cpu = <&cpu3_0>;
3030 }; 2882 };
3031 2883
3032 core1 { 2884 core1 {
3033 cpu = 2885 cpu = <&cpu3_1>;
3034 }; 2886 };
3035 }; 2887 };
3036 }; 2888 };
3037 2889
3038 l2c_0: l2-cache0 { 2890 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 2891 cache-size = <2097152>;
3042 cache-line-size = <64 2892 cache-line-size = <64>;
3043 cache-sets = <2048>; 2893 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 2894 next-level-cache = <&l3c>;
3046 }; 2895 };
3047 2896
3048 l2c_1: l2-cache1 { 2897 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 2898 cache-size = <2097152>;
3052 cache-line-size = <64 2899 cache-line-size = <64>;
3053 cache-sets = <2048>; 2900 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 2901 next-level-cache = <&l3c>;
3056 }; 2902 };
3057 2903
3058 l2c_2: l2-cache2 { 2904 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 2905 cache-size = <2097152>;
3062 cache-line-size = <64 2906 cache-line-size = <64>;
3063 cache-sets = <2048>; 2907 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 2908 next-level-cache = <&l3c>;
3066 }; 2909 };
3067 2910
3068 l2c_3: l2-cache3 { 2911 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 2912 cache-size = <2097152>;
3072 cache-line-size = <64 2913 cache-line-size = <64>;
3073 cache-sets = <2048>; 2914 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 2915 next-level-cache = <&l3c>;
3076 }; 2916 };
3077 2917
3078 l3c: l3-cache { 2918 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 2919 cache-size = <4194304>;
3082 cache-line-size = <64 2920 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 2921 cache-sets = <4096>;
3085 }; 2922 };
3086 }; 2923 };
3087 2924
3088 pmu { 2925 pmu {
3089 compatible = "nvidia,carmel-p 2926 compatible = "nvidia,carmel-pmu";
3090 interrupts = <GIC_SPI 384 IRQ 2927 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 385 IRQ 2928 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 386 IRQ 2929 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 387 IRQ 2930 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 388 IRQ 2931 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 389 IRQ 2932 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 390 IRQ 2933 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 391 IRQ 2934 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3098 interrupt-affinity = <&cpu0_0 2935 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3099 &cpu2_0 2936 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3100 }; 2937 };
3101 2938
3102 psci { 2939 psci {
3103 compatible = "arm,psci-1.0"; 2940 compatible = "arm,psci-1.0";
3104 status = "okay"; 2941 status = "okay";
3105 method = "smc"; 2942 method = "smc";
3106 }; 2943 };
3107 2944
3108 tcu: serial { <<
3109 compatible = "nvidia,tegra194 <<
3110 mboxes = <&hsp_top0 TEGRA_HSP <<
3111 <&hsp_aon TEGRA_HSP_ <<
3112 mbox-names = "rx", "tx"; <<
3113 }; <<
3114 <<
3115 sound { 2945 sound {
3116 status = "disabled"; 2946 status = "disabled";
3117 2947
3118 clocks = <&bpmp TEGRA194_CLK_ 2948 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_ 2949 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120 clock-names = "pll_a", "plla_ 2950 clock-names = "pll_a", "plla_out0";
3121 assigned-clocks = <&bpmp TEGR 2951 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGR 2952 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGR 2953 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124 assigned-clock-parents = <0>, 2954 assigned-clock-parents = <0>,
3125 <&bp 2955 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bp 2956 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3127 /* 2957 /*
3128 * PLLA supports dynamic ramp 2958 * PLLA supports dynamic ramp. Below initial rate is chosen
3129 * for this to work and oscil 2959 * for this to work and oscillate between base rates required
3130 * for 8x and 11.025x sample 2960 * for 8x and 11.025x sample rate streams.
3131 */ 2961 */
3132 assigned-clock-rates = <25800 2962 assigned-clock-rates = <258000000>;
>> 2963 };
>> 2964
>> 2965 tcu: serial {
>> 2966 compatible = "nvidia,tegra194-tcu";
>> 2967 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
>> 2968 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
>> 2969 mbox-names = "rx", "tx";
3133 }; 2970 };
3134 2971
3135 thermal-zones { 2972 thermal-zones {
3136 cpu-thermal { 2973 cpu-thermal {
3137 thermal-sensors = <&{ 2974 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 2975 status = "disabled";
3139 }; 2976 };
3140 2977
3141 gpu-thermal { 2978 gpu-thermal {
3142 thermal-sensors = <&{ 2979 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 2980 status = "disabled";
3144 }; 2981 };
3145 2982
3146 aux-thermal { 2983 aux-thermal {
3147 thermal-sensors = <&{ 2984 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 2985 status = "disabled";
3149 }; 2986 };
3150 2987
3151 pllx-thermal { 2988 pllx-thermal {
3152 thermal-sensors = <&{ 2989 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 2990 status = "disabled";
3154 }; 2991 };
3155 2992
3156 ao-thermal { 2993 ao-thermal {
3157 thermal-sensors = <&{ 2994 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 2995 status = "disabled";
3159 }; 2996 };
3160 2997
3161 tj-thermal { 2998 tj-thermal {
3162 thermal-sensors = <&{ 2999 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 3000 status = "disabled";
3164 }; 3001 };
3165 }; 3002 };
3166 3003
3167 timer { 3004 timer {
3168 compatible = "arm,armv8-timer 3005 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 3006 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 3007 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 3008 <GIC_PPI 14
3172 (GIC_CPU_MASK 3009 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 3010 <GIC_PPI 11
3174 (GIC_CPU_MASK 3011 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 3012 <GIC_PPI 10
3176 (GIC_CPU_MASK 3013 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 3014 interrupt-parent = <&gic>;
3178 always-on; 3015 always-on;
3179 }; 3016 };
3180 }; 3017 };
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