1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h> 2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate 7 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h> 8 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-th 9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h> 10 #include <dt-bindings/memory/tegra194-mc.h>
12 11
13 / { 12 / {
14 compatible = "nvidia,tegra194"; 13 compatible = "nvidia,tegra194";
15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
16 #address-cells = <2>; 15 #address-cells = <2>;
17 #size-cells = <2>; 16 #size-cells = <2>;
18 17
19 /* control backbone */ 18 /* control backbone */
20 bus@0 { !! 19 cbb@0 {
21 compatible = "simple-bus"; 20 compatible = "simple-bus";
>> 21 #address-cells = <1>;
>> 22 #size-cells = <1>;
>> 23 ranges = <0x0 0x0 0x0 0x40000000>;
22 24
23 #address-cells = <2>; !! 25 misc@100000 {
24 #size-cells = <2>; <<
25 ranges = <0x0 0x0 0x0 0x0 0x10 <<
26 <<
27 apbmisc: misc@100000 { <<
28 compatible = "nvidia,t 26 compatible = "nvidia,tegra194-misc";
29 reg = <0x0 0x00100000 !! 27 reg = <0x00100000 0xf000>,
30 <0x0 0x0010f000 !! 28 <0x0010f000 0x1000>;
31 }; 29 };
32 30
33 gpio: gpio@2200000 { 31 gpio: gpio@2200000 {
34 compatible = "nvidia,t 32 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security" 33 reg-names = "security", "gpio";
36 reg = <0x0 0x2200000 0 !! 34 reg = <0x2200000 0x10000>,
37 <0x0 0x2210000 0 !! 35 <0x2210000 0x10000>;
38 interrupts = <GIC_SPI 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI <<
40 <GIC_SPI <<
41 <GIC_SPI <<
42 <GIC_SPI <<
43 <GIC_SPI <<
44 <GIC_SPI <<
45 <GIC_SPI <<
46 <GIC_SPI 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI <<
48 <GIC_SPI <<
49 <GIC_SPI <<
50 <GIC_SPI <<
51 <GIC_SPI <<
52 <GIC_SPI <<
53 <GIC_SPI <<
54 <GIC_SPI 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI <<
56 <GIC_SPI <<
57 <GIC_SPI <<
58 <GIC_SPI <<
59 <GIC_SPI <<
60 <GIC_SPI <<
61 <GIC_SPI <<
62 <GIC_SPI 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI <<
64 <GIC_SPI <<
65 <GIC_SPI <<
66 <GIC_SPI <<
67 <GIC_SPI <<
68 <GIC_SPI <<
69 <GIC_SPI <<
70 <GIC_SPI 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI !! 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
72 <GIC_SPI <<
73 <GIC_SPI <<
74 <GIC_SPI <<
75 <GIC_SPI <<
76 <GIC_SPI <<
77 <GIC_SPI <<
78 <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 #interrupt-cells = <2> 42 #interrupt-cells = <2>;
87 interrupt-controller; 43 interrupt-controller;
88 #gpio-cells = <2>; 44 #gpio-cells = <2>;
89 gpio-controller; 45 gpio-controller;
90 gpio-ranges = <&pinmux <<
91 }; <<
92 <<
93 cbb-noc@2300000 { <<
94 compatible = "nvidia,t <<
95 reg = <0x0 0x02300000 <<
96 interrupts = <GIC_SPI <<
97 <GIC_SPI <<
98 nvidia,axi2apb = <&axi <<
99 nvidia,apbmisc = <&apb <<
100 status = "okay"; <<
101 }; <<
102 <<
103 axi2apb: axi2apb@2390000 { <<
104 compatible = "nvidia,t <<
105 reg = <0x0 0x2390000 0 <<
106 <0x0 0x23a0000 0 <<
107 <0x0 0x23b0000 0 <<
108 <0x0 0x23c0000 0 <<
109 <0x0 0x23d0000 0 <<
110 <0x0 0x23e0000 0 <<
111 status = "okay"; <<
112 }; <<
113 <<
114 pinmux: pinmux@2430000 { <<
115 compatible = "nvidia,t <<
116 reg = <0x0 0x2430000 0 <<
117 status = "okay"; <<
118 <<
119 pex_clkreq_c5_bi_dir_s <<
120 clkreq { <<
121 nvidia <<
122 nvidia <<
123 nvidia <<
124 nvidia <<
125 nvidia <<
126 nvidia <<
127 }; <<
128 }; <<
129 <<
130 pex_rst_c5_out_state: <<
131 pex_rst { <<
132 nvidia <<
133 nvidia <<
134 nvidia <<
135 nvidia <<
136 nvidia <<
137 nvidia <<
138 }; <<
139 }; <<
140 }; 46 };
141 47
142 ethernet@2490000 { 48 ethernet@2490000 {
143 compatible = "nvidia,t 49 compatible = "nvidia,tegra194-eqos",
144 "nvidia,t 50 "nvidia,tegra186-eqos",
145 "snps,dwc 51 "snps,dwc-qos-ethernet-4.10";
146 reg = <0x0 0x02490000 !! 52 reg = <0x02490000 0x10000>;
147 interrupts = <GIC_SPI 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&bpmp TEGRA1 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA1 55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA1 56 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA1 57 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA1 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_ 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA1 60 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos"; 61 reset-names = "eqos";
156 interconnects = <&mc T <<
157 <&mc T <<
158 interconnect-names = " <<
159 iommus = <&smmu TEGRA1 <<
160 status = "disabled"; 62 status = "disabled";
161 63
162 snps,write-requests = 64 snps,write-requests = <1>;
163 snps,read-requests = < 65 snps,read-requests = <3>;
164 snps,burst-map = <0x7> 66 snps,burst-map = <0x7>;
165 snps,txpbl = <16>; 67 snps,txpbl = <16>;
166 snps,rxpbl = <8>; 68 snps,rxpbl = <8>;
167 }; 69 };
168 70
169 gpcdma: dma-controller@2600000 <<
170 compatible = "nvidia,t <<
171 "nvidia,t <<
172 reg = <0x0 0x2600000 0 <<
173 resets = <&bpmp TEGRA1 <<
174 reset-names = "gpcdma" <<
175 interrupts = <GIC_SPI <<
176 <GIC_SPI <<
177 <GIC_SPI <<
178 <GIC_SPI <<
179 <GIC_SPI <<
180 <GIC_SPI <<
181 <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 #dma-cells = <1>; <<
208 iommus = <&smmu TEGRA1 <<
209 dma-coherent; <<
210 dma-channel-mask = <0x <<
211 status = "okay"; <<
212 }; <<
213 <<
214 aconnect@2900000 { 71 aconnect@2900000 {
215 compatible = "nvidia,t 72 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,t 73 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA1 74 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA1 75 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", " 76 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp 77 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> 78 #address-cells = <1>;
>> 79 #size-cells = <1>;
>> 80 ranges = <0x02900000 0x02900000 0x200000>;
221 status = "disabled"; 81 status = "disabled";
222 82
223 #address-cells = <2>; !! 83 dma-controller@2930000 {
224 #size-cells = <2>; <<
225 ranges = <0x0 0x029000 <<
226 <<
227 tegra_ahub: ahub@29008 <<
228 compatible = " <<
229 " <<
230 reg = <0x0 0x0 <<
231 clocks = <&bpm <<
232 clock-names = <<
233 assigned-clock <<
234 assigned-clock <<
235 assigned-clock <<
236 status = "disa <<
237 <<
238 #address-cells <<
239 #size-cells = <<
240 ranges = <0x0 <<
241 <<
242 tegra_i2s1: i2 <<
243 compat <<
244 <<
245 reg = <<
246 clocks <<
247 <<
248 clock- <<
249 assign <<
250 assign <<
251 assign <<
252 sound- <<
253 status <<
254 }; <<
255 <<
256 tegra_i2s2: i2 <<
257 compat <<
258 <<
259 reg = <<
260 clocks <<
261 <<
262 clock- <<
263 assign <<
264 assign <<
265 assign <<
266 sound- <<
267 status <<
268 }; <<
269 <<
270 tegra_i2s3: i2 <<
271 compat <<
272 <<
273 reg = <<
274 clocks <<
275 <<
276 clock- <<
277 assign <<
278 assign <<
279 assign <<
280 sound- <<
281 status <<
282 }; <<
283 <<
284 tegra_i2s4: i2 <<
285 compat <<
286 <<
287 reg = <<
288 clocks <<
289 <<
290 clock- <<
291 assign <<
292 assign <<
293 assign <<
294 sound- <<
295 status <<
296 }; <<
297 <<
298 tegra_i2s5: i2 <<
299 compat <<
300 <<
301 reg = <<
302 clocks <<
303 <<
304 clock- <<
305 assign <<
306 assign <<
307 assign <<
308 sound- <<
309 status <<
310 }; <<
311 <<
312 tegra_i2s6: i2 <<
313 compat <<
314 <<
315 reg = <<
316 clocks <<
317 <<
318 clock- <<
319 assign <<
320 assign <<
321 assign <<
322 sound- <<
323 status <<
324 }; <<
325 <<
326 tegra_sfc1: sf <<
327 compat <<
328 <<
329 reg = <<
330 sound- <<
331 status <<
332 }; <<
333 <<
334 tegra_sfc2: sf <<
335 compat <<
336 <<
337 reg = <<
338 sound- <<
339 status <<
340 }; <<
341 <<
342 tegra_sfc3: sf <<
343 compat <<
344 <<
345 reg = <<
346 sound- <<
347 status <<
348 }; <<
349 <<
350 tegra_sfc4: sf <<
351 compat <<
352 <<
353 reg = <<
354 sound- <<
355 status <<
356 }; <<
357 <<
358 tegra_amx1: am <<
359 compat <<
360 reg = <<
361 sound- <<
362 status <<
363 }; <<
364 <<
365 tegra_amx2: am <<
366 compat <<
367 reg = <<
368 sound- <<
369 status <<
370 }; <<
371 <<
372 tegra_amx3: am <<
373 compat <<
374 reg = <<
375 sound- <<
376 status <<
377 }; <<
378 <<
379 tegra_amx4: am <<
380 compat <<
381 reg = <<
382 sound- <<
383 status <<
384 }; <<
385 <<
386 tegra_adx1: ad <<
387 compat <<
388 <<
389 reg = <<
390 sound- <<
391 status <<
392 }; <<
393 <<
394 tegra_adx2: ad <<
395 compat <<
396 <<
397 reg = <<
398 sound- <<
399 status <<
400 }; <<
401 <<
402 tegra_adx3: ad <<
403 compat <<
404 <<
405 reg = <<
406 sound- <<
407 status <<
408 }; <<
409 <<
410 tegra_adx4: ad <<
411 compat <<
412 <<
413 reg = <<
414 sound- <<
415 status <<
416 }; <<
417 <<
418 tegra_dmic1: d <<
419 compat <<
420 <<
421 reg = <<
422 clocks <<
423 clock- <<
424 assign <<
425 assign <<
426 assign <<
427 sound- <<
428 status <<
429 }; <<
430 <<
431 tegra_dmic2: d <<
432 compat <<
433 <<
434 reg = <<
435 clocks <<
436 clock- <<
437 assign <<
438 assign <<
439 assign <<
440 sound- <<
441 status <<
442 }; <<
443 <<
444 tegra_dmic3: d <<
445 compat <<
446 <<
447 reg = <<
448 clocks <<
449 clock- <<
450 assign <<
451 assign <<
452 assign <<
453 sound- <<
454 status <<
455 }; <<
456 <<
457 tegra_dmic4: d <<
458 compat <<
459 <<
460 reg = <<
461 clocks <<
462 clock- <<
463 assign <<
464 assign <<
465 assign <<
466 sound- <<
467 status <<
468 }; <<
469 <<
470 tegra_dspk1: d <<
471 compat <<
472 <<
473 reg = <<
474 clocks <<
475 clock- <<
476 assign <<
477 assign <<
478 assign <<
479 sound- <<
480 status <<
481 }; <<
482 <<
483 tegra_dspk2: d <<
484 compat <<
485 <<
486 reg = <<
487 clocks <<
488 clock- <<
489 assign <<
490 assign <<
491 assign <<
492 sound- <<
493 status <<
494 }; <<
495 <<
496 tegra_ope1: pr <<
497 compat <<
498 <<
499 reg = <<
500 sound- <<
501 status <<
502 <<
503 #addre <<
504 #size- <<
505 ranges <<
506 <<
507 equali <<
508 <<
509 <<
510 <<
511 }; <<
512 <<
513 dynami <<
514 <<
515 <<
516 <<
517 }; <<
518 }; <<
519 <<
520 tegra_mvc1: mv <<
521 compat <<
522 <<
523 reg = <<
524 sound- <<
525 status <<
526 }; <<
527 <<
528 tegra_mvc2: mv <<
529 compat <<
530 <<
531 reg = <<
532 sound- <<
533 status <<
534 }; <<
535 <<
536 tegra_amixer: <<
537 compat <<
538 <<
539 reg = <<
540 sound- <<
541 status <<
542 }; <<
543 <<
544 tegra_admaif: <<
545 compat <<
546 <<
547 reg = <<
548 dmas = <<
549 <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 <<
556 <<
557 <<
558 <<
559 <<
560 <<
561 <<
562 <<
563 <<
564 <<
565 <<
566 <<
567 <<
568 dma-na <<
569 <<
570 <<
571 <<
572 <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 <<
579 <<
580 <<
581 <<
582 <<
583 <<
584 <<
585 <<
586 <<
587 <<
588 status <<
589 interc <<
590 <<
591 interc <<
592 iommus <<
593 }; <<
594 <<
595 tegra_asrc: as <<
596 compat <<
597 <<
598 reg = <<
599 sound- <<
600 status <<
601 }; <<
602 }; <<
603 <<
604 adma: dma-controller@2 <<
605 compatible = " 84 compatible = "nvidia,tegra194-adma",
606 " 85 "nvidia,tegra186-adma";
607 reg = <0x0 0x0 !! 86 reg = <0x02930000 0x20000>;
608 interrupt-pare 87 interrupt-parent = <&agic>;
609 interrupts = 88 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
610 89 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
611 90 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
612 91 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
613 92 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
614 93 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
615 94 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
616 95 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
617 96 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
618 97 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
619 98 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
620 99 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
621 100 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
622 101 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
623 102 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
624 103 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
625 104 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
626 105 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
627 106 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
628 107 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
629 108 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
630 109 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
631 110 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
632 111 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
633 112 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
634 113 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
635 114 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
636 115 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
637 116 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
638 117 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
639 118 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
640 119 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
641 #dma-cells = < 120 #dma-cells = <1>;
642 clocks = <&bpm 121 clocks = <&bpmp TEGRA194_CLK_AHUB>;
643 clock-names = 122 clock-names = "d_audio";
644 status = "disa 123 status = "disabled";
645 }; 124 };
646 125
647 agic: interrupt-contro 126 agic: interrupt-controller@2a40000 {
648 compatible = " 127 compatible = "nvidia,tegra194-agic",
649 " 128 "nvidia,tegra210-agic";
650 #interrupt-cel 129 #interrupt-cells = <3>;
651 interrupt-cont 130 interrupt-controller;
652 reg = <0x0 0x0 !! 131 reg = <0x02a41000 0x1000>,
653 <0x0 0x0 !! 132 <0x02a42000 0x2000>;
654 interrupts = < 133 interrupts = <GIC_SPI 145
655 134 (GIC_CPU_MASK_SIMPLE(4) |
656 135 IRQ_TYPE_LEVEL_HIGH)>;
657 clocks = <&bpm 136 clocks = <&bpmp TEGRA194_CLK_APE>;
658 clock-names = 137 clock-names = "clk";
659 status = "disa 138 status = "disabled";
660 }; 139 };
661 }; 140 };
662 141
>> 142 pinmux: pinmux@2430000 {
>> 143 compatible = "nvidia,tegra194-pinmux";
>> 144 reg = <0x2430000 0x17000
>> 145 0xc300000 0x4000>;
>> 146
>> 147 status = "okay";
>> 148
>> 149 pex_rst_c5_out_state: pex_rst_c5_out {
>> 150 pex_rst {
>> 151 nvidia,pins = "pex_l5_rst_n_pgg1";
>> 152 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
>> 153 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
>> 154 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
>> 155 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
>> 156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> 157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
>> 158 };
>> 159 };
>> 160
>> 161 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
>> 162 clkreq {
>> 163 nvidia,pins = "pex_l5_clkreq_n_pgg0";
>> 164 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
>> 165 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
>> 166 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
>> 167 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
>> 168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
>> 170 };
>> 171 };
>> 172 };
>> 173
663 mc: memory-controller@2c00000 174 mc: memory-controller@2c00000 {
664 compatible = "nvidia,t 175 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 !! 176 reg = <0x02c00000 0x100000>,
666 <0x0 0x02c10000 !! 177 <0x02b80000 0x040000>,
667 <0x0 0x02c20000 !! 178 <0x01700000 0x100000>;
668 <0x0 0x02c30000 <<
669 <0x0 0x02c40000 <<
670 <0x0 0x02c50000 <<
671 <0x0 0x02b80000 <<
672 <0x0 0x02b90000 <<
673 <0x0 0x02ba0000 <<
674 <0x0 0x02bb0000 <<
675 <0x0 0x01700000 <<
676 <0x0 0x01710000 <<
677 <0x0 0x01720000 <<
678 <0x0 0x01730000 <<
679 <0x0 0x01740000 <<
680 <0x0 0x01750000 <<
681 <0x0 0x01760000 <<
682 <0x0 0x01770000 <<
683 reg-names = "sid", "br <<
684 "ch4", "ch <<
685 "ch11", "c <<
686 interrupts = <GIC_SPI <<
687 #interconnect-cells = <<
688 status = "disabled"; 179 status = "disabled";
689 180
690 #address-cells = <2>; 181 #address-cells = <2>;
691 #size-cells = <2>; 182 #size-cells = <2>;
692 ranges = <0x0 0x017000 !! 183
693 <0x0 0x02b800 !! 184 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
694 <0x0 0x02c000 !! 185 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
>> 186 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
695 187
696 /* 188 /*
697 * Bit 39 of addresses 189 * Bit 39 of addresses passing through the memory
698 * controller selects 190 * controller selects the XBAR format used when memory
699 * is accessed. This i 191 * is accessed. This is used to transparently access
700 * memory in the XBAR 192 * memory in the XBAR format used by the discrete GPU
701 * (bit 39 set) or Teg 193 * (bit 39 set) or Tegra (bit 39 clear).
702 * 194 *
703 * As a consequence, t 195 * As a consequence, the operating system must ensure
704 * that bit 39 is neve 196 * that bit 39 is never used implicitly, for example
705 * via an I/O virtual 197 * via an I/O virtual address mapping of an IOMMU. If
706 * devices require acc 198 * devices require access to the XBAR switch, their
707 * drivers must set th 199 * drivers must set this bit explicitly.
708 * 200 *
709 * Limit the DMA range 201 * Limit the DMA range for memory clients to [38:0].
710 */ 202 */
711 dma-ranges = <0x0 0x0 !! 203 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
712 204
713 emc: external-memory-c 205 emc: external-memory-controller@2c60000 {
714 compatible = " 206 compatible = "nvidia,tegra194-emc";
715 reg = <0x0 0x0 207 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x0 208 <0x0 0x01780000 0x0 0x80000>;
717 interrupts = < <<
718 clocks = <&bpm 209 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = 210 clock-names = "emc";
720 211
721 #interconnect- <<
722 <<
723 nvidia,bpmp = 212 nvidia,bpmp = <&bpmp>;
724 }; 213 };
725 }; 214 };
726 215
727 timer@3010000 { <<
728 compatible = "nvidia,t <<
729 reg = <0x0 0x03010000 <<
730 interrupts = <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 status = "okay"; <<
741 }; <<
742 <<
743 uarta: serial@3100000 { 216 uarta: serial@3100000 {
744 compatible = "nvidia,t 217 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
745 reg = <0x0 0x03100000 !! 218 reg = <0x03100000 0x40>;
746 reg-shift = <2>; 219 reg-shift = <2>;
747 interrupts = <GIC_SPI 220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&bpmp TEGRA1 221 clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> 222 clock-names = "serial";
749 resets = <&bpmp TEGRA1 223 resets = <&bpmp TEGRA194_RESET_UARTA>;
>> 224 reset-names = "serial";
750 status = "disabled"; 225 status = "disabled";
751 }; 226 };
752 227
753 uartb: serial@3110000 { 228 uartb: serial@3110000 {
754 compatible = "nvidia,t 229 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
755 reg = <0x0 0x03110000 !! 230 reg = <0x03110000 0x40>;
756 reg-shift = <2>; 231 reg-shift = <2>;
757 interrupts = <GIC_SPI 232 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&bpmp TEGRA1 233 clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> 234 clock-names = "serial";
759 resets = <&bpmp TEGRA1 235 resets = <&bpmp TEGRA194_RESET_UARTB>;
>> 236 reset-names = "serial";
760 status = "disabled"; 237 status = "disabled";
761 }; 238 };
762 239
763 uartd: serial@3130000 { 240 uartd: serial@3130000 {
764 compatible = "nvidia,t 241 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg = <0x0 0x03130000 !! 242 reg = <0x03130000 0x40>;
766 reg-shift = <2>; 243 reg-shift = <2>;
767 interrupts = <GIC_SPI 244 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&bpmp TEGRA1 245 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial" 246 clock-names = "serial";
770 resets = <&bpmp TEGRA1 247 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial" 248 reset-names = "serial";
772 status = "disabled"; 249 status = "disabled";
773 }; 250 };
774 251
775 uarte: serial@3140000 { 252 uarte: serial@3140000 {
776 compatible = "nvidia,t 253 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg = <0x0 0x03140000 !! 254 reg = <0x03140000 0x40>;
778 reg-shift = <2>; 255 reg-shift = <2>;
779 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA1 257 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial" 258 clock-names = "serial";
782 resets = <&bpmp TEGRA1 259 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial" 260 reset-names = "serial";
784 status = "disabled"; 261 status = "disabled";
785 }; 262 };
786 263
787 uartf: serial@3150000 { 264 uartf: serial@3150000 {
788 compatible = "nvidia,t 265 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg = <0x0 0x03150000 !! 266 reg = <0x03150000 0x40>;
790 reg-shift = <2>; 267 reg-shift = <2>;
791 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&bpmp TEGRA1 269 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial" 270 clock-names = "serial";
794 resets = <&bpmp TEGRA1 271 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial" 272 reset-names = "serial";
796 status = "disabled"; 273 status = "disabled";
797 }; 274 };
798 275
799 gen1_i2c: i2c@3160000 { 276 gen1_i2c: i2c@3160000 {
800 compatible = "nvidia,t 277 compatible = "nvidia,tegra194-i2c";
801 reg = <0x0 0x03160000 !! 278 reg = <0x03160000 0x10000>;
802 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 280 #address-cells = <1>;
804 #size-cells = <0>; 281 #size-cells = <0>;
805 clocks = <&bpmp TEGRA1 282 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk 283 clock-names = "div-clk";
807 resets = <&bpmp TEGRA1 284 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c"; 285 reset-names = "i2c";
809 dmas = <&gpcdma 21>, < <<
810 dma-names = "rx", "tx" <<
811 status = "disabled"; 286 status = "disabled";
812 }; 287 };
813 288
814 uarth: serial@3170000 { 289 uarth: serial@3170000 {
815 compatible = "nvidia,t 290 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
816 reg = <0x0 0x03170000 !! 291 reg = <0x03170000 0x40>;
817 reg-shift = <2>; 292 reg-shift = <2>;
818 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&bpmp TEGRA1 294 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial" 295 clock-names = "serial";
821 resets = <&bpmp TEGRA1 296 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial" 297 reset-names = "serial";
823 status = "disabled"; 298 status = "disabled";
824 }; 299 };
825 300
826 cam_i2c: i2c@3180000 { 301 cam_i2c: i2c@3180000 {
827 compatible = "nvidia,t 302 compatible = "nvidia,tegra194-i2c";
828 reg = <0x0 0x03180000 !! 303 reg = <0x03180000 0x10000>;
829 interrupts = <GIC_SPI 304 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
830 #address-cells = <1>; 305 #address-cells = <1>;
831 #size-cells = <0>; 306 #size-cells = <0>;
832 clocks = <&bpmp TEGRA1 307 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk 308 clock-names = "div-clk";
834 resets = <&bpmp TEGRA1 309 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c"; 310 reset-names = "i2c";
836 dmas = <&gpcdma 23>, < <<
837 dma-names = "rx", "tx" <<
838 status = "disabled"; 311 status = "disabled";
839 }; 312 };
840 313
841 /* shares pads with dpaux1 */ 314 /* shares pads with dpaux1 */
842 dp_aux_ch1_i2c: i2c@3190000 { 315 dp_aux_ch1_i2c: i2c@3190000 {
843 compatible = "nvidia,t 316 compatible = "nvidia,tegra194-i2c";
844 reg = <0x0 0x03190000 !! 317 reg = <0x03190000 0x10000>;
845 interrupts = <GIC_SPI 318 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>; 319 #address-cells = <1>;
847 #size-cells = <0>; 320 #size-cells = <0>;
848 clocks = <&bpmp TEGRA1 321 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk 322 clock-names = "div-clk";
850 resets = <&bpmp TEGRA1 323 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c"; 324 reset-names = "i2c";
852 pinctrl-0 = <&state_dp <<
853 pinctrl-1 = <&state_dp <<
854 pinctrl-names = "defau <<
855 dmas = <&gpcdma 26>, < <<
856 dma-names = "rx", "tx" <<
857 status = "disabled"; 325 status = "disabled";
858 }; 326 };
859 327
860 /* shares pads with dpaux0 */ 328 /* shares pads with dpaux0 */
861 dp_aux_ch0_i2c: i2c@31b0000 { 329 dp_aux_ch0_i2c: i2c@31b0000 {
862 compatible = "nvidia,t 330 compatible = "nvidia,tegra194-i2c";
863 reg = <0x0 0x031b0000 !! 331 reg = <0x031b0000 0x10000>;
864 interrupts = <GIC_SPI 332 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>; 333 #address-cells = <1>;
866 #size-cells = <0>; 334 #size-cells = <0>;
867 clocks = <&bpmp TEGRA1 335 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk 336 clock-names = "div-clk";
869 resets = <&bpmp TEGRA1 337 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c"; 338 reset-names = "i2c";
871 pinctrl-0 = <&state_dp <<
872 pinctrl-1 = <&state_dp <<
873 pinctrl-names = "defau <<
874 dmas = <&gpcdma 30>, < <<
875 dma-names = "rx", "tx" <<
876 status = "disabled"; 339 status = "disabled";
877 }; 340 };
878 341
879 /* shares pads with dpaux2 */ !! 342 gen7_i2c: i2c@31c0000 {
880 dp_aux_ch2_i2c: i2c@31c0000 { <<
881 compatible = "nvidia,t 343 compatible = "nvidia,tegra194-i2c";
882 reg = <0x0 0x031c0000 !! 344 reg = <0x031c0000 0x10000>;
883 interrupts = <GIC_SPI 345 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>; 346 #address-cells = <1>;
885 #size-cells = <0>; 347 #size-cells = <0>;
886 clocks = <&bpmp TEGRA1 348 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk 349 clock-names = "div-clk";
888 resets = <&bpmp TEGRA1 350 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c"; 351 reset-names = "i2c";
890 pinctrl-0 = <&state_dp <<
891 pinctrl-1 = <&state_dp <<
892 pinctrl-names = "defau <<
893 dmas = <&gpcdma 27>, < <<
894 dma-names = "rx", "tx" <<
895 status = "disabled"; 352 status = "disabled";
896 }; 353 };
897 354
898 /* shares pads with dpaux3 */ !! 355 gen9_i2c: i2c@31e0000 {
899 dp_aux_ch3_i2c: i2c@31e0000 { <<
900 compatible = "nvidia,t 356 compatible = "nvidia,tegra194-i2c";
901 reg = <0x0 0x031e0000 !! 357 reg = <0x031e0000 0x10000>;
902 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
903 #address-cells = <1>; 359 #address-cells = <1>;
904 #size-cells = <0>; 360 #size-cells = <0>;
905 clocks = <&bpmp TEGRA1 361 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk 362 clock-names = "div-clk";
907 resets = <&bpmp TEGRA1 363 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c"; 364 reset-names = "i2c";
909 pinctrl-0 = <&state_dp <<
910 pinctrl-1 = <&state_dp <<
911 pinctrl-names = "defau <<
912 dmas = <&gpcdma 31>, < <<
913 dma-names = "rx", "tx" <<
914 status = "disabled"; <<
915 }; <<
916 <<
917 spi@3270000 { <<
918 compatible = "nvidia,t <<
919 reg = <0x0 0x3270000 0 <<
920 interrupts = <GIC_SPI <<
921 #address-cells = <1>; <<
922 #size-cells = <0>; <<
923 clocks = <&bpmp TEGRA1 <<
924 <&bpmp TEGRA1 <<
925 clock-names = "qspi", <<
926 resets = <&bpmp TEGRA1 <<
927 status = "disabled"; 365 status = "disabled";
928 }; 366 };
929 367
930 pwm1: pwm@3280000 { 368 pwm1: pwm@3280000 {
931 compatible = "nvidia,t 369 compatible = "nvidia,tegra194-pwm",
932 "nvidia,t 370 "nvidia,tegra186-pwm";
933 reg = <0x0 0x3280000 0 !! 371 reg = <0x3280000 0x10000>;
934 clocks = <&bpmp TEGRA1 372 clocks = <&bpmp TEGRA194_CLK_PWM1>;
>> 373 clock-names = "pwm";
935 resets = <&bpmp TEGRA1 374 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm"; 375 reset-names = "pwm";
937 status = "disabled"; 376 status = "disabled";
938 #pwm-cells = <2>; 377 #pwm-cells = <2>;
939 }; 378 };
940 379
941 pwm2: pwm@3290000 { 380 pwm2: pwm@3290000 {
942 compatible = "nvidia,t 381 compatible = "nvidia,tegra194-pwm",
943 "nvidia,t 382 "nvidia,tegra186-pwm";
944 reg = <0x0 0x3290000 0 !! 383 reg = <0x3290000 0x10000>;
945 clocks = <&bpmp TEGRA1 384 clocks = <&bpmp TEGRA194_CLK_PWM2>;
>> 385 clock-names = "pwm";
946 resets = <&bpmp TEGRA1 386 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm"; 387 reset-names = "pwm";
948 status = "disabled"; 388 status = "disabled";
949 #pwm-cells = <2>; 389 #pwm-cells = <2>;
950 }; 390 };
951 391
952 pwm3: pwm@32a0000 { 392 pwm3: pwm@32a0000 {
953 compatible = "nvidia,t 393 compatible = "nvidia,tegra194-pwm",
954 "nvidia,t 394 "nvidia,tegra186-pwm";
955 reg = <0x0 0x32a0000 0 !! 395 reg = <0x32a0000 0x10000>;
956 clocks = <&bpmp TEGRA1 396 clocks = <&bpmp TEGRA194_CLK_PWM3>;
>> 397 clock-names = "pwm";
957 resets = <&bpmp TEGRA1 398 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm"; 399 reset-names = "pwm";
959 status = "disabled"; 400 status = "disabled";
960 #pwm-cells = <2>; 401 #pwm-cells = <2>;
961 }; 402 };
962 403
963 pwm5: pwm@32c0000 { 404 pwm5: pwm@32c0000 {
964 compatible = "nvidia,t 405 compatible = "nvidia,tegra194-pwm",
965 "nvidia,t 406 "nvidia,tegra186-pwm";
966 reg = <0x0 0x32c0000 0 !! 407 reg = <0x32c0000 0x10000>;
967 clocks = <&bpmp TEGRA1 408 clocks = <&bpmp TEGRA194_CLK_PWM5>;
>> 409 clock-names = "pwm";
968 resets = <&bpmp TEGRA1 410 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm"; 411 reset-names = "pwm";
970 status = "disabled"; 412 status = "disabled";
971 #pwm-cells = <2>; 413 #pwm-cells = <2>;
972 }; 414 };
973 415
974 pwm6: pwm@32d0000 { 416 pwm6: pwm@32d0000 {
975 compatible = "nvidia,t 417 compatible = "nvidia,tegra194-pwm",
976 "nvidia,t 418 "nvidia,tegra186-pwm";
977 reg = <0x0 0x32d0000 0 !! 419 reg = <0x32d0000 0x10000>;
978 clocks = <&bpmp TEGRA1 420 clocks = <&bpmp TEGRA194_CLK_PWM6>;
>> 421 clock-names = "pwm";
979 resets = <&bpmp TEGRA1 422 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm"; 423 reset-names = "pwm";
981 status = "disabled"; 424 status = "disabled";
982 #pwm-cells = <2>; 425 #pwm-cells = <2>;
983 }; 426 };
984 427
985 pwm7: pwm@32e0000 { 428 pwm7: pwm@32e0000 {
986 compatible = "nvidia,t 429 compatible = "nvidia,tegra194-pwm",
987 "nvidia,t 430 "nvidia,tegra186-pwm";
988 reg = <0x0 0x32e0000 0 !! 431 reg = <0x32e0000 0x10000>;
989 clocks = <&bpmp TEGRA1 432 clocks = <&bpmp TEGRA194_CLK_PWM7>;
>> 433 clock-names = "pwm";
990 resets = <&bpmp TEGRA1 434 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm"; 435 reset-names = "pwm";
992 status = "disabled"; 436 status = "disabled";
993 #pwm-cells = <2>; 437 #pwm-cells = <2>;
994 }; 438 };
995 439
996 pwm8: pwm@32f0000 { 440 pwm8: pwm@32f0000 {
997 compatible = "nvidia,t 441 compatible = "nvidia,tegra194-pwm",
998 "nvidia,t 442 "nvidia,tegra186-pwm";
999 reg = <0x0 0x32f0000 0 !! 443 reg = <0x32f0000 0x10000>;
1000 clocks = <&bpmp TEGRA 444 clocks = <&bpmp TEGRA194_CLK_PWM8>;
>> 445 clock-names = "pwm";
1001 resets = <&bpmp TEGRA 446 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm"; 447 reset-names = "pwm";
1003 status = "disabled"; 448 status = "disabled";
1004 #pwm-cells = <2>; 449 #pwm-cells = <2>;
1005 }; 450 };
1006 451
1007 spi@3300000 { !! 452 sdmmc1: sdhci@3400000 {
1008 compatible = "nvidia, !! 453 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1009 reg = <0x0 0x3300000 !! 454 reg = <0x03400000 0x10000>;
1010 interrupts = <GIC_SPI <<
1011 #address-cells = <1>; <<
1012 #size-cells = <0>; <<
1013 clocks = <&bpmp TEGRA <<
1014 <&bpmp TEGRA <<
1015 clock-names = "qspi", <<
1016 resets = <&bpmp TEGRA <<
1017 status = "disabled"; <<
1018 }; <<
1019 <<
1020 sdmmc1: mmc@3400000 { <<
1021 compatible = "nvidia, <<
1022 reg = <0x0 0x03400000 <<
1023 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&bpmp TEGRA !! 456 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
1025 <&bpmp TEGRA !! 457 clock-names = "sdhci";
1026 clock-names = "sdhci" <<
1027 assigned-clocks = <&b <<
1028 <&b <<
1029 assigned-clock-parent <<
1030 <&b <<
1031 <&b <<
1032 resets = <&bpmp TEGRA 458 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci" 459 reset-names = "sdhci";
1034 interconnects = <&mc <<
1035 <&mc <<
1036 interconnect-names = <<
1037 iommus = <&smmu TEGRA <<
1038 pinctrl-names = "sdmm <<
1039 pinctrl-0 = <&sdmmc1_ <<
1040 pinctrl-1 = <&sdmmc1_ <<
1041 nvidia,pad-autocal-pu 460 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042 461 <0x07>;
1043 nvidia,pad-autocal-pu 462 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044 463 <0x07>;
1045 nvidia,pad-autocal-pu 464 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pu 465 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047 466 <0x07>;
1048 nvidia,pad-autocal-pu 467 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pu 468 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = 469 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = 470 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25; <<
1053 sd-uhs-sdr50; <<
1054 sd-uhs-ddr50; <<
1055 sd-uhs-sdr104; <<
1056 status = "disabled"; 471 status = "disabled";
1057 }; 472 };
1058 473
1059 sdmmc3: mmc@3440000 { !! 474 sdmmc3: sdhci@3440000 {
1060 compatible = "nvidia, !! 475 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1061 reg = <0x0 0x03440000 !! 476 reg = <0x03440000 0x10000>;
1062 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&bpmp TEGRA !! 478 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
1064 <&bpmp TEGRA !! 479 clock-names = "sdhci";
1065 clock-names = "sdhci" <<
1066 assigned-clocks = <&b <<
1067 <&b <<
1068 assigned-clock-parent <<
1069 <&b <<
1070 <&b <<
1071 resets = <&bpmp TEGRA 480 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci" 481 reset-names = "sdhci";
1073 interconnects = <&mc <<
1074 <&mc <<
1075 interconnect-names = <<
1076 iommus = <&smmu TEGRA <<
1077 pinctrl-names = "sdmm <<
1078 pinctrl-0 = <&sdmmc3_ <<
1079 pinctrl-1 = <&sdmmc3_ <<
1080 nvidia,pad-autocal-pu 482 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pu 483 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pu 484 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pu 485 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084 486 <0x07>;
1085 nvidia,pad-autocal-pu 487 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pu 488 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087 489 <0x07>;
1088 nvidia,pad-autocal-pu 490 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pu 491 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = 492 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = 493 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25; <<
1093 sd-uhs-sdr50; <<
1094 sd-uhs-ddr50; <<
1095 sd-uhs-sdr104; <<
1096 status = "disabled"; 494 status = "disabled";
1097 }; 495 };
1098 496
1099 sdmmc4: mmc@3460000 { !! 497 sdmmc4: sdhci@3460000 {
1100 compatible = "nvidia, !! 498 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
1101 reg = <0x0 0x03460000 !! 499 reg = <0x03460000 0x10000>;
1102 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&bpmp TEGRA !! 501 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
1104 <&bpmp TEGRA !! 502 clock-names = "sdhci";
1105 clock-names = "sdhci" <<
1106 assigned-clocks = <&b 503 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&b 504 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parent 505 assigned-clock-parents =
1109 <&b 506 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA 507 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci" 508 reset-names = "sdhci";
1112 interconnects = <&mc <<
1113 <&mc <<
1114 interconnect-names = <<
1115 iommus = <&smmu TEGRA <<
1116 nvidia,pad-autocal-pu 509 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pu 510 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pu 511 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pu 512 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120 513 <0x0a>;
1121 nvidia,pad-autocal-pu 514 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pu 515 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123 516 <0x0a>;
1124 nvidia,default-tap = 517 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = 518 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40 519 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed; <<
1128 mmc-ddr-1_8v; <<
1129 mmc-hs200-1_8v; <<
1130 mmc-hs400-1_8v; <<
1131 mmc-hs400-enhanced-st <<
1132 supports-cqe; 520 supports-cqe;
1133 status = "disabled"; 521 status = "disabled";
1134 }; 522 };
1135 523
1136 hda@3510000 { 524 hda@3510000 {
1137 compatible = "nvidia, !! 525 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1138 reg = <0x0 0x3510000 !! 526 reg = <0x3510000 0x10000>;
1139 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&bpmp TEGRA 528 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA !! 529 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
1142 <&bpmp TEGRA !! 530 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
1143 clock-names = "hda", !! 531 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
1144 resets = <&bpmp TEGRA 532 resets = <&bpmp TEGRA194_RESET_HDA>,
>> 533 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
1145 <&bpmp TEGRA 534 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", !! 535 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
1147 power-domains = <&bpm 536 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148 interconnects = <&mc <<
1149 <&mc <<
1150 interconnect-names = <<
1151 iommus = <&smmu TEGRA <<
1152 status = "disabled"; <<
1153 }; <<
1154 <<
1155 xusb_padctl: padctl@3520000 { <<
1156 compatible = "nvidia, <<
1157 reg = <0x0 0x03520000 <<
1158 <0x0 0x03540000 <<
1159 reg-names = "padctl", <<
1160 interrupts = <GIC_SPI <<
1161 <<
1162 resets = <&bpmp TEGRA <<
1163 reset-names = "padctl <<
1164 <<
1165 status = "disabled"; <<
1166 <<
1167 pads { <<
1168 usb2 { <<
1169 clock <<
1170 clock <<
1171 <<
1172 lanes <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 <<
1178 <<
1179 <<
1180 <<
1181 <<
1182 <<
1183 <<
1184 <<
1185 <<
1186 <<
1187 <<
1188 <<
1189 <<
1190 <<
1191 <<
1192 <<
1193 <<
1194 <<
1195 <<
1196 }; <<
1197 }; <<
1198 <<
1199 usb3 { <<
1200 lanes <<
1201 <<
1202 <<
1203 <<
1204 <<
1205 <<
1206 <<
1207 <<
1208 <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 <<
1214 <<
1215 <<
1216 <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 <<
1222 <<
1223 <<
1224 }; <<
1225 }; <<
1226 }; <<
1227 <<
1228 ports { <<
1229 usb2-0 { <<
1230 statu <<
1231 }; <<
1232 <<
1233 usb2-1 { <<
1234 statu <<
1235 }; <<
1236 <<
1237 usb2-2 { <<
1238 statu <<
1239 }; <<
1240 <<
1241 usb2-3 { <<
1242 statu <<
1243 }; <<
1244 <<
1245 usb3-0 { <<
1246 statu <<
1247 }; <<
1248 <<
1249 usb3-1 { <<
1250 statu <<
1251 }; <<
1252 <<
1253 usb3-2 { <<
1254 statu <<
1255 }; <<
1256 <<
1257 usb3-3 { <<
1258 statu <<
1259 }; <<
1260 }; <<
1261 }; <<
1262 <<
1263 usb@3550000 { <<
1264 compatible = "nvidia, <<
1265 reg = <0x0 0x03550000 <<
1266 <0x0 0x03558000 <<
1267 reg-names = "base", " <<
1268 interrupts = <GIC_SPI <<
1269 clocks = <&bpmp TEGRA <<
1270 <&bpmp TEGRA <<
1271 <&bpmp TEGRA <<
1272 <&bpmp TEGRA <<
1273 clock-names = "dev", <<
1274 interconnects = <&mc <<
1275 <&mc <<
1276 interconnect-names = <<
1277 iommus = <&smmu TEGRA <<
1278 power-domains = <&bpm <<
1279 <&bpm <<
1280 power-domain-names = <<
1281 nvidia,xusb-padctl = <<
1282 dma-coherent; <<
1283 status = "disabled"; <<
1284 }; <<
1285 <<
1286 usb@3610000 { <<
1287 compatible = "nvidia, <<
1288 reg = <0x0 0x03610000 <<
1289 <0x0 0x03600000 <<
1290 reg-names = "hcd", "f <<
1291 <<
1292 interrupts = <GIC_SPI <<
1293 <GIC_SPI <<
1294 <<
1295 clocks = <&bpmp TEGRA <<
1296 <&bpmp TEGRA <<
1297 <&bpmp TEGRA <<
1298 <&bpmp TEGRA <<
1299 <&bpmp TEGRA <<
1300 <&bpmp TEGRA <<
1301 <&bpmp TEGRA <<
1302 <&bpmp TEGRA <<
1303 <&bpmp TEGRA <<
1304 clock-names = "xusb_h <<
1305 "xusb_s <<
1306 "xusb_f <<
1307 "pll_e" <<
1308 interconnects = <&mc <<
1309 <&mc <<
1310 interconnect-names = <<
1311 iommus = <&smmu TEGRA <<
1312 <<
1313 power-domains = <&bpm <<
1314 <&bpm <<
1315 power-domain-names = <<
1316 <<
1317 nvidia,xusb-padctl = <<
1318 status = "disabled"; 537 status = "disabled";
1319 }; 538 };
1320 539
1321 fuse@3820000 { 540 fuse@3820000 {
1322 compatible = "nvidia, 541 compatible = "nvidia,tegra194-efuse";
1323 reg = <0x0 0x03820000 !! 542 reg = <0x03820000 0x10000>;
1324 clocks = <&bpmp TEGRA 543 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse"; 544 clock-names = "fuse";
1326 }; 545 };
1327 546
1328 gic: interrupt-controller@388 547 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic 548 compatible = "arm,gic-400";
1330 #interrupt-cells = <3 549 #interrupt-cells = <3>;
1331 interrupt-controller; 550 interrupt-controller;
1332 reg = <0x0 0x03881000 !! 551 reg = <0x03881000 0x1000>,
1333 <0x0 0x03882000 !! 552 <0x03882000 0x2000>,
1334 <0x0 0x03884000 !! 553 <0x03884000 0x2000>,
1335 <0x0 0x03886000 !! 554 <0x03886000 0x2000>;
1336 interrupts = <GIC_PPI 555 interrupts = <GIC_PPI 9
1337 (GIC_CPU_MASK 556 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338 interrupt-parent = <& 557 interrupt-parent = <&gic>;
1339 }; 558 };
1340 559
1341 cec@3960000 { 560 cec@3960000 {
1342 compatible = "nvidia, 561 compatible = "nvidia,tegra194-cec";
1343 reg = <0x0 0x03960000 !! 562 reg = <0x03960000 0x10000>;
1344 interrupts = <GIC_SPI 563 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA 564 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec"; 565 clock-names = "cec";
1347 status = "disabled"; 566 status = "disabled";
1348 }; 567 };
1349 568
1350 hte_lic: hardware-timestamp@3 <<
1351 compatible = "nvidia, <<
1352 reg = <0x0 0x3aa0000 <<
1353 interrupts = <GIC_SPI <<
1354 nvidia,int-threshold <<
1355 nvidia,slices = <11>; <<
1356 #timestamp-cells = <1 <<
1357 status = "okay"; <<
1358 }; <<
1359 <<
1360 hsp_top0: hsp@3c00000 { 569 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia, !! 570 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1362 reg = <0x0 0x03c00000 !! 571 reg = <0x03c00000 0xa0000>;
1363 interrupts = <GIC_SPI 572 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 573 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 574 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 575 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 576 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 577 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 578 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 579 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 580 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "do 581 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373 "sh 582 "shared3", "shared4", "shared5", "shared6",
1374 "sh 583 "shared7";
1375 #mbox-cells = <2>; 584 #mbox-cells = <2>;
1376 }; 585 };
1377 586
1378 p2u_hsio_0: phy@3e10000 { 587 p2u_hsio_0: phy@3e10000 {
1379 compatible = "nvidia, 588 compatible = "nvidia,tegra194-p2u";
1380 reg = <0x0 0x03e10000 !! 589 reg = <0x03e10000 0x10000>;
1381 reg-names = "ctl"; 590 reg-names = "ctl";
1382 591
1383 #phy-cells = <0>; 592 #phy-cells = <0>;
1384 }; 593 };
1385 594
1386 p2u_hsio_1: phy@3e20000 { 595 p2u_hsio_1: phy@3e20000 {
1387 compatible = "nvidia, 596 compatible = "nvidia,tegra194-p2u";
1388 reg = <0x0 0x03e20000 !! 597 reg = <0x03e20000 0x10000>;
1389 reg-names = "ctl"; 598 reg-names = "ctl";
1390 599
1391 #phy-cells = <0>; 600 #phy-cells = <0>;
1392 }; 601 };
1393 602
1394 p2u_hsio_2: phy@3e30000 { 603 p2u_hsio_2: phy@3e30000 {
1395 compatible = "nvidia, 604 compatible = "nvidia,tegra194-p2u";
1396 reg = <0x0 0x03e30000 !! 605 reg = <0x03e30000 0x10000>;
1397 reg-names = "ctl"; 606 reg-names = "ctl";
1398 607
1399 #phy-cells = <0>; 608 #phy-cells = <0>;
1400 }; 609 };
1401 610
1402 p2u_hsio_3: phy@3e40000 { 611 p2u_hsio_3: phy@3e40000 {
1403 compatible = "nvidia, 612 compatible = "nvidia,tegra194-p2u";
1404 reg = <0x0 0x03e40000 !! 613 reg = <0x03e40000 0x10000>;
1405 reg-names = "ctl"; 614 reg-names = "ctl";
1406 615
1407 #phy-cells = <0>; 616 #phy-cells = <0>;
1408 }; 617 };
1409 618
1410 p2u_hsio_4: phy@3e50000 { 619 p2u_hsio_4: phy@3e50000 {
1411 compatible = "nvidia, 620 compatible = "nvidia,tegra194-p2u";
1412 reg = <0x0 0x03e50000 !! 621 reg = <0x03e50000 0x10000>;
1413 reg-names = "ctl"; 622 reg-names = "ctl";
1414 623
1415 #phy-cells = <0>; 624 #phy-cells = <0>;
1416 }; 625 };
1417 626
1418 p2u_hsio_5: phy@3e60000 { 627 p2u_hsio_5: phy@3e60000 {
1419 compatible = "nvidia, 628 compatible = "nvidia,tegra194-p2u";
1420 reg = <0x0 0x03e60000 !! 629 reg = <0x03e60000 0x10000>;
1421 reg-names = "ctl"; 630 reg-names = "ctl";
1422 631
1423 #phy-cells = <0>; 632 #phy-cells = <0>;
1424 }; 633 };
1425 634
1426 p2u_hsio_6: phy@3e70000 { 635 p2u_hsio_6: phy@3e70000 {
1427 compatible = "nvidia, 636 compatible = "nvidia,tegra194-p2u";
1428 reg = <0x0 0x03e70000 !! 637 reg = <0x03e70000 0x10000>;
1429 reg-names = "ctl"; 638 reg-names = "ctl";
1430 639
1431 #phy-cells = <0>; 640 #phy-cells = <0>;
1432 }; 641 };
1433 642
1434 p2u_hsio_7: phy@3e80000 { 643 p2u_hsio_7: phy@3e80000 {
1435 compatible = "nvidia, 644 compatible = "nvidia,tegra194-p2u";
1436 reg = <0x0 0x03e80000 !! 645 reg = <0x03e80000 0x10000>;
1437 reg-names = "ctl"; 646 reg-names = "ctl";
1438 647
1439 #phy-cells = <0>; 648 #phy-cells = <0>;
1440 }; 649 };
1441 650
1442 p2u_hsio_8: phy@3e90000 { 651 p2u_hsio_8: phy@3e90000 {
1443 compatible = "nvidia, 652 compatible = "nvidia,tegra194-p2u";
1444 reg = <0x0 0x03e90000 !! 653 reg = <0x03e90000 0x10000>;
1445 reg-names = "ctl"; 654 reg-names = "ctl";
1446 655
1447 #phy-cells = <0>; 656 #phy-cells = <0>;
1448 }; 657 };
1449 658
1450 p2u_hsio_9: phy@3ea0000 { 659 p2u_hsio_9: phy@3ea0000 {
1451 compatible = "nvidia, 660 compatible = "nvidia,tegra194-p2u";
1452 reg = <0x0 0x03ea0000 !! 661 reg = <0x03ea0000 0x10000>;
1453 reg-names = "ctl"; 662 reg-names = "ctl";
1454 663
1455 #phy-cells = <0>; 664 #phy-cells = <0>;
1456 }; 665 };
1457 666
1458 p2u_nvhs_0: phy@3eb0000 { 667 p2u_nvhs_0: phy@3eb0000 {
1459 compatible = "nvidia, 668 compatible = "nvidia,tegra194-p2u";
1460 reg = <0x0 0x03eb0000 !! 669 reg = <0x03eb0000 0x10000>;
1461 reg-names = "ctl"; 670 reg-names = "ctl";
1462 671
1463 #phy-cells = <0>; 672 #phy-cells = <0>;
1464 }; 673 };
1465 674
1466 p2u_nvhs_1: phy@3ec0000 { 675 p2u_nvhs_1: phy@3ec0000 {
1467 compatible = "nvidia, 676 compatible = "nvidia,tegra194-p2u";
1468 reg = <0x0 0x03ec0000 !! 677 reg = <0x03ec0000 0x10000>;
1469 reg-names = "ctl"; 678 reg-names = "ctl";
1470 679
1471 #phy-cells = <0>; 680 #phy-cells = <0>;
1472 }; 681 };
1473 682
1474 p2u_nvhs_2: phy@3ed0000 { 683 p2u_nvhs_2: phy@3ed0000 {
1475 compatible = "nvidia, 684 compatible = "nvidia,tegra194-p2u";
1476 reg = <0x0 0x03ed0000 !! 685 reg = <0x03ed0000 0x10000>;
1477 reg-names = "ctl"; 686 reg-names = "ctl";
1478 687
1479 #phy-cells = <0>; 688 #phy-cells = <0>;
1480 }; 689 };
1481 690
1482 p2u_nvhs_3: phy@3ee0000 { 691 p2u_nvhs_3: phy@3ee0000 {
1483 compatible = "nvidia, 692 compatible = "nvidia,tegra194-p2u";
1484 reg = <0x0 0x03ee0000 !! 693 reg = <0x03ee0000 0x10000>;
1485 reg-names = "ctl"; 694 reg-names = "ctl";
1486 695
1487 #phy-cells = <0>; 696 #phy-cells = <0>;
1488 }; 697 };
1489 698
1490 p2u_nvhs_4: phy@3ef0000 { 699 p2u_nvhs_4: phy@3ef0000 {
1491 compatible = "nvidia, 700 compatible = "nvidia,tegra194-p2u";
1492 reg = <0x0 0x03ef0000 !! 701 reg = <0x03ef0000 0x10000>;
1493 reg-names = "ctl"; 702 reg-names = "ctl";
1494 703
1495 #phy-cells = <0>; 704 #phy-cells = <0>;
1496 }; 705 };
1497 706
1498 p2u_nvhs_5: phy@3f00000 { 707 p2u_nvhs_5: phy@3f00000 {
1499 compatible = "nvidia, 708 compatible = "nvidia,tegra194-p2u";
1500 reg = <0x0 0x03f00000 !! 709 reg = <0x03f00000 0x10000>;
1501 reg-names = "ctl"; 710 reg-names = "ctl";
1502 711
1503 #phy-cells = <0>; 712 #phy-cells = <0>;
1504 }; 713 };
1505 714
1506 p2u_nvhs_6: phy@3f10000 { 715 p2u_nvhs_6: phy@3f10000 {
1507 compatible = "nvidia, 716 compatible = "nvidia,tegra194-p2u";
1508 reg = <0x0 0x03f10000 !! 717 reg = <0x03f10000 0x10000>;
1509 reg-names = "ctl"; 718 reg-names = "ctl";
1510 719
1511 #phy-cells = <0>; 720 #phy-cells = <0>;
1512 }; 721 };
1513 722
1514 p2u_nvhs_7: phy@3f20000 { 723 p2u_nvhs_7: phy@3f20000 {
1515 compatible = "nvidia, 724 compatible = "nvidia,tegra194-p2u";
1516 reg = <0x0 0x03f20000 !! 725 reg = <0x03f20000 0x10000>;
1517 reg-names = "ctl"; 726 reg-names = "ctl";
1518 727
1519 #phy-cells = <0>; 728 #phy-cells = <0>;
1520 }; 729 };
1521 730
1522 p2u_hsio_10: phy@3f30000 { 731 p2u_hsio_10: phy@3f30000 {
1523 compatible = "nvidia, 732 compatible = "nvidia,tegra194-p2u";
1524 reg = <0x0 0x03f30000 !! 733 reg = <0x03f30000 0x10000>;
1525 reg-names = "ctl"; 734 reg-names = "ctl";
1526 735
1527 #phy-cells = <0>; 736 #phy-cells = <0>;
1528 }; 737 };
1529 738
1530 p2u_hsio_11: phy@3f40000 { 739 p2u_hsio_11: phy@3f40000 {
1531 compatible = "nvidia, 740 compatible = "nvidia,tegra194-p2u";
1532 reg = <0x0 0x03f40000 !! 741 reg = <0x03f40000 0x10000>;
1533 reg-names = "ctl"; 742 reg-names = "ctl";
1534 743
1535 #phy-cells = <0>; 744 #phy-cells = <0>;
1536 }; 745 };
1537 746
1538 sce-noc@b600000 { <<
1539 compatible = "nvidia, <<
1540 reg = <0x0 0xb600000 <<
1541 interrupts = <GIC_SPI <<
1542 <GIC_SPI <<
1543 nvidia,axi2apb = <&ax <<
1544 nvidia,apbmisc = <&ap <<
1545 status = "okay"; <<
1546 }; <<
1547 <<
1548 rce-noc@be00000 { <<
1549 compatible = "nvidia, <<
1550 reg = <0x0 0xbe00000 <<
1551 interrupts = <GIC_SPI <<
1552 <GIC_SPI <<
1553 nvidia,axi2apb = <&ax <<
1554 nvidia,apbmisc = <&ap <<
1555 status = "okay"; <<
1556 }; <<
1557 <<
1558 hsp_aon: hsp@c150000 { 747 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia, !! 748 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1560 reg = <0x0 0x0c150000 !! 749 reg = <0x0c150000 0xa0000>;
1561 interrupts = <GIC_SPI 750 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 751 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 752 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 753 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565 /* 754 /*
1566 * Shared interrupt 0 755 * Shared interrupt 0 is routed only to AON/SPE, so
1567 * we only have 4 sha 756 * we only have 4 shared interrupts for the CCPLEX.
1568 */ 757 */
1569 interrupt-names = "sh 758 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>; 759 #mbox-cells = <2>;
1571 }; 760 };
1572 761
1573 hte_aon: hardware-timestamp@c <<
1574 compatible = "nvidia, <<
1575 reg = <0x0 0xc1e0000 <<
1576 interrupts = <GIC_SPI <<
1577 nvidia,int-threshold <<
1578 nvidia,slices = <3>; <<
1579 #timestamp-cells = <1 <<
1580 status = "okay"; <<
1581 }; <<
1582 <<
1583 gen2_i2c: i2c@c240000 { 762 gen2_i2c: i2c@c240000 {
1584 compatible = "nvidia, 763 compatible = "nvidia,tegra194-i2c";
1585 reg = <0x0 0x0c240000 !! 764 reg = <0x0c240000 0x10000>;
1586 interrupts = <GIC_SPI 765 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>; 766 #address-cells = <1>;
1588 #size-cells = <0>; 767 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA 768 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-cl 769 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA 770 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c"; 771 reset-names = "i2c";
1593 dmas = <&gpcdma 22>, <<
1594 dma-names = "rx", "tx <<
1595 status = "disabled"; 772 status = "disabled";
1596 }; 773 };
1597 774
1598 gen8_i2c: i2c@c250000 { 775 gen8_i2c: i2c@c250000 {
1599 compatible = "nvidia, 776 compatible = "nvidia,tegra194-i2c";
1600 reg = <0x0 0x0c250000 !! 777 reg = <0x0c250000 0x10000>;
1601 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>; 779 #address-cells = <1>;
1603 #size-cells = <0>; 780 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA 781 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-cl 782 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA 783 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c"; 784 reset-names = "i2c";
1608 dmas = <&gpcdma 0>, < <<
1609 dma-names = "rx", "tx <<
1610 status = "disabled"; 785 status = "disabled";
1611 }; 786 };
1612 787
1613 uartc: serial@c280000 { 788 uartc: serial@c280000 {
1614 compatible = "nvidia, 789 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615 reg = <0x0 0x0c280000 !! 790 reg = <0x0c280000 0x40>;
1616 reg-shift = <2>; 791 reg-shift = <2>;
1617 interrupts = <GIC_SPI 792 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&bpmp TEGRA 793 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial 794 clock-names = "serial";
1620 resets = <&bpmp TEGRA 795 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial 796 reset-names = "serial";
1622 status = "disabled"; 797 status = "disabled";
1623 }; 798 };
1624 799
1625 uartg: serial@c290000 { 800 uartg: serial@c290000 {
1626 compatible = "nvidia, 801 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627 reg = <0x0 0x0c290000 !! 802 reg = <0x0c290000 0x40>;
1628 reg-shift = <2>; 803 reg-shift = <2>;
1629 interrupts = <GIC_SPI 804 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&bpmp TEGRA 805 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial 806 clock-names = "serial";
1632 resets = <&bpmp TEGRA 807 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial 808 reset-names = "serial";
1634 status = "disabled"; 809 status = "disabled";
1635 }; 810 };
1636 811
1637 rtc: rtc@c2a0000 { 812 rtc: rtc@c2a0000 {
1638 compatible = "nvidia, 813 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639 reg = <0x0 0x0c2a0000 !! 814 reg = <0x0c2a0000 0x10000>;
1640 interrupt-parent = <& 815 interrupt-parent = <&pmc>;
1641 interrupts = <73 IRQ_ 816 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&bpmp TEGRA 817 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc"; 818 clock-names = "rtc";
1644 status = "disabled"; 819 status = "disabled";
1645 }; 820 };
1646 821
1647 gpio_aon: gpio@c2f0000 { 822 gpio_aon: gpio@c2f0000 {
1648 compatible = "nvidia, 823 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security 824 reg-names = "security", "gpio";
1650 reg = <0x0 0xc2f0000 !! 825 reg = <0xc2f0000 0x1000>,
1651 <0x0 0xc2f1000 !! 826 <0xc2f1000 0x1000>;
1652 interrupts = <GIC_SPI 827 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 828 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 829 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 830 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1656 gpio-controller; 831 gpio-controller;
1657 #gpio-cells = <2>; 832 #gpio-cells = <2>;
1658 interrupt-controller; 833 interrupt-controller;
1659 #interrupt-cells = <2 834 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmu <<
1661 }; <<
1662 <<
1663 pinmux_aon: pinmux@c300000 { <<
1664 compatible = "nvidia, <<
1665 reg = <0x0 0xc300000 <<
1666 <<
1667 status = "okay"; <<
1668 }; 835 };
1669 836
1670 pwm4: pwm@c340000 { 837 pwm4: pwm@c340000 {
1671 compatible = "nvidia, 838 compatible = "nvidia,tegra194-pwm",
1672 "nvidia, 839 "nvidia,tegra186-pwm";
1673 reg = <0x0 0xc340000 !! 840 reg = <0xc340000 0x10000>;
1674 clocks = <&bpmp TEGRA 841 clocks = <&bpmp TEGRA194_CLK_PWM4>;
>> 842 clock-names = "pwm";
1675 resets = <&bpmp TEGRA 843 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm"; 844 reset-names = "pwm";
1677 status = "disabled"; 845 status = "disabled";
1678 #pwm-cells = <2>; 846 #pwm-cells = <2>;
1679 }; 847 };
1680 848
1681 pmc: pmc@c360000 { 849 pmc: pmc@c360000 {
1682 compatible = "nvidia, 850 compatible = "nvidia,tegra194-pmc";
1683 reg = <0x0 0x0c360000 !! 851 reg = <0x0c360000 0x10000>,
1684 <0x0 0x0c370000 !! 852 <0x0c370000 0x10000>,
1685 <0x0 0x0c380000 !! 853 <0x0c380000 0x10000>,
1686 <0x0 0x0c390000 !! 854 <0x0c390000 0x10000>,
1687 <0x0 0x0c3a0000 !! 855 <0x0c3a0000 0x10000>;
1688 reg-names = "pmc", "w 856 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689 857
1690 #interrupt-cells = <2 858 #interrupt-cells = <2>;
1691 interrupt-controller; 859 interrupt-controller;
1692 <<
1693 sdmmc1_1v8: sdmmc1-1v <<
1694 pins = "sdmmc <<
1695 power-source <<
1696 }; <<
1697 <<
1698 sdmmc1_3v3: sdmmc1-3v <<
1699 pins = "sdmmc <<
1700 power-source <<
1701 }; <<
1702 <<
1703 sdmmc3_1v8: sdmmc3-1v <<
1704 pins = "sdmmc <<
1705 power-source <<
1706 }; <<
1707 <<
1708 sdmmc3_3v3: sdmmc3-3v <<
1709 pins = "sdmmc <<
1710 power-source <<
1711 }; <<
1712 }; <<
1713 <<
1714 aon-noc@c600000 { <<
1715 compatible = "nvidia, <<
1716 reg = <0x0 0xc600000 <<
1717 interrupts = <GIC_SPI <<
1718 <GIC_SPI <<
1719 nvidia,apbmisc = <&ap <<
1720 status = "okay"; <<
1721 }; <<
1722 <<
1723 bpmp-noc@d600000 { <<
1724 compatible = "nvidia, <<
1725 reg = <0x0 0xd600000 <<
1726 interrupts = <GIC_SPI <<
1727 <GIC_SPI <<
1728 nvidia,axi2apb = <&ax <<
1729 nvidia,apbmisc = <&ap <<
1730 status = "okay"; <<
1731 }; <<
1732 <<
1733 iommu@10000000 { <<
1734 compatible = "nvidia, <<
1735 reg = <0x0 0x10000000 <<
1736 interrupts = <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 <GIC_SPI <<
1747 <GIC_SPI <<
1748 <GIC_SPI <<
1749 <GIC_SPI <<
1750 <GIC_SPI <<
1751 <GIC_SPI <<
1752 <GIC_SPI <<
1753 <GIC_SPI <<
1754 <GIC_SPI <<
1755 <GIC_SPI <<
1756 <GIC_SPI <<
1757 <GIC_SPI <<
1758 <GIC_SPI <<
1759 <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 <GIC_SPI <<
1770 <GIC_SPI <<
1771 <GIC_SPI <<
1772 <GIC_SPI <<
1773 <GIC_SPI <<
1774 <GIC_SPI <<
1775 <GIC_SPI <<
1776 <GIC_SPI <<
1777 <GIC_SPI <<
1778 <GIC_SPI <<
1779 <GIC_SPI <<
1780 <GIC_SPI <<
1781 <GIC_SPI <<
1782 <GIC_SPI <<
1783 <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 <GIC_SPI <<
1792 <GIC_SPI <<
1793 <GIC_SPI <<
1794 <GIC_SPI <<
1795 <GIC_SPI <<
1796 <GIC_SPI <<
1797 <GIC_SPI <<
1798 <GIC_SPI <<
1799 <GIC_SPI <<
1800 <GIC_SPI <<
1801 stream-match-mask = < <<
1802 #global-interrupts = <<
1803 #iommu-cells = <1>; <<
1804 <<
1805 nvidia,memory-control <<
1806 status = "disabled"; <<
1807 }; <<
1808 <<
1809 smmu: iommu@12000000 { <<
1810 compatible = "nvidia, <<
1811 reg = <0x0 0x12000000 <<
1812 <0x0 0x11000000 <<
1813 interrupts = <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 <GIC_SPI <<
1834 <GIC_SPI <<
1835 <GIC_SPI <<
1836 <GIC_SPI <<
1837 <GIC_SPI <<
1838 <GIC_SPI <<
1839 <GIC_SPI <<
1840 <GIC_SPI <<
1841 <GIC_SPI <<
1842 <GIC_SPI <<
1843 <GIC_SPI <<
1844 <GIC_SPI <<
1845 <GIC_SPI <<
1846 <GIC_SPI <<
1847 <GIC_SPI <<
1848 <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 <GIC_SPI <<
1857 <GIC_SPI <<
1858 <GIC_SPI <<
1859 <GIC_SPI <<
1860 <GIC_SPI <<
1861 <GIC_SPI <<
1862 <GIC_SPI <<
1863 <GIC_SPI <<
1864 <GIC_SPI <<
1865 <GIC_SPI <<
1866 <GIC_SPI <<
1867 <GIC_SPI <<
1868 <GIC_SPI <<
1869 <GIC_SPI <<
1870 <GIC_SPI <<
1871 <GIC_SPI <<
1872 <GIC_SPI <<
1873 <GIC_SPI <<
1874 <GIC_SPI <<
1875 <GIC_SPI <<
1876 <GIC_SPI <<
1877 <GIC_SPI <<
1878 <GIC_SPI <<
1879 stream-match-mask = < <<
1880 #global-interrupts = <<
1881 #iommu-cells = <1>; <<
1882 <<
1883 nvidia,memory-control <<
1884 status = "okay"; <<
1885 }; 860 };
1886 861
1887 host1x@13e00000 { 862 host1x@13e00000 {
1888 compatible = "nvidia, !! 863 compatible = "nvidia,tegra194-host1x", "simple-bus";
1889 reg = <0x0 0x13e00000 !! 864 reg = <0x13e00000 0x10000>,
1890 <0x0 0x13e10000 !! 865 <0x13e10000 0x10000>;
1891 reg-names = "hypervis 866 reg-names = "hypervisor", "vm";
1892 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 868 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894 interrupt-names = "sy <<
1895 clocks = <&bpmp TEGRA 869 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x 870 clock-names = "host1x";
1897 resets = <&bpmp TEGRA 871 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x 872 reset-names = "host1x";
1899 873
1900 #address-cells = <2>; !! 874 #address-cells = <1>;
1901 #size-cells = <2>; !! 875 #size-cells = <1>;
1902 ranges = <0x0 0x14800 <<
1903 <<
1904 interconnects = <&mc <<
1905 interconnect-names = <<
1906 iommus = <&smmu TEGRA <<
1907 dma-coherent; <<
1908 <<
1909 /* Context isolation <<
1910 iommu-map = <0 &smmu <<
1911 <1 &smmu <<
1912 <2 &smmu <<
1913 <3 &smmu <<
1914 <4 &smmu <<
1915 <5 &smmu <<
1916 <6 &smmu <<
1917 <7 &smmu <<
1918 <<
1919 nvdec@15140000 { <<
1920 compatible = <<
1921 reg = <0x0 0x <<
1922 clocks = <&bp <<
1923 clock-names = <<
1924 resets = <&bp <<
1925 reset-names = <<
1926 <<
1927 power-domains <<
1928 interconnects <<
1929 <<
1930 <<
1931 interconnect- <<
1932 iommus = <&sm <<
1933 dma-coherent; <<
1934 876
1935 nvidia,host1x !! 877 ranges = <0x15000000 0x15000000 0x01000000>;
1936 }; <<
1937 878
1938 display-hub@15200000 879 display-hub@15200000 {
1939 compatible = !! 880 compatible = "nvidia,tegra194-display", "simple-bus";
1940 reg = <0x0 0x !! 881 reg = <0x15200000 0x00040000>;
1941 resets = <&bp 882 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bp 883 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bp 884 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bp 885 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bp 886 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bp 887 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bp 888 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = 889 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949 890 "wgrp3", "wgrp4", "wgrp5";
1950 clocks = <&bp 891 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bp 892 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = 893 clock-names = "disp", "hub";
1953 status = "dis 894 status = "disabled";
1954 895
1955 power-domains 896 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956 897
1957 #address-cell !! 898 #address-cells = <1>;
1958 #size-cells = !! 899 #size-cells = <1>;
1959 ranges = <0x0 !! 900
>> 901 ranges = <0x15200000 0x15200000 0x40000>;
1960 902
1961 display@15200 903 display@15200000 {
1962 compa 904 compatible = "nvidia,tegra194-dc";
1963 reg = !! 905 reg = <0x15200000 0x10000>;
1964 inter 906 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965 clock 907 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock 908 clock-names = "dc";
1967 reset 909 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset 910 reset-names = "dc";
1969 911
1970 power 912 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971 inter <<
1972 <<
1973 inter <<
1974 913
1975 nvidi 914 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidi 915 nvidia,head = <0>;
1977 }; 916 };
1978 917
1979 display@15210 918 display@15210000 {
1980 compa 919 compatible = "nvidia,tegra194-dc";
1981 reg = !! 920 reg = <0x15210000 0x10000>;
1982 inter 921 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983 clock 922 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock 923 clock-names = "dc";
1985 reset 924 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset 925 reset-names = "dc";
1987 926
1988 power 927 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989 inter <<
1990 <<
1991 inter <<
1992 928
1993 nvidi 929 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidi 930 nvidia,head = <1>;
1995 }; 931 };
1996 932
1997 display@15220 933 display@15220000 {
1998 compa 934 compatible = "nvidia,tegra194-dc";
1999 reg = !! 935 reg = <0x15220000 0x10000>;
2000 inter 936 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001 clock 937 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock 938 clock-names = "dc";
2003 reset 939 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset 940 reset-names = "dc";
2005 941
2006 power 942 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007 inter <<
2008 <<
2009 inter <<
2010 943
2011 nvidi 944 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012 nvidi 945 nvidia,head = <2>;
2013 }; 946 };
2014 947
2015 display@15230 948 display@15230000 {
2016 compa 949 compatible = "nvidia,tegra194-dc";
2017 reg = !! 950 reg = <0x15230000 0x10000>;
2018 inter 951 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019 clock 952 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock 953 clock-names = "dc";
2021 reset 954 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset 955 reset-names = "dc";
2023 956
2024 power 957 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025 inter <<
2026 <<
2027 inter <<
2028 958
2029 nvidi 959 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030 nvidi 960 nvidia,head = <3>;
2031 }; 961 };
2032 }; 962 };
2033 963
2034 vic@15340000 { 964 vic@15340000 {
2035 compatible = 965 compatible = "nvidia,tegra194-vic";
2036 reg = <0x0 0x !! 966 reg = <0x15340000 0x00040000>;
2037 interrupts = 967 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038 clocks = <&bp 968 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = 969 clock-names = "vic";
2040 resets = <&bp 970 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = 971 reset-names = "vic";
2042 972
2043 power-domains 973 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044 interconnects <<
2045 <<
2046 interconnect- <<
2047 iommus = <&sm <<
2048 dma-coherent; <<
2049 }; <<
2050 <<
2051 nvjpg@15380000 { <<
2052 compatible = <<
2053 reg = <0x0 0x <<
2054 clocks = <&bp <<
2055 clock-names = <<
2056 resets = <&bp <<
2057 reset-names = <<
2058 <<
2059 power-domains <<
2060 interconnects <<
2061 <<
2062 interconnect- <<
2063 iommus = <&sm <<
2064 dma-coherent; <<
2065 }; <<
2066 <<
2067 nvdec@15480000 { <<
2068 compatible = <<
2069 reg = <0x0 0x <<
2070 clocks = <&bp <<
2071 clock-names = <<
2072 resets = <&bp <<
2073 reset-names = <<
2074 <<
2075 power-domains <<
2076 interconnects <<
2077 <<
2078 <<
2079 interconnect- <<
2080 iommus = <&sm <<
2081 dma-coherent; <<
2082 <<
2083 nvidia,host1x <<
2084 }; <<
2085 <<
2086 nvenc@154c0000 { <<
2087 compatible = <<
2088 reg = <0x0 0x <<
2089 clocks = <&bp <<
2090 clock-names = <<
2091 resets = <&bp <<
2092 reset-names = <<
2093 <<
2094 power-domains <<
2095 interconnects <<
2096 <<
2097 <<
2098 interconnect- <<
2099 iommus = <&sm <<
2100 dma-coherent; <<
2101 <<
2102 nvidia,host1x <<
2103 }; 974 };
2104 975
2105 dpaux0: dpaux@155c000 976 dpaux0: dpaux@155c0000 {
2106 compatible = 977 compatible = "nvidia,tegra194-dpaux";
2107 reg = <0x0 0x !! 978 reg = <0x155c0000 0x10000>;
2108 interrupts = 979 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109 clocks = <&bp 980 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bp 981 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = 982 clock-names = "dpaux", "parent";
2112 resets = <&bp 983 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = 984 reset-names = "dpaux";
2114 status = "dis 985 status = "disabled";
2115 986
2116 power-domains 987 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117 988
2118 state_dpaux0_ 989 state_dpaux0_aux: pinmux-aux {
2119 group 990 groups = "dpaux-io";
2120 funct 991 function = "aux";
2121 }; 992 };
2122 993
2123 state_dpaux0_ 994 state_dpaux0_i2c: pinmux-i2c {
2124 group 995 groups = "dpaux-io";
2125 funct 996 function = "i2c";
2126 }; 997 };
2127 998
2128 state_dpaux0_ 999 state_dpaux0_off: pinmux-off {
2129 group 1000 groups = "dpaux-io";
2130 funct 1001 function = "off";
2131 }; 1002 };
2132 1003
2133 i2c-bus { 1004 i2c-bus {
2134 #addr 1005 #address-cells = <1>;
2135 #size 1006 #size-cells = <0>;
2136 }; 1007 };
2137 }; 1008 };
2138 1009
2139 dpaux1: dpaux@155d000 1010 dpaux1: dpaux@155d0000 {
2140 compatible = 1011 compatible = "nvidia,tegra194-dpaux";
2141 reg = <0x0 0x !! 1012 reg = <0x155d0000 0x10000>;
2142 interrupts = 1013 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143 clocks = <&bp 1014 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bp 1015 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = 1016 clock-names = "dpaux", "parent";
2146 resets = <&bp 1017 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = 1018 reset-names = "dpaux";
2148 status = "dis 1019 status = "disabled";
2149 1020
2150 power-domains 1021 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151 1022
2152 state_dpaux1_ 1023 state_dpaux1_aux: pinmux-aux {
2153 group 1024 groups = "dpaux-io";
2154 funct 1025 function = "aux";
2155 }; 1026 };
2156 1027
2157 state_dpaux1_ 1028 state_dpaux1_i2c: pinmux-i2c {
2158 group 1029 groups = "dpaux-io";
2159 funct 1030 function = "i2c";
2160 }; 1031 };
2161 1032
2162 state_dpaux1_ 1033 state_dpaux1_off: pinmux-off {
2163 group 1034 groups = "dpaux-io";
2164 funct 1035 function = "off";
2165 }; 1036 };
2166 1037
2167 i2c-bus { 1038 i2c-bus {
2168 #addr 1039 #address-cells = <1>;
2169 #size 1040 #size-cells = <0>;
2170 }; 1041 };
2171 }; 1042 };
2172 1043
2173 dpaux2: dpaux@155e000 1044 dpaux2: dpaux@155e0000 {
2174 compatible = 1045 compatible = "nvidia,tegra194-dpaux";
2175 reg = <0x0 0x !! 1046 reg = <0x155e0000 0x10000>;
2176 interrupts = 1047 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177 clocks = <&bp 1048 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bp 1049 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = 1050 clock-names = "dpaux", "parent";
2180 resets = <&bp 1051 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = 1052 reset-names = "dpaux";
2182 status = "dis 1053 status = "disabled";
2183 1054
2184 power-domains 1055 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185 1056
2186 state_dpaux2_ 1057 state_dpaux2_aux: pinmux-aux {
2187 group 1058 groups = "dpaux-io";
2188 funct 1059 function = "aux";
2189 }; 1060 };
2190 1061
2191 state_dpaux2_ 1062 state_dpaux2_i2c: pinmux-i2c {
2192 group 1063 groups = "dpaux-io";
2193 funct 1064 function = "i2c";
2194 }; 1065 };
2195 1066
2196 state_dpaux2_ 1067 state_dpaux2_off: pinmux-off {
2197 group 1068 groups = "dpaux-io";
2198 funct 1069 function = "off";
2199 }; 1070 };
2200 1071
2201 i2c-bus { 1072 i2c-bus {
2202 #addr 1073 #address-cells = <1>;
2203 #size 1074 #size-cells = <0>;
2204 }; 1075 };
2205 }; 1076 };
2206 1077
2207 dpaux3: dpaux@155f000 1078 dpaux3: dpaux@155f0000 {
2208 compatible = 1079 compatible = "nvidia,tegra194-dpaux";
2209 reg = <0x0 0x !! 1080 reg = <0x155f0000 0x10000>;
2210 interrupts = 1081 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211 clocks = <&bp 1082 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bp 1083 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = 1084 clock-names = "dpaux", "parent";
2214 resets = <&bp 1085 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = 1086 reset-names = "dpaux";
2216 status = "dis 1087 status = "disabled";
2217 1088
2218 power-domains 1089 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219 1090
2220 state_dpaux3_ 1091 state_dpaux3_aux: pinmux-aux {
2221 group 1092 groups = "dpaux-io";
2222 funct 1093 function = "aux";
2223 }; 1094 };
2224 1095
2225 state_dpaux3_ 1096 state_dpaux3_i2c: pinmux-i2c {
2226 group 1097 groups = "dpaux-io";
2227 funct 1098 function = "i2c";
2228 }; 1099 };
2229 1100
2230 state_dpaux3_ 1101 state_dpaux3_off: pinmux-off {
2231 group 1102 groups = "dpaux-io";
2232 funct 1103 function = "off";
2233 }; 1104 };
2234 1105
2235 i2c-bus { 1106 i2c-bus {
2236 #addr 1107 #address-cells = <1>;
2237 #size 1108 #size-cells = <0>;
2238 }; 1109 };
2239 }; 1110 };
2240 1111
2241 nvenc@15a80000 { <<
2242 compatible = <<
2243 reg = <0x0 0x <<
2244 clocks = <&bp <<
2245 clock-names = <<
2246 resets = <&bp <<
2247 reset-names = <<
2248 <<
2249 power-domains <<
2250 interconnects <<
2251 <<
2252 <<
2253 interconnect- <<
2254 iommus = <&sm <<
2255 dma-coherent; <<
2256 <<
2257 nvidia,host1x <<
2258 }; <<
2259 <<
2260 sor0: sor@15b00000 { 1112 sor0: sor@15b00000 {
2261 compatible = 1113 compatible = "nvidia,tegra194-sor";
2262 reg = <0x0 0x !! 1114 reg = <0x15b00000 0x40000>;
2263 interrupts = 1115 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264 clocks = <&bp 1116 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bp 1117 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bp 1118 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bp 1119 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bp 1120 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bp 1121 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = 1122 clock-names = "sor", "out", "parent", "dp", "safe",
2271 1123 "pad";
2272 resets = <&bp 1124 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = 1125 reset-names = "sor";
2274 pinctrl-0 = < 1126 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = < 1127 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = < 1128 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names 1129 pinctrl-names = "aux", "i2c", "off";
2278 status = "dis 1130 status = "disabled";
2279 1131
2280 power-domains 1132 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281 nvidia,interf 1133 nvidia,interface = <0>;
2282 }; 1134 };
2283 1135
2284 sor1: sor@15b40000 { 1136 sor1: sor@15b40000 {
2285 compatible = 1137 compatible = "nvidia,tegra194-sor";
2286 reg = <0x0 0x !! 1138 reg = <0x15b40000 0x40000>;
2287 interrupts = 1139 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&bp 1140 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bp 1141 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bp 1142 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bp 1143 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bp 1144 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bp 1145 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = 1146 clock-names = "sor", "out", "parent", "dp", "safe",
2295 1147 "pad";
2296 resets = <&bp 1148 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = 1149 reset-names = "sor";
2298 pinctrl-0 = < 1150 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = < 1151 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = < 1152 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names 1153 pinctrl-names = "aux", "i2c", "off";
2302 status = "dis 1154 status = "disabled";
2303 1155
2304 power-domains 1156 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305 nvidia,interf 1157 nvidia,interface = <1>;
2306 }; 1158 };
2307 1159
2308 sor2: sor@15b80000 { 1160 sor2: sor@15b80000 {
2309 compatible = 1161 compatible = "nvidia,tegra194-sor";
2310 reg = <0x0 0x !! 1162 reg = <0x15b80000 0x40000>;
2311 interrupts = 1163 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&bp 1164 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bp 1165 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bp 1166 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bp 1167 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bp 1168 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bp 1169 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = 1170 clock-names = "sor", "out", "parent", "dp", "safe",
2319 1171 "pad";
2320 resets = <&bp 1172 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = 1173 reset-names = "sor";
2322 pinctrl-0 = < 1174 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = < 1175 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = < 1176 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names 1177 pinctrl-names = "aux", "i2c", "off";
2326 status = "dis 1178 status = "disabled";
2327 1179
2328 power-domains 1180 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329 nvidia,interf 1181 nvidia,interface = <2>;
2330 }; 1182 };
2331 1183
2332 sor3: sor@15bc0000 { 1184 sor3: sor@15bc0000 {
2333 compatible = 1185 compatible = "nvidia,tegra194-sor";
2334 reg = <0x0 0x !! 1186 reg = <0x15bc0000 0x40000>;
2335 interrupts = 1187 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&bp 1188 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bp 1189 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bp 1190 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bp 1191 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bp 1192 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bp 1193 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = 1194 clock-names = "sor", "out", "parent", "dp", "safe",
2343 1195 "pad";
2344 resets = <&bp 1196 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = 1197 reset-names = "sor";
2346 pinctrl-0 = < 1198 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = < 1199 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = < 1200 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names 1201 pinctrl-names = "aux", "i2c", "off";
2350 status = "dis 1202 status = "disabled";
2351 1203
2352 power-domains 1204 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353 nvidia,interf 1205 nvidia,interface = <3>;
2354 }; 1206 };
2355 }; 1207 };
>> 1208 };
2356 1209
2357 pcie@14100000 { !! 1210 pcie@14100000 {
2358 compatible = "nvidia, !! 1211 compatible = "nvidia,tegra194-pcie";
2359 power-domains = <&bpm !! 1212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2360 reg = <0x00 0x1410000 !! 1213 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
2361 <0x00 0x3000000 !! 1214 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
2362 <0x00 0x3004000 !! 1215 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
2363 <0x00 0x3008000 !! 1216 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2364 reg-names = "appl", " !! 1217 reg-names = "appl", "config", "atu_dma", "dbi";
2365 <<
2366 status = "disabled"; <<
2367 <<
2368 #address-cells = <3>; <<
2369 #size-cells = <2>; <<
2370 device_type = "pci"; <<
2371 num-lanes = <1>; <<
2372 linux,pci-domain = <1 <<
2373 <<
2374 clocks = <&bpmp TEGRA <<
2375 clock-names = "core"; <<
2376 <<
2377 resets = <&bpmp TEGRA <<
2378 <&bpmp TEGRA <<
2379 reset-names = "apb", <<
2380 <<
2381 interrupts = <GIC_SPI <<
2382 <GIC_SPI <<
2383 interrupt-names = "in <<
2384 <<
2385 #interrupt-cells = <1 <<
2386 interrupt-map-mask = <<
2387 interrupt-map = <0 0 <<
2388 <<
2389 nvidia,bpmp = <&bpmp <<
2390 <<
2391 nvidia,aspm-cmrt-us = <<
2392 nvidia,aspm-pwr-on-t- <<
2393 nvidia,aspm-l0s-entra <<
2394 <<
2395 bus-range = <0x0 0xff <<
2396 <<
2397 ranges = <0x43000000 <<
2398 <0x02000000 <<
2399 <0x01000000 <<
2400 <<
2401 interconnects = <&mc <<
2402 <&mc <<
2403 interconnect-names = <<
2404 iommu-map = <0x0 &smm <<
2405 iommu-map-mask = <0x0 <<
2406 dma-coherent; <<
2407 }; <<
2408 <<
2409 pcie@14120000 { <<
2410 compatible = "nvidia, <<
2411 power-domains = <&bpm <<
2412 reg = <0x00 0x1412000 <<
2413 <0x00 0x3200000 <<
2414 <0x00 0x3204000 <<
2415 <0x00 0x3208000 <<
2416 reg-names = "appl", " <<
2417 <<
2418 status = "disabled"; <<
2419 <<
2420 #address-cells = <3>; <<
2421 #size-cells = <2>; <<
2422 device_type = "pci"; <<
2423 num-lanes = <1>; <<
2424 linux,pci-domain = <2 <<
2425 <<
2426 clocks = <&bpmp TEGRA <<
2427 clock-names = "core"; <<
2428 <<
2429 resets = <&bpmp TEGRA <<
2430 <&bpmp TEGRA <<
2431 reset-names = "apb", <<
2432 <<
2433 interrupts = <GIC_SPI <<
2434 <GIC_SPI <<
2435 interrupt-names = "in <<
2436 <<
2437 #interrupt-cells = <1 <<
2438 interrupt-map-mask = <<
2439 interrupt-map = <0 0 <<
2440 <<
2441 nvidia,bpmp = <&bpmp <<
2442 <<
2443 nvidia,aspm-cmrt-us = <<
2444 nvidia,aspm-pwr-on-t- <<
2445 nvidia,aspm-l0s-entra <<
2446 <<
2447 bus-range = <0x0 0xff <<
2448 <<
2449 ranges = <0x43000000 <<
2450 <0x02000000 <<
2451 <0x01000000 <<
2452 <<
2453 interconnects = <&mc <<
2454 <&mc <<
2455 interconnect-names = <<
2456 iommu-map = <0x0 &smm <<
2457 iommu-map-mask = <0x0 <<
2458 dma-coherent; <<
2459 }; <<
2460 <<
2461 pcie@14140000 { <<
2462 compatible = "nvidia, <<
2463 power-domains = <&bpm <<
2464 reg = <0x00 0x1414000 <<
2465 <0x00 0x3400000 <<
2466 <0x00 0x3404000 <<
2467 <0x00 0x3408000 <<
2468 reg-names = "appl", " <<
2469 <<
2470 status = "disabled"; <<
2471 <<
2472 #address-cells = <3>; <<
2473 #size-cells = <2>; <<
2474 device_type = "pci"; <<
2475 num-lanes = <1>; <<
2476 linux,pci-domain = <3 <<
2477 <<
2478 clocks = <&bpmp TEGRA <<
2479 clock-names = "core"; <<
2480 <<
2481 resets = <&bpmp TEGRA <<
2482 <&bpmp TEGRA <<
2483 reset-names = "apb", <<
2484 <<
2485 interrupts = <GIC_SPI <<
2486 <GIC_SPI <<
2487 interrupt-names = "in <<
2488 <<
2489 #interrupt-cells = <1 <<
2490 interrupt-map-mask = <<
2491 interrupt-map = <0 0 <<
2492 <<
2493 nvidia,bpmp = <&bpmp <<
2494 <<
2495 nvidia,aspm-cmrt-us = <<
2496 nvidia,aspm-pwr-on-t- <<
2497 nvidia,aspm-l0s-entra <<
2498 <<
2499 bus-range = <0x0 0xff <<
2500 <<
2501 ranges = <0x43000000 <<
2502 <0x02000000 <<
2503 <0x01000000 <<
2504 <<
2505 interconnects = <&mc <<
2506 <&mc <<
2507 interconnect-names = <<
2508 iommu-map = <0x0 &smm <<
2509 iommu-map-mask = <0x0 <<
2510 dma-coherent; <<
2511 }; <<
2512 <<
2513 pcie@14160000 { <<
2514 compatible = "nvidia, <<
2515 power-domains = <&bpm <<
2516 reg = <0x00 0x1416000 <<
2517 <0x00 0x3600000 <<
2518 <0x00 0x3604000 <<
2519 <0x00 0x3608000 <<
2520 reg-names = "appl", " <<
2521 <<
2522 status = "disabled"; <<
2523 <<
2524 #address-cells = <3>; <<
2525 #size-cells = <2>; <<
2526 device_type = "pci"; <<
2527 num-lanes = <4>; <<
2528 linux,pci-domain = <4 <<
2529 1218
2530 clocks = <&bpmp TEGRA !! 1219 status = "disabled";
2531 clock-names = "core"; <<
2532 1220
2533 resets = <&bpmp TEGRA !! 1221 #address-cells = <3>;
2534 <&bpmp TEGRA !! 1222 #size-cells = <2>;
2535 reset-names = "apb", !! 1223 device_type = "pci";
>> 1224 num-lanes = <1>;
>> 1225 num-viewport = <8>;
>> 1226 linux,pci-domain = <1>;
>> 1227
>> 1228 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
>> 1229 clock-names = "core";
>> 1230
>> 1231 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
>> 1232 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
>> 1233 reset-names = "apb", "core";
>> 1234
>> 1235 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1236 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1237 interrupt-names = "intr", "msi";
>> 1238
>> 1239 #interrupt-cells = <1>;
>> 1240 interrupt-map-mask = <0 0 0 0>;
>> 1241 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 1242
>> 1243 nvidia,bpmp = <&bpmp 1>;
>> 1244
>> 1245 nvidia,aspm-cmrt-us = <60>;
>> 1246 nvidia,aspm-pwr-on-t-us = <20>;
>> 1247 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1248
>> 1249 bus-range = <0x0 0xff>;
>> 1250 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1251 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
>> 1252 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
>> 1253 };
2536 1254
2537 interrupts = <GIC_SPI !! 1255 pcie@14120000 {
2538 <GIC_SPI !! 1256 compatible = "nvidia,tegra194-pcie";
2539 interrupt-names = "in !! 1257 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1258 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
>> 1259 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
>> 1260 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1261 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1262 reg-names = "appl", "config", "atu_dma", "dbi";
2540 1263
2541 #interrupt-cells = <1 !! 1264 status = "disabled";
2542 interrupt-map-mask = <<
2543 interrupt-map = <0 0 <<
2544 1265
2545 nvidia,bpmp = <&bpmp !! 1266 #address-cells = <3>;
>> 1267 #size-cells = <2>;
>> 1268 device_type = "pci";
>> 1269 num-lanes = <1>;
>> 1270 num-viewport = <8>;
>> 1271 linux,pci-domain = <2>;
>> 1272
>> 1273 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
>> 1274 clock-names = "core";
>> 1275
>> 1276 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
>> 1277 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
>> 1278 reset-names = "apb", "core";
>> 1279
>> 1280 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1281 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1282 interrupt-names = "intr", "msi";
>> 1283
>> 1284 #interrupt-cells = <1>;
>> 1285 interrupt-map-mask = <0 0 0 0>;
>> 1286 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 1287
>> 1288 nvidia,bpmp = <&bpmp 2>;
>> 1289
>> 1290 nvidia,aspm-cmrt-us = <60>;
>> 1291 nvidia,aspm-pwr-on-t-us = <20>;
>> 1292 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1293
>> 1294 bus-range = <0x0 0xff>;
>> 1295 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1296 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
>> 1297 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
>> 1298 };
2546 1299
2547 nvidia,aspm-cmrt-us = !! 1300 pcie@14140000 {
2548 nvidia,aspm-pwr-on-t- !! 1301 compatible = "nvidia,tegra194-pcie";
2549 nvidia,aspm-l0s-entra !! 1302 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
>> 1303 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
>> 1304 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
>> 1305 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1306 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1307 reg-names = "appl", "config", "atu_dma", "dbi";
2550 1308
2551 bus-range = <0x0 0xff !! 1309 status = "disabled";
2552 1310
2553 ranges = <0x43000000 !! 1311 #address-cells = <3>;
2554 <0x02000000 !! 1312 #size-cells = <2>;
2555 <0x01000000 !! 1313 device_type = "pci";
>> 1314 num-lanes = <1>;
>> 1315 num-viewport = <8>;
>> 1316 linux,pci-domain = <3>;
>> 1317
>> 1318 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
>> 1319 clock-names = "core";
>> 1320
>> 1321 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
>> 1322 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
>> 1323 reset-names = "apb", "core";
>> 1324
>> 1325 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1326 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1327 interrupt-names = "intr", "msi";
>> 1328
>> 1329 #interrupt-cells = <1>;
>> 1330 interrupt-map-mask = <0 0 0 0>;
>> 1331 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>> 1332
>> 1333 nvidia,bpmp = <&bpmp 3>;
>> 1334
>> 1335 nvidia,aspm-cmrt-us = <60>;
>> 1336 nvidia,aspm-pwr-on-t-us = <20>;
>> 1337 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1338
>> 1339 bus-range = <0x0 0xff>;
>> 1340 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1341 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
>> 1342 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
>> 1343 };
2556 1344
2557 interconnects = <&mc !! 1345 pcie@14160000 {
2558 <&mc !! 1346 compatible = "nvidia,tegra194-pcie";
2559 interconnect-names = !! 1347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2560 iommu-map = <0x0 &smm !! 1348 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
2561 iommu-map-mask = <0x0 !! 1349 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
2562 dma-coherent; !! 1350 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
2563 }; !! 1351 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1352 reg-names = "appl", "config", "atu_dma", "dbi";
2564 1353
2565 pcie-ep@14160000 { !! 1354 status = "disabled";
2566 compatible = "nvidia, <<
2567 power-domains = <&bpm <<
2568 reg = <0x00 0x1416000 <<
2569 <0x00 0x3604000 <<
2570 <0x00 0x3608000 <<
2571 <0x14 0x0000000 <<
2572 reg-names = "appl", " <<
2573 1355
2574 status = "disabled"; !! 1356 #address-cells = <3>;
>> 1357 #size-cells = <2>;
>> 1358 device_type = "pci";
>> 1359 num-lanes = <4>;
>> 1360 num-viewport = <8>;
>> 1361 linux,pci-domain = <4>;
>> 1362
>> 1363 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
>> 1364 clock-names = "core";
>> 1365
>> 1366 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
>> 1367 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1368 reset-names = "apb", "core";
>> 1369
>> 1370 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1371 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1372 interrupt-names = "intr", "msi";
>> 1373
>> 1374 #interrupt-cells = <1>;
>> 1375 interrupt-map-mask = <0 0 0 0>;
>> 1376 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 1377
>> 1378 nvidia,bpmp = <&bpmp 4>;
>> 1379
>> 1380 nvidia,aspm-cmrt-us = <60>;
>> 1381 nvidia,aspm-pwr-on-t-us = <20>;
>> 1382 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1383
>> 1384 bus-range = <0x0 0xff>;
>> 1385 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1386 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
>> 1387 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
>> 1388 };
2575 1389
2576 num-lanes = <4>; !! 1390 pcie@14180000 {
2577 num-ib-windows = <2>; !! 1391 compatible = "nvidia,tegra194-pcie";
2578 num-ob-windows = <8>; !! 1392 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 1393 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
>> 1394 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
>> 1395 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1396 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1397 reg-names = "appl", "config", "atu_dma", "dbi";
2579 1398
2580 clocks = <&bpmp TEGRA !! 1399 status = "disabled";
2581 clock-names = "core"; <<
2582 1400
2583 resets = <&bpmp TEGRA !! 1401 #address-cells = <3>;
2584 <&bpmp TEGRA !! 1402 #size-cells = <2>;
2585 reset-names = "apb", !! 1403 device_type = "pci";
>> 1404 num-lanes = <8>;
>> 1405 num-viewport = <8>;
>> 1406 linux,pci-domain = <0>;
>> 1407
>> 1408 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> 1409 clock-names = "core";
>> 1410
>> 1411 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> 1412 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> 1413 reset-names = "apb", "core";
>> 1414
>> 1415 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1416 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1417 interrupt-names = "intr", "msi";
>> 1418
>> 1419 #interrupt-cells = <1>;
>> 1420 interrupt-map-mask = <0 0 0 0>;
>> 1421 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 1422
>> 1423 nvidia,bpmp = <&bpmp 0>;
>> 1424
>> 1425 nvidia,aspm-cmrt-us = <60>;
>> 1426 nvidia,aspm-pwr-on-t-us = <20>;
>> 1427 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1428
>> 1429 bus-range = <0x0 0xff>;
>> 1430 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1431 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
>> 1432 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
>> 1433 };
2586 1434
2587 interrupts = <GIC_SPI !! 1435 pcie@141a0000 {
2588 interrupt-names = "in !! 1436 compatible = "nvidia,tegra194-pcie";
>> 1437 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 1438 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
>> 1439 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
>> 1440 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1441 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> 1442 reg-names = "appl", "config", "atu_dma", "dbi";
2589 1443
2590 nvidia,bpmp = <&bpmp !! 1444 status = "disabled";
2591 1445
2592 nvidia,aspm-cmrt-us = !! 1446 #address-cells = <3>;
2593 nvidia,aspm-pwr-on-t- !! 1447 #size-cells = <2>;
2594 nvidia,aspm-l0s-entra !! 1448 device_type = "pci";
>> 1449 num-lanes = <8>;
>> 1450 num-viewport = <8>;
>> 1451 linux,pci-domain = <5>;
>> 1452
>> 1453 pinctrl-names = "default";
>> 1454 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> 1455
>> 1456 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
>> 1457 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
>> 1458 clock-names = "core", "core_m";
>> 1459
>> 1460 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> 1461 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> 1462 reset-names = "apb", "core";
>> 1463
>> 1464 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> 1465 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> 1466 interrupt-names = "intr", "msi";
>> 1467
>> 1468 nvidia,bpmp = <&bpmp 5>;
>> 1469
>> 1470 #interrupt-cells = <1>;
>> 1471 interrupt-map-mask = <0 0 0 0>;
>> 1472 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
>> 1473
>> 1474 nvidia,aspm-cmrt-us = <60>;
>> 1475 nvidia,aspm-pwr-on-t-us = <20>;
>> 1476 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1477
>> 1478 bus-range = <0x0 0xff>;
>> 1479 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> 1480 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
>> 1481 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
>> 1482 };
2595 1483
2596 interconnects = <&mc !! 1484 pcie_ep@14160000 {
2597 <&mc !! 1485 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2598 interconnect-names = !! 1486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2599 iommu-map = <0x0 &smm !! 1487 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
2600 iommu-map-mask = <0x0 !! 1488 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
2601 dma-coherent; !! 1489 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
2602 }; !! 1490 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 1491 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2603 1492
2604 pcie@14180000 { !! 1493 status = "disabled";
2605 compatible = "nvidia, <<
2606 power-domains = <&bpm <<
2607 reg = <0x00 0x1418000 <<
2608 <0x00 0x3800000 <<
2609 <0x00 0x3804000 <<
2610 <0x00 0x3808000 <<
2611 reg-names = "appl", " <<
2612 1494
2613 status = "disabled"; !! 1495 num-lanes = <4>;
>> 1496 num-ib-windows = <2>;
>> 1497 num-ob-windows = <8>;
2614 1498
2615 #address-cells = <3>; !! 1499 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2616 #size-cells = <2>; !! 1500 clock-names = "core";
2617 device_type = "pci"; <<
2618 num-lanes = <8>; <<
2619 linux,pci-domain = <0 <<
2620 1501
2621 clocks = <&bpmp TEGRA !! 1502 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2622 clock-names = "core"; !! 1503 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
>> 1504 reset-names = "apb", "core";
2623 1505
2624 resets = <&bpmp TEGRA !! 1506 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2625 <&bpmp TEGRA !! 1507 interrupt-names = "intr";
2626 reset-names = "apb", <<
2627 1508
2628 interrupts = <GIC_SPI !! 1509 nvidia,bpmp = <&bpmp 4>;
2629 <GIC_SPI <<
2630 interrupt-names = "in <<
2631 1510
2632 #interrupt-cells = <1 !! 1511 nvidia,aspm-cmrt-us = <60>;
2633 interrupt-map-mask = !! 1512 nvidia,aspm-pwr-on-t-us = <20>;
2634 interrupt-map = <0 0 !! 1513 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1514 };
2635 1515
2636 nvidia,bpmp = <&bpmp !! 1516 pcie_ep@14180000 {
>> 1517 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
>> 1518 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> 1519 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
>> 1520 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1521 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
>> 1522 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 1523 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2637 1524
2638 nvidia,aspm-cmrt-us = !! 1525 status = "disabled";
2639 nvidia,aspm-pwr-on-t- <<
2640 nvidia,aspm-l0s-entra <<
2641 1526
2642 bus-range = <0x0 0xff !! 1527 num-lanes = <8>;
>> 1528 num-ib-windows = <2>;
>> 1529 num-ob-windows = <8>;
2643 1530
2644 ranges = <0x43000000 !! 1531 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2645 <0x02000000 !! 1532 clock-names = "core";
2646 <0x01000000 <<
2647 1533
2648 interconnects = <&mc !! 1534 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2649 <&mc !! 1535 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2650 interconnect-names = !! 1536 reset-names = "apb", "core";
2651 iommu-map = <0x0 &smm <<
2652 iommu-map-mask = <0x0 <<
2653 dma-coherent; <<
2654 }; <<
2655 1537
2656 pcie-ep@14180000 { !! 1538 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2657 compatible = "nvidia, !! 1539 interrupt-names = "intr";
2658 power-domains = <&bpm <<
2659 reg = <0x00 0x1418000 <<
2660 <0x00 0x3804000 <<
2661 <0x00 0x3808000 <<
2662 <0x18 0x0000000 <<
2663 reg-names = "appl", " <<
2664 1540
2665 status = "disabled"; !! 1541 nvidia,bpmp = <&bpmp 0>;
2666 1542
2667 num-lanes = <8>; !! 1543 nvidia,aspm-cmrt-us = <60>;
2668 num-ib-windows = <2>; !! 1544 nvidia,aspm-pwr-on-t-us = <20>;
2669 num-ob-windows = <8>; !! 1545 nvidia,aspm-l0s-entrance-latency-us = <3>;
>> 1546 };
2670 1547
2671 clocks = <&bpmp TEGRA !! 1548 pcie_ep@141a0000 {
2672 clock-names = "core"; !! 1549 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
>> 1550 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> 1551 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
>> 1552 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> 1553 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
>> 1554 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> 1555 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2673 1556
2674 resets = <&bpmp TEGRA !! 1557 status = "disabled";
2675 <&bpmp TEGRA <<
2676 reset-names = "apb", <<
2677 1558
2678 interrupts = <GIC_SPI !! 1559 num-lanes = <8>;
2679 interrupt-names = "in !! 1560 num-ib-windows = <2>;
>> 1561 num-ob-windows = <8>;
2680 1562
2681 nvidia,bpmp = <&bpmp !! 1563 pinctrl-names = "default";
>> 1564 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2682 1565
2683 nvidia,aspm-cmrt-us = !! 1566 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2684 nvidia,aspm-pwr-on-t- !! 1567 clock-names = "core";
2685 nvidia,aspm-l0s-entra <<
2686 1568
2687 interconnects = <&mc !! 1569 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2688 <&mc !! 1570 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2689 interconnect-names = !! 1571 reset-names = "apb", "core";
2690 iommu-map = <0x0 &smm <<
2691 iommu-map-mask = <0x0 <<
2692 dma-coherent; <<
2693 }; <<
2694 1572
2695 pcie@141a0000 { !! 1573 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2696 compatible = "nvidia, !! 1574 interrupt-names = "intr";
2697 power-domains = <&bpm <<
2698 reg = <0x00 0x141a000 <<
2699 <0x00 0x3a00000 <<
2700 <0x00 0x3a04000 <<
2701 <0x00 0x3a08000 <<
2702 reg-names = "appl", " <<
2703 1575
2704 status = "disabled"; !! 1576 nvidia,bpmp = <&bpmp 5>;
2705 1577
2706 #address-cells = <3>; !! 1578 nvidia,aspm-cmrt-us = <60>;
2707 #size-cells = <2>; !! 1579 nvidia,aspm-pwr-on-t-us = <20>;
2708 device_type = "pci"; !! 1580 nvidia,aspm-l0s-entrance-latency-us = <3>;
2709 num-lanes = <8>; <<
2710 linux,pci-domain = <5 <<
2711 <<
2712 pinctrl-names = "defa <<
2713 pinctrl-0 = <&pex_rst <<
2714 <<
2715 clocks = <&bpmp TEGRA <<
2716 clock-names = "core"; <<
2717 <<
2718 resets = <&bpmp TEGRA <<
2719 <&bpmp TEGRA <<
2720 reset-names = "apb", <<
2721 <<
2722 interrupts = <GIC_SPI <<
2723 <GIC_SPI <<
2724 interrupt-names = "in <<
2725 <<
2726 nvidia,bpmp = <&bpmp <<
2727 <<
2728 #interrupt-cells = <1 <<
2729 interrupt-map-mask = <<
2730 interrupt-map = <0 0 <<
2731 <<
2732 nvidia,aspm-cmrt-us = <<
2733 nvidia,aspm-pwr-on-t- <<
2734 nvidia,aspm-l0s-entra <<
2735 <<
2736 bus-range = <0x0 0xff <<
2737 <<
2738 ranges = <0x43000000 <<
2739 <0x02000000 <<
2740 <0x01000000 <<
2741 <<
2742 interconnects = <&mc <<
2743 <&mc <<
2744 interconnect-names = <<
2745 iommu-map = <0x0 &smm <<
2746 iommu-map-mask = <0x0 <<
2747 dma-coherent; <<
2748 }; <<
2749 <<
2750 pcie-ep@141a0000 { <<
2751 compatible = "nvidia, <<
2752 power-domains = <&bpm <<
2753 reg = <0x00 0x141a000 <<
2754 <0x00 0x3a04000 <<
2755 <0x00 0x3a08000 <<
2756 <0x1c 0x0000000 <<
2757 reg-names = "appl", " <<
2758 <<
2759 status = "disabled"; <<
2760 <<
2761 num-lanes = <8>; <<
2762 num-ib-windows = <2>; <<
2763 num-ob-windows = <8>; <<
2764 <<
2765 pinctrl-names = "defa <<
2766 pinctrl-0 = <&pex_clk <<
2767 <<
2768 clocks = <&bpmp TEGRA <<
2769 clock-names = "core"; <<
2770 <<
2771 resets = <&bpmp TEGRA <<
2772 <&bpmp TEGRA <<
2773 reset-names = "apb", <<
2774 <<
2775 interrupts = <GIC_SPI <<
2776 interrupt-names = "in <<
2777 <<
2778 nvidia,bpmp = <&bpmp <<
2779 <<
2780 nvidia,aspm-cmrt-us = <<
2781 nvidia,aspm-pwr-on-t- <<
2782 nvidia,aspm-l0s-entra <<
2783 <<
2784 interconnects = <&mc <<
2785 <&mc <<
2786 interconnect-names = <<
2787 iommu-map = <0x0 &smm <<
2788 iommu-map-mask = <0x0 <<
2789 dma-coherent; <<
2790 }; <<
2791 <<
2792 gpu@17000000 { <<
2793 compatible = "nvidia, <<
2794 reg = <0x0 0x17000000 <<
2795 <0x0 0x18000000 <<
2796 interrupts = <GIC_SPI <<
2797 <GIC_SPI <<
2798 interrupt-names = "st <<
2799 clocks = <&bpmp TEGRA <<
2800 <&bpmp TEGRA <<
2801 <&bpmp TEGRA <<
2802 clock-names = "gpu", <<
2803 resets = <&bpmp TEGRA <<
2804 reset-names = "gpu"; <<
2805 dma-coherent; <<
2806 <<
2807 power-domains = <&bpm <<
2808 interconnects = <&mc <<
2809 <&mc <<
2810 <&mc <<
2811 <&mc <<
2812 <&mc <<
2813 <&mc <<
2814 <&mc <<
2815 <&mc <<
2816 <&mc <<
2817 <&mc <<
2818 <&mc <<
2819 <&mc <<
2820 interconnect-names = <<
2821 <<
2822 <<
2823 <<
2824 }; <<
2825 }; 1581 };
2826 1582
2827 sram@40000000 { !! 1583 sysram@40000000 {
2828 compatible = "nvidia,tegra194 1584 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829 reg = <0x0 0x40000000 0x0 0x5 1585 reg = <0x0 0x40000000 0x0 0x50000>;
2830 <<
2831 #address-cells = <1>; 1586 #address-cells = <1>;
2832 #size-cells = <1>; 1587 #size-cells = <1>;
2833 ranges = <0x0 0x0 0x40000000 1588 ranges = <0x0 0x0 0x40000000 0x50000>;
2834 1589
2835 no-memory-wc; !! 1590 cpu_bpmp_tx: shmem@4e000 {
2836 !! 1591 compatible = "nvidia,tegra194-bpmp-shmem";
2837 cpu_bpmp_tx: sram@4e000 { <<
2838 reg = <0x4e000 0x1000 1592 reg = <0x4e000 0x1000>;
2839 label = "cpu-bpmp-tx" 1593 label = "cpu-bpmp-tx";
2840 pool; 1594 pool;
2841 }; 1595 };
2842 1596
2843 cpu_bpmp_rx: sram@4f000 { !! 1597 cpu_bpmp_rx: shmem@4f000 {
>> 1598 compatible = "nvidia,tegra194-bpmp-shmem";
2844 reg = <0x4f000 0x1000 1599 reg = <0x4f000 0x1000>;
2845 label = "cpu-bpmp-rx" 1600 label = "cpu-bpmp-rx";
2846 pool; 1601 pool;
2847 }; 1602 };
2848 }; 1603 };
2849 1604
2850 bpmp: bpmp { 1605 bpmp: bpmp {
2851 compatible = "nvidia,tegra186 1606 compatible = "nvidia,tegra186-bpmp";
2852 mboxes = <&hsp_top0 TEGRA_HSP 1607 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853 TEGRA_HSP 1608 TEGRA_HSP_DB_MASTER_BPMP>;
2854 shmem = <&cpu_bpmp_tx>, <&cpu !! 1609 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2855 #clock-cells = <1>; 1610 #clock-cells = <1>;
2856 #reset-cells = <1>; 1611 #reset-cells = <1>;
2857 #power-domain-cells = <1>; 1612 #power-domain-cells = <1>;
2858 interconnects = <&mc TEGRA194 <<
2859 <&mc TEGRA194 <<
2860 <&mc TEGRA194 <<
2861 <&mc TEGRA194 <<
2862 interconnect-names = "read", <<
2863 iommus = <&smmu TEGRA194_SID_ <<
2864 1613
2865 bpmp_i2c: i2c { 1614 bpmp_i2c: i2c {
2866 compatible = "nvidia, 1615 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = 1616 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>; 1617 #address-cells = <1>;
2869 #size-cells = <0>; 1618 #size-cells = <0>;
2870 }; 1619 };
2871 1620
2872 bpmp_thermal: thermal { 1621 bpmp_thermal: thermal {
2873 compatible = "nvidia, 1622 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells 1623 #thermal-sensor-cells = <1>;
2875 }; 1624 };
2876 }; 1625 };
2877 1626
2878 cpus { 1627 cpus {
2879 compatible = "nvidia,tegra194 <<
2880 nvidia,bpmp = <&bpmp>; <<
2881 #address-cells = <1>; 1628 #address-cells = <1>;
2882 #size-cells = <0>; 1629 #size-cells = <0>;
2883 1630
2884 cpu0_0: cpu@0 { 1631 cpu0_0: cpu@0 {
2885 compatible = "nvidia, 1632 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu"; 1633 device_type = "cpu";
2887 reg = <0x000>; 1634 reg = <0x000>;
2888 enable-method = "psci 1635 enable-method = "psci";
2889 i-cache-size = <13107 1636 i-cache-size = <131072>;
2890 i-cache-line-size = < 1637 i-cache-line-size = <64>;
2891 i-cache-sets = <512>; 1638 i-cache-sets = <512>;
2892 d-cache-size = <65536 1639 d-cache-size = <65536>;
2893 d-cache-line-size = < 1640 d-cache-line-size = <64>;
2894 d-cache-sets = <256>; 1641 d-cache-sets = <256>;
2895 next-level-cache = <& 1642 next-level-cache = <&l2c_0>;
2896 }; 1643 };
2897 1644
2898 cpu0_1: cpu@1 { 1645 cpu0_1: cpu@1 {
2899 compatible = "nvidia, 1646 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu"; 1647 device_type = "cpu";
2901 reg = <0x001>; 1648 reg = <0x001>;
2902 enable-method = "psci 1649 enable-method = "psci";
2903 i-cache-size = <13107 1650 i-cache-size = <131072>;
2904 i-cache-line-size = < 1651 i-cache-line-size = <64>;
2905 i-cache-sets = <512>; 1652 i-cache-sets = <512>;
2906 d-cache-size = <65536 1653 d-cache-size = <65536>;
2907 d-cache-line-size = < 1654 d-cache-line-size = <64>;
2908 d-cache-sets = <256>; 1655 d-cache-sets = <256>;
2909 next-level-cache = <& 1656 next-level-cache = <&l2c_0>;
2910 }; 1657 };
2911 1658
2912 cpu1_0: cpu@100 { 1659 cpu1_0: cpu@100 {
2913 compatible = "nvidia, 1660 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu"; 1661 device_type = "cpu";
2915 reg = <0x100>; 1662 reg = <0x100>;
2916 enable-method = "psci 1663 enable-method = "psci";
2917 i-cache-size = <13107 1664 i-cache-size = <131072>;
2918 i-cache-line-size = < 1665 i-cache-line-size = <64>;
2919 i-cache-sets = <512>; 1666 i-cache-sets = <512>;
2920 d-cache-size = <65536 1667 d-cache-size = <65536>;
2921 d-cache-line-size = < 1668 d-cache-line-size = <64>;
2922 d-cache-sets = <256>; 1669 d-cache-sets = <256>;
2923 next-level-cache = <& 1670 next-level-cache = <&l2c_1>;
2924 }; 1671 };
2925 1672
2926 cpu1_1: cpu@101 { 1673 cpu1_1: cpu@101 {
2927 compatible = "nvidia, 1674 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu"; 1675 device_type = "cpu";
2929 reg = <0x101>; 1676 reg = <0x101>;
2930 enable-method = "psci 1677 enable-method = "psci";
2931 i-cache-size = <13107 1678 i-cache-size = <131072>;
2932 i-cache-line-size = < 1679 i-cache-line-size = <64>;
2933 i-cache-sets = <512>; 1680 i-cache-sets = <512>;
2934 d-cache-size = <65536 1681 d-cache-size = <65536>;
2935 d-cache-line-size = < 1682 d-cache-line-size = <64>;
2936 d-cache-sets = <256>; 1683 d-cache-sets = <256>;
2937 next-level-cache = <& 1684 next-level-cache = <&l2c_1>;
2938 }; 1685 };
2939 1686
2940 cpu2_0: cpu@200 { 1687 cpu2_0: cpu@200 {
2941 compatible = "nvidia, 1688 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu"; 1689 device_type = "cpu";
2943 reg = <0x200>; 1690 reg = <0x200>;
2944 enable-method = "psci 1691 enable-method = "psci";
2945 i-cache-size = <13107 1692 i-cache-size = <131072>;
2946 i-cache-line-size = < 1693 i-cache-line-size = <64>;
2947 i-cache-sets = <512>; 1694 i-cache-sets = <512>;
2948 d-cache-size = <65536 1695 d-cache-size = <65536>;
2949 d-cache-line-size = < 1696 d-cache-line-size = <64>;
2950 d-cache-sets = <256>; 1697 d-cache-sets = <256>;
2951 next-level-cache = <& 1698 next-level-cache = <&l2c_2>;
2952 }; 1699 };
2953 1700
2954 cpu2_1: cpu@201 { 1701 cpu2_1: cpu@201 {
2955 compatible = "nvidia, 1702 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu"; 1703 device_type = "cpu";
2957 reg = <0x201>; 1704 reg = <0x201>;
2958 enable-method = "psci 1705 enable-method = "psci";
2959 i-cache-size = <13107 1706 i-cache-size = <131072>;
2960 i-cache-line-size = < 1707 i-cache-line-size = <64>;
2961 i-cache-sets = <512>; 1708 i-cache-sets = <512>;
2962 d-cache-size = <65536 1709 d-cache-size = <65536>;
2963 d-cache-line-size = < 1710 d-cache-line-size = <64>;
2964 d-cache-sets = <256>; 1711 d-cache-sets = <256>;
2965 next-level-cache = <& 1712 next-level-cache = <&l2c_2>;
2966 }; 1713 };
2967 1714
2968 cpu3_0: cpu@300 { 1715 cpu3_0: cpu@300 {
2969 compatible = "nvidia, 1716 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu"; 1717 device_type = "cpu";
2971 reg = <0x300>; 1718 reg = <0x300>;
2972 enable-method = "psci 1719 enable-method = "psci";
2973 i-cache-size = <13107 1720 i-cache-size = <131072>;
2974 i-cache-line-size = < 1721 i-cache-line-size = <64>;
2975 i-cache-sets = <512>; 1722 i-cache-sets = <512>;
2976 d-cache-size = <65536 1723 d-cache-size = <65536>;
2977 d-cache-line-size = < 1724 d-cache-line-size = <64>;
2978 d-cache-sets = <256>; 1725 d-cache-sets = <256>;
2979 next-level-cache = <& 1726 next-level-cache = <&l2c_3>;
2980 }; 1727 };
2981 1728
2982 cpu3_1: cpu@301 { 1729 cpu3_1: cpu@301 {
2983 compatible = "nvidia, 1730 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu"; 1731 device_type = "cpu";
2985 reg = <0x301>; 1732 reg = <0x301>;
2986 enable-method = "psci 1733 enable-method = "psci";
2987 i-cache-size = <13107 1734 i-cache-size = <131072>;
2988 i-cache-line-size = < 1735 i-cache-line-size = <64>;
2989 i-cache-sets = <512>; 1736 i-cache-sets = <512>;
2990 d-cache-size = <65536 1737 d-cache-size = <65536>;
2991 d-cache-line-size = < 1738 d-cache-line-size = <64>;
2992 d-cache-sets = <256>; 1739 d-cache-sets = <256>;
2993 next-level-cache = <& 1740 next-level-cache = <&l2c_3>;
2994 }; 1741 };
2995 1742
2996 cpu-map { 1743 cpu-map {
2997 cluster0 { 1744 cluster0 {
2998 core0 { 1745 core0 {
2999 cpu = 1746 cpu = <&cpu0_0>;
3000 }; 1747 };
3001 1748
3002 core1 { 1749 core1 {
3003 cpu = 1750 cpu = <&cpu0_1>;
3004 }; 1751 };
3005 }; 1752 };
3006 1753
3007 cluster1 { 1754 cluster1 {
3008 core0 { 1755 core0 {
3009 cpu = 1756 cpu = <&cpu1_0>;
3010 }; 1757 };
3011 1758
3012 core1 { 1759 core1 {
3013 cpu = 1760 cpu = <&cpu1_1>;
3014 }; 1761 };
3015 }; 1762 };
3016 1763
3017 cluster2 { 1764 cluster2 {
3018 core0 { 1765 core0 {
3019 cpu = 1766 cpu = <&cpu2_0>;
3020 }; 1767 };
3021 1768
3022 core1 { 1769 core1 {
3023 cpu = 1770 cpu = <&cpu2_1>;
3024 }; 1771 };
3025 }; 1772 };
3026 1773
3027 cluster3 { 1774 cluster3 {
3028 core0 { 1775 core0 {
3029 cpu = 1776 cpu = <&cpu3_0>;
3030 }; 1777 };
3031 1778
3032 core1 { 1779 core1 {
3033 cpu = 1780 cpu = <&cpu3_1>;
3034 }; 1781 };
3035 }; 1782 };
3036 }; 1783 };
3037 1784
3038 l2c_0: l2-cache0 { 1785 l2c_0: l2-cache0 {
3039 compatible = "cache"; <<
3040 cache-unified; <<
3041 cache-size = <2097152 1786 cache-size = <2097152>;
3042 cache-line-size = <64 1787 cache-line-size = <64>;
3043 cache-sets = <2048>; 1788 cache-sets = <2048>;
3044 cache-level = <2>; <<
3045 next-level-cache = <& 1789 next-level-cache = <&l3c>;
3046 }; 1790 };
3047 1791
3048 l2c_1: l2-cache1 { 1792 l2c_1: l2-cache1 {
3049 compatible = "cache"; <<
3050 cache-unified; <<
3051 cache-size = <2097152 1793 cache-size = <2097152>;
3052 cache-line-size = <64 1794 cache-line-size = <64>;
3053 cache-sets = <2048>; 1795 cache-sets = <2048>;
3054 cache-level = <2>; <<
3055 next-level-cache = <& 1796 next-level-cache = <&l3c>;
3056 }; 1797 };
3057 1798
3058 l2c_2: l2-cache2 { 1799 l2c_2: l2-cache2 {
3059 compatible = "cache"; <<
3060 cache-unified; <<
3061 cache-size = <2097152 1800 cache-size = <2097152>;
3062 cache-line-size = <64 1801 cache-line-size = <64>;
3063 cache-sets = <2048>; 1802 cache-sets = <2048>;
3064 cache-level = <2>; <<
3065 next-level-cache = <& 1803 next-level-cache = <&l3c>;
3066 }; 1804 };
3067 1805
3068 l2c_3: l2-cache3 { 1806 l2c_3: l2-cache3 {
3069 compatible = "cache"; <<
3070 cache-unified; <<
3071 cache-size = <2097152 1807 cache-size = <2097152>;
3072 cache-line-size = <64 1808 cache-line-size = <64>;
3073 cache-sets = <2048>; 1809 cache-sets = <2048>;
3074 cache-level = <2>; <<
3075 next-level-cache = <& 1810 next-level-cache = <&l3c>;
3076 }; 1811 };
3077 1812
3078 l3c: l3-cache { 1813 l3c: l3-cache {
3079 compatible = "cache"; <<
3080 cache-unified; <<
3081 cache-size = <4194304 1814 cache-size = <4194304>;
3082 cache-line-size = <64 1815 cache-line-size = <64>;
3083 cache-level = <3>; <<
3084 cache-sets = <4096>; 1816 cache-sets = <4096>;
3085 }; 1817 };
3086 }; 1818 };
3087 1819
3088 pmu { <<
3089 compatible = "nvidia,carmel-p <<
3090 interrupts = <GIC_SPI 384 IRQ <<
3091 <GIC_SPI 385 IRQ <<
3092 <GIC_SPI 386 IRQ <<
3093 <GIC_SPI 387 IRQ <<
3094 <GIC_SPI 388 IRQ <<
3095 <GIC_SPI 389 IRQ <<
3096 <GIC_SPI 390 IRQ <<
3097 <GIC_SPI 391 IRQ <<
3098 interrupt-affinity = <&cpu0_0 <<
3099 &cpu2_0 <<
3100 }; <<
3101 <<
3102 psci { 1820 psci {
3103 compatible = "arm,psci-1.0"; 1821 compatible = "arm,psci-1.0";
3104 status = "okay"; 1822 status = "okay";
3105 method = "smc"; 1823 method = "smc";
3106 }; 1824 };
3107 1825
3108 tcu: serial { !! 1826 tcu: tcu {
3109 compatible = "nvidia,tegra194 1827 compatible = "nvidia,tegra194-tcu";
3110 mboxes = <&hsp_top0 TEGRA_HSP 1828 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3111 <&hsp_aon TEGRA_HSP_ !! 1829 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3112 mbox-names = "rx", "tx"; 1830 mbox-names = "rx", "tx";
3113 }; 1831 };
3114 1832
3115 sound { <<
3116 status = "disabled"; <<
3117 <<
3118 clocks = <&bpmp TEGRA194_CLK_ <<
3119 <&bpmp TEGRA194_CLK_ <<
3120 clock-names = "pll_a", "plla_ <<
3121 assigned-clocks = <&bpmp TEGR <<
3122 <&bpmp TEGR <<
3123 <&bpmp TEGR <<
3124 assigned-clock-parents = <0>, <<
3125 <&bp <<
3126 <&bp <<
3127 /* <<
3128 * PLLA supports dynamic ramp <<
3129 * for this to work and oscil <<
3130 * for 8x and 11.025x sample <<
3131 */ <<
3132 assigned-clock-rates = <25800 <<
3133 }; <<
3134 <<
3135 thermal-zones { 1833 thermal-zones {
3136 cpu-thermal { !! 1834 cpu {
3137 thermal-sensors = <&{ !! 1835 thermal-sensors = <&{/bpmp/thermal}
>> 1836 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138 status = "disabled"; 1837 status = "disabled";
3139 }; 1838 };
3140 1839
3141 gpu-thermal { !! 1840 gpu {
3142 thermal-sensors = <&{ !! 1841 thermal-sensors = <&{/bpmp/thermal}
>> 1842 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143 status = "disabled"; 1843 status = "disabled";
3144 }; 1844 };
3145 1845
3146 aux-thermal { !! 1846 aux {
3147 thermal-sensors = <&{ !! 1847 thermal-sensors = <&{/bpmp/thermal}
>> 1848 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148 status = "disabled"; 1849 status = "disabled";
3149 }; 1850 };
3150 1851
3151 pllx-thermal { !! 1852 pllx {
3152 thermal-sensors = <&{ !! 1853 thermal-sensors = <&{/bpmp/thermal}
>> 1854 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153 status = "disabled"; 1855 status = "disabled";
3154 }; 1856 };
3155 1857
3156 ao-thermal { !! 1858 ao {
3157 thermal-sensors = <&{ !! 1859 thermal-sensors = <&{/bpmp/thermal}
>> 1860 TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158 status = "disabled"; 1861 status = "disabled";
3159 }; 1862 };
3160 1863
3161 tj-thermal { !! 1864 tj {
3162 thermal-sensors = <&{ !! 1865 thermal-sensors = <&{/bpmp/thermal}
>> 1866 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163 status = "disabled"; 1867 status = "disabled";
3164 }; 1868 };
3165 }; 1869 };
3166 1870
3167 timer { 1871 timer {
3168 compatible = "arm,armv8-timer 1872 compatible = "arm,armv8-timer";
3169 interrupts = <GIC_PPI 13 1873 interrupts = <GIC_PPI 13
3170 (GIC_CPU_MASK 1874 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171 <GIC_PPI 14 1875 <GIC_PPI 14
3172 (GIC_CPU_MASK 1876 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173 <GIC_PPI 11 1877 <GIC_PPI 11
3174 (GIC_CPU_MASK 1878 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175 <GIC_PPI 10 1879 <GIC_PPI 10
3176 (GIC_CPU_MASK 1880 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177 interrupt-parent = <&gic>; 1881 interrupt-parent = <&gic>;
3178 always-on; 1882 always-on;
3179 }; 1883 };
3180 }; 1884 };
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