1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
3
4 #include "tegra210.dtsi"
5
6 / {
7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,t
9
10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@3c"
12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta;
14 };
15
16 chosen {
17 stdout-path = "serial0:115200n
18 };
19
20 memory@80000000 {
21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0>
23 };
24
25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>;
27 };
28
29 /* debug port */
30 serial@70006000 {
31 /delete-property/ dmas;
32 /delete-property/ dma-names;
33 status = "okay";
34 };
35
36 serial@70006300 {
37 /delete-property/ reg-shift;
38 status = "okay";
39 compatible = "nvidia,tegra30-h
40 reset-names = "serial";
41
42 bluetooth {
43 compatible = "brcm,bcm
44 device-wakeup-gpios =
45 shutdown-gpios = <&gpi
46 interrupt-parent = <&g
47 interrupts = <TEGRA_GP
48 interrupt-names = "hos
49 };
50 };
51
52 i2c@7000c400 {
53 status = "okay";
54
55 power-sensor@40 {
56 compatible = "ti,ina32
57 reg = <0x40>;
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 input@0 {
62 reg = <0x0>;
63 label = "VDD_I
64 shunt-resistor
65 };
66
67 input@1 {
68 reg = <0x1>;
69 label = "VDD_G
70 shunt-resistor
71 };
72
73 input@2 {
74 reg = <0x2>;
75 label = "VDD_C
76 shunt-resistor
77 };
78 };
79 };
80
81 i2c@7000c500 {
82 status = "okay";
83
84 /* module ID EEPROM */
85 eeprom@50 {
86 compatible = "atmel,24
87 reg = <0x50>;
88
89 label = "module";
90 vcc-supply = <&vdd_1v8
91 address-width = <8>;
92 pagesize = <8>;
93 size = <256>;
94 read-only;
95 };
96 };
97
98 i2c@7000d000 {
99 status = "okay";
100 clock-frequency = <400000>;
101
102 pmic: pmic@3c {
103 compatible = "maxim,ma
104 reg = <0x3c>;
105 interrupt-parent = <&t
106 interrupts = <51 IRQ_T
107
108 #interrupt-cells = <2>
109 interrupt-controller;
110
111 #gpio-cells = <2>;
112 gpio-controller;
113
114 pinctrl-names = "defau
115 pinctrl-0 = <&max77620
116
117 fps {
118 fps0 {
119 maxim,
120 maxim,
121 };
122
123 fps1 {
124 maxim,
125 maxim,
126 };
127
128 fps2 {
129 maxim,
130 };
131 };
132
133 max77620_default: pinm
134 gpio0 {
135 pins =
136 functi
137 };
138
139 gpio1 {
140 pins =
141 functi
142 drive-
143 maxim,
144 maxim,
145 maxim,
146 };
147
148 gpio2_3 {
149 pins =
150 functi
151 drive-
152 maxim,
153 };
154
155 gpio4 {
156 pins =
157 functi
158 };
159
160 gpio5_6_7 {
161 pins =
162 functi
163 drive-
164 };
165 };
166
167 regulators {
168 in-ldo0-1-supp
169 in-ldo7-8-supp
170 in-sd3-supply
171
172 vdd_soc: sd0 {
173 regula
174 regula
175 regula
176 regula
177 regula
178
179 regula
180 regula
181
182 maxim,
183 };
184
185 vdd_ddr: sd1 {
186 regula
187 regula
188 regula
189
190 regula
191 regula
192
193 maxim,
194 };
195
196 vdd_pre: sd2 {
197 regula
198 regula
199 regula
200
201 regula
202 regula
203
204 maxim,
205 };
206
207 vdd_1v8: sd3 {
208 regula
209 regula
210 regula
211 regula
212 regula
213
214 regula
215 regula
216
217 maxim,
218 };
219
220 vdd_sys_1v2: l
221 regula
222 regula
223 regula
224 regula
225 regula
226
227 regula
228 regula
229
230 maxim,
231 };
232
233 vdd_pex_1v05:
234 regula
235 regula
236 regula
237
238 regula
239 regula
240
241 maxim,
242 };
243
244 vddio_sdmmc: l
245 regula
246 regula
247 regula
248 regula
249 regula
250
251 regula
252 regula
253
254 maxim,
255 };
256
257 vdd_cam_hv: ld
258 regula
259 regula
260 regula
261
262 regula
263 regula
264
265 maxim,
266 };
267
268 vdd_rtc: ldo4
269 regula
270 regula
271 regula
272 regula
273 regula
274
275 regula
276 regula
277
278 maxim,
279 };
280
281 vdd_ts_hv: ldo
282 regula
283 regula
284 regula
285
286 regula
287 regula
288
289 maxim,
290 };
291
292 vdd_ts: ldo6 {
293 regula
294 regula
295 regula
296
297 regula
298 regula
299
300 maxim,
301 maxim,
302 maxim,
303 };
304
305 avdd_1v05_pll:
306 regula
307 regula
308 regula
309 regula
310 regula
311
312 regula
313 regula
314
315 maxim,
316 };
317
318 avdd_1v05: ldo
319 regula
320 regula
321 regula
322
323 regula
324 regula
325
326 maxim,
327 };
328 };
329 };
330 };
331
332 pmc@7000e400 {
333 nvidia,invert-interrupt;
334 nvidia,suspend-mode = <0>;
335 nvidia,cpu-pwr-good-time = <0>
336 nvidia,cpu-pwr-off-time = <0>;
337 nvidia,core-pwr-good-time = <4
338 nvidia,core-pwr-off-time = <39
339 nvidia,core-power-req-active-h
340 nvidia,sys-clock-req-active-hi
341 };
342
343 mmc@700b0200 {
344 status = "okay";
345 bus-width = <4>;
346 non-removable;
347 power-gpios = <&gpio TEGRA_GPI
348 vqmmc-supply = <&vdd_1v8>;
349 vmmc-supply = <&vdd_3v3_sys>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352
353 wifi@1 {
354 compatible = "brcm,bcm
355 reg = <1>;
356 interrupt-parent = <&g
357 interrupts = <TEGRA_GP
358 interrupt-names = "hos
359 };
360 };
361
362 /* eMMC */
363 mmc@700b0600 {
364 status = "okay";
365 bus-width = <8>;
366 non-removable;
367 vqmmc-supply = <&vdd_1v8>;
368 };
369
370 clk32k_in: clock-32k {
371 compatible = "fixed-clock";
372 clock-frequency = <32768>;
373 #clock-cells = <0>;
374 };
375
376 cpus {
377 cpu@0 {
378 enable-method = "psci"
379 };
380
381 cpu@1 {
382 enable-method = "psci"
383 };
384
385 cpu@2 {
386 enable-method = "psci"
387 };
388
389 cpu@3 {
390 enable-method = "psci"
391 };
392
393 idle-states {
394 cpu-sleep {
395 status = "okay
396 };
397 };
398 };
399
400 psci {
401 compatible = "arm,psci-0.2";
402 method = "smc";
403 };
404
405 vdd_gpu: regulator-vdd-gpu {
406 compatible = "pwm-regulator";
407 pwms = <&pwm 1 8000>;
408 regulator-name = "VDD_GPU";
409 regulator-min-microvolt = <710
410 regulator-max-microvolt = <132
411 enable-gpios = <&pmic 6 GPIO_A
412 regulator-ramp-delay = <80>;
413 regulator-enable-ramp-delay =
414 regulator-settling-time-us = <
415 };
416 };
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