1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h> 2 #include <dt-bindings/mfd/max77620.h>
3 3
4 #include "tegra210.dtsi" 4 #include "tegra210.dtsi"
5 5
6 / { 6 / {
7 model = "NVIDIA Jetson TX1"; 7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,t 8 compatible = "nvidia,p2180", "nvidia,tegra210";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@3c" 11 rtc0 = "/i2c@7000d000/pmic@3c";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta; 13 serial0 = &uarta;
14 }; 14 };
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@80000000 { 20 memory@80000000 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0> 22 reg = <0x0 0x80000000 0x1 0x0>;
23 }; 23 };
24 24
25 gpu@57000000 { 25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>; 26 vdd-supply = <&vdd_gpu>;
27 }; 27 };
28 28
29 /* debug port */ 29 /* debug port */
30 serial@70006000 { 30 serial@70006000 {
31 /delete-property/ dmas; <<
32 /delete-property/ dma-names; <<
33 status = "okay"; 31 status = "okay";
34 }; 32 };
35 33
36 serial@70006300 { <<
37 /delete-property/ reg-shift; <<
38 status = "okay"; <<
39 compatible = "nvidia,tegra30-h <<
40 reset-names = "serial"; <<
41 <<
42 bluetooth { <<
43 compatible = "brcm,bcm <<
44 device-wakeup-gpios = <<
45 shutdown-gpios = <&gpi <<
46 interrupt-parent = <&g <<
47 interrupts = <TEGRA_GP <<
48 interrupt-names = "hos <<
49 }; <<
50 }; <<
51 <<
52 i2c@7000c400 { <<
53 status = "okay"; <<
54 <<
55 power-sensor@40 { <<
56 compatible = "ti,ina32 <<
57 reg = <0x40>; <<
58 #address-cells = <1>; <<
59 #size-cells = <0>; <<
60 <<
61 input@0 { <<
62 reg = <0x0>; <<
63 label = "VDD_I <<
64 shunt-resistor <<
65 }; <<
66 <<
67 input@1 { <<
68 reg = <0x1>; <<
69 label = "VDD_G <<
70 shunt-resistor <<
71 }; <<
72 <<
73 input@2 { <<
74 reg = <0x2>; <<
75 label = "VDD_C <<
76 shunt-resistor <<
77 }; <<
78 }; <<
79 }; <<
80 <<
81 i2c@7000c500 { <<
82 status = "okay"; <<
83 <<
84 /* module ID EEPROM */ <<
85 eeprom@50 { <<
86 compatible = "atmel,24 <<
87 reg = <0x50>; <<
88 <<
89 label = "module"; <<
90 vcc-supply = <&vdd_1v8 <<
91 address-width = <8>; <<
92 pagesize = <8>; <<
93 size = <256>; <<
94 read-only; <<
95 }; <<
96 }; <<
97 <<
98 i2c@7000d000 { 34 i2c@7000d000 {
99 status = "okay"; 35 status = "okay";
100 clock-frequency = <400000>; 36 clock-frequency = <400000>;
101 37
102 pmic: pmic@3c { 38 pmic: pmic@3c {
103 compatible = "maxim,ma 39 compatible = "maxim,max77620";
104 reg = <0x3c>; 40 reg = <0x3c>;
105 interrupt-parent = <&t 41 interrupt-parent = <&tegra_pmc>;
106 interrupts = <51 IRQ_T 42 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
107 43
108 #interrupt-cells = <2> 44 #interrupt-cells = <2>;
109 interrupt-controller; 45 interrupt-controller;
110 46
111 #gpio-cells = <2>; 47 #gpio-cells = <2>;
112 gpio-controller; 48 gpio-controller;
113 49
114 pinctrl-names = "defau 50 pinctrl-names = "default";
115 pinctrl-0 = <&max77620 51 pinctrl-0 = <&max77620_default>;
116 52
117 fps { <<
118 fps0 { <<
119 maxim, <<
120 maxim, <<
121 }; <<
122 <<
123 fps1 { <<
124 maxim, <<
125 maxim, <<
126 }; <<
127 <<
128 fps2 { <<
129 maxim, <<
130 }; <<
131 }; <<
132 <<
133 max77620_default: pinm 53 max77620_default: pinmux {
134 gpio0 { 54 gpio0 {
135 pins = 55 pins = "gpio0";
136 functi 56 function = "gpio";
137 }; 57 };
138 58
139 gpio1 { 59 gpio1 {
140 pins = 60 pins = "gpio1";
141 functi 61 function = "fps-out";
142 drive- 62 drive-push-pull = <1>;
143 maxim, 63 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
144 maxim, 64 maxim,active-fps-power-up-slot = <7>;
145 maxim, 65 maxim,active-fps-power-down-slot = <0>;
146 }; 66 };
147 67
148 gpio2_3 { 68 gpio2_3 {
149 pins = 69 pins = "gpio2", "gpio3";
150 functi 70 function = "fps-out";
151 drive- 71 drive-open-drain = <1>;
152 maxim, 72 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
153 }; 73 };
154 74
155 gpio4 { 75 gpio4 {
156 pins = 76 pins = "gpio4";
157 functi 77 function = "32k-out1";
158 }; 78 };
159 79
160 gpio5_6_7 { 80 gpio5_6_7 {
161 pins = 81 pins = "gpio5", "gpio6", "gpio7";
162 functi 82 function = "gpio";
163 drive- 83 drive-push-pull = <1>;
164 }; 84 };
165 }; 85 };
166 86
>> 87 fps {
>> 88 fps0 {
>> 89 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 90 maxim,suspend-fps-time-period-us = <1280>;
>> 91 };
>> 92
>> 93 fps1 {
>> 94 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 95 maxim,suspend-fps-time-period-us = <1280>;
>> 96 };
>> 97
>> 98 fps2 {
>> 99 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 100 };
>> 101 };
>> 102
167 regulators { 103 regulators {
168 in-ldo0-1-supp 104 in-ldo0-1-supply = <&vdd_pre>;
169 in-ldo7-8-supp 105 in-ldo7-8-supply = <&vdd_pre>;
170 in-sd3-supply 106 in-sd3-supply = <&vdd_5v0_sys>;
171 107
172 vdd_soc: sd0 { 108 vdd_soc: sd0 {
173 regula 109 regulator-name = "VDD_SOC";
174 regula 110 regulator-min-microvolt = <600000>;
175 regula 111 regulator-max-microvolt = <1400000>;
176 regula 112 regulator-always-on;
177 regula 113 regulator-boot-on;
178 114
179 regula 115 regulator-enable-ramp-delay = <146>;
180 regula 116 regulator-ramp-delay = <27500>;
181 117
182 maxim, 118 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
183 }; 119 };
184 120
185 vdd_ddr: sd1 { 121 vdd_ddr: sd1 {
186 regula 122 regulator-name = "VDD_DDR_1V1_PMIC";
187 regula 123 regulator-always-on;
188 regula 124 regulator-boot-on;
189 125
190 regula 126 regulator-enable-ramp-delay = <130>;
191 regula 127 regulator-ramp-delay = <27500>;
192 128
193 maxim, 129 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
194 }; 130 };
195 131
196 vdd_pre: sd2 { 132 vdd_pre: sd2 {
197 regula 133 regulator-name = "VDD_PRE_REG_1V35";
198 regula 134 regulator-min-microvolt = <1350000>;
199 regula 135 regulator-max-microvolt = <1350000>;
200 136
201 regula 137 regulator-enable-ramp-delay = <176>;
202 regula 138 regulator-ramp-delay = <27500>;
203 139
204 maxim, 140 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
205 }; 141 };
206 142
207 vdd_1v8: sd3 { 143 vdd_1v8: sd3 {
208 regula 144 regulator-name = "VDD_1V8";
209 regula 145 regulator-min-microvolt = <1800000>;
210 regula 146 regulator-max-microvolt = <1800000>;
211 regula 147 regulator-always-on;
212 regula 148 regulator-boot-on;
213 149
214 regula 150 regulator-enable-ramp-delay = <242>;
215 regula 151 regulator-ramp-delay = <27500>;
216 152
217 maxim, 153 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 }; 154 };
219 155
220 vdd_sys_1v2: l 156 vdd_sys_1v2: ldo0 {
221 regula 157 regulator-name = "AVDD_SYS_1V2";
222 regula 158 regulator-min-microvolt = <1200000>;
223 regula 159 regulator-max-microvolt = <1200000>;
224 regula 160 regulator-always-on;
225 regula 161 regulator-boot-on;
226 162
227 regula 163 regulator-enable-ramp-delay = <26>;
228 regula 164 regulator-ramp-delay = <100000>;
229 165
230 maxim, 166 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
231 }; 167 };
232 168
233 vdd_pex_1v05: 169 vdd_pex_1v05: ldo1 {
234 regula 170 regulator-name = "VDD_PEX_1V05";
235 regula 171 regulator-min-microvolt = <1050000>;
236 regula 172 regulator-max-microvolt = <1050000>;
237 173
238 regula 174 regulator-enable-ramp-delay = <22>;
239 regula 175 regulator-ramp-delay = <100000>;
240 176
241 maxim, 177 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
242 }; 178 };
243 179
244 vddio_sdmmc: l 180 vddio_sdmmc: ldo2 {
245 regula 181 regulator-name = "VDDIO_SDMMC";
246 regula 182 regulator-min-microvolt = <1800000>;
247 regula 183 regulator-max-microvolt = <3300000>;
248 regula 184 regulator-always-on;
249 regula 185 regulator-boot-on;
250 186
251 regula 187 regulator-enable-ramp-delay = <62>;
252 regula 188 regulator-ramp-delay = <100000>;
253 189
254 maxim, 190 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
255 }; 191 };
256 192
257 vdd_cam_hv: ld 193 vdd_cam_hv: ldo3 {
258 regula 194 regulator-name = "VDD_CAM_HV";
259 regula 195 regulator-min-microvolt = <2800000>;
260 regula 196 regulator-max-microvolt = <2800000>;
261 197
262 regula 198 regulator-enable-ramp-delay = <50>;
263 regula 199 regulator-ramp-delay = <100000>;
264 200
265 maxim, 201 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
266 }; 202 };
267 203
268 vdd_rtc: ldo4 204 vdd_rtc: ldo4 {
269 regula 205 regulator-name = "VDD_RTC";
270 regula 206 regulator-min-microvolt = <850000>;
271 regula 207 regulator-max-microvolt = <850000>;
272 regula 208 regulator-always-on;
273 regula 209 regulator-boot-on;
274 210
275 regula 211 regulator-enable-ramp-delay = <22>;
276 regula 212 regulator-ramp-delay = <100000>;
277 213
278 maxim, 214 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
279 }; 215 };
280 216
281 vdd_ts_hv: ldo 217 vdd_ts_hv: ldo5 {
282 regula 218 regulator-name = "VDD_TS_HV";
283 regula 219 regulator-min-microvolt = <3300000>;
284 regula 220 regulator-max-microvolt = <3300000>;
285 221
286 regula 222 regulator-enable-ramp-delay = <62>;
287 regula 223 regulator-ramp-delay = <100000>;
288 224
289 maxim, 225 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
290 }; 226 };
291 227
292 vdd_ts: ldo6 { 228 vdd_ts: ldo6 {
293 regula 229 regulator-name = "VDD_TS_1V8";
294 regula 230 regulator-min-microvolt = <1800000>;
295 regula 231 regulator-max-microvolt = <1800000>;
296 232
297 regula 233 regulator-enable-ramp-delay = <36>;
298 regula 234 regulator-ramp-delay = <100000>;
299 235
300 maxim, 236 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
301 maxim, 237 maxim,active-fps-power-up-slot = <7>;
302 maxim, 238 maxim,active-fps-power-down-slot = <0>;
303 }; 239 };
304 240
305 avdd_1v05_pll: 241 avdd_1v05_pll: ldo7 {
306 regula 242 regulator-name = "AVDD_1V05_PLL";
307 regula 243 regulator-min-microvolt = <1050000>;
308 regula 244 regulator-max-microvolt = <1050000>;
309 regula 245 regulator-always-on;
310 regula 246 regulator-boot-on;
311 247
312 regula 248 regulator-enable-ramp-delay = <24>;
313 regula 249 regulator-ramp-delay = <100000>;
314 250
315 maxim, 251 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
316 }; 252 };
317 253
318 avdd_1v05: ldo 254 avdd_1v05: ldo8 {
319 regula 255 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
320 regula 256 regulator-min-microvolt = <1050000>;
321 regula 257 regulator-max-microvolt = <1050000>;
322 258
323 regula 259 regulator-enable-ramp-delay = <22>;
324 regula 260 regulator-ramp-delay = <100000>;
325 261
326 maxim, 262 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
327 }; 263 };
328 }; 264 };
329 }; 265 };
330 }; 266 };
331 267
>> 268 i2c@7000c500 {
>> 269 status = "okay";
>> 270
>> 271 /* module ID EEPROM */
>> 272 eeprom@50 {
>> 273 compatible = "atmel,24c02";
>> 274 reg = <0x50>;
>> 275
>> 276 label = "module";
>> 277 vcc-supply = <&vdd_1v8>;
>> 278 address-width = <8>;
>> 279 pagesize = <8>;
>> 280 size = <256>;
>> 281 read-only;
>> 282 };
>> 283 };
>> 284
332 pmc@7000e400 { 285 pmc@7000e400 {
333 nvidia,invert-interrupt; 286 nvidia,invert-interrupt;
334 nvidia,suspend-mode = <0>; 287 nvidia,suspend-mode = <0>;
335 nvidia,cpu-pwr-good-time = <0> 288 nvidia,cpu-pwr-good-time = <0>;
336 nvidia,cpu-pwr-off-time = <0>; 289 nvidia,cpu-pwr-off-time = <0>;
337 nvidia,core-pwr-good-time = <4 290 nvidia,core-pwr-good-time = <4587 3876>;
338 nvidia,core-pwr-off-time = <39 291 nvidia,core-pwr-off-time = <39065>;
339 nvidia,core-power-req-active-h 292 nvidia,core-power-req-active-high;
340 nvidia,sys-clock-req-active-hi 293 nvidia,sys-clock-req-active-high;
341 }; <<
342 <<
343 mmc@700b0200 { <<
344 status = "okay"; <<
345 bus-width = <4>; <<
346 non-removable; <<
347 power-gpios = <&gpio TEGRA_GPI <<
348 vqmmc-supply = <&vdd_1v8>; <<
349 vmmc-supply = <&vdd_3v3_sys>; <<
350 #address-cells = <1>; <<
351 #size-cells = <0>; <<
352 <<
353 wifi@1 { <<
354 compatible = "brcm,bcm <<
355 reg = <1>; <<
356 interrupt-parent = <&g <<
357 interrupts = <TEGRA_GP <<
358 interrupt-names = "hos <<
359 }; <<
360 }; 294 };
361 295
362 /* eMMC */ 296 /* eMMC */
363 mmc@700b0600 { 297 mmc@700b0600 {
364 status = "okay"; 298 status = "okay";
365 bus-width = <8>; 299 bus-width = <8>;
366 non-removable; 300 non-removable;
367 vqmmc-supply = <&vdd_1v8>; 301 vqmmc-supply = <&vdd_1v8>;
368 }; 302 };
369 303
370 clk32k_in: clock-32k { 304 clk32k_in: clock-32k {
371 compatible = "fixed-clock"; 305 compatible = "fixed-clock";
372 clock-frequency = <32768>; 306 clock-frequency = <32768>;
373 #clock-cells = <0>; 307 #clock-cells = <0>;
374 }; 308 };
375 309
376 cpus { 310 cpus {
377 cpu@0 { 311 cpu@0 {
378 enable-method = "psci" 312 enable-method = "psci";
379 }; 313 };
380 314
381 cpu@1 { 315 cpu@1 {
382 enable-method = "psci" 316 enable-method = "psci";
383 }; 317 };
384 318
385 cpu@2 { 319 cpu@2 {
386 enable-method = "psci" 320 enable-method = "psci";
387 }; 321 };
388 322
389 cpu@3 { 323 cpu@3 {
390 enable-method = "psci" 324 enable-method = "psci";
391 }; 325 };
392 326
393 idle-states { 327 idle-states {
394 cpu-sleep { 328 cpu-sleep {
395 status = "okay 329 status = "okay";
396 }; 330 };
397 }; 331 };
398 }; 332 };
399 333
400 psci { 334 psci {
401 compatible = "arm,psci-0.2"; 335 compatible = "arm,psci-0.2";
402 method = "smc"; 336 method = "smc";
403 }; 337 };
404 338
405 vdd_gpu: regulator-vdd-gpu { 339 vdd_gpu: regulator-vdd-gpu {
406 compatible = "pwm-regulator"; 340 compatible = "pwm-regulator";
407 pwms = <&pwm 1 8000>; 341 pwms = <&pwm 1 8000>;
408 regulator-name = "VDD_GPU"; 342 regulator-name = "VDD_GPU";
409 regulator-min-microvolt = <710 343 regulator-min-microvolt = <710000>;
410 regulator-max-microvolt = <132 344 regulator-max-microvolt = <1320000>;
411 enable-gpios = <&pmic 6 GPIO_A 345 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
412 regulator-ramp-delay = <80>; 346 regulator-ramp-delay = <80>;
413 regulator-enable-ramp-delay = 347 regulator-enable-ramp-delay = <2000>;
414 regulator-settling-time-us = < 348 regulator-settling-time-us = <160>;
415 }; 349 };
416 }; 350 };
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