1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h> 2 #include <dt-bindings/mfd/max77620.h>
3 3
4 #include "tegra210.dtsi" 4 #include "tegra210.dtsi"
5 5
6 / { 6 / {
7 model = "NVIDIA Jetson TX1"; 7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,t 8 compatible = "nvidia,p2180", "nvidia,tegra210";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@3c" 11 rtc0 = "/i2c@7000d000/pmic@3c";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta; 13 serial0 = &uarta;
14 }; 14 };
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@80000000 { !! 20 memory {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0> 22 reg = <0x0 0x80000000 0x1 0x0>;
23 }; 23 };
24 24
25 gpu@57000000 { 25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>; 26 vdd-supply = <&vdd_gpu>;
27 }; 27 };
28 28
29 /* debug port */ 29 /* debug port */
30 serial@70006000 { 30 serial@70006000 {
31 /delete-property/ dmas; <<
32 /delete-property/ dma-names; <<
33 status = "okay"; 31 status = "okay";
34 }; 32 };
35 33
36 serial@70006300 { <<
37 /delete-property/ reg-shift; <<
38 status = "okay"; <<
39 compatible = "nvidia,tegra30-h <<
40 reset-names = "serial"; <<
41 <<
42 bluetooth { <<
43 compatible = "brcm,bcm <<
44 device-wakeup-gpios = <<
45 shutdown-gpios = <&gpi <<
46 interrupt-parent = <&g <<
47 interrupts = <TEGRA_GP <<
48 interrupt-names = "hos <<
49 }; <<
50 }; <<
51 <<
52 i2c@7000c400 { <<
53 status = "okay"; <<
54 <<
55 power-sensor@40 { <<
56 compatible = "ti,ina32 <<
57 reg = <0x40>; <<
58 #address-cells = <1>; <<
59 #size-cells = <0>; <<
60 <<
61 input@0 { <<
62 reg = <0x0>; <<
63 label = "VDD_I <<
64 shunt-resistor <<
65 }; <<
66 <<
67 input@1 { <<
68 reg = <0x1>; <<
69 label = "VDD_G <<
70 shunt-resistor <<
71 }; <<
72 <<
73 input@2 { <<
74 reg = <0x2>; <<
75 label = "VDD_C <<
76 shunt-resistor <<
77 }; <<
78 }; <<
79 }; <<
80 <<
81 i2c@7000c500 { <<
82 status = "okay"; <<
83 <<
84 /* module ID EEPROM */ <<
85 eeprom@50 { <<
86 compatible = "atmel,24 <<
87 reg = <0x50>; <<
88 <<
89 label = "module"; <<
90 vcc-supply = <&vdd_1v8 <<
91 address-width = <8>; <<
92 pagesize = <8>; <<
93 size = <256>; <<
94 read-only; <<
95 }; <<
96 }; <<
97 <<
98 i2c@7000d000 { 34 i2c@7000d000 {
99 status = "okay"; 35 status = "okay";
100 clock-frequency = <400000>; 36 clock-frequency = <400000>;
101 37
102 pmic: pmic@3c { 38 pmic: pmic@3c {
103 compatible = "maxim,ma 39 compatible = "maxim,max77620";
104 reg = <0x3c>; 40 reg = <0x3c>;
105 interrupt-parent = <&t !! 41 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
106 interrupts = <51 IRQ_T <<
107 42
108 #interrupt-cells = <2> 43 #interrupt-cells = <2>;
109 interrupt-controller; 44 interrupt-controller;
110 45
111 #gpio-cells = <2>; 46 #gpio-cells = <2>;
112 gpio-controller; 47 gpio-controller;
113 48
114 pinctrl-names = "defau 49 pinctrl-names = "default";
115 pinctrl-0 = <&max77620 50 pinctrl-0 = <&max77620_default>;
116 51
117 fps { <<
118 fps0 { <<
119 maxim, <<
120 maxim, <<
121 }; <<
122 <<
123 fps1 { <<
124 maxim, <<
125 maxim, <<
126 }; <<
127 <<
128 fps2 { <<
129 maxim, <<
130 }; <<
131 }; <<
132 <<
133 max77620_default: pinm 52 max77620_default: pinmux {
134 gpio0 { 53 gpio0 {
135 pins = 54 pins = "gpio0";
136 functi 55 function = "gpio";
137 }; 56 };
138 57
139 gpio1 { 58 gpio1 {
140 pins = 59 pins = "gpio1";
141 functi 60 function = "fps-out";
142 drive- 61 drive-push-pull = <1>;
143 maxim, 62 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
144 maxim, 63 maxim,active-fps-power-up-slot = <7>;
145 maxim, 64 maxim,active-fps-power-down-slot = <0>;
146 }; 65 };
147 66
148 gpio2_3 { 67 gpio2_3 {
149 pins = 68 pins = "gpio2", "gpio3";
150 functi 69 function = "fps-out";
151 drive- 70 drive-open-drain = <1>;
152 maxim, 71 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
153 }; 72 };
154 73
155 gpio4 { 74 gpio4 {
156 pins = 75 pins = "gpio4";
157 functi 76 function = "32k-out1";
158 }; 77 };
159 78
160 gpio5_6_7 { 79 gpio5_6_7 {
161 pins = 80 pins = "gpio5", "gpio6", "gpio7";
162 functi 81 function = "gpio";
163 drive- 82 drive-push-pull = <1>;
164 }; 83 };
165 }; 84 };
166 85
>> 86 fps {
>> 87 fps0 {
>> 88 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 89 maxim,suspend-fps-time-period-us = <1280>;
>> 90 };
>> 91
>> 92 fps1 {
>> 93 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 94 maxim,suspend-fps-time-period-us = <1280>;
>> 95 };
>> 96
>> 97 fps2 {
>> 98 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 99 };
>> 100 };
>> 101
167 regulators { 102 regulators {
168 in-ldo0-1-supp 103 in-ldo0-1-supply = <&vdd_pre>;
169 in-ldo7-8-supp 104 in-ldo7-8-supply = <&vdd_pre>;
170 in-sd3-supply 105 in-sd3-supply = <&vdd_5v0_sys>;
171 106
172 vdd_soc: sd0 { 107 vdd_soc: sd0 {
173 regula 108 regulator-name = "VDD_SOC";
174 regula 109 regulator-min-microvolt = <600000>;
175 regula 110 regulator-max-microvolt = <1400000>;
176 regula 111 regulator-always-on;
177 regula 112 regulator-boot-on;
178 113
179 regula 114 regulator-enable-ramp-delay = <146>;
180 regula 115 regulator-ramp-delay = <27500>;
181 116
182 maxim, 117 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
183 }; 118 };
184 119
185 vdd_ddr: sd1 { 120 vdd_ddr: sd1 {
186 regula 121 regulator-name = "VDD_DDR_1V1_PMIC";
187 regula 122 regulator-always-on;
188 regula 123 regulator-boot-on;
189 124
190 regula 125 regulator-enable-ramp-delay = <130>;
191 regula 126 regulator-ramp-delay = <27500>;
192 127
193 maxim, 128 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
194 }; 129 };
195 130
196 vdd_pre: sd2 { 131 vdd_pre: sd2 {
197 regula 132 regulator-name = "VDD_PRE_REG_1V35";
198 regula 133 regulator-min-microvolt = <1350000>;
199 regula 134 regulator-max-microvolt = <1350000>;
200 135
201 regula 136 regulator-enable-ramp-delay = <176>;
202 regula 137 regulator-ramp-delay = <27500>;
203 138
204 maxim, 139 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
205 }; 140 };
206 141
207 vdd_1v8: sd3 { 142 vdd_1v8: sd3 {
208 regula 143 regulator-name = "VDD_1V8";
209 regula 144 regulator-min-microvolt = <1800000>;
210 regula 145 regulator-max-microvolt = <1800000>;
211 regula 146 regulator-always-on;
212 regula 147 regulator-boot-on;
213 148
214 regula 149 regulator-enable-ramp-delay = <242>;
215 regula 150 regulator-ramp-delay = <27500>;
216 151
217 maxim, 152 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 }; 153 };
219 154
220 vdd_sys_1v2: l 155 vdd_sys_1v2: ldo0 {
221 regula 156 regulator-name = "AVDD_SYS_1V2";
222 regula 157 regulator-min-microvolt = <1200000>;
223 regula 158 regulator-max-microvolt = <1200000>;
224 regula 159 regulator-always-on;
225 regula 160 regulator-boot-on;
226 161
227 regula 162 regulator-enable-ramp-delay = <26>;
228 regula 163 regulator-ramp-delay = <100000>;
229 164
230 maxim, 165 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
231 }; 166 };
232 167
233 vdd_pex_1v05: 168 vdd_pex_1v05: ldo1 {
234 regula 169 regulator-name = "VDD_PEX_1V05";
235 regula 170 regulator-min-microvolt = <1050000>;
236 regula 171 regulator-max-microvolt = <1050000>;
237 172
238 regula 173 regulator-enable-ramp-delay = <22>;
239 regula 174 regulator-ramp-delay = <100000>;
240 175
241 maxim, 176 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
242 }; 177 };
243 178
244 vddio_sdmmc: l 179 vddio_sdmmc: ldo2 {
245 regula 180 regulator-name = "VDDIO_SDMMC";
246 regula 181 regulator-min-microvolt = <1800000>;
247 regula 182 regulator-max-microvolt = <3300000>;
248 regula 183 regulator-always-on;
249 regula 184 regulator-boot-on;
250 185
251 regula 186 regulator-enable-ramp-delay = <62>;
252 regula 187 regulator-ramp-delay = <100000>;
253 188
254 maxim, 189 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
255 }; 190 };
256 191
257 vdd_cam_hv: ld 192 vdd_cam_hv: ldo3 {
258 regula 193 regulator-name = "VDD_CAM_HV";
259 regula 194 regulator-min-microvolt = <2800000>;
260 regula 195 regulator-max-microvolt = <2800000>;
261 196
262 regula 197 regulator-enable-ramp-delay = <50>;
263 regula 198 regulator-ramp-delay = <100000>;
264 199
265 maxim, 200 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
266 }; 201 };
267 202
268 vdd_rtc: ldo4 203 vdd_rtc: ldo4 {
269 regula 204 regulator-name = "VDD_RTC";
270 regula 205 regulator-min-microvolt = <850000>;
271 regula 206 regulator-max-microvolt = <850000>;
272 regula 207 regulator-always-on;
273 regula 208 regulator-boot-on;
274 209
275 regula 210 regulator-enable-ramp-delay = <22>;
276 regula 211 regulator-ramp-delay = <100000>;
277 212
278 maxim, 213 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
279 }; 214 };
280 215
281 vdd_ts_hv: ldo 216 vdd_ts_hv: ldo5 {
282 regula 217 regulator-name = "VDD_TS_HV";
283 regula 218 regulator-min-microvolt = <3300000>;
284 regula 219 regulator-max-microvolt = <3300000>;
285 220
286 regula 221 regulator-enable-ramp-delay = <62>;
287 regula 222 regulator-ramp-delay = <100000>;
288 223
289 maxim, 224 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
290 }; 225 };
291 226
292 vdd_ts: ldo6 { 227 vdd_ts: ldo6 {
293 regula 228 regulator-name = "VDD_TS_1V8";
294 regula 229 regulator-min-microvolt = <1800000>;
295 regula 230 regulator-max-microvolt = <1800000>;
296 231
297 regula 232 regulator-enable-ramp-delay = <36>;
298 regula 233 regulator-ramp-delay = <100000>;
299 234
300 maxim, 235 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
301 maxim, 236 maxim,active-fps-power-up-slot = <7>;
302 maxim, 237 maxim,active-fps-power-down-slot = <0>;
303 }; 238 };
304 239
305 avdd_1v05_pll: 240 avdd_1v05_pll: ldo7 {
306 regula 241 regulator-name = "AVDD_1V05_PLL";
307 regula 242 regulator-min-microvolt = <1050000>;
308 regula 243 regulator-max-microvolt = <1050000>;
309 regula 244 regulator-always-on;
310 regula 245 regulator-boot-on;
311 246
312 regula 247 regulator-enable-ramp-delay = <24>;
313 regula 248 regulator-ramp-delay = <100000>;
314 249
315 maxim, 250 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
316 }; 251 };
317 252
318 avdd_1v05: ldo 253 avdd_1v05: ldo8 {
319 regula 254 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
320 regula 255 regulator-min-microvolt = <1050000>;
321 regula 256 regulator-max-microvolt = <1050000>;
322 257
323 regula 258 regulator-enable-ramp-delay = <22>;
324 regula 259 regulator-ramp-delay = <100000>;
325 260
326 maxim, 261 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
327 }; 262 };
328 }; 263 };
329 }; 264 };
330 }; 265 };
331 266
>> 267 i2c@7000c500 {
>> 268 /* module ID EEPROM */
>> 269 eeprom@50 {
>> 270 compatible = "atmel,24c02";
>> 271 reg = <0x50>;
>> 272
>> 273 address-bits = <8>;
>> 274 page-size = <8>;
>> 275 size = <256>;
>> 276 read-only;
>> 277 };
>> 278 };
>> 279
332 pmc@7000e400 { 280 pmc@7000e400 {
333 nvidia,invert-interrupt; 281 nvidia,invert-interrupt;
334 nvidia,suspend-mode = <0>; 282 nvidia,suspend-mode = <0>;
335 nvidia,cpu-pwr-good-time = <0> 283 nvidia,cpu-pwr-good-time = <0>;
336 nvidia,cpu-pwr-off-time = <0>; 284 nvidia,cpu-pwr-off-time = <0>;
337 nvidia,core-pwr-good-time = <4 285 nvidia,core-pwr-good-time = <4587 3876>;
338 nvidia,core-pwr-off-time = <39 286 nvidia,core-pwr-off-time = <39065>;
339 nvidia,core-power-req-active-h 287 nvidia,core-power-req-active-high;
340 nvidia,sys-clock-req-active-hi 288 nvidia,sys-clock-req-active-high;
341 }; 289 };
342 290
343 mmc@700b0200 { <<
344 status = "okay"; <<
345 bus-width = <4>; <<
346 non-removable; <<
347 power-gpios = <&gpio TEGRA_GPI <<
348 vqmmc-supply = <&vdd_1v8>; <<
349 vmmc-supply = <&vdd_3v3_sys>; <<
350 #address-cells = <1>; <<
351 #size-cells = <0>; <<
352 <<
353 wifi@1 { <<
354 compatible = "brcm,bcm <<
355 reg = <1>; <<
356 interrupt-parent = <&g <<
357 interrupts = <TEGRA_GP <<
358 interrupt-names = "hos <<
359 }; <<
360 }; <<
361 <<
362 /* eMMC */ 291 /* eMMC */
363 mmc@700b0600 { !! 292 sdhci@700b0600 {
364 status = "okay"; 293 status = "okay";
365 bus-width = <8>; 294 bus-width = <8>;
366 non-removable; 295 non-removable;
367 vqmmc-supply = <&vdd_1v8>; 296 vqmmc-supply = <&vdd_1v8>;
368 }; 297 };
369 298
370 clk32k_in: clock-32k { !! 299 clocks {
371 compatible = "fixed-clock"; !! 300 compatible = "simple-bus";
372 clock-frequency = <32768>; !! 301 #address-cells = <1>;
373 #clock-cells = <0>; !! 302 #size-cells = <0>;
>> 303
>> 304 clk32k_in: clock@0 {
>> 305 compatible = "fixed-clock";
>> 306 reg = <0>;
>> 307 #clock-cells = <0>;
>> 308 clock-frequency = <32768>;
>> 309 };
374 }; 310 };
375 311
376 cpus { 312 cpus {
377 cpu@0 { 313 cpu@0 {
378 enable-method = "psci" 314 enable-method = "psci";
379 }; 315 };
380 316
381 cpu@1 { 317 cpu@1 {
382 enable-method = "psci" 318 enable-method = "psci";
383 }; 319 };
384 320
385 cpu@2 { 321 cpu@2 {
386 enable-method = "psci" 322 enable-method = "psci";
387 }; 323 };
388 324
389 cpu@3 { 325 cpu@3 {
390 enable-method = "psci" 326 enable-method = "psci";
391 }; 327 };
392 328
393 idle-states { 329 idle-states {
394 cpu-sleep { 330 cpu-sleep {
395 status = "okay 331 status = "okay";
396 }; 332 };
397 }; 333 };
398 }; 334 };
399 335
400 psci { 336 psci {
401 compatible = "arm,psci-0.2"; 337 compatible = "arm,psci-0.2";
402 method = "smc"; 338 method = "smc";
403 }; 339 };
404 340
405 vdd_gpu: regulator-vdd-gpu { !! 341 regulators {
406 compatible = "pwm-regulator"; !! 342 vdd_gpu: regulator@100 {
407 pwms = <&pwm 1 8000>; !! 343 compatible = "pwm-regulator";
408 regulator-name = "VDD_GPU"; !! 344 reg = <100>;
409 regulator-min-microvolt = <710 !! 345 pwms = <&pwm 1 4880>;
410 regulator-max-microvolt = <132 !! 346 regulator-name = "VDD_GPU";
411 enable-gpios = <&pmic 6 GPIO_A !! 347 regulator-min-microvolt = <710000>;
412 regulator-ramp-delay = <80>; !! 348 regulator-max-microvolt = <1320000>;
413 regulator-enable-ramp-delay = !! 349 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
414 regulator-settling-time-us = < !! 350 regulator-ramp-delay = <80>;
>> 351 regulator-enable-ramp-delay = <2000>;
>> 352 regulator-settling-time-us = <160>;
>> 353 };
415 }; 354 };
416 }; 355 };
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